Adding of additional support to Cadence PCIe controller (i.e. pci-j721e.c)
for up to 4x lanes, and reworking of driver to define maximum lanes per
board configuration.
Changes from v1:
* Reworked 'PCI: j721e: Add PCIe 4x lane selection support' to not cause
regressions on 1-2x lane platforms
Changes from v2:
* Correct dev_warn format string from %d to %u since lane count is a unsigned
integer
* Update CC list
Changes from v3:
* Use the max_lanes setting per chip for the mask size required since bootloader
could have set num_lanes to a higher value that the device tree which would leave
in an undefined state
* Reorder patches do the previous change to not break bisect
* Remove line breaking for dev_warn to allow better grepping and since no strict
80 columns anymore
Changes from v4:
* Correct invalid settings for j7200 PCIe RC + EP
* Add j784s4 configuration for selection of 4x lanes
Changes from v5:
* Dropped 'PCI: j721e: Add warnings on num-lanes misconfiguration' patch from series
* Reworded 'PCI: j721e: Add per platform maximum lane settings' commit message
* Added yaml documentation and schema checks for ti,j721e-pci-* lane checking
Changes from v6:
* Fix wordwrapping in commit messages from ~65 columns to correct 75 columns
* Re-ran get_maintainers.pl to add missing maintainers in CC
Matt Ranostay (5):
dt-bindings: PCI: ti,j721e-pci-*: add checks for num-lanes
PCI: j721e: Add per platform maximum lane settings
PCI: j721e: Add PCIe 4x lane selection support
dt-bindings: PCI: ti,j721e-pci-*: add j784s4-pci-* compatible strings
PCI: j721e: add j784s4 PCIe configuration
.../bindings/pci/ti,j721e-pci-ep.yaml | 40 +++++++++++++++--
.../bindings/pci/ti,j721e-pci-host.yaml | 40 +++++++++++++++--
drivers/pci/controller/cadence/pci-j721e.c | 44 ++++++++++++++++---
3 files changed, 113 insertions(+), 11 deletions(-)
--
2.38.GIT
Various platforms have different maximum amount of lanes that can be
selected. Add max_lanes to struct j721e_pcie to allow for detection of this
which is needed to calculate the needed bitmask size for the possible lane
count.
Signed-off-by: Matt Ranostay <[email protected]>
Signed-off-by: Vignesh Raghavendra <[email protected]>
---
drivers/pci/controller/cadence/pci-j721e.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index cc83a8925ce0..8990f58d64d5 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -47,8 +47,6 @@ enum link_status {
#define GENERATION_SEL_MASK GENMASK(1, 0)
-#define MAX_LANES 2
-
struct j721e_pcie {
struct cdns_pcie *cdns_pcie;
struct clk *refclk;
@@ -71,6 +69,7 @@ struct j721e_pcie_data {
unsigned int quirk_disable_flr:1;
u32 linkdown_irq_regfield;
unsigned int byte_access_allowed:1;
+ unsigned int max_lanes;
};
static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
@@ -290,11 +289,13 @@ static const struct j721e_pcie_data j721e_pcie_rc_data = {
.quirk_retrain_flag = true,
.byte_access_allowed = false,
.linkdown_irq_regfield = LINK_DOWN,
+ .max_lanes = 2,
};
static const struct j721e_pcie_data j721e_pcie_ep_data = {
.mode = PCI_MODE_EP,
.linkdown_irq_regfield = LINK_DOWN,
+ .max_lanes = 2,
};
static const struct j721e_pcie_data j7200_pcie_rc_data = {
@@ -302,23 +303,27 @@ static const struct j721e_pcie_data j7200_pcie_rc_data = {
.quirk_detect_quiet_flag = true,
.linkdown_irq_regfield = J7200_LINK_DOWN,
.byte_access_allowed = true,
+ .max_lanes = 2,
};
static const struct j721e_pcie_data j7200_pcie_ep_data = {
.mode = PCI_MODE_EP,
.quirk_detect_quiet_flag = true,
.quirk_disable_flr = true,
+ .max_lanes = 2,
};
static const struct j721e_pcie_data am64_pcie_rc_data = {
.mode = PCI_MODE_RC,
.linkdown_irq_regfield = J7200_LINK_DOWN,
.byte_access_allowed = true,
+ .max_lanes = 1,
};
static const struct j721e_pcie_data am64_pcie_ep_data = {
.mode = PCI_MODE_EP,
.linkdown_irq_regfield = J7200_LINK_DOWN,
+ .max_lanes = 1,
};
static const struct of_device_id of_j721e_pcie_match[] = {
@@ -432,7 +437,7 @@ static int j721e_pcie_probe(struct platform_device *pdev)
pcie->user_cfg_base = base;
ret = of_property_read_u32(node, "num-lanes", &num_lanes);
- if (ret || num_lanes > MAX_LANES)
+ if (ret || num_lanes > data->max_lanes)
num_lanes = 1;
pcie->num_lanes = num_lanes;
--
2.38.GIT
Add PCIe configuration for j784s4 platform which has 4x lane support.
Tested-by: Achal Verma <[email protected]>
Signed-off-by: Matt Ranostay <[email protected]>
---
drivers/pci/controller/cadence/pci-j721e.c | 23 ++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index dab3db9be6d8..c484d658c18a 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -330,6 +330,21 @@ static const struct j721e_pcie_data am64_pcie_ep_data = {
.max_lanes = 1,
};
+static const struct j721e_pcie_data j784s4_pcie_rc_data = {
+ .mode = PCI_MODE_RC,
+ .quirk_retrain_flag = true,
+ .is_intc_v1 = true,
+ .byte_access_allowed = false,
+ .linkdown_irq_regfield = LINK_DOWN,
+ .max_lanes = 4,
+};
+
+static const struct j721e_pcie_data j784s4_pcie_ep_data = {
+ .mode = PCI_MODE_EP,
+ .linkdown_irq_regfield = LINK_DOWN,
+ .max_lanes = 4,
+};
+
static const struct of_device_id of_j721e_pcie_match[] = {
{
.compatible = "ti,j721e-pcie-host",
@@ -355,6 +370,14 @@ static const struct of_device_id of_j721e_pcie_match[] = {
.compatible = "ti,am64-pcie-ep",
.data = &am64_pcie_ep_data,
},
+ {
+ .compatible = "ti,j784s4-pcie-host",
+ .data = &j784s4_pcie_rc_data,
+ },
+ {
+ .compatible = "ti,j784s4-pcie-ep",
+ .data = &j784s4_pcie_ep_data,
+ },
{},
};
--
2.38.GIT
Add num-lanes schema checks based on compatible string on available lanes
for that platform.
Signed-off-by: Matt Ranostay <[email protected]>
---
.../bindings/pci/ti,j721e-pci-ep.yaml | 28 +++++++++++++++++--
.../bindings/pci/ti,j721e-pci-host.yaml | 28 +++++++++++++++++--
2 files changed, 50 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
index 10e6eabdff53..1aeea168d3d0 100644
--- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
@@ -10,9 +10,6 @@ title: TI J721E PCI EP (PCIe Wrapper)
maintainers:
- Kishon Vijay Abraham I <[email protected]>
-allOf:
- - $ref: "cdns-pcie-ep.yaml#"
-
properties:
compatible:
oneOf:
@@ -65,6 +62,31 @@ properties:
items:
- const: link_state
+allOf:
+ - $ref: "cdns-pcie-ep.yaml#"
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,am64-pcie-ep
+ then:
+ properties:
+ num-lanes:
+ minimum: 1
+ maximum: 1
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,j7200-pcie-ep
+ - ti,j721e-pcie-ep
+ then:
+ properties:
+ num-lanes:
+ minimum: 1
+ maximum: 2
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
index b0513b197d08..8eca0d08303f 100644
--- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
+++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
@@ -10,9 +10,6 @@ title: TI J721E PCI Host (PCIe Wrapper)
maintainers:
- Kishon Vijay Abraham I <[email protected]>
-allOf:
- - $ref: "cdns-pcie-host.yaml#"
-
properties:
compatible:
oneOf:
@@ -98,6 +95,31 @@ properties:
interrupts:
maxItems: 1
+allOf:
+ - $ref: "cdns-pcie-host.yaml#"
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,am64-pcie-host
+ then:
+ properties:
+ num-lanes:
+ minimum: 1
+ maximum: 1
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,j7200-pcie-host
+ - ti,j721e-pcie-host
+ then:
+ properties:
+ num-lanes:
+ minimum: 1
+ maximum: 2
+
required:
- compatible
- reg
--
2.38.GIT
Add support for setting of two-bit field that allows selection of 4x lane
PCIe which was previously limited to only 2x lanes.
Signed-off-by: Matt Ranostay <[email protected]>
Reviewed-by: Vignesh Raghavendra <[email protected]>
---
drivers/pci/controller/cadence/pci-j721e.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index 8990f58d64d5..dab3db9be6d8 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -42,7 +42,6 @@ enum link_status {
};
#define J721E_MODE_RC BIT(7)
-#define LANE_COUNT_MASK BIT(8)
#define LANE_COUNT(n) ((n) << 8)
#define GENERATION_SEL_MASK GENMASK(1, 0)
@@ -52,6 +51,7 @@ struct j721e_pcie {
struct clk *refclk;
u32 mode;
u32 num_lanes;
+ u32 max_lanes;
void __iomem *user_cfg_base;
void __iomem *intd_cfg_base;
u32 linkdown_irq_regfield;
@@ -205,11 +205,15 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
{
struct device *dev = pcie->cdns_pcie->dev;
u32 lanes = pcie->num_lanes;
+ u32 mask = GENMASK(8, 8);
u32 val = 0;
int ret;
+ if (pcie->max_lanes == 4)
+ mask = GENMASK(9, 8);
+
val = LANE_COUNT(lanes - 1);
- ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val);
+ ret = regmap_update_bits(syscon, offset, mask, val);
if (ret)
dev_err(dev, "failed to set link count\n");
@@ -439,6 +443,8 @@ static int j721e_pcie_probe(struct platform_device *pdev)
ret = of_property_read_u32(node, "num-lanes", &num_lanes);
if (ret || num_lanes > data->max_lanes)
num_lanes = 1;
+
+ pcie->max_lanes = data->max_lanes;
pcie->num_lanes = num_lanes;
if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
--
2.38.GIT
Add definition for j784s4-pci-ep + j784s4-pci-host devices along with
schema checks for num-lanes.
Signed-off-by: Matt Ranostay <[email protected]>
---
.../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 12 ++++++++++++
.../devicetree/bindings/pci/ti,j721e-pci-host.yaml | 12 ++++++++++++
2 files changed, 24 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
index 1aeea168d3d0..2e6226cbd1d3 100644
--- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
@@ -14,6 +14,7 @@ properties:
compatible:
oneOf:
- const: ti,j721e-pcie-ep
+ - const: ti,j784s4-pcie-ep
- description: PCIe EP controller in AM64
items:
- const: ti,am64-pcie-ep
@@ -87,6 +88,17 @@ allOf:
minimum: 1
maximum: 2
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,j784s4-pcie-ep
+ then:
+ properties:
+ num-lanes:
+ minimum: 1
+ maximum: 4
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
index 8eca0d08303f..100d3f556adb 100644
--- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
+++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
@@ -14,6 +14,7 @@ properties:
compatible:
oneOf:
- const: ti,j721e-pcie-host
+ - const: ti,j784s4-pcie-host
- description: PCIe controller in AM64
items:
- const: ti,am64-pcie-host
@@ -120,6 +121,17 @@ allOf:
minimum: 1
maximum: 2
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,j784s4-pcie-host
+ then:
+ properties:
+ num-lanes:
+ minimum: 1
+ maximum: 4
+
required:
- compatible
- reg
--
2.38.GIT
On 24/11/2022 10:12, Matt Ranostay wrote:
> Add support for setting of two-bit field that allows selection of 4x lane
> PCIe which was previously limited to only 2x lanes.
>
> Signed-off-by: Matt Ranostay <[email protected]>
> Reviewed-by: Vignesh Raghavendra <[email protected]>
> ---
> drivers/pci/controller/cadence/pci-j721e.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> index 8990f58d64d5..dab3db9be6d8 100644
> --- a/drivers/pci/controller/cadence/pci-j721e.c
> +++ b/drivers/pci/controller/cadence/pci-j721e.c
> @@ -42,7 +42,6 @@ enum link_status {
> };
>
> #define J721E_MODE_RC BIT(7)
> -#define LANE_COUNT_MASK BIT(8)
> #define LANE_COUNT(n) ((n) << 8)
>
> #define GENERATION_SEL_MASK GENMASK(1, 0)
> @@ -52,6 +51,7 @@ struct j721e_pcie {
> struct clk *refclk;
> u32 mode;
> u32 num_lanes;
> + u32 max_lanes;
> void __iomem *user_cfg_base;
> void __iomem *intd_cfg_base;
> u32 linkdown_irq_regfield;
> @@ -205,11 +205,15 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
> {
> struct device *dev = pcie->cdns_pcie->dev;
> u32 lanes = pcie->num_lanes;
> + u32 mask = GENMASK(8, 8);
u32 mask = BIT(8);
> u32 val = 0;
> int ret;
>
> + if (pcie->max_lanes == 4)
> + mask = GENMASK(9, 8);
> +
> val = LANE_COUNT(lanes - 1);
> - ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val);
> + ret = regmap_update_bits(syscon, offset, mask, val);
> if (ret)
> dev_err(dev, "failed to set link count\n");
>
> @@ -439,6 +443,8 @@ static int j721e_pcie_probe(struct platform_device *pdev)
> ret = of_property_read_u32(node, "num-lanes", &num_lanes);
> if (ret || num_lanes > data->max_lanes)
> num_lanes = 1;
> +
> + pcie->max_lanes = data->max_lanes;
> pcie->num_lanes = num_lanes;
>
> if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
Reviewed-by: Roger Quadros <[email protected]>
cheers,
-roger
On 24/11/2022 10:12, Matt Ranostay wrote:
> Add PCIe configuration for j784s4 platform which has 4x lane support.
>
> Tested-by: Achal Verma <[email protected]>
> Signed-off-by: Matt Ranostay <[email protected]>
Reviewed-by: Roger Quadros <[email protected]>
> ---
> drivers/pci/controller/cadence/pci-j721e.c | 23 ++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> index dab3db9be6d8..c484d658c18a 100644
> --- a/drivers/pci/controller/cadence/pci-j721e.c
> +++ b/drivers/pci/controller/cadence/pci-j721e.c
> @@ -330,6 +330,21 @@ static const struct j721e_pcie_data am64_pcie_ep_data = {
> .max_lanes = 1,
> };
>
> +static const struct j721e_pcie_data j784s4_pcie_rc_data = {
> + .mode = PCI_MODE_RC,
> + .quirk_retrain_flag = true,
> + .is_intc_v1 = true,
> + .byte_access_allowed = false,
> + .linkdown_irq_regfield = LINK_DOWN,
> + .max_lanes = 4,
> +};
> +
> +static const struct j721e_pcie_data j784s4_pcie_ep_data = {
> + .mode = PCI_MODE_EP,
> + .linkdown_irq_regfield = LINK_DOWN,
> + .max_lanes = 4,
> +};
> +
> static const struct of_device_id of_j721e_pcie_match[] = {
> {
> .compatible = "ti,j721e-pcie-host",
> @@ -355,6 +370,14 @@ static const struct of_device_id of_j721e_pcie_match[] = {
> .compatible = "ti,am64-pcie-ep",
> .data = &am64_pcie_ep_data,
> },
> + {
> + .compatible = "ti,j784s4-pcie-host",
> + .data = &j784s4_pcie_rc_data,
> + },
> + {
> + .compatible = "ti,j784s4-pcie-ep",
> + .data = &j784s4_pcie_ep_data,
> + },
> {},
> };
>
--
cheers,
-roger
Hi Matt,
On 24/11/2022 10:12, Matt Ranostay wrote:
> Various platforms have different maximum amount of lanes that can be
> selected. Add max_lanes to struct j721e_pcie to allow for detection of this
> which is needed to calculate the needed bitmask size for the possible lane
> count.
>
> Signed-off-by: Matt Ranostay <[email protected]>
> Signed-off-by: Vignesh Raghavendra <[email protected]>
> ---
> drivers/pci/controller/cadence/pci-j721e.c | 11 ++++++++---
> 1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> index cc83a8925ce0..8990f58d64d5 100644
> --- a/drivers/pci/controller/cadence/pci-j721e.c
> +++ b/drivers/pci/controller/cadence/pci-j721e.c
> @@ -47,8 +47,6 @@ enum link_status {
>
> #define GENERATION_SEL_MASK GENMASK(1, 0)
>
> -#define MAX_LANES 2
> -
> struct j721e_pcie {
> struct cdns_pcie *cdns_pcie;
> struct clk *refclk;
> @@ -71,6 +69,7 @@ struct j721e_pcie_data {
> unsigned int quirk_disable_flr:1;
> u32 linkdown_irq_regfield;
> unsigned int byte_access_allowed:1;
> + unsigned int max_lanes;
> };
>
> static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
> @@ -290,11 +289,13 @@ static const struct j721e_pcie_data j721e_pcie_rc_data = {
> .quirk_retrain_flag = true,
> .byte_access_allowed = false,
> .linkdown_irq_regfield = LINK_DOWN,
> + .max_lanes = 2,
> };
>
> static const struct j721e_pcie_data j721e_pcie_ep_data = {
> .mode = PCI_MODE_EP,
> .linkdown_irq_regfield = LINK_DOWN,
> + .max_lanes = 2,
> };
>
> static const struct j721e_pcie_data j7200_pcie_rc_data = {
> @@ -302,23 +303,27 @@ static const struct j721e_pcie_data j7200_pcie_rc_data = {
> .quirk_detect_quiet_flag = true,
> .linkdown_irq_regfield = J7200_LINK_DOWN,
> .byte_access_allowed = true,
> + .max_lanes = 2,
> };
>
> static const struct j721e_pcie_data j7200_pcie_ep_data = {
> .mode = PCI_MODE_EP,
> .quirk_detect_quiet_flag = true,
> .quirk_disable_flr = true,
> + .max_lanes = 2,
> };
>
> static const struct j721e_pcie_data am64_pcie_rc_data = {
> .mode = PCI_MODE_RC,
> .linkdown_irq_regfield = J7200_LINK_DOWN,
> .byte_access_allowed = true,
> + .max_lanes = 1,
> };
>
> static const struct j721e_pcie_data am64_pcie_ep_data = {
> .mode = PCI_MODE_EP,
> .linkdown_irq_regfield = J7200_LINK_DOWN,
> + .max_lanes = 1,
> };
>
> static const struct of_device_id of_j721e_pcie_match[] = {
> @@ -432,7 +437,7 @@ static int j721e_pcie_probe(struct platform_device *pdev)
> pcie->user_cfg_base = base;
>
> ret = of_property_read_u32(node, "num-lanes", &num_lanes);
> - if (ret || num_lanes > MAX_LANES)
> + if (ret || num_lanes > data->max_lanes)
> num_lanes = 1;
num_lanes = data->max_lanes; ?
Should we also print an error message saying that invalid num-lanes
was supplied in device tree?
Is it better to error out of probe?
> pcie->num_lanes = num_lanes;
>
cheers,
-roger
Hi Matt,
I love your patch! Yet something to improve:
[auto build test ERROR on helgaas-pci/next]
[also build test ERROR on next-20221125]
[cannot apply to helgaas-pci/for-linus linus/master v6.1-rc6]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Matt-Ranostay/PCI-add-4x-lane-support-for-pci-j721e-controllers/20221124-161712
base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
patch link: https://lore.kernel.org/r/20221124081221.1206167-6-mranostay%40ti.com
patch subject: [PATCH v7 5/5] PCI: j721e: add j784s4 PCIe configuration
config: i386-randconfig-a015
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/ee3fcfcf1caaa25a9ba8ccceaf917e0bd43c38a4
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Matt-Ranostay/PCI-add-4x-lane-support-for-pci-j721e-controllers/20221124-161712
git checkout ee3fcfcf1caaa25a9ba8ccceaf917e0bd43c38a4
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>
All errors (new ones prefixed by >>):
>> drivers/pci/controller/cadence/pci-j721e.c:336:3: error: field designator 'is_intc_v1' does not refer to any field in type 'const struct j721e_pcie_data'
.is_intc_v1 = true,
^
1 error generated.
vim +336 drivers/pci/controller/cadence/pci-j721e.c
332
333 static const struct j721e_pcie_data j784s4_pcie_rc_data = {
334 .mode = PCI_MODE_RC,
335 .quirk_retrain_flag = true,
> 336 .is_intc_v1 = true,
337 .byte_access_allowed = false,
338 .linkdown_irq_regfield = LINK_DOWN,
339 .max_lanes = 4,
340 };
341
--
0-DAY CI Kernel Test Service
https://01.org/lkp
On 24/11/2022 09:12, Matt Ranostay wrote:
> Add num-lanes schema checks based on compatible string on available lanes
> for that platform.
>
> Signed-off-by: Matt Ranostay <[email protected]>
> ---
> .../bindings/pci/ti,j721e-pci-ep.yaml | 28 +++++++++++++++++--
> .../bindings/pci/ti,j721e-pci-host.yaml | 28 +++++++++++++++++--
> 2 files changed, 50 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
> index 10e6eabdff53..1aeea168d3d0 100644
> --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
> +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
> @@ -10,9 +10,6 @@ title: TI J721E PCI EP (PCIe Wrapper)
> maintainers:
> - Kishon Vijay Abraham I <[email protected]>
>
> -allOf:
> - - $ref: "cdns-pcie-ep.yaml#"
> -
> properties:
> compatible:
> oneOf:
> @@ -65,6 +62,31 @@ properties:
> items:
> - const: link_state
>
> +allOf:
> + - $ref: "cdns-pcie-ep.yaml#"
While moving it, drop the quotes.
> + - if:
> + properties:
> + compatible:
> + enum:
> + - ti,am64-pcie-ep
> + then:
> + properties:
> + num-lanes:
> + minimum: 1
> + maximum: 1
> +
> + - if:
> + properties:
> + compatible:
> + enum:
> + - ti,j7200-pcie-ep
> + - ti,j721e-pcie-ep
> + then:
> + properties:
> + num-lanes:
> + minimum: 1
> + maximum: 2
> +
> required:
> - compatible
> - reg
> diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
> index b0513b197d08..8eca0d08303f 100644
> --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
> +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
> @@ -10,9 +10,6 @@ title: TI J721E PCI Host (PCIe Wrapper)
> maintainers:
> - Kishon Vijay Abraham I <[email protected]>
>
> -allOf:
> - - $ref: "cdns-pcie-host.yaml#"
> -
> properties:
> compatible:
> oneOf:
> @@ -98,6 +95,31 @@ properties:
> interrupts:
> maxItems: 1
>
> +allOf:
> + - $ref: "cdns-pcie-host.yaml#"
Same here.
> + - if:
> + properties:
> + compatible:
> + enum:
> + - ti,am64-pcie-host
> + then:
> + properties:
> + num-lanes:
const: 1
Best regards,
Krzysztof
On 24/11/2022 09:12, Matt Ranostay wrote:
> Add definition for j784s4-pci-ep + j784s4-pci-host devices along with
> schema checks for num-lanes.
>
> Signed-off-by: Matt Ranostay <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
Hi Rob,
I think your comment:
https://lore.kernel.org/linux-pci/CAL_JsqJ5cOLXhD-73esmhVwMEWGT+w3SJC14Z0jY4tQJQRA7iw@mail.gmail.com
was related to the commit log wording and not necessarily
the actual diff. Please let me know if you are happy with
this change and I shall merge the series.
Thanks,
Lorenzo
On Thu, Nov 24, 2022 at 12:12:19AM -0800, Matt Ranostay wrote:
> Add support for setting of two-bit field that allows selection of 4x lane
> PCIe which was previously limited to only 2x lanes.
>
> Signed-off-by: Matt Ranostay <[email protected]>
> Reviewed-by: Vignesh Raghavendra <[email protected]>
> ---
> drivers/pci/controller/cadence/pci-j721e.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> index 8990f58d64d5..dab3db9be6d8 100644
> --- a/drivers/pci/controller/cadence/pci-j721e.c
> +++ b/drivers/pci/controller/cadence/pci-j721e.c
> @@ -42,7 +42,6 @@ enum link_status {
> };
>
> #define J721E_MODE_RC BIT(7)
> -#define LANE_COUNT_MASK BIT(8)
> #define LANE_COUNT(n) ((n) << 8)
>
> #define GENERATION_SEL_MASK GENMASK(1, 0)
> @@ -52,6 +51,7 @@ struct j721e_pcie {
> struct clk *refclk;
> u32 mode;
> u32 num_lanes;
> + u32 max_lanes;
> void __iomem *user_cfg_base;
> void __iomem *intd_cfg_base;
> u32 linkdown_irq_regfield;
> @@ -205,11 +205,15 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
> {
> struct device *dev = pcie->cdns_pcie->dev;
> u32 lanes = pcie->num_lanes;
> + u32 mask = GENMASK(8, 8);
> u32 val = 0;
> int ret;
>
> + if (pcie->max_lanes == 4)
> + mask = GENMASK(9, 8);
> +
> val = LANE_COUNT(lanes - 1);
> - ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val);
> + ret = regmap_update_bits(syscon, offset, mask, val);
> if (ret)
> dev_err(dev, "failed to set link count\n");
>
> @@ -439,6 +443,8 @@ static int j721e_pcie_probe(struct platform_device *pdev)
> ret = of_property_read_u32(node, "num-lanes", &num_lanes);
> if (ret || num_lanes > data->max_lanes)
> num_lanes = 1;
> +
> + pcie->max_lanes = data->max_lanes;
> pcie->num_lanes = num_lanes;
>
> if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
> --
> 2.38.GIT
>