Intel PCIe is Synopsys based controller. Intel PCIe driver uses
DesignWare PCIe framework for host initialization and register
configurations.
Changes on v10:
Rebase the patches on mainline v5.4
Squashed the patch that fixes the below issue to this patch series.
WARNING: unmet direct dependencies detected for PCIE_DW_HOST
Depends on [n]: PCI [=y] && PCI_MSI_IRQ_DOMAIN [=n]
Selected by [y]:
- PCIE_INTEL_GW [=y] && PCI [=y] && OF [=y] && (X86 [=y] || COMPILE_TEST [=n])
"reportedby Randy Dunlap <[email protected]>"
Dilip Kota (3):
dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller
PCI: dwc: intel: PCIe RC controller driver
PCI: artpec6: Configure FTS with dwc helper function
.../devicetree/bindings/pci/intel-gw-pcie.yaml | 138 ++++++
drivers/pci/controller/dwc/Kconfig | 11 +
drivers/pci/controller/dwc/Makefile | 1 +
drivers/pci/controller/dwc/pcie-artpec6.c | 8 +-
drivers/pci/controller/dwc/pcie-designware.c | 57 +++
drivers/pci/controller/dwc/pcie-designware.h | 12 +
drivers/pci/controller/dwc/pcie-intel-gw.c | 545 +++++++++++++++++++++
include/uapi/linux/pci_regs.h | 1 +
8 files changed, 766 insertions(+), 7 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
create mode 100644 drivers/pci/controller/dwc/pcie-intel-gw.c
--
2.11.0
Use DesignWare helper functions to configure Fast Training
Sequence. Drop the respective code in the driver.
Signed-off-by: Dilip Kota <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Andrew Murray <[email protected]>
---
Changes on v10:
No change.
drivers/pci/controller/dwc/pcie-artpec6.c | 8 +-------
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c
index d00252bd8fae..02d93b8c7942 100644
--- a/drivers/pci/controller/dwc/pcie-artpec6.c
+++ b/drivers/pci/controller/dwc/pcie-artpec6.c
@@ -51,9 +51,6 @@ static const struct of_device_id artpec6_pcie_of_match[];
#define ACK_N_FTS_MASK GENMASK(15, 8)
#define ACK_N_FTS(x) (((x) << 8) & ACK_N_FTS_MASK)
-#define FAST_TRAINING_SEQ_MASK GENMASK(7, 0)
-#define FAST_TRAINING_SEQ(x) (((x) << 0) & FAST_TRAINING_SEQ_MASK)
-
/* ARTPEC-6 specific registers */
#define PCIECFG 0x18
#define PCIECFG_DBG_OEN BIT(24)
@@ -313,10 +310,7 @@ static void artpec6_pcie_set_nfts(struct artpec6_pcie *artpec6_pcie)
* Set the Number of Fast Training Sequences that the core
* advertises as its N_FTS during Gen2 or Gen3 link training.
*/
- val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
- val &= ~FAST_TRAINING_SEQ_MASK;
- val |= FAST_TRAINING_SEQ(180);
- dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
+ dw_pcie_link_set_n_fts(pci, 180);
}
static void artpec6_pcie_assert_core_reset(struct artpec6_pcie *artpec6_pcie)
--
2.11.0
On Fri, Dec 06, 2019 at 03:27:47PM +0800, Dilip Kota wrote:
> Intel PCIe is Synopsys based controller. Intel PCIe driver uses
> DesignWare PCIe framework for host initialization and register
> configurations.
>
> Changes on v10:
> Rebase the patches on mainline v5.4
I meant current mainline (given that the PCI PR for v5.5 is now
merged), not v5.4, patchset does not apply. Given that v5.5-rc1
is coming up, please rebase on top of v5.5-rc1 and repost it I
will try to merge it then.
Thanks,
Lorenzo
> Squashed the patch that fixes the below issue to this patch series.
>
> WARNING: unmet direct dependencies detected for PCIE_DW_HOST
> Depends on [n]: PCI [=y] && PCI_MSI_IRQ_DOMAIN [=n]
> Selected by [y]:
> - PCIE_INTEL_GW [=y] && PCI [=y] && OF [=y] && (X86 [=y] || COMPILE_TEST [=n])
> "reportedby Randy Dunlap <[email protected]>"
>
> Dilip Kota (3):
> dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller
> PCI: dwc: intel: PCIe RC controller driver
> PCI: artpec6: Configure FTS with dwc helper function
>
> .../devicetree/bindings/pci/intel-gw-pcie.yaml | 138 ++++++
> drivers/pci/controller/dwc/Kconfig | 11 +
> drivers/pci/controller/dwc/Makefile | 1 +
> drivers/pci/controller/dwc/pcie-artpec6.c | 8 +-
> drivers/pci/controller/dwc/pcie-designware.c | 57 +++
> drivers/pci/controller/dwc/pcie-designware.h | 12 +
> drivers/pci/controller/dwc/pcie-intel-gw.c | 545 +++++++++++++++++++++
> include/uapi/linux/pci_regs.h | 1 +
> 8 files changed, 766 insertions(+), 7 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
> create mode 100644 drivers/pci/controller/dwc/pcie-intel-gw.c
>
> --
> 2.11.0
>