Hi,
I am updating DT patches which were there part of DP v11 series sent by
Laurent in past [1]. Patches have been removed in v12 [2].
The series is rebased on the top of [3] which wired si5341 clock chip.
[1] http://lore.kernel.org/r/[email protected]
[2] http://lore.kernel.org/r/[email protected]
[3] http://lore.kernel.org/r/[email protected]
Thanks,
Michal
Laurent Pinchart (2):
arm64: dts: zynqmp: Add DPDMA node
arm64: dts: zynqmp: Wire up the DisplayPort subsystem
Michal Simek (1):
arm64: dts: zynqmp: Add DisplayPort subsystem
.../arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 10 ++++++
.../boot/dts/xilinx/zynqmp-zcu100-revC.dts | 31 ++++++++++++++++++
.../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 10 ++++++
.../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 11 +++++++
.../boot/dts/xilinx/zynqmp-zcu104-revC.dts | 11 +++++++
.../boot/dts/xilinx/zynqmp-zcu106-revA.dts | 11 +++++++
.../boot/dts/xilinx/zynqmp-zcu111-revA.dts | 11 +++++++
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 32 +++++++++++++++++++
8 files changed, 127 insertions(+)
--
2.30.0
From: Laurent Pinchart <[email protected]>
Enable the dpsub device and wire it up to the PS-GTR PHY lanes routed to
the DisplayPort connector.
Signed-off-by: Laurent Pinchart <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
---
Wire all the boards
---
.../boot/dts/xilinx/zynqmp-zcu100-revC.dts | 31 +++++++++++++++++++
.../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 10 ++++++
.../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 11 +++++++
.../boot/dts/xilinx/zynqmp-zcu104-revC.dts | 11 +++++++
.../boot/dts/xilinx/zynqmp-zcu106-revA.dts | 11 +++++++
.../boot/dts/xilinx/zynqmp-zcu111-revA.dts | 11 +++++++
6 files changed, 85 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
index 71ebcaadb7c8..a53598c3624b 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
@@ -15,6 +15,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
/ {
model = "ZynqMP ZCU100 RevC";
@@ -108,6 +109,18 @@ ina226 {
compatible = "iio-hwmon";
io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;
};
+
+ si5335a_0: clk26 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ si5335a_1: clk27 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
};
&dcc {
@@ -224,6 +237,13 @@ i2csw_7: i2c@7 {
};
};
+&psgtr {
+ status = "okay";
+ /* usb3, dps */
+ clocks = <&si5335a_0>, <&si5335a_1>;
+ clock-names = "ref0", "ref1";
+};
+
&rtc {
status = "okay";
};
@@ -295,3 +315,14 @@ &usb1 {
&watchdog0 {
status = "okay";
};
+
+&zynqmp_dpdma {
+ status = "okay";
+};
+
+&zynqmp_dpsub {
+ status = "okay";
+ phy-names = "dp-phy0", "dp-phy1";
+ phys = <&psgtr 1 PHY_TYPE_DP 0 1>,
+ <&psgtr 0 PHY_TYPE_DP 1 1>;
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
index 9abd10f6785a..12e8bd48dc8c 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
@@ -714,3 +714,13 @@ &usb0 {
&watchdog0 {
status = "okay";
};
+
+&zynqmp_dpdma {
+ status = "okay";
+};
+
+&zynqmp_dpsub {
+ status = "okay";
+ phy-names = "dp-phy0";
+ phys = <&psgtr 1 PHY_TYPE_DP 0 3>;
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
index 8ede619fea52..5637e1c17fdf 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
@@ -224,3 +224,14 @@ &usb0 {
&watchdog0 {
status = "okay";
};
+
+&zynqmp_dpdma {
+ status = "okay";
+};
+
+&zynqmp_dpsub {
+ status = "okay";
+ phy-names = "dp-phy0", "dp-phy1";
+ phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
+ <&psgtr 0 PHY_TYPE_DP 1 3>;
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
index 414f98f1831e..7f2e32831b05 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
@@ -280,3 +280,14 @@ &usb0 {
&watchdog0 {
status = "okay";
};
+
+&zynqmp_dpdma {
+ status = "okay";
+};
+
+&zynqmp_dpsub {
+ status = "okay";
+ phy-names = "dp-phy0", "dp-phy1";
+ phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
+ <&psgtr 0 PHY_TYPE_DP 1 3>;
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
index d60a30787022..18771e868399 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
@@ -156,6 +156,17 @@ &dcc {
status = "okay";
};
+&zynqmp_dpdma {
+ status = "okay";
+};
+
+&zynqmp_dpsub {
+ status = "okay";
+ phy-names = "dp-phy0", "dp-phy1";
+ phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
+ <&psgtr 0 PHY_TYPE_DP 1 3>;
+};
+
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
index 758de05c4a4b..d4b68f0d0098 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
@@ -584,3 +584,14 @@ &usb0 {
status = "okay";
dr_mode = "host";
};
+
+&zynqmp_dpdma {
+ status = "okay";
+};
+
+&zynqmp_dpsub {
+ status = "okay";
+ phy-names = "dp-phy0", "dp-phy1";
+ phys = <&psgtr 1 PHY_TYPE_DP 0 1>,
+ <&psgtr 0 PHY_TYPE_DP 1 1>;
+};
--
2.30.0
From: Laurent Pinchart <[email protected]>
Add a DT node for the DisplayPort DMA engine (DPDMA).
Signed-off-by: Laurent Pinchart <[email protected]>
Acked-by: Michal Simek <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
---
Changed node possition.
---
arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 4 ++++
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 10 ++++++++++
2 files changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
index 3ca7e4ee51b5..c676afc95f6d 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
@@ -227,3 +227,7 @@ &watchdog0 {
&lpd_watchdog {
clocks = <&zynqmp_clk LPD_WDT>;
};
+
+&zynqmp_dpdma {
+ clocks = <&zynqmp_clk DPDMA_REF>;
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 66d53521ec58..f12cd24adbee 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -847,5 +847,15 @@ lpd_watchdog: watchdog@ff150000 {
reg = <0x0 0xff150000 0x0 0x1000>;
timeout-sec = <10>;
};
+
+ zynqmp_dpdma: dma-controller@fd4c0000 {
+ compatible = "xlnx,zynqmp-dpdma";
+ status = "disabled";
+ reg = <0x0 0xfd4c0000 0x0 0x1000>;
+ interrupts = <0 122 4>;
+ interrupt-parent = <&gic>;
+ clock-names = "axi_clk";
+ #dma-cells = <1>;
+ };
};
};
--
2.30.0
Add a DT node for the DisplayPort subsystem, a hard IP present in the
Zynq Ultrascale+ MPSoC.
Signed-off-by: Laurent Pinchart <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
---
Change node position and label.
---
.../arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 6 +++++
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 22 +++++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
index c676afc95f6d..cf5295224750 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
@@ -231,3 +231,9 @@ &lpd_watchdog {
&zynqmp_dpdma {
clocks = <&zynqmp_clk DPDMA_REF>;
};
+
+&zynqmp_dpsub {
+ clocks = <&zynqmp_clk TOPSW_LSBUS>,
+ <&zynqmp_clk DP_AUDIO_REF>,
+ <&zynqmp_clk DP_VIDEO_REF>;
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index f12cd24adbee..a3b391d18787 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -12,6 +12,7 @@
* the License, or (at your option) any later version.
*/
+#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
#include <dt-bindings/power/xlnx-zynqmp-power.h>
#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
@@ -857,5 +858,26 @@ zynqmp_dpdma: dma-controller@fd4c0000 {
clock-names = "axi_clk";
#dma-cells = <1>;
};
+
+ zynqmp_dpsub: display@fd4a0000 {
+ compatible = "xlnx,zynqmp-dpsub-1.7";
+ status = "disabled";
+ reg = <0x0 0xfd4a0000 0x0 0x1000>,
+ <0x0 0xfd4aa000 0x0 0x1000>,
+ <0x0 0xfd4ab000 0x0 0x1000>,
+ <0x0 0xfd4ac000 0x0 0x1000>;
+ reg-names = "dp", "blend", "av_buf", "aud";
+ interrupts = <0 119 4>;
+ interrupt-parent = <&gic>;
+ clock-names = "dp_apb_clk", "dp_aud_clk",
+ "dp_vtc_pixel_clk_in";
+ power-domains = <&zynqmp_firmware PD_DP>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_DP>;
+ dma-names = "vid0", "vid1", "vid2", "gfx0";
+ dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>,
+ <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,
+ <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,
+ <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;
+ };
};
};
--
2.30.0
Hi Michal,
Thank you for the patch.
On Thu, Jan 21, 2021 at 01:36:07PM +0100, Michal Simek wrote:
> From: Laurent Pinchart <[email protected]>
>
> Enable the dpsub device and wire it up to the PS-GTR PHY lanes routed to
> the DisplayPort connector.
>
> Signed-off-by: Laurent Pinchart <[email protected]>
> Signed-off-by: Michal Simek <[email protected]>
> ---
>
> Wire all the boards
>
> ---
> .../boot/dts/xilinx/zynqmp-zcu100-revC.dts | 31 +++++++++++++++++++
> .../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 10 ++++++
> .../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 11 +++++++
> .../boot/dts/xilinx/zynqmp-zcu104-revC.dts | 11 +++++++
> .../boot/dts/xilinx/zynqmp-zcu106-revA.dts | 11 +++++++
> .../boot/dts/xilinx/zynqmp-zcu111-revA.dts | 11 +++++++
> 6 files changed, 85 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
> index 71ebcaadb7c8..a53598c3624b 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
> @@ -15,6 +15,7 @@
> #include <dt-bindings/input/input.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/phy/phy.h>
>
> / {
> model = "ZynqMP ZCU100 RevC";
> @@ -108,6 +109,18 @@ ina226 {
> compatible = "iio-hwmon";
> io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;
> };
> +
> + si5335a_0: clk26 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <26000000>;
> + };
> +
> + si5335a_1: clk27 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <27000000>;
> + };
This is fine as a workaround for now, but I'm still wondering how we'll
solve this properly. We can declare the SI5335A in DT without wiring the
output that provides the clock to the PS, otherwise it will be disabled
as part of the boot process.
> };
>
> &dcc {
> @@ -224,6 +237,13 @@ i2csw_7: i2c@7 {
> };
> };
>
> +&psgtr {
> + status = "okay";
> + /* usb3, dps */
> + clocks = <&si5335a_0>, <&si5335a_1>;
> + clock-names = "ref0", "ref1";
> +};
> +
> &rtc {
> status = "okay";
> };
> @@ -295,3 +315,14 @@ &usb1 {
> &watchdog0 {
> status = "okay";
> };
> +
> +&zynqmp_dpdma {
> + status = "okay";
> +};
> +
> +&zynqmp_dpsub {
> + status = "okay";
> + phy-names = "dp-phy0", "dp-phy1";
> + phys = <&psgtr 1 PHY_TYPE_DP 0 1>,
> + <&psgtr 0 PHY_TYPE_DP 1 1>;
> +};
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> index 9abd10f6785a..12e8bd48dc8c 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> @@ -714,3 +714,13 @@ &usb0 {
> &watchdog0 {
> status = "okay";
> };
> +
> +&zynqmp_dpdma {
> + status = "okay";
> +};
> +
> +&zynqmp_dpsub {
> + status = "okay";
> + phy-names = "dp-phy0";
> + phys = <&psgtr 1 PHY_TYPE_DP 0 3>;
> +};
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
> index 8ede619fea52..5637e1c17fdf 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
> @@ -224,3 +224,14 @@ &usb0 {
> &watchdog0 {
> status = "okay";
> };
> +
> +&zynqmp_dpdma {
> + status = "okay";
> +};
> +
> +&zynqmp_dpsub {
> + status = "okay";
> + phy-names = "dp-phy0", "dp-phy1";
> + phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
> + <&psgtr 0 PHY_TYPE_DP 1 3>;
> +};
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
> index 414f98f1831e..7f2e32831b05 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
> @@ -280,3 +280,14 @@ &usb0 {
> &watchdog0 {
> status = "okay";
> };
> +
> +&zynqmp_dpdma {
> + status = "okay";
> +};
> +
> +&zynqmp_dpsub {
> + status = "okay";
> + phy-names = "dp-phy0", "dp-phy1";
> + phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
> + <&psgtr 0 PHY_TYPE_DP 1 3>;
> +};
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
> index d60a30787022..18771e868399 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
> @@ -156,6 +156,17 @@ &dcc {
> status = "okay";
> };
>
> +&zynqmp_dpdma {
> + status = "okay";
> +};
> +
> +&zynqmp_dpsub {
> + status = "okay";
> + phy-names = "dp-phy0", "dp-phy1";
> + phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
> + <&psgtr 0 PHY_TYPE_DP 1 3>;
> +};
> +
> /* fpd_dma clk 667MHz, lpd_dma 500MHz */
> &fpd_dma_chan1 {
> status = "okay";
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
> index 758de05c4a4b..d4b68f0d0098 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
> @@ -584,3 +584,14 @@ &usb0 {
> status = "okay";
> dr_mode = "host";
> };
> +
> +&zynqmp_dpdma {
> + status = "okay";
> +};
> +
> +&zynqmp_dpsub {
> + status = "okay";
> + phy-names = "dp-phy0", "dp-phy1";
> + phys = <&psgtr 1 PHY_TYPE_DP 0 1>,
> + <&psgtr 0 PHY_TYPE_DP 1 1>;
> +};
--
Regards,
Laurent Pinchart
Hi Laurent,
On 1/21/21 11:37 PM, Laurent Pinchart wrote:
> Hi Michal,
>
> Thank you for the patch.
>
> On Thu, Jan 21, 2021 at 01:36:07PM +0100, Michal Simek wrote:
>> From: Laurent Pinchart <[email protected]>
>>
>> Enable the dpsub device and wire it up to the PS-GTR PHY lanes routed to
>> the DisplayPort connector.
>>
>> Signed-off-by: Laurent Pinchart <[email protected]>
>> Signed-off-by: Michal Simek <[email protected]>
>> ---
>>
>> Wire all the boards
>>
>> ---
>> .../boot/dts/xilinx/zynqmp-zcu100-revC.dts | 31 +++++++++++++++++++
>> .../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 10 ++++++
>> .../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 11 +++++++
>> .../boot/dts/xilinx/zynqmp-zcu104-revC.dts | 11 +++++++
>> .../boot/dts/xilinx/zynqmp-zcu106-revA.dts | 11 +++++++
>> .../boot/dts/xilinx/zynqmp-zcu111-revA.dts | 11 +++++++
>> 6 files changed, 85 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>> index 71ebcaadb7c8..a53598c3624b 100644
>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>> @@ -15,6 +15,7 @@
>> #include <dt-bindings/input/input.h>
>> #include <dt-bindings/interrupt-controller/irq.h>
>> #include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/phy/phy.h>
>>
>> / {
>> model = "ZynqMP ZCU100 RevC";
>> @@ -108,6 +109,18 @@ ina226 {
>> compatible = "iio-hwmon";
>> io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;
>> };
>> +
>> + si5335a_0: clk26 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <26000000>;
>> + };
>> +
>> + si5335a_1: clk27 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <27000000>;
>> + };
>
> This is fine as a workaround for now, but I'm still wondering how we'll
> solve this properly. We can declare the SI5335A in DT without wiring the
> output that provides the clock to the PS, otherwise it will be disabled
> as part of the boot process.
All these clock chips are preprogrammed to certain rate and enabled by
default. It means there doesn't need to be any SW handling to enable it.
When driver for these clock chips comes we can change this that's why I
used labels which are saying which output it is.
Thanks,
Michal
Hi Michal,
On Fri, Jan 22, 2021 at 08:19:15AM +0100, Michal Simek wrote:
> On 1/21/21 11:37 PM, Laurent Pinchart wrote:
> > On Thu, Jan 21, 2021 at 01:36:07PM +0100, Michal Simek wrote:
> >> From: Laurent Pinchart <[email protected]>
> >>
> >> Enable the dpsub device and wire it up to the PS-GTR PHY lanes routed to
> >> the DisplayPort connector.
> >>
> >> Signed-off-by: Laurent Pinchart <[email protected]>
> >> Signed-off-by: Michal Simek <[email protected]>
> >> ---
> >>
> >> Wire all the boards
> >>
> >> ---
> >> .../boot/dts/xilinx/zynqmp-zcu100-revC.dts | 31 +++++++++++++++++++
> >> .../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 10 ++++++
> >> .../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 11 +++++++
> >> .../boot/dts/xilinx/zynqmp-zcu104-revC.dts | 11 +++++++
> >> .../boot/dts/xilinx/zynqmp-zcu106-revA.dts | 11 +++++++
> >> .../boot/dts/xilinx/zynqmp-zcu111-revA.dts | 11 +++++++
> >> 6 files changed, 85 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
> >> index 71ebcaadb7c8..a53598c3624b 100644
> >> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
> >> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
> >> @@ -15,6 +15,7 @@
> >> #include <dt-bindings/input/input.h>
> >> #include <dt-bindings/interrupt-controller/irq.h>
> >> #include <dt-bindings/gpio/gpio.h>
> >> +#include <dt-bindings/phy/phy.h>
> >>
> >> / {
> >> model = "ZynqMP ZCU100 RevC";
> >> @@ -108,6 +109,18 @@ ina226 {
> >> compatible = "iio-hwmon";
> >> io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;
> >> };
> >> +
> >> + si5335a_0: clk26 {
> >> + compatible = "fixed-clock";
> >> + #clock-cells = <0>;
> >> + clock-frequency = <26000000>;
> >> + };
> >> +
> >> + si5335a_1: clk27 {
> >> + compatible = "fixed-clock";
> >> + #clock-cells = <0>;
> >> + clock-frequency = <27000000>;
> >> + };
> >
> > This is fine as a workaround for now, but I'm still wondering how we'll
> > solve this properly. We can declare the SI5335A in DT without wiring the
> > output that provides the clock to the PS, otherwise it will be disabled
> > as part of the boot process.
>
> All these clock chips are preprogrammed to certain rate and enabled by
> default. It means there doesn't need to be any SW handling to enable it.
> When driver for these clock chips comes we can change this that's why I
> used labels which are saying which output it is.
Unless I'm mistaken, on the ZCU106 board, the chip is an SI5341B, which
has a driver already. I tried to declare it in DT, but the PS_REF_CLK
then got disabled at the end of boot, and the system wasn't happy about
it :-)
--
Regards,
Laurent Pinchart
Hi Laurent,
On 1/22/21 8:46 AM, Laurent Pinchart wrote:
> Hi Michal,
>
> On Fri, Jan 22, 2021 at 08:19:15AM +0100, Michal Simek wrote:
>> On 1/21/21 11:37 PM, Laurent Pinchart wrote:
>>> On Thu, Jan 21, 2021 at 01:36:07PM +0100, Michal Simek wrote:
>>>> From: Laurent Pinchart <[email protected]>
>>>>
>>>> Enable the dpsub device and wire it up to the PS-GTR PHY lanes routed to
>>>> the DisplayPort connector.
>>>>
>>>> Signed-off-by: Laurent Pinchart <[email protected]>
>>>> Signed-off-by: Michal Simek <[email protected]>
>>>> ---
>>>>
>>>> Wire all the boards
>>>>
>>>> ---
>>>> .../boot/dts/xilinx/zynqmp-zcu100-revC.dts | 31 +++++++++++++++++++
>>>> .../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 10 ++++++
>>>> .../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 11 +++++++
>>>> .../boot/dts/xilinx/zynqmp-zcu104-revC.dts | 11 +++++++
>>>> .../boot/dts/xilinx/zynqmp-zcu106-revA.dts | 11 +++++++
>>>> .../boot/dts/xilinx/zynqmp-zcu111-revA.dts | 11 +++++++
>>>> 6 files changed, 85 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>>>> index 71ebcaadb7c8..a53598c3624b 100644
>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>>>> @@ -15,6 +15,7 @@
>>>> #include <dt-bindings/input/input.h>
>>>> #include <dt-bindings/interrupt-controller/irq.h>
>>>> #include <dt-bindings/gpio/gpio.h>
>>>> +#include <dt-bindings/phy/phy.h>
>>>>
>>>> / {
>>>> model = "ZynqMP ZCU100 RevC";
>>>> @@ -108,6 +109,18 @@ ina226 {
>>>> compatible = "iio-hwmon";
>>>> io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;
>>>> };
>>>> +
>>>> + si5335a_0: clk26 {
>>>> + compatible = "fixed-clock";
>>>> + #clock-cells = <0>;
>>>> + clock-frequency = <26000000>;
>>>> + };
>>>> +
>>>> + si5335a_1: clk27 {
>>>> + compatible = "fixed-clock";
>>>> + #clock-cells = <0>;
>>>> + clock-frequency = <27000000>;
>>>> + };
>>>
>>> This is fine as a workaround for now, but I'm still wondering how we'll
>>> solve this properly. We can declare the SI5335A in DT without wiring the
>>> output that provides the clock to the PS, otherwise it will be disabled
>>> as part of the boot process.
>>
>> All these clock chips are preprogrammed to certain rate and enabled by
>> default. It means there doesn't need to be any SW handling to enable it.
>> When driver for these clock chips comes we can change this that's why I
>> used labels which are saying which output it is.
>
> Unless I'm mistaken, on the ZCU106 board, the chip is an SI5341B, which
> has a driver already. I tried to declare it in DT, but the PS_REF_CLK
> then got disabled at the end of boot, and the system wasn't happy about
> it :-)
In series before si5341 chips are enabled as the part of sata
enablement. Maybe you missed always-on parameter.
si5341_9: out@9 {
/* refclk9 used for PS_REF_CLK 33.3 MHz */
reg = <9>;
always-on;
};
I just retest it and I can't see any issue. Sata
I see DP driver probed but I can't see anything on 4k monitor but maybe
there should be something to setup (I use fs from 2015).
thanks,
Michal
Hi,
On 1/21/21 1:36 PM, Michal Simek wrote:
> Hi,
>
> I am updating DT patches which were there part of DP v11 series sent by
> Laurent in past [1]. Patches have been removed in v12 [2].
> The series is rebased on the top of [3] which wired si5341 clock chip.
>
> [1] http://lore.kernel.org/r/[email protected]
> [2] http://lore.kernel.org/r/[email protected]
> [3] http://lore.kernel.org/r/[email protected]
>
> Thanks,
> Michal
>
>
> Laurent Pinchart (2):
> arm64: dts: zynqmp: Add DPDMA node
> arm64: dts: zynqmp: Wire up the DisplayPort subsystem
>
> Michal Simek (1):
> arm64: dts: zynqmp: Add DisplayPort subsystem
>
> .../arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 10 ++++++
> .../boot/dts/xilinx/zynqmp-zcu100-revC.dts | 31 ++++++++++++++++++
> .../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 10 ++++++
> .../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 11 +++++++
> .../boot/dts/xilinx/zynqmp-zcu104-revC.dts | 11 +++++++
> .../boot/dts/xilinx/zynqmp-zcu106-revA.dts | 11 +++++++
> .../boot/dts/xilinx/zynqmp-zcu111-revA.dts | 11 +++++++
> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 32 +++++++++++++++++++
> 8 files changed, 127 insertions(+)
>
Applied all.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: http://www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs