LinuxLists.cc - [PATCH v12 0/3] mfd: Add Renesas R-Car Gen3 RPC-IF MFD & SPI driver

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Subject: [PATCH v12 3/3] dt-bindings: mfd: Document Renesas R-Car Gen3 RPC-IF MFD bindings

Document the bindings used by the Renesas R-Car Gen3 RPC-IF MFD.

Signed-off-by: Mason Yang <[email protected]>
---
.../devicetree/bindings/mfd/mfd-renesas-rpc.txt | 40 ++++++++++++++++++++++
1 file changed, 40 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt

diff --git a/Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt b/Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt
new file mode 100644
index 0000000..668b822
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt
@@ -0,0 +1,40 @@
+Renesas R-Car Gen3 RPC-IF MFD Device Tree Bindings
+--------------------------------------------------
+
+Required properties:
+- compatible: should be an SoC-specific compatible value, followed by
+ "renesas,rcar-gen3-rpc" as a fallback.
+ supported SoC-specific values are:
+ "renesas,r8a77995-rpc" (R-Car D3)
+- reg: should contain three register areas:
+ first for the base address of RPC-IF registers,
+ second for the direct mapping read mode and
+ third for the write buffer area.
+- reg-names: should contain "regs", "dirmap" and "wbuf"
+- clocks: should contain 1 entries for the module's clock
+- clock-names: should contain "rpc"
+- #address-cells: should be 1
+- #size-cells: should be 0
+
+Example:
+
+ rpc: rpc-if@ee200000 {
+ compatible = "renesas,r8a77995-rpc", "renesas,rcar-gen3-rpc";
+ reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x4000000>,
+ <0 0xee208000 0 0x100>;
+ reg-names = "regs", "dirmap", "wbuf";
+ clocks = <&cpg CPG_MOD 917>;
+ clock-names = "rpc";
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 917>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ };
+ };
--
1.9.1

2019-04-24 07:42:26

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Subject: [PATCH v12 2/3] spi: Add Renesas R-Car Gen3 RPC-IF SPI controller driver

Add a driver for Renesas R-Car Gen3 RPC-IF SPI controller.

Signed-off-by: Mason Yang <[email protected]>
Signed-off-by: Sergei Shtylyov <[email protected]>
---
drivers/spi/Kconfig | 6 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-renesas-rpc.c | 571 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 578 insertions(+)
create mode 100644 drivers/spi/spi-renesas-rpc.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index f761655..1f52bcf 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -564,6 +564,12 @@ config SPI_RSPI
help
SPI driver for Renesas RSPI and QSPI blocks.

+config SPI_RENESAS_RPC
+ tristate "Renesas R-Car Gen3 RPC-IF controller"
+ depends on ARCH_RENESAS || COMPILE_TEST
+ help
+ SPI driver for Renesas R-Car Gen3 RPC-IF.
+
config SPI_QCOM_QSPI
tristate "QTI QSPI controller"
depends on ARCH_QCOM
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d8fc03c..b3a3deb 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -86,6 +86,7 @@ obj-$(CONFIG_SPI_QUP) += spi-qup.o
obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o
obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o
obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
+obj-$(CONFIG_SPI_RENESAS_RPC) += spi-renesas-rpc.o
obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
spi-s3c24xx-hw-y := spi-s3c24xx.o
spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o
diff --git a/drivers/spi/spi-renesas-rpc.c b/drivers/spi/spi-renesas-rpc.c
new file mode 100644
index 0000000..c2202d4
--- /dev/null
+++ b/drivers/spi/spi-renesas-rpc.c
@@ -0,0 +1,571 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2018 ~ 2019 Renesas Solutions Corp.
+// Copyright (C) 2019 Macronix International Co., Ltd.
+//
+// R-Car Gen3 RPC-IF SPI/QSPI/Octa driver
+//
+// Author:
+// Mason Yang <[email protected]>
+//
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/log2.h>
+#include <linux/iopoll.h>
+#include <linux/mfd/renesas-rpc.h>
+#include <linux/module.h>
+#include <linux/mtd/mtd.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi-mem.h>
+
+#include <asm/unaligned.h>
+
+struct rpc_spi {
+ struct rpc_mfd *mfd;
+ u32 cur_speed_hz;
+ u32 cmd;
+ u32 addr;
+ u32 dummy;
+ u32 smcr;
+ u32 smenr;
+ u32 xferlen;
+ u32 totalxferlen;
+ enum spi_mem_data_dir xfer_dir;
+};
+
+static int rpc_spi_set_freq(struct rpc_spi *rpc, unsigned long freq)
+{
+ int ret;
+
+ if (rpc->cur_speed_hz == freq)
+ return 0;
+
+ ret = clk_set_rate(rpc->mfd->clk_rpc, freq);
+ if (ret)
+ return ret;
+
+ rpc->cur_speed_hz = freq;
+ return ret;
+}
+
+static void rpc_spi_hw_init(struct rpc_spi *rpc)
+{
+ //
+ // NOTE: The 0x260 are undocumented bits, but they must be set.
+ // RPC_PHYCNT_STRTIM is strobe timing adjustment bit,
+ // 0x0 : the delay is biggest,
+ // 0x1 : the delay is 2nd biggest,
+ // On H3 ES1.x, the value should be 0, while on others,
+ // the value should be 6.
+ //
+ regmap_write(rpc->mfd->regmap, RPC_PHYCNT, RPC_PHYCNT_CAL |
+ RPC_PHYCNT_STRTIM(6) | 0x260);
+
+ //
+ // NOTE: The 0x1511144 are undocumented bits, but they must be set
+ // for RPC_PHYOFFSET1.
+ // The 0x31 are undocumented bits, but they must be set
+ // for RPC_PHYOFFSET2.
+ //
+ regmap_write(rpc->mfd->regmap, RPC_PHYOFFSET1,
+ RPC_PHYOFFSET1_DDRTMG(3) | 0x1511144);
+ regmap_write(rpc->mfd->regmap, RPC_PHYOFFSET2, 0x31 |
+ RPC_PHYOFFSET2_OCTTMG(4));
+ regmap_write(rpc->mfd->regmap, RPC_SSLDR, RPC_SSLDR_SPNDL(7) |
+ RPC_SSLDR_SLNDL(7) | RPC_SSLDR_SCKDL(7));
+ regmap_write(rpc->mfd->regmap, RPC_CMNCR, RPC_CMNCR_MD |
+ RPC_CMNCR_SFDE | RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ |
+ RPC_CMNCR_BSZ(0));
+}
+
+static int wait_msg_xfer_end(struct rpc_spi *rpc)
+{
+ u32 sts;
+
+ return regmap_read_poll_timeout(rpc->mfd->regmap, RPC_CMNSR, sts,
+ sts & RPC_CMNSR_TEND, 0, USEC_PER_SEC);
+}
+
+static u8 rpc_bits_set(u32 nbytes)
+{
+ nbytes = clamp(nbytes, 1U, 4U);
+
+ return GENMASK(3, 4 - nbytes);
+}
+
+static int rpc_spi_io_xfer(struct rpc_spi *rpc,
+ const void *tx_buf, void *rx_buf)
+{
+ u32 smenr, smcr, data, pos = 0;
+ int ret;
+
+ regmap_update_bits(rpc->mfd->regmap, RPC_CMNCR, RPC_CMNCR_MD,
+ RPC_CMNCR_MD);
+ regmap_write(rpc->mfd->regmap, RPC_SMDRENR, 0);
+ regmap_write(rpc->mfd->regmap, RPC_SMCMR, rpc->cmd);
+ regmap_write(rpc->mfd->regmap, RPC_SMDMCR, rpc->dummy);
+ regmap_write(rpc->mfd->regmap, RPC_SMADR, rpc->addr);
+ smenr = rpc->smenr;
+
+ if (tx_buf) {
+ while (pos < rpc->xferlen) {
+ u32 nbytes = rpc->xferlen - pos;
+
+ regmap_write(rpc->mfd->regmap, RPC_SMWDR0,
+ get_unaligned((u32 *)(tx_buf + pos)));
+
+ smcr = rpc->smcr | RPC_SMCR_SPIE;
+
+ if (nbytes > 4) {
+ nbytes = 4;
+ smcr |= RPC_SMCR_SSLKP;
+ }
+
+ regmap_write(rpc->mfd->regmap, RPC_SMENR, smenr);
+ regmap_write(rpc->mfd->regmap, RPC_SMCR, smcr);
+ ret = wait_msg_xfer_end(rpc);
+ if (ret)
+ goto err_out;
+
+ pos += nbytes;
+ smenr = rpc->smenr & ~RPC_SMENR_CDE &
+ ~RPC_SMENR_ADE(0xf);
+ }
+ } else if (rx_buf) {
+ //
+ // RPC-IF spoils the data for the commands without an address
+ // phase (like RDID) in the manual mode, so we'll have to work
+ // around this issue by using the external address space read
+ // mode instead.
+ //
+ if (!(smenr & RPC_SMENR_ADE(0xf)) && rpc->mfd->dirmap) {
+ regmap_update_bits(rpc->mfd->regmap, RPC_CMNCR,
+ RPC_CMNCR_MD, 0);
+ regmap_write(rpc->mfd->regmap, RPC_DRCR,
+ RPC_DRCR_RBURST(32) | RPC_DRCR_RBE);
+ regmap_write(rpc->mfd->regmap, RPC_DREAR,
+ RPC_DREAR_EAC(1));
+ regmap_write(rpc->mfd->regmap, RPC_DRCMR, rpc->cmd);
+ regmap_write(rpc->mfd->regmap, RPC_DRDMCR, rpc->dummy);
+ regmap_write(rpc->mfd->regmap, RPC_DROPR, 0);
+ regmap_write(rpc->mfd->regmap, RPC_DRENR, smenr);
+ memcpy_fromio(rx_buf, rpc->mfd->dirmap, rpc->xferlen);
+ regmap_write(rpc->mfd->regmap, RPC_DRCR, RPC_DRCR_RCF);
+ } else {
+ while (pos < rpc->xferlen) {
+ u32 nbytes = rpc->xferlen - pos;
+
+ if (nbytes > 4)
+ nbytes = 4;
+
+ regmap_write(rpc->mfd->regmap, RPC_SMENR,
+ smenr);
+ regmap_write(rpc->mfd->regmap, RPC_SMCR,
+ rpc->smcr | RPC_SMCR_SPIE);
+ ret = wait_msg_xfer_end(rpc);
+ if (ret)
+ goto err_out;
+
+ regmap_read(rpc->mfd->regmap, RPC_SMRDR0,
+ &data);
+ memcpy(rx_buf + pos, &data, nbytes);
+ pos += nbytes;
+
+ regmap_write(rpc->mfd->regmap, RPC_SMADR,
+ rpc->addr + pos);
+ }
+ }
+ } else {
+ regmap_write(rpc->mfd->regmap, RPC_SMENR, rpc->smenr);
+ regmap_write(rpc->mfd->regmap, RPC_SMCR,
+ rpc->smcr | RPC_SMCR_SPIE);
+ ret = wait_msg_xfer_end(rpc);
+ if (ret)
+ goto err_out;
+ }
+
+ return 0;
+
+err_out:
+ return reset_control_reset(rpc->mfd->rstc);
+}
+
+static void rpc_spi_mem_set_prep_op_cfg(struct spi_device *spi,
+ const struct spi_mem_op *op,
+ u64 *offs, size_t *len)
+{
+ struct rpc_spi *rpc = spi_controller_get_devdata(spi->controller);
+
+ rpc->cmd = RPC_SMCMR_CMD(op->cmd.opcode);
+ rpc->smenr = RPC_SMENR_CDE |
+ RPC_SMENR_CDB(ilog2(op->cmd.buswidth));
+ rpc->totalxferlen = 1;
+ rpc->xfer_dir = SPI_MEM_NO_DATA;
+ rpc->xferlen = 0;
+ rpc->addr = 0;
+
+ if (op->addr.nbytes) {
+ rpc->smenr |= RPC_SMENR_ADB(ilog2(op->addr.buswidth));
+ if (op->addr.nbytes == 4)
+ rpc->smenr |= RPC_SMENR_ADE(0xf);
+ else
+ rpc->smenr |= RPC_SMENR_ADE(0x7);
+
+ if (offs && len)
+ rpc->addr = *offs;
+ else
+ rpc->addr = op->addr.val;
+ rpc->totalxferlen += op->addr.nbytes;
+ }
+
+ if (op->dummy.nbytes) {
+ rpc->smenr |= RPC_SMENR_DME;
+ rpc->dummy = RPC_SMDMCR_DMCYC(op->dummy.nbytes * 8 /
+ op->dummy.buswidth);
+ rpc->totalxferlen += op->dummy.nbytes;
+ }
+
+ if (op->data.nbytes || (offs && len)) {
+ switch (op->data.dir) {
+ case SPI_MEM_DATA_IN:
+ rpc->smcr = RPC_SMCR_SPIRE;
+ rpc->xfer_dir = SPI_MEM_DATA_IN;
+ break;
+ case SPI_MEM_DATA_OUT:
+ rpc->smcr = RPC_SMCR_SPIWE;
+ rpc->xfer_dir = SPI_MEM_DATA_OUT;
+ break;
+ default:
+ break;
+ }
+
+ if (offs && len) {
+ rpc->smenr |= RPC_SMENR_SPIDE(rpc_bits_set(*len)) |
+ RPC_SMENR_SPIDB(ilog2(op->data.buswidth));
+ rpc->xferlen = *len;
+ rpc->totalxferlen += *len;
+ } else {
+ rpc->smenr |=
+ RPC_SMENR_SPIDE(rpc_bits_set(op->data.nbytes)) |
+ RPC_SMENR_SPIDB(ilog2(op->data.buswidth));
+ rpc->xferlen = op->data.nbytes;
+ rpc->totalxferlen += op->data.nbytes;
+ }
+ }
+}
+
+static bool rpc_spi_mem_supports_op(struct spi_mem *mem,
+ const struct spi_mem_op *op)
+{
+ if (op->data.buswidth > 4 || op->addr.buswidth > 4 ||
+ op->dummy.buswidth > 4 || op->cmd.buswidth > 4 ||
+ op->addr.nbytes > 4)
+ return false;
+
+ return true;
+}
+
+static ssize_t rpc_spi_mem_dirmap_read(struct spi_mem_dirmap_desc *desc,
+ u64 offs, size_t len, void *buf)
+{
+ struct rpc_spi *rpc =
+ spi_controller_get_devdata(desc->mem->spi->controller);
+ loff_t from = offs & (RPC_DIRMAP_SIZE - 1);
+ size_t size = RPC_DIRMAP_SIZE - from;
+ int ret;
+
+ if (offs + desc->info.offset + len > U32_MAX)
+ return -EINVAL;
+
+ if (len > size)
+ len = size;
+
+ ret = rpc_spi_set_freq(rpc, desc->mem->spi->max_speed_hz);
+ if (ret)
+ return ret;
+
+ rpc_spi_mem_set_prep_op_cfg(desc->mem->spi,
+ &desc->info.op_tmpl, &offs, &len);
+
+ regmap_update_bits(rpc->mfd->regmap, RPC_CMNCR, RPC_CMNCR_MD, 0);
+ regmap_write(rpc->mfd->regmap, RPC_DRCR, RPC_DRCR_RBURST(32) |
+ RPC_DRCR_RBE);
+
+ regmap_write(rpc->mfd->regmap, RPC_DRCMR, rpc->cmd);
+ regmap_write(rpc->mfd->regmap, RPC_DREAR,
+ RPC_DREAR_EAV(offs >> 25) | RPC_DREAR_EAC(1));
+ regmap_write(rpc->mfd->regmap, RPC_DROPR, 0);
+ regmap_write(rpc->mfd->regmap, RPC_DRENR, rpc->smenr);
+ regmap_write(rpc->mfd->regmap, RPC_DRDMCR, rpc->dummy);
+ regmap_write(rpc->mfd->regmap, RPC_DRDRENR, 0);
+
+ memcpy_fromio(buf, rpc->mfd->dirmap + desc->info.offset + from, len);
+
+ return len;
+}
+
+static int rpc_spi_mem_dirmap_create(struct spi_mem_dirmap_desc *desc)
+{
+ struct rpc_spi *rpc =
+ spi_controller_get_devdata(desc->mem->spi->controller);
+
+ if (desc->info.offset + desc->info.length > U32_MAX)
+ return -ENOTSUPP;
+
+ if (!rpc_spi_mem_supports_op(desc->mem, &desc->info.op_tmpl))
+ return -ENOTSUPP;
+
+ if (!rpc->mfd->dirmap &&
+ desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN)
+ return -ENOTSUPP;
+
+ if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT)
+ return -ENOTSUPP;
+
+ return 0;
+}
+
+static int rpc_spi_mem_exec_op(struct spi_mem *mem,
+ const struct spi_mem_op *op)
+{
+ struct rpc_spi *rpc = spi_controller_get_devdata(mem->spi->controller);
+ int ret;
+
+ ret = rpc_spi_set_freq(rpc, mem->spi->max_speed_hz);
+ if (ret)
+ return ret;
+
+ rpc_spi_mem_set_prep_op_cfg(mem->spi, op, NULL, NULL);
+
+ ret = rpc_spi_io_xfer(rpc,
+ op->data.dir == SPI_MEM_DATA_OUT ?
+ op->data.buf.out : NULL,
+ op->data.dir == SPI_MEM_DATA_IN ?
+ op->data.buf.in : NULL);
+
+ return ret;
+}
+
+static const struct spi_controller_mem_ops rpc_spi_mem_ops = {
+ .supports_op = rpc_spi_mem_supports_op,
+ .exec_op = rpc_spi_mem_exec_op,
+ .dirmap_create = rpc_spi_mem_dirmap_create,
+ .dirmap_read = rpc_spi_mem_dirmap_read,
+};
+
+static void rpc_spi_transfer_setup(struct rpc_spi *rpc,
+ struct spi_message *msg)
+{
+ struct spi_transfer *t, xfer[4] = { };
+ u32 i, xfercnt, xferpos = 0;
+
+ rpc->totalxferlen = 0;
+ rpc->xfer_dir = SPI_MEM_NO_DATA;
+
+ list_for_each_entry(t, &msg->transfers, transfer_list) {
+ if (t->tx_buf) {
+ xfer[xferpos].tx_buf = t->tx_buf;
+ xfer[xferpos].tx_nbits = t->tx_nbits;
+ }
+
+ if (t->rx_buf) {
+ xfer[xferpos].rx_buf = t->rx_buf;
+ xfer[xferpos].rx_nbits = t->rx_nbits;
+ }
+
+ if (t->len) {
+ xfer[xferpos++].len = t->len;
+ rpc->totalxferlen += t->len;
+ }
+
+ if (list_is_last(&t->transfer_list, &msg->transfers)) {
+ if (xferpos > 1) {
+ if (t->rx_buf) {
+ rpc->xfer_dir = SPI_MEM_DATA_IN;
+ rpc->smcr = RPC_SMCR_SPIRE;
+ } else if (t->tx_buf) {
+ rpc->xfer_dir = SPI_MEM_DATA_OUT;
+ rpc->smcr = RPC_SMCR_SPIWE;
+ }
+ }
+ }
+ }
+
+ xfercnt = xferpos;
+ rpc->xferlen = xfer[--xferpos].len;
+ rpc->cmd = RPC_SMCMR_CMD(((u8 *)xfer[0].tx_buf)[0]);
+ rpc->smenr = RPC_SMENR_CDE |
+ RPC_SMENR_CDB(ilog2((unsigned int)xfer[0].tx_nbits));
+ rpc->addr = 0;
+
+ if (xfercnt > 2 && xfer[1].len && xfer[1].tx_buf) {
+ rpc->smenr |=
+ RPC_SMENR_ADB(ilog2((unsigned int)xfer[1].tx_nbits));
+
+ for (i = 0; i < xfer[1].len; i++)
+ rpc->addr |= ((u8 *)xfer[1].tx_buf)[i] <<
+ (8 * (xfer[1].len - i - 1));
+
+ if (xfer[1].len == 4)
+ rpc->smenr |= RPC_SMENR_ADE(0xf);
+ else
+ rpc->smenr |= RPC_SMENR_ADE(0x7);
+ }
+
+ if (xfercnt > 3 && xfer[2].len && xfer[2].tx_buf) {
+ rpc->smenr |= RPC_SMENR_DME;
+ rpc->dummy = RPC_SMDMCR_DMCYC(xfer[2].len * 8 /
+ xfer[2].tx_nbits);
+ }
+
+ for (i = xfercnt - 1; i < xfercnt && xfercnt > 1; i++) {
+ if (xfer[i].rx_buf) {
+ rpc->smenr |=
+ RPC_SMENR_SPIDE(rpc_bits_set(xfer[i].len)) |
+ RPC_SMENR_SPIDB(ilog2
+ ((unsigned int)xfer[i].rx_nbits));
+ } else if (xfer[i].tx_buf) {
+ rpc->smenr |=
+ RPC_SMENR_SPIDE(rpc_bits_set(xfer[i].len)) |
+ RPC_SMENR_SPIDB(ilog2
+ ((unsigned int)xfer[i].tx_nbits));
+ }
+ }
+}
+
+static inline int rpc_spi_xfer_message(struct rpc_spi *rpc,
+ struct spi_transfer *data_xfer)
+{
+ int ret;
+
+ ret = rpc_spi_set_freq(rpc, data_xfer->speed_hz);
+ if (ret)
+ return ret;
+
+ ret = rpc_spi_io_xfer(rpc,
+ rpc->xfer_dir == SPI_MEM_DATA_OUT ?
+ data_xfer->tx_buf : NULL,
+ rpc->xfer_dir == SPI_MEM_DATA_IN ?
+ data_xfer->rx_buf : NULL);
+
+ return ret;
+}
+
+static int rpc_spi_transfer_one_message(struct spi_controller *ctlr,
+ struct spi_message *msg)
+{
+ struct rpc_spi *rpc = spi_controller_get_devdata(ctlr);
+ struct spi_transfer *data_xfer;
+ int ret;
+
+ rpc_spi_transfer_setup(rpc, msg);
+
+ data_xfer = list_last_entry(&msg->transfers, struct spi_transfer,
+ transfer_list);
+
+ ret = rpc_spi_xfer_message(rpc, data_xfer);
+ if (ret)
+ goto out;
+
+ msg->status = 0;
+ msg->actual_length = rpc->totalxferlen;
+out:
+ spi_finalize_current_message(ctlr);
+ return 0;
+}
+
+static int rpc_spi_probe(struct platform_device *pdev)
+{
+ struct spi_controller *ctlr;
+ struct rpc_mfd *rpc_mfd = dev_get_drvdata(pdev->dev.parent);
+ struct rpc_spi *rpc;
+ int ret;
+
+ ctlr = spi_alloc_master(&pdev->dev, sizeof(*rpc));
+ if (!ctlr)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, ctlr);
+
+ rpc = spi_controller_get_devdata(ctlr);
+
+ rpc->mfd = rpc_mfd;
+ ctlr->dev.of_node = pdev->dev.parent->of_node;
+
+ pm_runtime_enable(&pdev->dev);
+ ctlr->auto_runtime_pm = true;
+
+ ctlr->num_chipselect = 1;
+ ctlr->mem_ops = &rpc_spi_mem_ops;
+ ctlr->transfer_one_message = rpc_spi_transfer_one_message;
+
+ ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
+ ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_TX_QUAD | SPI_RX_QUAD;
+
+ pm_runtime_get_sync(&pdev->dev);
+ rpc_spi_hw_init(rpc);
+ pm_runtime_put(&pdev->dev);
+
+ ret = spi_register_controller(ctlr);
+ if (ret) {
+ dev_err(&pdev->dev, "spi_register_controller failed\n");
+ goto err_put_ctlr;
+ }
+ return 0;
+
+err_put_ctlr:
+ spi_controller_put(ctlr);
+ pm_runtime_disable(&pdev->dev);
+
+ return ret;
+}
+
+static int rpc_spi_remove(struct platform_device *pdev)
+{
+ struct spi_controller *ctlr = platform_get_drvdata(pdev);
+
+ pm_runtime_disable(&pdev->dev);
+ spi_unregister_controller(ctlr);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int rpc_spi_suspend(struct device *dev)
+{
+ struct spi_controller *ctlr = dev_get_drvdata(dev);
+
+ return spi_controller_suspend(ctlr);
+}
+
+static int rpc_spi_resume(struct device *dev)
+{
+ struct spi_controller *ctlr = dev_get_drvdata(dev);
+
+ return spi_controller_resume(ctlr);
+}
+
+static SIMPLE_DEV_PM_OPS(rpc_spi_pm_ops, rpc_spi_suspend, rpc_spi_resume);
+#define DEV_PM_OPS (&rpc_spi_pm_ops)
+#else
+#define DEV_PM_OPS NULL
+#endif
+
+static struct platform_driver rpc_spi_driver = {
+ .probe = rpc_spi_probe,
+ .remove = rpc_spi_remove,
+ .driver = {
+ .name = "rpc-spi",
+ .pm = DEV_PM_OPS,
+ },
+};
+module_platform_driver(rpc_spi_driver);
+
+MODULE_AUTHOR("Mason Yang <[email protected]>");
+MODULE_DESCRIPTION("Renesas R-Car Gen3 RPC-IF SPI controller driver");
+MODULE_LICENSE("GPL v2");
--
1.9.1

2019-04-24 10:59:55

[permalink] [raw]

Subject: [PATCH v12 1/3] mfd: Add Renesas R-Car Gen3 RPC-IF MFD driver

Add a driver for Renesas R-Car Gen3 RPC-IF MFD.

Signed-off-by: Mason Yang <[email protected]>
---
drivers/mfd/Kconfig | 9 +++
drivers/mfd/Makefile | 1 +
drivers/mfd/renesas-rpc.c | 125 +++++++++++++++++++++++++++++++++++
include/linux/mfd/renesas-rpc.h | 141 ++++++++++++++++++++++++++++++++++++++++
4 files changed, 276 insertions(+)
create mode 100644 drivers/mfd/renesas-rpc.c
create mode 100644 include/linux/mfd/renesas-rpc.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 26ad646..efdb1b9 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -978,6 +978,15 @@ config MFD_RDC321X
southbridge which provides access to GPIOs and Watchdog using the
southbridge PCI device configuration space.

+config MFD_RENESAS_RPC
+ tristate "Renesas R-Car Gen3 RPC-IF MFD driver"
+ select MFD_CORE
+ depends on ARCH_RENESAS
+ help
+ This supports Renesas R-Car Gen3 RPC-IF multifunction device
+ which provides either SPI host or HyperFlash.
+ You have to select individual components under the corresponding menu.
+
config MFD_RT5033
tristate "Richtek RT5033 Power Management IC"
depends on I2C
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index b4569ed7..4a49699 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -183,6 +183,7 @@ obj-$(CONFIG_MFD_INTEL_QUARK_I2C_GPIO) += intel_quark_i2c_gpio.o
obj-$(CONFIG_LPC_SCH) += lpc_sch.o
obj-$(CONFIG_LPC_ICH) += lpc_ich.o
obj-$(CONFIG_MFD_RDC321X) += rdc321x-southbridge.o
+obj-$(CONFIG_MFD_RENESAS_RPC) += renesas-rpc.o
obj-$(CONFIG_MFD_JANZ_CMODIO) += janz-cmodio.o
obj-$(CONFIG_MFD_JZ4740_ADC) += jz4740-adc.o
obj-$(CONFIG_MFD_TPS6586X) += tps6586x.o
diff --git a/drivers/mfd/renesas-rpc.c b/drivers/mfd/renesas-rpc.c
new file mode 100644
index 0000000..c80c8d1
--- /dev/null
+++ b/drivers/mfd/renesas-rpc.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2018 ~ 2019 Renesas Solutions Corp.
+// Copyright (C) 2019 Macronix International Co., Ltd.
+//
+// R-Car Gen3 RPC-IF MFD driver
+//
+// Author:
+// Mason Yang <[email protected]>
+//
+
+#include <linux/clk.h>
+#include <linux/mfd/core.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/regmap.h>
+#include <linux/mfd/renesas-rpc.h>
+#include <linux/reset.h>
+
+static const struct mfd_cell rpc_hf_ctlr = {
+ .name = "rpc-hf",
+};
+
+static const struct mfd_cell rpc_spi_ctlr = {
+ .name = "rpc-spi",
+};
+
+static const struct regmap_range rpc_mfd_volatile_ranges[] = {
+ regmap_reg_range(RPC_SMRDR0, RPC_SMRDR1),
+ regmap_reg_range(RPC_SMWDR0, RPC_SMWDR1),
+ regmap_reg_range(RPC_CMNSR, RPC_CMNSR),
+};
+
+static const struct regmap_access_table rpc_mfd_volatile_table = {
+ .yes_ranges = rpc_mfd_volatile_ranges,
+ .n_yes_ranges = ARRAY_SIZE(rpc_mfd_volatile_ranges),
+};
+
+static const struct regmap_config rpc_mfd_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .fast_io = true,
+ .max_register = RPC_PHYOFFSET2,
+ .volatile_table = &rpc_mfd_volatile_table,
+};
+
+static int rpc_mfd_probe(struct platform_device *pdev)
+{
+ struct device_node *flash;
+ const struct mfd_cell *cell;
+ struct resource *res;
+ struct rpc_mfd *rpc;
+ void __iomem *base;
+
+ flash = of_get_next_child(pdev->dev.of_node, NULL);
+ if (!flash) {
+ dev_warn(&pdev->dev, "no flash node found\n");
+ return -ENODEV;
+ }
+
+ if (of_device_is_compatible(flash, "jedec,spi-nor")) {
+ cell = &rpc_spi_ctlr;
+ } else if (of_device_is_compatible(flash, "cfi-flash")) {
+ cell = &rpc_hf_ctlr;
+ } else {
+ dev_warn(&pdev->dev, "unknown flash type\n");
+ return -ENODEV;
+ }
+
+ rpc = devm_kzalloc(&pdev->dev, sizeof(*rpc), GFP_KERNEL);
+ if (!rpc)
+ return -ENOMEM;
+
+ rpc->clk_rpc = devm_clk_get(&pdev->dev, "rpc");
+ if (IS_ERR(rpc->clk_rpc))
+ return PTR_ERR(rpc->clk_rpc);
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ rpc->regmap = devm_regmap_init_mmio(&pdev->dev, base,
+ &rpc_mfd_regmap_config);
+ if (IS_ERR(rpc->regmap)) {
+ dev_err(&pdev->dev,
+ "failed to init regmap for rpc-mfd, error %ld\n",
+ PTR_ERR(rpc->regmap));
+ return PTR_ERR(rpc->regmap);
+ }
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap");
+ rpc->dirmap = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(rpc->dirmap))
+ rpc->dirmap = NULL;
+
+ rpc->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
+ if (IS_ERR(rpc->rstc))
+ return PTR_ERR(rpc->rstc);
+
+ platform_set_drvdata(pdev, rpc);
+
+ return devm_mfd_add_devices(&pdev->dev, -1, cell, 1, NULL, 0, NULL);
+}
+
+static const struct of_device_id rpc_mfd_of_match[] = {
+ { .compatible = "renesas,rcar-gen3-rpc", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, rpc_mfd_of_match);
+
+static struct platform_driver rpc_mfd_driver = {
+ .probe = rpc_mfd_probe,
+ .driver = {
+ .name = "rpc-mfd",
+ .of_match_table = rpc_mfd_of_match,
+ },
+};
+module_platform_driver(rpc_mfd_driver);
+
+MODULE_AUTHOR("Mason Yang <[email protected]>");
+MODULE_DESCRIPTION("Renesas R-Car Gen3 RPC MFD driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/mfd/renesas-rpc.h b/include/linux/mfd/renesas-rpc.h
new file mode 100644
index 0000000..bc53d02
--- /dev/null
+++ b/include/linux/mfd/renesas-rpc.h
@@ -0,0 +1,141 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2018 ~ 2019 Renesas Solutions Corp.
+// Copyright (C) 2019 Macronix International Co., Ltd.
+//
+// R-Car Gen3 RPC-IF MFD driver
+//
+// Author:
+// Mason Yang <[email protected]>
+//
+
+#ifndef __MFD_RENESAS_RPC_H
+#define __MFD_RENESAS_RPC_H
+
+#define RPC_CMNCR 0x0000 // R/W
+#define RPC_CMNCR_MD BIT(31)
+#define RPC_CMNCR_SFDE BIT(24) // undocumented bit but must be set
+#define RPC_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
+#define RPC_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
+#define RPC_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
+#define RPC_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
+#define RPC_CMNCR_MOIIO_HIZ (RPC_CMNCR_MOIIO0(3) | RPC_CMNCR_MOIIO1(3) | \
+ RPC_CMNCR_MOIIO2(3) | RPC_CMNCR_MOIIO3(3))
+#define RPC_CMNCR_IO3FV(val) (((val) & 0x3) << 14) // undocumented
+#define RPC_CMNCR_IO2FV(val) (((val) & 0x3) << 12) // undocumented
+#define RPC_CMNCR_IO0FV(val) (((val) & 0x3) << 8)
+#define RPC_CMNCR_IOFV_HIZ (RPC_CMNCR_IO0FV(3) | RPC_CMNCR_IO2FV(3) | \
+ RPC_CMNCR_IO3FV(3))
+#define RPC_CMNCR_BSZ(val) (((val) & 0x3) << 0)
+
+#define RPC_SSLDR 0x0004 // R/W
+#define RPC_SSLDR_SPNDL(d) (((d) & 0x7) << 16)
+#define RPC_SSLDR_SLNDL(d) (((d) & 0x7) << 8)
+#define RPC_SSLDR_SCKDL(d) (((d) & 0x7) << 0)
+
+#define RPC_DRCR 0x000C // R/W
+#define RPC_DRCR_SSLN BIT(24)
+#define RPC_DRCR_RBURST(v) ((((v) - 1) & 0x1F) << 16)
+#define RPC_DRCR_RCF BIT(9)
+#define RPC_DRCR_RBE BIT(8)
+#define RPC_DRCR_SSLE BIT(0)
+
+#define RPC_DRCMR 0x0010 // R/W
+#define RPC_DRCMR_CMD(c) (((c) & 0xFF) << 16)
+#define RPC_DRCMR_OCMD(c) (((c) & 0xFF) << 0)
+
+#define RPC_DREAR 0x0014 // R/W
+#define RPC_DREAR_EAV(c) (((c) & 0xf) << 16)
+#define RPC_DREAR_EAC(c) (((c) & 0x7) << 0)
+
+#define RPC_DROPR 0x0018 // R/W
+
+#define RPC_DRENR 0x001C // R/W
+#define RPC_DRENR_CDB(o) (u32)((((o) & 0x3) << 30))
+#define RPC_DRENR_OCDB(o) (((o) & 0x3) << 28)
+#define RPC_DRENR_ADB(o) (((o) & 0x3) << 24)
+#define RPC_DRENR_OPDB(o) (((o) & 0x3) << 20)
+#define RPC_DRENR_DRDB(o) (((o) & 0x3) << 16)
+#define RPC_DRENR_DME BIT(15)
+#define RPC_DRENR_CDE BIT(14)
+#define RPC_DRENR_OCDE BIT(12)
+#define RPC_DRENR_ADE(v) (((v) & 0xF) << 8)
+#define RPC_DRENR_OPDE(v) (((v) & 0xF) << 4)
+
+#define RPC_SMCR 0x0020 // R/W
+#define RPC_SMCR_SSLKP BIT(8)
+#define RPC_SMCR_SPIRE BIT(2)
+#define RPC_SMCR_SPIWE BIT(1)
+#define RPC_SMCR_SPIE BIT(0)
+
+#define RPC_SMCMR 0x0024 // R/W
+#define RPC_SMCMR_CMD(c) (((c) & 0xFF) << 16)
+#define RPC_SMCMR_OCMD(c) (((c) & 0xFF) << 0)
+
+#define RPC_SMADR 0x0028 // R/W
+#define RPC_SMOPR 0x002C // R/W
+#define RPC_SMOPR_OPD3(o) (((o) & 0xFF) << 24)
+#define RPC_SMOPR_OPD2(o) (((o) & 0xFF) << 16)
+#define RPC_SMOPR_OPD1(o) (((o) & 0xFF) << 8)
+#define RPC_SMOPR_OPD0(o) (((o) & 0xFF) << 0)
+
+#define RPC_SMENR 0x0030 // R/W
+#define RPC_SMENR_CDB(o) (((o) & 0x3) << 30)
+#define RPC_SMENR_OCDB(o) (((o) & 0x3) << 28)
+#define RPC_SMENR_ADB(o) (((o) & 0x3) << 24)
+#define RPC_SMENR_OPDB(o) (((o) & 0x3) << 20)
+#define RPC_SMENR_SPIDB(o) (((o) & 0x3) << 16)
+#define RPC_SMENR_DME BIT(15)
+#define RPC_SMENR_CDE BIT(14)
+#define RPC_SMENR_OCDE BIT(12)
+#define RPC_SMENR_ADE(v) (((v) & 0xF) << 8)
+#define RPC_SMENR_OPDE(v) (((v) & 0xF) << 4)
+#define RPC_SMENR_SPIDE(v) (((v) & 0xF) << 0)
+
+#define RPC_SMRDR0 0x0038 // R
+#define RPC_SMRDR1 0x003C // R
+#define RPC_SMWDR0 0x0040 // W
+#define RPC_SMWDR1 0x0044 // W
+
+#define RPC_CMNSR 0x0048 // R
+#define RPC_CMNSR_SSLF BIT(1)
+#define RPC_CMNSR_TEND BIT(0)
+
+#define RPC_DRDMCR 0x0058 // R/W
+#define RPC_DRDRENR 0x005C // R/W
+
+#define RPC_SMDMCR 0x0060 // R/W
+#define RPC_SMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
+
+#define RPC_SMDRENR 0x0064 // R/W
+#define RPC_SMDRENR_HYPE (0x7 << 12)
+#define RPC_SMDRENR_ADDRE BIT(8)
+#define RPC_SMDRENR_OPDRE BIT(4)
+#define RPC_SMDRENR_SPIDRE BIT(0)
+
+#define RPC_PHYCNT 0x007C // R/W
+#define RPC_PHYCNT_CAL BIT(31)
+#define PRC_PHYCNT_OCTA_AA BIT(22)
+#define PRC_PHYCNT_OCTA_SA BIT(23)
+#define PRC_PHYCNT_EXDS BIT(21)
+#define RPC_PHYCNT_OCT BIT(20)
+#define RPC_PHYCNT_STRTIM(v) (((v) & 0x7) << 15)
+#define RPC_PHYCNT_WBUF2 BIT(4)
+#define RPC_PHYCNT_WBUF BIT(2)
+#define RPC_PHYCNT_PHYMEM(v) (((v) & 0x3) << 0)
+
+#define RPC_PHYOFFSET1 0x0080 // R/W
+#define RPC_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28)
+#define RPC_PHYOFFSET2 0x0084 // R/W
+#define RPC_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8)
+
+#define RPC_DIRMAP_SIZE 0x4000000
+
+struct rpc_mfd {
+ struct clk *clk_rpc;
+ void __iomem *dirmap;
+ struct regmap *regmap;
+ struct reset_control *rstc;
+};
+
+#endif // __MFD_RENESAS_RPC_H
--
1.9.1

2019-04-25 07:12:59

by Rob Herring (Arm)

[permalink] [raw]

Subject: Re: [PATCH v12 3/3] dt-bindings: mfd: Document Renesas R-Car Gen3 RPC-IF MFD bindings

On Wed, Apr 24, 2019 at 03:55:36PM +0800, Mason Yang wrote:
> Document the bindings used by the Renesas R-Car Gen3 RPC-IF MFD.
>
> Signed-off-by: Mason Yang <[email protected]>
> ---
> .../devicetree/bindings/mfd/mfd-renesas-rpc.txt | 40 ++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt
>
> diff --git a/Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt b/Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt
> new file mode 100644
> index 0000000..668b822
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt
> @@ -0,0 +1,40 @@
> +Renesas R-Car Gen3 RPC-IF MFD Device Tree Bindings
> +--------------------------------------------------

Looks like a SPI flash controller from the example. What makes it an
MFD?

> +
> +Required properties:
> +- compatible: should be an SoC-specific compatible value, followed by
> + "renesas,rcar-gen3-rpc" as a fallback.
> + supported SoC-specific values are:
> + "renesas,r8a77995-rpc" (R-Car D3)
> +- reg: should contain three register areas:
> + first for the base address of RPC-IF registers,
> + second for the direct mapping read mode and
> + third for the write buffer area.
> +- reg-names: should contain "regs", "dirmap" and "wbuf"
> +- clocks: should contain 1 entries for the module's clock
> +- clock-names: should contain "rpc"
> +- #address-cells: should be 1
> +- #size-cells: should be 0
> +
> +Example:
> +
> + rpc: rpc-if@ee200000 {
> + compatible = "renesas,r8a77995-rpc", "renesas,rcar-gen3-rpc";
> + reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x4000000>,
> + <0 0xee208000 0 0x100>;
> + reg-names = "regs", "dirmap", "wbuf";
> + clocks = <&cpg CPG_MOD 917>;
> + clock-names = "rpc";
> + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> + resets = <&cpg 917>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + flash@0 {
> + compatible = "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <40000000>;
> + spi-tx-bus-width = <1>;
> + spi-rx-bus-width = <1>;
> + };
> + };
> --
> 1.9.1
>

2019-04-25 10:06:07

by Marek Vasut

[permalink] [raw]

Subject: Re: [PATCH v12 3/3] dt-bindings: mfd: Document Renesas R-Car Gen3 RPC-IF MFD bindings

On 4/24/19 11:23 PM, Rob Herring wrote:
> On Wed, Apr 24, 2019 at 03:55:36PM +0800, Mason Yang wrote:
>> Document the bindings used by the Renesas R-Car Gen3 RPC-IF MFD.
>>
>> Signed-off-by: Mason Yang <[email protected]>
>> ---
>> .../devicetree/bindings/mfd/mfd-renesas-rpc.txt | 40 ++++++++++++++++++++++
>> 1 file changed, 40 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt
>>
>> diff --git a/Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt b/Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt
>> new file mode 100644
>> index 0000000..668b822
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt
>> @@ -0,0 +1,40 @@
>> +Renesas R-Car Gen3 RPC-IF MFD Device Tree Bindings
>> +--------------------------------------------------
>
> Looks like a SPI flash controller from the example. What makes it an
> MFD?

It supports both SPI NOR and HyperFlash (CFI-compliant flash with
different bus interface).

>> +
>> +Required properties:
>> +- compatible: should be an SoC-specific compatible value, followed by
>> + "renesas,rcar-gen3-rpc" as a fallback.
>> + supported SoC-specific values are:
>> + "renesas,r8a77995-rpc" (R-Car D3)
>> +- reg: should contain three register areas:
>> + first for the base address of RPC-IF registers,
>> + second for the direct mapping read mode and
>> + third for the write buffer area.
>> +- reg-names: should contain "regs", "dirmap" and "wbuf"
>> +- clocks: should contain 1 entries for the module's clock
>> +- clock-names: should contain "rpc"
>> +- #address-cells: should be 1
>> +- #size-cells: should be 0
>> +
>> +Example:
>> +
>> + rpc: rpc-if@ee200000 {
>> + compatible = "renesas,r8a77995-rpc", "renesas,rcar-gen3-rpc";
>> + reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x4000000>,
>> + <0 0xee208000 0 0x100>;
>> + reg-names = "regs", "dirmap", "wbuf";
>> + clocks = <&cpg CPG_MOD 917>;
>> + clock-names = "rpc";
>> + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
>> + resets = <&cpg 917>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + flash@0 {
>> + compatible = "jedec,spi-nor";
>> + reg = <0>;
>> + spi-max-frequency = <40000000>;
>> + spi-tx-bus-width = <1>;
>> + spi-rx-bus-width = <1>;
>> + };
>> + };
>> --
>> 1.9.1
>>

--
Best regards,
Marek Vasut

2019-04-25 23:16:08

by Rob Herring (Arm)

[permalink] [raw]

Subject: Re: [PATCH v12 3/3] dt-bindings: mfd: Document Renesas R-Car Gen3 RPC-IF MFD bindings

On Wed, Apr 24, 2019 at 4:54 PM Marek Vasut <[email protected]> wrote:
>
> On 4/24/19 11:23 PM, Rob Herring wrote:
> > On Wed, Apr 24, 2019 at 03:55:36PM +0800, Mason Yang wrote:
> >> Document the bindings used by the Renesas R-Car Gen3 RPC-IF MFD.
> >>
> >> Signed-off-by: Mason Yang <[email protected]>
> >> ---
> >> .../devicetree/bindings/mfd/mfd-renesas-rpc.txt | 40 ++++++++++++++++++++++
> >> 1 file changed, 40 insertions(+)
> >> create mode 100644 Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt
> >>
> >> diff --git a/Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt b/Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt
> >> new file mode 100644
> >> index 0000000..668b822
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt
> >> @@ -0,0 +1,40 @@
> >> +Renesas R-Car Gen3 RPC-IF MFD Device Tree Bindings
> >> +--------------------------------------------------
> >
> > Looks like a SPI flash controller from the example. What makes it an
> > MFD?
>
> It supports both SPI NOR and HyperFlash (CFI-compliant flash with
> different bus interface).

Not sure that really makes it an MFD. Lee probably has an opinion.

In any case, can we get a complete binding that shows both.

Rob

2019-04-26 02:30:17

by Marek Vasut

[permalink] [raw]

Subject: Re: [PATCH v12 3/3] dt-bindings: mfd: Document Renesas R-Car Gen3 RPC-IF MFD bindings

On 4/26/19 1:07 AM, Rob Herring wrote:
> On Wed, Apr 24, 2019 at 4:54 PM Marek Vasut <[email protected]> wrote:
>>
>> On 4/24/19 11:23 PM, Rob Herring wrote:
>>> On Wed, Apr 24, 2019 at 03:55:36PM +0800, Mason Yang wrote:
>>>> Document the bindings used by the Renesas R-Car Gen3 RPC-IF MFD.
>>>>
>>>> Signed-off-by: Mason Yang <[email protected]>
>>>> ---
>>>> .../devicetree/bindings/mfd/mfd-renesas-rpc.txt | 40 ++++++++++++++++++++++
>>>> 1 file changed, 40 insertions(+)
>>>> create mode 100644 Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt b/Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt
>>>> new file mode 100644
>>>> index 0000000..668b822
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt
>>>> @@ -0,0 +1,40 @@
>>>> +Renesas R-Car Gen3 RPC-IF MFD Device Tree Bindings
>>>> +--------------------------------------------------
>>>
>>> Looks like a SPI flash controller from the example. What makes it an
>>> MFD?
>>
>> It supports both SPI NOR and HyperFlash (CFI-compliant flash with
>> different bus interface).
>
> Not sure that really makes it an MFD. Lee probably has an opinion.
>
> In any case, can we get a complete binding that shows both.

Presumably that would only mean the flash compatible is some "cfi,nor"
or somesuch. But I agree, would be nice to have both in the example.

--
Best regards,
Marek Vasut

2019-05-07 13:00:08

[permalink] [raw]

Subject: Re: [PATCH v12 3/3] dt-bindings: mfd: Document Renesas R-Car Gen3 RPC-IF MFD bindings

On Wed, 24 Apr 2019, Marek Vasut wrote:

> On 4/24/19 11:23 PM, Rob Herring wrote:
> > On Wed, Apr 24, 2019 at 03:55:36PM +0800, Mason Yang wrote:
> >> Document the bindings used by the Renesas R-Car Gen3 RPC-IF MFD.
> >>
> >> Signed-off-by: Mason Yang <[email protected]>
> >> ---
> >> .../devicetree/bindings/mfd/mfd-renesas-rpc.txt | 40 ++++++++++++++++++++++
> >> 1 file changed, 40 insertions(+)
> >> create mode 100644 Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt
> >>
> >> diff --git a/Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt b/Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt
> >> new file mode 100644
> >> index 0000000..668b822
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt
> >> @@ -0,0 +1,40 @@
> >> +Renesas R-Car Gen3 RPC-IF MFD Device Tree Bindings
> >> +--------------------------------------------------
> >
> > Looks like a SPI flash controller from the example. What makes it an
> > MFD?
>
> It supports both SPI NOR and HyperFlash (CFI-compliant flash with
> different bus interface).

Looks like you're registering one OR the other.

Why don't you just do this from DT?

No reason for this to be an MFD IMHO.

--
Lee Jones [李琼斯]
Linaro Services Technical Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

2019-05-08 03:53:26

by Marek Vasut

[permalink] [raw]

Subject: Re: [PATCH v12 3/3] dt-bindings: mfd: Document Renesas R-Car Gen3 RPC-IF MFD bindings

On 5/8/19 4:48 AM, [email protected] wrote:
> Hi Jones,
>
>> "Lee Jones" <[email protected]>
>> 2019/05/07 下午 08:58
>>
>> To
>>
>> "Marek Vasut" <[email protected]>,
>>
>> cc
>>
>> "Rob Herring" <[email protected]>, "Mason Yang"
>> <[email protected]>, [email protected], linux-
>> [email protected], [email protected],
>> [email protected], [email protected], "Geert
>> Uytterhoeven" <[email protected]>,
>> [email protected], [email protected],
>> [email protected], [email protected], "Simon Horman"
>> <[email protected]>, [email protected]
>>
>> Subject
>>
>> Re: [PATCH v12 3/3] dt-bindings: mfd: Document Renesas R-Car Gen3
>> RPC-IF MFD bindings
>>
>> On Wed, 24 Apr 2019, Marek Vasut wrote:
>>
>> > On 4/24/19 11:23 PM, Rob Herring wrote:
>> > > On Wed, Apr 24, 2019 at 03:55:36PM +0800, Mason Yang wrote:
>> > >> Document the bindings used by the Renesas R-Car Gen3 RPC-IF MFD.
>> > >>
>> > >> Signed-off-by: Mason Yang <[email protected]>
>> > >> ---
>> > >> .../devicetree/bindings/mfd/mfd-renesas-rpc.txt | 40 ++++++
>> ++++++++++++++++
>> > >> 1 file changed, 40 insertions(+)
>> > >> create mode 100644 Documentation/devicetree/bindings/mfd/mfd-
>> renesas-rpc.txt
>> > >>
>> > >> diff --git a/Documentation/devicetree/bindings/mfd/mfd-renesas-
>> rpc.txt b/Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt
>> > >> new file mode 100644
>> > >> index 0000000..668b822
>> > >> --- /dev/null
>> > >> +++ b/Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt
>> > >> @@ -0,0 +1,40 @@
>> > >> +Renesas R-Car Gen3 RPC-IF MFD Device Tree Bindings
>> > >> +--------------------------------------------------
>> > >
>> > > Looks like a SPI flash controller from the example. What makes it an
>> > > MFD?
>> >
>> > It supports both SPI NOR and HyperFlash (CFI-compliant flash with
>> > different bus interface).
>>
>> Looks like you're registering one OR the other.
>>
>> Why don't you just do this from DT?
>>
>> No reason for this to be an MFD IMHO.
>
>
> okay, I will patch it back to SPI mode only.

I don't think that's what Lee meant . The controller supports _both_
modes , hence it would have the same compatible string. You just need to
extract the mode of operation from the DT.

--
Best regards,
Marek Vasut

2019-05-08 06:37:00

[permalink] [raw]

Subject: Re: [PATCH v12 3/3] dt-bindings: mfd: Document Renesas R-Car Gen3 RPC-IF MFD bindings

On Wed, 08 May 2019, Marek Vasut wrote:

> On 5/8/19 4:48 AM, [email protected] wrote:
> > Hi Jones,
> >
> >> "Lee Jones" <[email protected]>
> >> 2019/05/07 下午 08:58
> >>
> >> To
> >>
> >> "Marek Vasut" <[email protected]>,
> >>
> >> cc
> >>
> >> "Rob Herring" <[email protected]>, "Mason Yang"
> >> <[email protected]>, [email protected], linux-
> >> [email protected], [email protected],
> >> [email protected], [email protected], "Geert
> >> Uytterhoeven" <[email protected]>,
> >> [email protected], [email protected],
> >> [email protected], [email protected], "Simon Horman"
> >> <[email protected]>, [email protected]
> >>
> >> Subject
> >>
> >> Re: [PATCH v12 3/3] dt-bindings: mfd: Document Renesas R-Car Gen3
> >> RPC-IF MFD bindings
> >>
> >> On Wed, 24 Apr 2019, Marek Vasut wrote:
> >>
> >> > On 4/24/19 11:23 PM, Rob Herring wrote:
> >> > > On Wed, Apr 24, 2019 at 03:55:36PM +0800, Mason Yang wrote:
> >> > >> Document the bindings used by the Renesas R-Car Gen3 RPC-IF MFD.
> >> > >>
> >> > >> Signed-off-by: Mason Yang <[email protected]>
> >> > >> ---
> >> > >> .../devicetree/bindings/mfd/mfd-renesas-rpc.txt | 40 ++++++
> >> ++++++++++++++++
> >> > >> 1 file changed, 40 insertions(+)
> >> > >> create mode 100644 Documentation/devicetree/bindings/mfd/mfd-
> >> renesas-rpc.txt
> >> > >>
> >> > >> diff --git a/Documentation/devicetree/bindings/mfd/mfd-renesas-
> >> rpc.txt b/Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt
> >> > >> new file mode 100644
> >> > >> index 0000000..668b822
> >> > >> --- /dev/null
> >> > >> +++ b/Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt
> >> > >> @@ -0,0 +1,40 @@
> >> > >> +Renesas R-Car Gen3 RPC-IF MFD Device Tree Bindings
> >> > >> +--------------------------------------------------
> >> > >
> >> > > Looks like a SPI flash controller from the example. What makes it an
> >> > > MFD?
> >> >
> >> > It supports both SPI NOR and HyperFlash (CFI-compliant flash with
> >> > different bus interface).
> >>
> >> Looks like you're registering one OR the other.
> >>
> >> Why don't you just do this from DT?
> >>
> >> No reason for this to be an MFD IMHO.
> >
> >
> > okay, I will patch it back to SPI mode only.
>
> I don't think that's what Lee meant . The controller supports _both_
> modes , hence it would have the same compatible string. You just need to
> extract the mode of operation from the DT.

HiSilicon attempted to upstream something similar, only their
controller provided NAND and NOR functionality. They used different
compatible strings to differentiate between the varying
technologies.

They too tried to use MFD as a means to select between them (which was
also NACKed). Not sure what they ended up doing, but the original
submission and (half of) the conversation can be found at [0]. Some
more of the thread continues at [1].

Hope that helps.

[0] https://groups.google.com/forum/#!topic/fa.linux.kernel/F6i9o8sfOIw
[1] https://marc.info/?l=devicetree&m=147669165104431&w=2

--
Lee Jones [李琼斯]
Linaro Services Technical Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

2019-05-09 19:25:34

[permalink] [raw]

Subject: Re: [PATCH v12 3/3] dt-bindings: mfd: Document Renesas R-Car Gen3 RPC-IF MFD bindings

Hello!

On 05/09/2019 05:06 AM, [email protected] wrote:

[...]
>> > >> > On 4/24/19 11:23 PM, Rob Herring wrote:
>> > >> > > On Wed, Apr 24, 2019 at 03:55:36PM +0800, Mason Yang wrote:
>> > >> > >> Document the bindings used by the Renesas R-Car Gen3 RPC-IF MFD.
>> > >> > >>
>> > >> > >> Signed-off-by: Mason Yang <[email protected]>
>> > >> > >> ---
>> > >> > >> .../devicetree/bindings/mfd/mfd-renesas-rpc.txt | 40 ++++++
>> > >> ++++++++++++++++
>> > >> > >> 1 file changed, 40 insertions(+)
>> > >> > >> create mode 100644 Documentation/devicetree/bindings/mfd/mfd-
>> > >> renesas-rpc.txt
>> > >> > >>
>> > >> > >> diff --git a/Documentation/devicetree/bindings/mfd/mfd-renesas-
>> > >> rpc.txt b/Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt
>> > >> > >> new file mode 100644
>> > >> > >> index 0000000..668b822
>> > >> > >> --- /dev/null
>> > >> > >> +++ b/Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt
>> > >> > >> @@ -0,0 +1,40 @@
>> > >> > >> +Renesas R-Car Gen3 RPC-IF MFD Device Tree Bindings
>> > >> > >> +--------------------------------------------------
>> > >> > >
>> > >> > > Looks like a SPI flash controller from the example. What makes it an
>> > >> > > MFD?
>> > >> >
>> > >> > It supports both SPI NOR and HyperFlash (CFI-compliant flash with
>> > >> > different bus interface).
>> > >>
>> > >> Looks like you're registering one OR the other.
>> > >>
>> > >> Why don't you just do this from DT?
>> > >>
>> > >> No reason for this to be an MFD IMHO.
>> > >
>> > >
>> > > okay, I will patch it back to SPI mode only.
>> >
>> > I don't think that's what Lee meant . The controller supports _both_
>> > modes , hence it would have the same compatible string. You just need to
>> > extract the mode of operation from the DT.
>>
>> HiSilicon attempted to upstream something similar, only their
>> controller provided NAND and NOR functionality. They used different
>> compatible strings to differentiate between the varying
>> technologies.
>>
>> They too tried to use MFD as a means to select between them (which was
>> also NACKed). Not sure what they ended up doing, but the original
>> submission and (half of) the conversation can be found at [0]. Some
>> more of the thread continues at [1].
>>
>> Hope that helps.
>>
>> [0] https://groups.google.com/forum/#!topic/fa.linux.kernel/F6i9o8sfOIw
>> [1] https://marc.info/?l=devicetree&m=147669165104431&w=2
>
>
> Hi Marek,
>
> By Jones's comments:
> --------------------------------------------------------------------------
>> From: Shunquan Lin <[email protected]>
>>
>> This patch adds driver support for HiSilicon Flash Memory
>> Controller(FMC). HiSilicon FMC is a multi-functions device which
>> supports SPI Nor flash controller, SPI nand Flash controller and
>> parallel nand flash controller.
>
> MFDs are for devices which span multiple subsystems.

And we do! One of the subdrivers will live under drivers/spi/, the other
under drivers/mtd/...

>
> Please submit this to MTD.
>
> _https://marc.info/?l=devicetree&m=147376842210229&w=2_
> -------------------------------------------------------------------------------------------------
>
>
> I will patch RPC-IF back to SPI mode according to previous patches:

I still don't see why you want to do this...

> -----------------------------------------------------------------------
> On 2/12/19 3:22 PM, Mark Brown wrote:
>> The patch
>>
>> spi: Add Renesas R-Car Gen3 RPC-IF SPI controller driver
>>
>> has been applied to the spi tree at
>>
>> https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git
>>
>> All being well this means that it will be integrated into the linux-next
>> tree (usually sometime in the next 24 hours) and sent to Linus during
>> the next merge window (or sooner if it is a bug fix), however if
>> problems are discovered then the patch may be dropped or reverted.
>>
>> You may get further e-mails resulting from automated or manual testing
>> and review of the tree, please engage with people reporting problems and
>> send followup patches addressing any issues that are reported if needed.
>>
>> If any updates are required or you are submitting further changes they
>> should be sent as incremental updates against current git, existing
>> patches will not be replaced.
>>
>> Please add any relevant lists and maintainers to the CCs when replying
>> to this mail.
> ------------------------------------------------------------------------
>
> agreed it ?

No, I don't agree.

[...]
> thanks & best regards,
> Mason

MBR, Sergei

2019-05-13 07:42:59

[permalink] [raw]

Subject: Re: [PATCH v12 3/3] dt-bindings: mfd: Document Renesas R-Car Gen3 RPC-IF MFD bindings

Hi Mason,

On Fri, May 10, 2019 at 3:09 AM <[email protected]> wrote:
> > "Sergei Shtylyov" <[email protected]>
> > 2019/05/10 上午 03:24
> > [email protected], "Rob Herring" <[email protected]>, [email protected]
> > On 05/09/2019 05:06 AM, [email protected] wrote:
> >
> > [...]
> > >> > >> > On 4/24/19 11:23 PM, Rob Herring wrote:
> > >> > >> > > On Wed, Apr 24, 2019 at 03:55:36PM +0800, Mason Yang wrote:
> > >> > >> > >> Document the bindings used by the Renesas R-Car Gen3 RPC-IF MFD.
> > >> > >> > >>
> > >> > >> > >> Signed-off-by: Mason Yang <[email protected]>
> > >> > >> > >> ---
> > >> > >> > >> .../devicetree/bindings/mfd/mfd-renesas-rpc.txt | 40 ++++++
> > >> > >> ++++++++++++++++
> > >> > >> > >> 1 file changed, 40 insertions(+)
> > >> > >> > >> create mode 100644 Documentation/devicetree/bindings/mfd/mfd-
> > >> > >> renesas-rpc.txt
> > >> > >> > >>
> > >> > >> > >> diff --git a/Documentation/devicetree/bindings/mfd/mfd-renesas-
> > >> > >> rpc.txt b/Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt
> > >> > >> > >> new file mode 100644
> > >> > >> > >> index 0000000..668b822
> > >> > >> > >> --- /dev/null
> > >> > >> > >> +++ b/Documentation/devicetree/bindings/mfd/mfd-renesas-rpc.txt
> > >> > >> > >> @@ -0,0 +1,40 @@
> > >> > >> > >> +Renesas R-Car Gen3 RPC-IF MFD Device Tree Bindings
> > >> > >> > >> +--------------------------------------------------
> > >> > >> > >
> > >> > >> > > Looks like a SPI flash controller from the example. What
> > makes it an
> > >> > >> > > MFD?
> > >> > >> >
> > >> > >> > It supports both SPI NOR and HyperFlash (CFI-compliant flash with
> > >> > >> > different bus interface).
> > >> > >>
> > >> > >> Looks like you're registering one OR the other.
> > >> > >>
> > >> > >> Why don't you just do this from DT?
> > >> > >>
> > >> > >> No reason for this to be an MFD IMHO.
> > >> > >
> > >> > >
> > >> > > okay, I will patch it back to SPI mode only.
> > >> >
> > >> > I don't think that's what Lee meant . The controller supports _both_
> > >> > modes , hence it would have the same compatible string. You just need to
> > >> > extract the mode of operation from the DT.
> > >>
> > >> HiSilicon attempted to upstream something similar, only their
> > >> controller provided NAND and NOR functionality. They used different
> > >> compatible strings to differentiate between the varying
> > >> technologies.
> > >>
> > >> They too tried to use MFD as a means to select between them (which was
> > >> also NACKed). Not sure what they ended up doing, but the original
> > >> submission and (half of) the conversation can be found at [0]. Some
> > >> more of the thread continues at [1].
> > >>
> > >> Hope that helps.
> > >>
> > >> [0] https://groups.google.com/forum/#!topic/fa.linux.kernel/F6i9o8sfOIw
> > >> [1] https://marc.info/?l=devicetree&m=147669165104431&w=2
> > >
> > >
> > > Hi Marek,
> > >
> > > By Jones's comments:
> > > --------------------------------------------------------------------------
> > >> From: Shunquan Lin <[email protected]>
> > >>
> > >> This patch adds driver support for HiSilicon Flash Memory
> > >> Controller(FMC). HiSilicon FMC is a multi-functions device which
> > >> supports SPI Nor flash controller, SPI nand Flash controller and
> > >> parallel nand flash controller.
> > >
> > > MFDs are for devices which span multiple subsystems.
> >
> > And we do! One of the subdrivers will live under drivers/spi/, the other
> > under drivers/mtd/...
> >
>
> From my point of view, I think Jones mean to MFD's subsystems are working simultaneously
> at the run-time, one period of time is working for sub-device-1 and later period of time
> is working for sub-device-2 and so on.
>
> But for RPC-IF, SPI or HF mode is decided at boot time by pins configure and later in kernel
> by dtb, RPC-IF can't switch SPI and HF mode at the run time.

> So far, Jones seems don't agree RPC-IF to MFD and then RPC MFD will not applied
> to mfd tree by him !

There's precedence for such constructs being an MFD: please see
drivers/mfd/at91-usart.c, which registers a single MFD cell for either
serial or SPI.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

2019-05-13 16:13:30

[permalink] [raw]

Subject: Re: [PATCH v12 3/3] dt-bindings: mfd: Document Renesas R-Car Gen3 RPC-IF MFD bindings

Hi Mason,

Note that if you send multipart/text+html emails, they will be dropped silently
by most Linux mailing lists.
Hence I'm quoting your last email fully, to give other people a chance
reading it (and commenting).

On Mon, May 13, 2019 at 11:37 AM <[email protected]> wrote:
> > > > [...]
> > > > >> > >> > On 4/24/19 11:23 PM, Rob Herring wrote:
> > > > >> > >> > > On Wed, Apr 24, 2019 at 03:55:36PM +0800, Mason Yang wrote:
> > > > >> > >> > >> Document the bindings used by the Renesas R-Car
> > Gen3 RPC-IF MFD.
> > > > >> > >> > >>
> > > > >> > >> > >> Signed-off-by: Mason Yang <[email protected]>
> > > > >> > >> > >> ---
> > > > >> > >> > >> .../devicetree/bindings/mfd/mfd-renesas-rpc.txt
> > | 40 ++++++
> > > > >> > >> ++++++++++++++++
> > > > >> > >> > >> 1 file changed, 40 insertions(+)
> > > > >> > >> > >> create mode 100644 Documentation/devicetree/
> > bindings/mfd/mfd-
> > > > >> > >> renesas-rpc.txt
> > > > >> > >> > >>
> > > > >> > >> > >> diff --git a/Documentation/devicetree/bindings/mfd/
> > mfd-renesas-
> > > > >> > >> rpc.txt b/Documentation/devicetree/bindings/mfd/mfd-
> > renesas-rpc.txt
> > > > >> > >> > >> new file mode 100644
> > > > >> > >> > >> index 0000000..668b822
> > > > >> > >> > >> --- /dev/null
> > > > >> > >> > >> +++ b/Documentation/devicetree/bindings/mfd/mfd-
> > renesas-rpc.txt
> > > > >> > >> > >> @@ -0,0 +1,40 @@
> > > > >> > >> > >> +Renesas R-Car Gen3 RPC-IF MFD Device Tree Bindings
> > > > >> > >> > >> +--------------------------------------------------
> > > > >> > >> > >
> > > > >> > >> > > Looks like a SPI flash controller from the example. What
> > > > makes it an
> > > > >> > >> > > MFD?
> > > > >> > >> >
> > > > >> > >> > It supports both SPI NOR and HyperFlash (CFI-compliantflash with
> > > > >> > >> > different bus interface).
> > > > >> > >>
> > > > >> > >> Looks like you're registering one OR the other.
> > > > >> > >>
> > > > >> > >> Why don't you just do this from DT?
> > > > >> > >>
> > > > >> > >> No reason for this to be an MFD IMHO.
> > > > >> > >
> > > > >> > >
> > > > >> > > okay, I will patch it back to SPI mode only.
> > > > >> >
> > > > >> > I don't think that's what Lee meant . The controller supports _both_
> > > > >> > modes , hence it would have the same compatible string. You
> > just need to
> > > > >> > extract the mode of operation from the DT.
> > > > >>
> > > > >> HiSilicon attempted to upstream something similar, only their
> > > > >> controller provided NAND and NOR functionality. They used different
> > > > >> compatible strings to differentiate between the varying
> > > > >> technologies.
> > > > >>
> > > > >> They too tried to use MFD as a means to select between them (which was
> > > > >> also NACKed). Not sure what they ended up doing, but the original
> > > > >> submission and (half of) the conversation can be found at [0]. Some
> > > > >> more of the thread continues at [1].
> > > > >>
> > > > >> Hope that helps.
> > > > >>
> > > > >> [0] https://groups.google.com/forum/#!topic/fa.linux.kernel/F6i9o8sfOIw
> > > > >> [1] https://marc.info/?l=devicetree&m=147669165104431&w=2
> > > > >
> > > > >
> > > > > Hi Marek,
> > > > >
> > > > > By Jones's comments:
> > > > >
> > --------------------------------------------------------------------------
> > > > >> From: Shunquan Lin <[email protected]>
> > > > >>
> > > > >> This patch adds driver support for HiSilicon Flash Memory
> > > > >> Controller(FMC). HiSilicon FMC is a multi-functions device which
> > > > >> supports SPI Nor flash controller, SPI nand Flash controller and
> > > > >> parallel nand flash controller.
> > > > >
> > > > > MFDs are for devices which span multiple subsystems.
> > > >
> > > > And we do! One of the subdrivers will live under drivers/
> > spi/, the other
> > > > under drivers/mtd/...
> > > >
> > >
> > > From my point of view, I think Jones mean to MFD's subsystems are
> > working simultaneously
> > > at the run-time, one period of time is working for sub-device-1
> > and later period of time
> > > is working for sub-device-2 and so on.
> > >
> > > But for RPC-IF, SPI or HF mode is decided at boot time by pins
> > configure and later in kernel
> > > by dtb, RPC-IF can't switch SPI and HF mode at the run time.
> >
> > > So far, Jones seems don't agree RPC-IF to MFD and then RPC MFD
> > will not applied
> > > to mfd tree by him !
> >
> > There's precedence for such constructs being an MFD: please see
> > drivers/mfd/at91-usart.c, which registers a single MFD cell for either
> > serial or SPI.
>
> okay, many thanks for your information.
>
> How about to patch RPF-IF dts to:
> -------------------------------------------------------------->
>
> Renesas R-Car Gen3 RPC-IF controller Device Tree Bindings
> ---------------------------------------------------------
>
> RPC-IF supports both SPI NOR and HyperFlash (CFI-compliant flash)
>
> Required properties:
> - compatible: should be an SoC-specific compatible value, followed by
> "renesas,rcar-gen3-rpc" as a fallback.
> supported SoC-specific values are:
> "renesas,r8a77995-rpc" (R-Car D3)
> - reg: should contain three register areas:
> first for the base address of RPC-IF registers,
> second for the direct mapping read mode and
> third for the write buffer area.
> - reg-names: should contain "regs", "dirmap" and "wbuf"
> - clocks: should contain 1 entries for the module's clock
> - clock-names: should contain "rpc"
>
> Example:
> - SPI mode:
>
> rpc: rpc-if@ee200000 {
> compatible = "renesas,r8a77995-rpc", "renesas,rcar-gen3-rpc";
> reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x4000000>,
> <0 0xee208000 0 0x100>;
> reg-names = "regs", "dirmap", "wbuf";
> clocks = <&cpg CPG_MOD 917>;
> clock-names = "rpc";
> power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> resets = <&cpg 917>;
> #address-cells = <1>;
> #size-cells = <0>;
>
> flash@0 {
> compatible = "jedec,spi-nor";
> reg = <0>;
> spi-max-frequency = <40000000>;
> spi-tx-bus-width = <1>;
> spi-rx-bus-width = <1>;
> };
> };
>
> - HF mode:
> rpc: rpc-if@ee200000 {
> compatible = "renesas,r8a77995-rpc", "renesas,rcar-gen3-rpc";
> reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x4000000>,
> <0 0xee208000 0 0x100>;
> reg-names = "regs", "dirmap", "wbuf";
> clocks = <&cpg CPG_MOD 917>;
> clock-names = "rpc";
> power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> resets = <&cpg 917>;
> #address-cells = <1>;
> #size-cells = <1>;
>
> flash@0 {
> compatible = "cfi-flash";
> reg = <0 0x4000000>;
> };
> };
>
> --------------------------------------------------------------<
>
> Is it OK ?

I'll defer to the MTD experts.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

2019-05-13 19:53:43

[permalink] [raw]

Subject: Re: [PATCH v12 3/3] dt-bindings: mfd: Document Renesas R-Car Gen3 RPC-IF MFD bindings

Hello!

On 05/13/2019 12:37 PM, [email protected] wrote:

>> > > [...]
>> > > >> > >> > On 4/24/19 11:23 PM, Rob Herring wrote:
>> > > >> > >> > > On Wed, Apr 24, 2019 at 03:55:36PM +0800, Mason Yang wrote:
>> > > >> > >> > >> Document the bindings used by the Renesas R-Car
>> Gen3 RPC-IF MFD.
>> > > >> > >> > >>
>> > > >> > >> > >> Signed-off-by: Mason Yang <[email protected]>
>> > > >> > >> > >> ---
>> > > >> > >> > >> .../devicetree/bindings/mfd/mfd-renesas-rpc.txt
>> | 40 ++++++
>> > > >> > >> ++++++++++++++++
>> > > >> > >> > >> 1 file changed, 40 insertions(+)
>> > > >> > >> > >> create mode 100644 Documentation/devicetree/
>> bindings/mfd/mfd-
>> > > >> > >> renesas-rpc.txt
>> > > >> > >> > >>
>> > > >> > >> > >> diff --git a/Documentation/devicetree/bindings/mfd/
>> mfd-renesas-
>> > > >> > >> rpc.txt b/Documentation/devicetree/bindings/mfd/mfd-
>> renesas-rpc.txt
>> > > >> > >> > >> new file mode 100644
>> > > >> > >> > >> index 0000000..668b822
>> > > >> > >> > >> --- /dev/null
>> > > >> > >> > >> +++ b/Documentation/devicetree/bindings/mfd/mfd-
>> renesas-rpc.txt
>> > > >> > >> > >> @@ -0,0 +1,40 @@
>> > > >> > >> > >> +Renesas R-Car Gen3 RPC-IF MFD Device Tree Bindings
>> > > >> > >> > >> +--------------------------------------------------
>> > > >> > >> > >
>> > > >> > >> > > Looks like a SPI flash controller from the example. What
>> > > makes it an
>> > > >> > >> > > MFD?
>> > > >> > >> >
>> > > >> > >> > It supports both SPI NOR and HyperFlash (CFI-compliantflash with
>> > > >> > >> > different bus interface).
>> > > >> > >>
>> > > >> > >> Looks like you're registering one OR the other.
>> > > >> > >>
>> > > >> > >> Why don't you just do this from DT?
>> > > >> > >>
>> > > >> > >> No reason for this to be an MFD IMHO.
>> > > >> > >
>> > > >> > >
>> > > >> > > okay, I will patch it back to SPI mode only.
>> > > >> >
>> > > >> > I don't think that's what Lee meant . The controller supports _both_
>> > > >> > modes , hence it would have the same compatible string. You
>> just need to
>> > > >> > extract the mode of operation from the DT.
>> > > >>
>> > > >> HiSilicon attempted to upstream something similar, only their
>> > > >> controller provided NAND and NOR functionality. They used different
>> > > >> compatible strings to differentiate between the varying
>> > > >> technologies.
>> > > >>
>> > > >> They too tried to use MFD as a means to select between them (which was
>> > > >> also NACKed). Not sure what they ended up doing, but the original
>> > > >> submission and (half of) the conversation can be found at [0]. Some
>> > > >> more of the thread continues at [1].
>> > > >>
>> > > >> Hope that helps.
>> > > >>
>> > > >> [0] https://groups.google.com/forum/#!topic/fa.linux.kernel/F6i9o8sfOIw
>> > > >> [1] https://marc.info/?l=devicetree&m=147669165104431&w=2
>> > > >
>> > > >
>> > > > Hi Marek,
>> > > >
>> > > > By Jones's comments:
>> > > >
>> --------------------------------------------------------------------------
>> > > >> From: Shunquan Lin <[email protected]>
>> > > >>
>> > > >> This patch adds driver support for HiSilicon Flash Memory
>> > > >> Controller(FMC). HiSilicon FMC is a multi-functions device which
>> > > >> supports SPI Nor flash controller, SPI nand Flash controller and
>> > > >> parallel nand flash controller.
>> > > >
>> > > > MFDs are for devices which span multiple subsystems.
>> > >
>> > > And we do! One of the subdrivers will live under drivers/
>> spi/, the other
>> > > under drivers/mtd/...
>> > >
>> >
>> > From my point of view, I think Jones mean to MFD's subsystems are
>> working simultaneously
>> > at the run-time, one period of time is working for sub-device-1
>> and later period of time
>> > is working for sub-device-2 and so on.
>> >
>> > But for RPC-IF, SPI or HF mode is decided at boot time by pins
>> configure and later in kernel
>> > by dtb, RPC-IF can't switch SPI and HF mode at the run time.
>>
>> > So far, Jones seems don't agree RPC-IF to MFD and then RPC MFD
>> will not applied
>> > to mfd tree by him !
>>
>> There's precedence for such constructs being an MFD: please see
>> drivers/mfd/at91-usart.c, which registers a single MFD cell for either
>> serial or SPI.

Thanks fir your example, Geert! :-)

> okay, many thanks for your information.
>
> How about to patch RPF-IF dts to:
> -------------------------------------------------------------->
>
> Renesas R-Car Gen3 RPC-IF controller Device Tree Bindings
> ---------------------------------------------------------
>
> RPC-IF supports both SPI NOR and HyperFlash (CFI-compliant flash)
>
> Required properties:
> - compatible: should be an SoC-specific compatible value, followed by
> "renesas,rcar-gen3-rpc" as a fallback.
> supported SoC-specific values are:
> "renesas,r8a77995-rpc" (R-Car D3)
> - reg: should contain three register areas:
> first for the base address of RPC-IF registers,

I'd drop "the base address" here.

> second for the direct mapping read mode and
> third for the write buffer area.
> - reg-names: should contain "regs", "dirmap" and "wbuf"
> - clocks: should contain 1 entries for the module's clock
> - clock-names: should contain "rpc"

I suspect we'd need the RPC/RPCD2 clocks mentioned as well (not sure yet)...
And how about "power-domains", "resets" (seen in the example below),
also what about #address-cells & #size-cells?

>
> Example:

Could you please indent with 1 or 2 tabs where you used 8 or 16 spaces?

> - SPI mode:
>
> rpc: rpc-if@ee200000 {

The node names should be generic, based on the device class. And in this
case I'd like to use "spi@ee200000" as otherwise dtc keeps bitching like below:

arch/arm64/boot/dts/renesas/r8a77980.dtsi:1344.21-1359.5: Warning (spi_bus_bridge):
/soc/rpc@ee200000: node name for SPI buses should be 'spi'
also defined at arch/arm64/boot/dts/renesas/r8a77980-condor.dts:283.6-343.3
arch/arm64/boot/dts/renesas/r8a77980-condor.dtb: Warning (spi_bus_reg):
Failed prerequisite 'spi_bus_bridge'

> - HF mode:
> rpc: rpc-if@ee200000 {

Again, spi@<...>.

> compatible = "renesas,r8a77995-rpc", "renesas,rcar-gen3-rpc";
> reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x4000000>,
> <0 0xee208000 0 0x100>;
> reg-names = "regs", "dirmap", "wbuf";
> clocks = <&cpg CPG_MOD 917>;
> clock-names = "rpc";
> power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> resets = <&cpg 917>;
> #address-cells = <1>;
> #size-cells = <1>;
>
> flash@0 {
> compatible = "cfi-flash";

The working HF implementation has "cypress,hyperflash" before "cfi-flash".

> reg = <0 0x4000000>;
> };
> };
>
> --------------------------------------------------------------<
>
> Is it OK ?

Yeah, seems good (assuming you fix the issues above).

[...]
> thanks & best regards,
> Mason

MBR, Sergei

2019-05-14 02:34:44

[permalink] [raw]

Subject: Re: [PATCH v12 3/3] dt-bindings: mfd: Document Renesas R-Car Gen3 RPC-IF MFD bindings

Hi Geert,

> Subject
>
> Re: [PATCH v12 3/3] dt-bindings: mfd: Document Renesas R-Car Gen3 RPC-IF
MFD bindings
>
> Hi Mason,
>
> Note that if you send multipart/text+html emails, they will be dropped
silently
> by most Linux mailing lists.
> Hence I'm quoting your last email fully, to give other people a chance
> reading it (and commenting).

Thanks for your remind !
I have configured my Lotus Notes to plain text mode only and it should be
OK
for Linux mailing lists now.

thanks & best regards,
Mason

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=====================================================================

============================================================================

CONFIDENTIALITY NOTE:

This e-mail and any attachments may contain confidential information and/or personal data, which is protected by applicable laws. Please be reminded that duplication, disclosure, distribution, or use of this e-mail (and/or its attachments) or any part thereof is prohibited. If you receive this e-mail in error, please notify us immediately and delete this mail as well as its attachment(s) from your system. In addition, please be informed that collection, processing, and/or use of personal data is prohibited unless expressly permitted by personal data protection laws. Thank you for your attention and cooperation.

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=====================================================================

2019-05-14 06:54:59

[permalink] [raw]

Subject: Re: [PATCH v12 2/3] spi: Add Renesas R-Car Gen3 RPC-IF SPI controller driver

On Wed, 24 Apr 2019, Mason Yang wrote:

> Add a driver for Renesas R-Car Gen3 RPC-IF SPI controller.
>
> Signed-off-by: Mason Yang <[email protected]>
> Signed-off-by: Sergei Shtylyov <[email protected]>
> ---
> drivers/spi/Kconfig | 6 +
> drivers/spi/Makefile | 1 +
> drivers/spi/spi-renesas-rpc.c | 571 ++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 578 insertions(+)
> create mode 100644 drivers/spi/spi-renesas-rpc.c
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index f761655..1f52bcf 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -564,6 +564,12 @@ config SPI_RSPI
> help
> SPI driver for Renesas RSPI and QSPI blocks.
>
> +config SPI_RENESAS_RPC
> + tristate "Renesas R-Car Gen3 RPC-IF controller"
> + depends on ARCH_RENESAS || COMPILE_TEST
> + help
> + SPI driver for Renesas R-Car Gen3 RPC-IF.
> +
> config SPI_QCOM_QSPI
> tristate "QTI QSPI controller"
> depends on ARCH_QCOM
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index d8fc03c..b3a3deb 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -86,6 +86,7 @@ obj-$(CONFIG_SPI_QUP) += spi-qup.o
> obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o
> obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o
> obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
> +obj-$(CONFIG_SPI_RENESAS_RPC) += spi-renesas-rpc.o
> obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
> spi-s3c24xx-hw-y := spi-s3c24xx.o
> spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o
> diff --git a/drivers/spi/spi-renesas-rpc.c b/drivers/spi/spi-renesas-rpc.c
> new file mode 100644
> index 0000000..c2202d4
> --- /dev/null
> +++ b/drivers/spi/spi-renesas-rpc.c
> @@ -0,0 +1,571 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (C) 2018 ~ 2019 Renesas Solutions Corp.
> +// Copyright (C) 2019 Macronix International Co., Ltd.
> +//
> +// R-Car Gen3 RPC-IF SPI/QSPI/Octa driver
> +//
> +// Author:
> +// Mason Yang <[email protected]>
> +//
> +
> +#include <linux/clk.h>
> +#include <linux/io.h>
> +#include <linux/log2.h>
> +#include <linux/iopoll.h>
> +#include <linux/mfd/renesas-rpc.h>
> +#include <linux/module.h>
> +#include <linux/mtd/mtd.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +#include <linux/spi/spi.h>
> +#include <linux/spi/spi-mem.h>
> +
> +#include <asm/unaligned.h>
> +
> +struct rpc_spi {
> + struct rpc_mfd *mfd;

The term MFD isn't a real thing. What you're obtaining below is
driver data and is normally articulated as 'ddata' in drivers.

> + u32 cur_speed_hz;
> + u32 cmd;
> + u32 addr;
> + u32 dummy;
> + u32 smcr;
> + u32 smenr;
> + u32 xferlen;
> + u32 totalxferlen;
> + enum spi_mem_data_dir xfer_dir;
> +};

[...]

> +static void rpc_spi_hw_init(struct rpc_spi *rpc)
> +{
> + //
> + // NOTE: The 0x260 are undocumented bits, but they must be set.
> + // RPC_PHYCNT_STRTIM is strobe timing adjustment bit,
> + // 0x0 : the delay is biggest,
> + // 0x1 : the delay is 2nd biggest,
> + // On H3 ES1.x, the value should be 0, while on others,
> + // the value should be 6.
> + //

C++ style comments? Is that a thing now?

> + regmap_write(rpc->mfd->regmap, RPC_PHYCNT, RPC_PHYCNT_CAL |
> + RPC_PHYCNT_STRTIM(6) | 0x260);
> +
> + //
> + // NOTE: The 0x1511144 are undocumented bits, but they must be set
> + // for RPC_PHYOFFSET1.
> + // The 0x31 are undocumented bits, but they must be set
> + // for RPC_PHYOFFSET2.
> + //
> + regmap_write(rpc->mfd->regmap, RPC_PHYOFFSET1,
> + RPC_PHYOFFSET1_DDRTMG(3) | 0x1511144);
> + regmap_write(rpc->mfd->regmap, RPC_PHYOFFSET2, 0x31 |
> + RPC_PHYOFFSET2_OCTTMG(4));
> + regmap_write(rpc->mfd->regmap, RPC_SSLDR, RPC_SSLDR_SPNDL(7) |
> + RPC_SSLDR_SLNDL(7) | RPC_SSLDR_SCKDL(7));
> + regmap_write(rpc->mfd->regmap, RPC_CMNCR, RPC_CMNCR_MD |
> + RPC_CMNCR_SFDE | RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ |
> + RPC_CMNCR_BSZ(0));
> +}

--
Lee Jones [李琼斯]
Linaro Services Technical Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

2019-05-14 09:48:37

[permalink] [raw]

Subject: Re: [PATCH v12 3/3] dt-bindings: mfd: Document Renesas R-Car Gen3 RPC-IF MFD bindings

Hello,

> >> There's precedence for such constructs being an MFD: please see
> >> drivers/mfd/at91-usart.c, which registers a single MFD cell for
either
> >> serial or SPI.
>
> Thanks fir your example, Geert! :-)
>
> > okay, many thanks for your information.
> >
> > How about to patch RPF-IF dts to:
> > -------------------------------------------------------------->
> >
> > Renesas R-Car Gen3 RPC-IF controller Device Tree Bindings
> > ---------------------------------------------------------
> >
> > RPC-IF supports both SPI NOR and HyperFlash (CFI-compliant flash)
> >
> > Required properties:
> > - compatible: should be an SoC-specific compatible value, followed
by
> > "renesas,rcar-gen3-rpc" as a fallback.
> > supported SoC-specific values are:
> > "renesas,r8a77995-rpc" (R-Car D3)
> > - reg: should contain three register areas:
> > first for the base address of RPC-IF registers,
>
> I'd drop "the base address" here.

okay.

>
> > second for the direct mapping read mode and
> > third for the write buffer area.
> > - reg-names: should contain "regs", "dirmap" and "wbuf"
> > - clocks: should contain 1 entries for the module's clock
> > - clock-names: should contain "rpc"
>
> I suspect we'd need the RPC/RPCD2 clocks mentioned as well (not sure
yet)...

Need it ?
RPCD2 is derived from RPC and it's value is half of RPC,
i.e., RPC = 160MHz, RPCD2 = 80 MHz

> And how about "power-domains", "resets" (seen in the example below),
> also what about #address-cells & #size-cells?
>
> >
> > Example:
>
> Could you please indent with 1 or 2 tabs where you used 8 or 16
spaces?
>
> > - SPI mode:
> >
> > rpc: rpc-if@ee200000 {
>
> The node names should be generic, based on the device class. And in
this
> case I'd like to use "spi@ee200000" as otherwise dtc keeps bitching like
below:

okay, patch to

rpc_if: spi@<...>

>
> arch/arm64/boot/dts/renesas/r8a77980.dtsi:1344.21-1359.5: Warning
(spi_bus_bridge):
> /soc/rpc@ee200000: node name for SPI buses should be 'spi'
> also defined at
arch/arm64/boot/dts/renesas/r8a77980-condor.dts:283.6-343.3
> arch/arm64/boot/dts/renesas/r8a77980-condor.dtb: Warning (spi_bus_reg):
> Failed prerequisite 'spi_bus_bridge'
>
>
> > - HF mode:
> > rpc: rpc-if@ee200000 {
>
> Again, spi@<...>.

what about rpc_if: hf@<...>

>
> > compatible = "renesas,r8a77995-rpc",
"renesas,rcar-gen3-rpc";
> > reg = <0 0xee200000 0 0x200>, <0 0x08000000 0
0x4000000>,
> > <0 0xee208000 0 0x100>;
> > reg-names = "regs", "dirmap", "wbuf";
> > clocks = <&cpg CPG_MOD 917>;
> > clock-names = "rpc";
> > power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> > resets = <&cpg 917>;
> > #address-cells = <1>;
> > #size-cells = <1>;
> >
> > flash@0 {
> > compatible = "cfi-flash";
>
> The working HF implementation has "cypress,hyperflash" before
"cfi-flash".
>
> > reg = <0 0x4000000>;
> > };
> > };
> >
> > --------------------------------------------------------------<
> >
> > Is it OK ?
>
> Yeah, seems good (assuming you fix the issues above).

Patch new DTS to
===============================================================>

+Renesas R-Car Gen3 RPC-IF controller Device Tree Bindings
+---------------------------------------------------------
+
+RPC-IF supports both SPI NOR and HyperFlash (CFI-compliant flash)
+
+Required properties:
+- compatible: should be an SoC-specific compatible value, followed by
+ "renesas,rcar-gen3-rpc" as a fallback.
+ supported SoC-specific values are:
+ "renesas,r8a77995-rpc" (R-Car
D3)
+- reg: should contain three register areas:
+ first for RPC-IF registers,
+ second for the direct mapping read mode and
+ third for the write buffer area.
+- reg-names: should contain "regs", "dirmap" and "wbuf"
+- clocks: should contain 1 entries for the module's clock
+- clock-names: should contain "rpc"
+- #address-cells: should be 1
+- #size-cells: should be 0
+
+Example:
+- SPI mode:
+
+ rpc_if: spi@ee200000 {
+ compatible = "renesas,r8a77995-rpc",
"renesas,rcar-gen3-rpc";
+ reg = <0 0xee200000 0 0x200>, <0
0x08000000 0 0x4000000>,
+ <0 0xee208000 0 0x100>;
+ reg-names = "regs", "dirmap", "wbuf";
+ clocks = <&cpg CPG_MOD 917>;
+ clock-names = "rpc";
+ power-domains = <&sysc
R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 917>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash@0 {
+ compatible =
"jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency =
<40000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ };
+ };
+
+- HF mode:
+ rpc_if: hf@ee200000 {
+ compatible = "renesas,r8a77995-rpc",
"renesas,rcar-gen3-rpc";
+ reg = <0 0xee200000 0 0x200>, <0
0x08000000 0 0x4000000>,
+ <0 0xee208000 0 0x100>;
+ reg-names = "regs", "dirmap", "wbuf";
+ clocks = <&cpg CPG_MOD 917>;
+ clock-names = "rpc";
+ power-domains = <&sysc
R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 917>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash@0 {
+ compatible =
"cypress,hyperflash", "cfi-flash";
+ reg = <0>;
+ };
+ };

=======================================================================<

OK ?

thanks & best regards,
Mason

CONFIDENTIALITY NOTE:

This e-mail and any attachments may contain confidential information
and/or personal data, which is protected by applicable laws. Please be
reminded that duplication, disclosure, distribution, or use of this e-mail
(and/or its attachments) or any part thereof is prohibited. If you receive
this e-mail in error, please notify us immediately and delete this mail as
well as its attachment(s) from your system. In addition, please be
informed that collection, processing, and/or use of personal data is
prohibited unless expressly permitted by personal data protection laws.
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2019-05-14 10:09:27

[permalink] [raw]

Subject: Re: [PATCH v12 3/3] dt-bindings: mfd: Document Renesas R-Car Gen3 RPC-IF MFD bindings

Hi Mason,

On Tue, May 14, 2019 at 11:46 AM <[email protected]> wrote:
> > >> There's precedence for such constructs being an MFD: please see
> > >> drivers/mfd/at91-usart.c, which registers a single MFD cell for
> > > second for the direct mapping read mode and
> > > third for the write buffer area.
> > > - reg-names: should contain "regs", "dirmap" and "wbuf"
> > > - clocks: should contain 1 entries for the module's clock
> > > - clock-names: should contain "rpc"
> >
> > I suspect we'd need the RPC/RPCD2 clocks mentioned as well (not sure
> yet)...
>
> Need it ?
> RPCD2 is derived from RPC and it's value is half of RPC,
> i.e., RPC = 160MHz, RPCD2 = 80 MHz

That hierarchy depends on the actual SoC, right?
AFAIU, both are derived from RPCSRC, and can be controlled individually
on some SoCs.

BTW, I still haven't seen a patch for drivers/clk/renesas/r8a77995-cpg-mssr.c
adding RPC-related clocks, so I have no idea what's the Linux view of the
hierarchy on your system.

Thanks!

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

2019-05-14 10:36:23

[permalink] [raw]

Subject: Re: [PATCH v12 3/3] dt-bindings: mfd: Document Renesas R-Car Gen3 RPC-IF MFD bindings

Hi Sergei,

> >
> > Could you please indent with 1 or 2 tabs where you used 8 or 16
spaces?

Sorry, I just copy this new DTS from git to my Notes email system,
therefore, the "tabs space" is not alignment with original file.

>
> Patch new DTS to
> ===============================================================>
>
> +Renesas R-Car Gen3 RPC-IF controller Device Tree Bindings
> +---------------------------------------------------------
> +
> +RPC-IF supports both SPI NOR and HyperFlash (CFI-compliant flash)
> +
> +Required properties:
> +- compatible: should be an SoC-specific compatible value, followed by
> + "renesas,rcar-gen3-rpc" as a fallback.
> + supported SoC-specific values are:
> + "renesas,r8a77995-rpc" (R-Car D3)
> +- reg: should contain three register areas:
> + first for RPC-IF registers,
> + second for the direct mapping read mode and
> + third for the write buffer area.
> +- reg-names: should contain "regs", "dirmap" and "wbuf"
> +- clocks: should contain 1 entries for the module's clock
> +- clock-names: should contain "rpc"
> +- #address-cells: should be 1
> +- #size-cells: should be 0
> +
> +Example:
> +- SPI mode:
> +
> + rpc_if: spi@ee200000 {
> + compatible = "renesas,r8a77995-rpc", "renesas,rcar-gen3-rpc";
> + reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x4000000>,
> + <0 0xee208000 0 0x100>;
> + reg-names = "regs", "dirmap", "wbuf";
> + clocks = <&cpg CPG_MOD 917>;
> + clock-names = "rpc";
> + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> + resets = <&cpg 917>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + flash@0 {
> + compatible = "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <40000000>;
> + spi-tx-bus-width = <1>;
> + spi-rx-bus-width = <1>;
> + };
> + };
> +
> +- HF mode:
> + rpc_if: hf@ee200000 {
> + compatible = "renesas,r8a77995-rpc", "renesas,rcar-gen3-rpc";
> + reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x4000000>,
> + <0 0xee208000 0 0x100>;
> + reg-names = "regs", "dirmap", "wbuf";
> + clocks = <&cpg CPG_MOD 917>;
> + clock-names = "rpc";
> + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> + resets = <&cpg 917>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + flash@0 {
> + compatible = "cypress,hyperflash", "cfi-flash";
> + reg = <0>;
> + };
> + };
>
> =======================================================================<

thanks for your review.

best regards,
Mason

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2019-05-14 20:30:48

[permalink] [raw]

Subject: Re: [PATCH v12 3/3] dt-bindings: mfd: Document Renesas R-Car Gen3 RPC-IF MFD bindings

On 05/14/2019 12:46 PM, [email protected] wrote:

>>>> There's precedence for such constructs being an MFD: please see
>>>> drivers/mfd/at91-usart.c, which registers a single MFD cell for
> either
>>>> serial or SPI.
>>
>> Thanks fir your example, Geert! :-)

s/fir/for/, not the firtree season anymore. :-)

>>> okay, many thanks for your information.
>>>
>>> How about to patch RPF-IF dts to:
>>> -------------------------------------------------------------->
>>>
>>> Renesas R-Car Gen3 RPC-IF controller Device Tree Bindings
>>> ---------------------------------------------------------
>>>
>>> RPC-IF supports both SPI NOR and HyperFlash (CFI-compliant flash)
>>>
>>> Required properties:
>>> - compatible: should be an SoC-specific compatible value, followed
> by
>>> "renesas,rcar-gen3-rpc" as a fallback.
>>> supported SoC-specific values are:
>>> "renesas,r8a77995-rpc" (R-Car D3)
>>> - reg: should contain three register areas:
>>> first for the base address of RPC-IF registers,
>>
>> I'd drop "the base address" here.
>
> okay.
>
>>> second for the direct mapping read mode and
>>> third for the write buffer area.
>>> - reg-names: should contain "regs", "dirmap" and "wbuf"
>>> - clocks: should contain 1 entries for the module's clock
>>> - clock-names: should contain "rpc"
>>
>> I suspect we'd need the RPC/RPCD2 clocks mentioned as well (not sure
> yet)...
>
> Need it ?

You seem to call clk_get_rate() on the module clock, I doubt that's
correct topologically...

> RPCD2 is derived from RPC and it's value is half of RPC,
> i.e., RPC = 160MHz, RPCD2 = 80 MHz

I know.

>> And how about "power-domains", "resets" (seen in the example below),
>> also what about #address-cells & #size-cells?
>>
>>>
>>> Example:
>>
>> Could you please indent with 1 or 2 tabs where you used 8 or 16
> spaces?
>>
>>> - SPI mode:
>>>
>>> rpc: rpc-if@ee200000 {
>>
>> The node names should be generic, based on the device class. And in
> this
>> case I'd like to use "spi@ee200000" as otherwise dtc keeps bitching like
> below:
>
> okay, patch to
>
> rpc_if: spi@<...>

That, or just keep the node label.

>> arch/arm64/boot/dts/renesas/r8a77980.dtsi:1344.21-1359.5: Warning
> (spi_bus_bridge):
>> /soc/rpc@ee200000: node name for SPI buses should be 'spi'
>> also defined at
> arch/arm64/boot/dts/renesas/r8a77980-condor.dts:283.6-343.3
>> arch/arm64/boot/dts/renesas/r8a77980-condor.dtb: Warning (spi_bus_reg):
>> Failed prerequisite 'spi_bus_bridge'
>>
>>
>>> - HF mode:
>>> rpc: rpc-if@ee200000 {
>>
>> Again, spi@<...>.
>
> what about rpc_if: hf@<...>

Can't change the node name, as it's declared in the .dtsi files, not *.dts
ones. And "spi" works for the HF case as well -- no complaints from dtc. :-)

>>> compatible = "renesas,r8a77995-rpc",
> "renesas,rcar-gen3-rpc";
>>> reg = <0 0xee200000 0 0x200>, <0 0x08000000 0
> 0x4000000>,
>>> <0 0xee208000 0 0x100>;
>>> reg-names = "regs", "dirmap", "wbuf";
>>> clocks = <&cpg CPG_MOD 917>;
>>> clock-names = "rpc";
>>> power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
>>> resets = <&cpg 917>;
>>> #address-cells = <1>;
>>> #size-cells = <1>;
>>>
>>> flash@0 {
>>> compatible = "cfi-flash";
>>
>> The working HF implementation has "cypress,hyperflash" before
> "cfi-flash".
>>
>>> reg = <0 0x4000000>;
>>> };
>>> };
>>>
>>> --------------------------------------------------------------<
>>>
>>> Is it OK ?
>>
>> Yeah, seems good (assuming you fix the issues above).
>
> Patch new DTS to
> ===============================================================>
>
> +Renesas R-Car Gen3 RPC-IF controller Device Tree Bindings
> +---------------------------------------------------------
> +
> +RPC-IF supports both SPI NOR and HyperFlash (CFI-compliant flash)
> +
> +Required properties:
> +- compatible: should be an SoC-specific compatible value, followed by
> + "renesas,rcar-gen3-rpc" as a fallback.
> + supported SoC-specific values are:
> + "renesas,r8a77995-rpc" (R-Car
> D3)
> +- reg: should contain three register areas:
> + first for RPC-IF registers,
> + second for the direct mapping read mode and
> + third for the write buffer area.
> +- reg-names: should contain "regs", "dirmap" and "wbuf"
> +- clocks: should contain 1 entries for the module's clock
> +- clock-names: should contain "rpc"
> +- #address-cells: should be 1
> +- #size-cells: should be 0

Still nothing about the "oower-domains" and "resets" props... :-(

> +
> +Example:
> +- SPI mode:
> +
> + rpc_if: spi@ee200000 {
> + compatible = "renesas,r8a77995-rpc",
> "renesas,rcar-gen3-rpc";
> + reg = <0 0xee200000 0 0x200>, <0
> 0x08000000 0 0x4000000>,
> + <0 0xee208000 0 0x100>;
> + reg-names = "regs", "dirmap", "wbuf";
> + clocks = <&cpg CPG_MOD 917>;
> + clock-names = "rpc";
> + power-domains = <&sysc
> R8A77995_PD_ALWAYS_ON>;
> + resets = <&cpg 917>;
> + #address-cells = <1>;
> + #size-cells = <0>;
[...]
> =======================================================================<
>
> OK ?

Yes, with the remaining issue fixed.

> thanks & best regards,
> Mason

[...]

MBR, Sergei

2019-05-15 05:56:52

[permalink] [raw]

Subject: Re: [PATCH v12 2/3] spi: Add Renesas R-Car Gen3 RPC-IF SPI controller driver

Hi Jones,

> > +
> > +struct rpc_spi {
> > + struct rpc_mfd *mfd;
>
> The term MFD isn't a real thing. What you're obtaining below is
> driver data and is normally articulated as 'ddata' in drivers.

yes, it's just imply that data is from MFD.

Should I rename "mfd" ?

>
> > + u32 cur_speed_hz;
> > + u32 cmd;
> > + u32 addr;
> > + u32 dummy;
> > + u32 smcr;
> > + u32 smenr;
> > + u32 xferlen;
> > + u32 totalxferlen;
> > + enum spi_mem_data_dir xfer_dir;
> > +};
>
> [...]
>
> > +static void rpc_spi_hw_init(struct rpc_spi *rpc)
> > +{
> > + //
> > + // NOTE: The 0x260 are undocumented bits, but they must be set.
> > + // RPC_PHYCNT_STRTIM is strobe timing adjustment bit,
> > + // 0x0 : the delay is biggest,
> > + // 0x1 : the delay is 2nd biggest,
> > + // On H3 ES1.x, the value should be 0, while on others,
> > + // the value should be 6.
> > + //
>
> C++ style comments? Is that a thing now?

It's kind of Mark's previous comments.

>
> > + regmap_write(rpc->mfd->regmap, RPC_PHYCNT, RPC_PHYCNT_CAL |
> > + RPC_PHYCNT_STRTIM(6) | 0x260);
> > +
> > + //
> > + // NOTE: The 0x1511144 are undocumented bits, but they must be set
> > + // for RPC_PHYOFFSET1.
> > + // The 0x31 are undocumented bits, but they must be set
> > + // for RPC_PHYOFFSET2.
> > + //
> > + regmap_write(rpc->mfd->regmap, RPC_PHYOFFSET1,
> > + RPC_PHYOFFSET1_DDRTMG(3) | 0x1511144);
> > + regmap_write(rpc->mfd->regmap, RPC_PHYOFFSET2, 0x31 |
> > + RPC_PHYOFFSET2_OCTTMG(4));
> > + regmap_write(rpc->mfd->regmap, RPC_SSLDR, RPC_SSLDR_SPNDL(7) |
> > + RPC_SSLDR_SLNDL(7) | RPC_SSLDR_SCKDL(7));
> > + regmap_write(rpc->mfd->regmap, RPC_CMNCR, RPC_CMNCR_MD |
> > + RPC_CMNCR_SFDE | RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ
|
> > + RPC_CMNCR_BSZ(0));
> > +}
>
> --
> Lee Jones [????˹]
> Linaro Services Technical Lead
> Linaro.org ?? Open source software for ARM SoCs
> Follow Linaro: Facebook | Twitter | Blog

thanks & best regards,
Mason

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2019-05-15 07:19:15

[permalink] [raw]

Subject: Re: [PATCH v12 2/3] spi: Add Renesas R-Car Gen3 RPC-IF SPI controller driver

On Wed, 15 May 2019, [email protected] wrote:

> Hi Jones,
>
>
> > > +
> > > +struct rpc_spi {
> > > + struct rpc_mfd *mfd;
> >
> > The term MFD isn't a real thing. What you're obtaining below is
> > driver data and is normally articulated as 'ddata' in drivers.
>
> yes, it's just imply that data is from MFD.
>
> Should I rename "mfd" ?

Yes please.

--
Lee Jones [李琼斯]
Linaro Services Technical Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

2019-05-20 07:33:12

[permalink] [raw]

Subject: Re: [PATCH v12 3/3] dt-bindings: mfd: Document Renesas R-Car Gen3 RPC-IF MFD bindings

Hi Sergei,

> >>> -------------------------------------------------------------->
> >>>
> >>> Renesas R-Car Gen3 RPC-IF controller Device Tree Bindings
> >>> ---------------------------------------------------------
> >>>
> >>> RPC-IF supports both SPI NOR and HyperFlash (CFI-compliant flash)
> >>>
> >>> Required properties:
> >>> - compatible: should be an SoC-specific compatible value, followed

> > by
> >>> "renesas,rcar-gen3-rpc" as a fallback.
> >>> supported SoC-specific values are:
> >>> "renesas,r8a77995-rpc" (R-Car D3)
> >>> - reg: should contain three register areas:
> >>> first for the base address of RPC-IF registers,
> >>
> >> I'd drop "the base address" here.
> >
> > okay.
> >
> >>> second for the direct mapping read mode and
> >>> third for the write buffer area.
> >>> - reg-names: should contain "regs", "dirmap" and "wbuf"
> >>> - clocks: should contain 1 entries for the module's clock
> >>> - clock-names: should contain "rpc"
> >>
> >> I suspect we'd need the RPC/RPCD2 clocks mentioned as well (not
sure
> > yet)...
> >
> > Need it ?
>
> You seem to call clk_get_rate() on the module clock, I doubt that's
> correct topologically...

I think it's correct but just like Geert mentioned that there is no any
patch
in drivers/clk/renesas/r8a77995-cpg-mssr.c adding RPC-related clocks.

I patched dt-bindings/clock/r8a77995-cpg-mssr.h for some simple testing

-#define R8A77995_CLK_RPC 29
-#define R8A77995_CLK_RPCD2 30
+#define R8A77995_CLK_RPC 31
+#define R8A77995_CLK_RPCD2 32

by clk_prepare_enable() & clk_disable_unprepare() with CPG_MOD 917
on D3 draak board, it is working fine.

> >>
> >>> - SPI mode:git
> >>>
> >>> rpc: rpc-if@ee200000 {
> >>
> >> The node names should be generic, based on the device class. And
in
> > this
> >> case I'd like to use "spi@ee200000" as otherwise dtc keeps bitching
like
> > below:
> >
> > okay, patch to
> >
> > rpc_if: spi@<...>
>
> That, or just keep the node label.

okay.

> >>> - HF mode:
> >>> rpc: rpc-if@ee200000 {
> >>
> >> Again, spi@<...>.
> >
> > what about rpc_if: hf@<...>
>
> Can't change the node name, as it's declared in the .dtsi files, not
*.dts
> ones. And "spi" works for the HF case as well -- no complaints from dtc.
:-)

okay,

Patch DTS to
===============================================================>
+Renesas R-Car Gen3 RPC-IF controller Device Tree Bindings
+---------------------------------------------------------
+
+RPC-IF supports both SPI NOR and HyperFlash (CFI-compliant flash)
+
+Required properties:
+- compatible: should be an SoC-specific compatible value, followed by
+ "renesas,rcar-gen3-rpc" as a fallback.
+ supported SoC-specific values are:
+ "renesas,r8a77995-rpc" (R-Car
D3)
+- reg: should contain three register areas:
+ first for RPC-IF registers,
+ second for the direct mapping read mode and
+ third for the write buffer area.
+- reg-names: should contain "regs", "dirmap" and "wbuf"
+- clocks: should contain 1 entries for the module's clock
+- clock-names: should contain "rpc"
+- power-domains: should contain system-controller(sysc) for
power-domain-cell
+- resets: should contain clock pulse generator(cpg) for reset-cell,
+ power-domain-cell and clock-cell
+- #address-cells: should be 1
+- #size-cells: should be 0
+
+Example:
+- SPI mode:
+
+ rpc: spi@ee200000 {
+ compatible = "renesas,r8a77995-rpc",
"renesas,rcar-gen3-rpc";
+ reg = <0 0xee200000 0 0x200>, <0
0x08000000 0 0x4000000>,
+ <0 0xee208000 0 0x100>;
+ reg-names = "regs", "dirmap", "wbuf";
+ clocks = <&cpg CPG_MOD 917>;
+ clock-names = "rpc";
+ power-domains = <&sysc
R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 917>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash@0 {
+ compatible =
"jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency =
<40000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ };
+ };
+
+- HF mode:
+ rpc: spi@ee200000 {
+ compatible = "renesas,r8a77995-rpc",
"renesas,rcar-gen3-rpc";
+ reg = <0 0xee200000 0 0x200>, <0
0x08000000 0 0x4000000>,
+ <0 0xee208000 0 0x100>;
+ reg-names = "regs", "dirmap", "wbuf";
+ clocks = <&cpg CPG_MOD 917>;
+ clock-names = "rpc";
+ power-domains = <&sysc
R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 917>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash@0 {
+ compatible =
"cypress,hyperflash", "cfi-flash";
+ reg = <0>;
+ };
+ };
===============================================================<

thanks & best regards,
Mason

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============================================================================

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2019-05-20 09:05:24

[permalink] [raw]

Subject: Re: [PATCH v12 3/3] dt-bindings: mfd: Document Renesas R-Car Gen3 RPC-IF MFD bindings

Hi Mason,

On Mon, May 20, 2019 at 9:24 AM <[email protected]> wrote:
> > >>> - clocks: should contain 1 entries for the module's clock
> > >>> - clock-names: should contain "rpc"
> > >>
> > >> I suspect we'd need the RPC/RPCD2 clocks mentioned as well (not
> sure
> > > yet)...
> > >
> > > Need it ?
> >
> > You seem to call clk_get_rate() on the module clock, I doubt that's
> > correct topologically...
>
> I think it's correct but just like Geert mentioned that there is no any
> patch
> in drivers/clk/renesas/r8a77995-cpg-mssr.c adding RPC-related clocks.
>
>
> I patched dt-bindings/clock/r8a77995-cpg-mssr.h for some simple testing
>
> -#define R8A77995_CLK_RPC 29
> -#define R8A77995_CLK_RPCD2 30
> +#define R8A77995_CLK_RPC 31
> +#define R8A77995_CLK_RPCD2 32

That change doesn't make sense to me...

> by clk_prepare_enable() & clk_disable_unprepare() with CPG_MOD 917
> on D3 draak board, it is working fine.

... and is not sufficient to allow the above two calls.

Besides, making explicit clk_prepare_enable() calls bypasses Runtime PM
and the automatic disabling of unused clocks, thus hiding bugs related to
Runtime PM. Which is probably why your driver doesn't work for Sergei...

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

2019-05-21 01:31:04

[permalink] [raw]

Subject: Re: [PATCH v12 3/3] dt-bindings: mfd: Document Renesas R-Car Gen3 RPC-IF MFD bindings

Hi Geert,

>
> On Mon, May 20, 2019 at 9:24 AM <[email protected]> wrote:
> > > >>> - clocks: should contain 1 entries for the module's clock
> > > >>> - clock-names: should contain "rpc"
> > > >>
> > > >> I suspect we'd need the RPC/RPCD2 clocks mentioned as well
(not
> > sure
> > > > yet)...
> > > >
> > > > Need it ?
> > >
> > > You seem to call clk_get_rate() on the module clock, I doubt
that's
> > > correct topologically...
> >
> > I think it's correct but just like Geert mentioned that there is no
any
> > patch
> > in drivers/clk/renesas/r8a77995-cpg-mssr.c adding RPC-related clocks.
> >
> >
> > I patched dt-bindings/clock/r8a77995-cpg-mssr.h for some simple
testing
> >
> > -#define R8A77995_CLK_RPC 29
> > -#define R8A77995_CLK_RPCD2 30
> > +#define R8A77995_CLK_RPC 31
> > +#define R8A77995_CLK_RPCD2 32
>
> That change doesn't make sense to me...
>
> > by clk_prepare_enable() & clk_disable_unprepare() with CPG_MOD 917
> > on D3 draak board, it is working fine.
>
> ... and is not sufficient to allow the above two calls.
>
> Besides, making explicit clk_prepare_enable() calls bypasses Runtime PM
> and the automatic disabling of unused clocks, thus hiding bugs related
to
> Runtime PM. Which is probably why your driver doesn't work for
Sergei...
>

Got it, thanks for your explanation.

best regards,
Mason

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2019-05-22 16:34:49

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Subject: Re: [PATCH v12 3/3] dt-bindings: mfd: Document Renesas R-Car Gen3 RPC-IF MFD bindings

On 05/20/2019 10:23 AM, [email protected] wrote:

>>>>> -------------------------------------------------------------->
>>>>>
>>>>> Renesas R-Car Gen3 RPC-IF controller Device Tree Bindings
>>>>> ---------------------------------------------------------
>>>>>
>>>>> RPC-IF supports both SPI NOR and HyperFlash (CFI-compliant flash)
>>>>>
>>>>> Required properties:
>>>>> - compatible: should be an SoC-specific compatible value, followed
>
>>> by
>>>>> "renesas,rcar-gen3-rpc" as a fallback.
>>>>> supported SoC-specific values are:
>>>>> "renesas,r8a77995-rpc" (R-Car D3)
>>>>> - reg: should contain three register areas:
>>>>> first for the base address of RPC-IF registers,
>>>>
>>>> I'd drop "the base address" here.
>>>
>>> okay.
>>>
>>>>> second for the direct mapping read mode and
>>>>> third for the write buffer area.
>>>>> - reg-names: should contain "regs", "dirmap" and "wbuf"
>>>>> - clocks: should contain 1 entries for the module's clock
>>>>> - clock-names: should contain "rpc"
>>>>
>>>> I suspect we'd need the RPC/RPCD2 clocks mentioned as well (not
> sure
>>> yet)...
>>>
>>> Need it ?
>>
>> You seem to call clk_get_rate() on the module clock, I doubt that's
>> correct topologically...

clk_set_rate(), sorry.

>
> I think it's correct but just like Geert mentioned that there is no any
> patch
> in drivers/clk/renesas/r8a77995-cpg-mssr.c adding RPC-related clocks.
>
>
> I patched dt-bindings/clock/r8a77995-cpg-mssr.h for some simple testing
>
> -#define R8A77995_CLK_RPC 29
> -#define R8A77995_CLK_RPCD2 30
> +#define R8A77995_CLK_RPC 31
> +#define R8A77995_CLK_RPCD2 32

Hm, what does this do?

> by clk_prepare_enable() & clk_disable_unprepare() with CPG_MOD 917
> on D3 draak board, it is working fine.

>>>>> - SPI mode:git
>>>>>
>>>>> rpc: rpc-if@ee200000 {
>>>>
>>>> The node names should be generic, based on the device class. And in
>>>> this
>>>> case I'd like to use "spi@ee200000" as otherwise dtc keeps bitching like
>>>> below:
>>>
>>> okay, patch to
>>>
>>> rpc_if: spi@<...>
>>
>> That, or just keep the node label.
>
> okay.
>
>>>>> - HF mode:
>>>>> rpc: rpc-if@ee200000 {
>>>>
>>>> Again, spi@<...>.
>>>
>>> what about rpc_if: hf@<...>
>>
>> Can't change the node name, as it's declared in the .dtsi files, not *.dts
>> ones. And "spi" works for the HF case as well -- no complaints from dtc.
> :-)

Maybe it's possible using the "name" prop, don't know...

> okay,
>
> Patch DTS to
> ===============================================================>
> +Renesas R-Car Gen3 RPC-IF controller Device Tree Bindings
> +---------------------------------------------------------
> +
> +RPC-IF supports both SPI NOR and HyperFlash (CFI-compliant flash)
> +
> +Required properties:
> +- compatible: should be an SoC-specific compatible value, followed by
> + "renesas,rcar-gen3-rpc" as a fallback.
> + supported SoC-specific values are:
> + "renesas,r8a77995-rpc" (R-Car
> D3)
> +- reg: should contain three register areas:
> + first for RPC-IF registers,
> + second for the direct mapping read mode and
> + third for the write buffer area.
> +- reg-names: should contain "regs", "dirmap" and "wbuf"
> +- clocks: should contain 1 entries for the module's clock

1 entry (clock node phandle and specifier).

> +- clock-names: should contain "rpc"
> +- power-domains: should contain system-controller(sysc) for
> power-domain-cell

What's "power-domain-cell"? I know "#power-domain-cells". I'd like this
to be "the power domain node's phandle and specifier".

> +- resets: should contain clock pulse generator(cpg) for reset-cell,

It's "#reset-cells" again. I'd like this to be "the reset node's phandle
and specifier".

> + power-domain-cell and clock-cell

Why mntion clock-cell at all here?

> +- #address-cells: should be 1
> +- #size-cells: should be 0
> +
> +Example:
> +- SPI mode:
> +
> + rpc: spi@ee200000 {
> + compatible = "renesas,r8a77995-rpc",
> "renesas,rcar-gen3-rpc";
> + reg = <0 0xee200000 0 0x200>, <0
> 0x08000000 0 0x4000000>,
> + <0 0xee208000 0 0x100>;
> + reg-names = "regs", "dirmap", "wbuf";
> + clocks = <&cpg CPG_MOD 917>;
> + clock-names = "rpc";
> + power-domains = <&sysc
> R8A77995_PD_ALWAYS_ON>;
> + resets = <&cpg 917>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + flash@0 {
> + compatible =
> "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency =
> <40000000>;
> + spi-tx-bus-width = <1>;
> + spi-rx-bus-width = <1>;
> + };
> + };
> +
> +- HF mode:

HyperFlash, please.

> + rpc: spi@ee200000 {
> + compatible = "renesas,r8a77995-rpc",
> "renesas,rcar-gen3-rpc";
> + reg = <0 0xee200000 0 0x200>, <0
> 0x08000000 0 0x4000000>,
> + <0 0xee208000 0 0x100>;
> + reg-names = "regs", "dirmap", "wbuf";
> + clocks = <&cpg CPG_MOD 917>;
> + clock-names = "rpc";
> + power-domains = <&sysc
> R8A77995_PD_ALWAYS_ON>;
> + resets = <&cpg 917>;
> + #address-cells = <1>;
> + #size-cells = <0>;

And I don't think duplicating the same device node is a good idea...

> + flash@0 {
> + compatible =
> "cypress,hyperflash", "cfi-flash";
> + reg = <0>;
> + };
> + };
> ===============================================================<
>
> thanks & best regards,
> Mason
[...]

MBR, Sergei

2019-05-22 17:25:48

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Subject: Re: [PATCH v12 3/3] dt-bindings: mfd: Document Renesas R-Car Gen3 RPC-IF MFD bindings

Hi Sergei,

On Wed, May 22, 2019 at 6:32 PM Sergei Shtylyov
<[email protected]> wrote:
> On 05/20/2019 10:23 AM, [email protected] wrote:
> > +- clocks: should contain 1 entries for the module's clock
>
> 1 entry (clock node phandle and specifier).

Doesn't "specifier" mean "phandle + optional arguments"?

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

2019-05-22 17:28:44

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Subject: Re: [PATCH v12 3/3] dt-bindings: mfd: Document Renesas R-Car Gen3 RPC-IF MFD bindings

On 05/22/2019 08:05 PM, Geert Uytterhoeven wrote:

>> On 05/20/2019 10:23 AM, [email protected] wrote:
>>> +- clocks: should contain 1 entries for the module's clock
>>
>> 1 entry (clock node phandle and specifier).
>
> Doesn't "specifier" mean "phandle + optional arguments"?

No.
E.g. when specifying the IRQs, the "interrupts" prop contains one or more
interrupt specifiers, the phandle is specified in the "interrupt-parent"
prop (see the DT spec).

> Gr{oetje,eeting}s,
>
> Geert

MBR, Sergei

2019-05-22 17:46:22