LinuxLists.cc - [PATCH v3 0/3] iio: adc: Add support for QCOM SPMI PMIC5 Gen3 ADC

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Subject: [PATCH v3 1/3] dt-bindings: iio/adc: Move QCOM ADC bindings to iio/adc folder

There are several files containing QCOM ADC macros for channel names
right now in the include/dt-bindings/iio folder. Since all of these
are specifically for adc, move the files to the
include/dt-bindings/iio/adc folder.

Also update all affected devicetree and driver files to fix compilation
errors seen with this move and update documentation files to fix
dtbinding check errors for the same.

Changes since v2:
- Updated some more new devicetree files requiring this change.

Acked-by: Lee Jones <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Jishnu Prakash <[email protected]>
---
.../devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml | 4 ++--
Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml | 2 +-
.../devicetree/bindings/thermal/qcom-spmi-adc-tm-hc.yaml | 2 +-
.../devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml | 6 +++---
arch/arm64/boot/dts/qcom/pm2250.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm6125.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm6150.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm6150l.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm660.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm660l.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm7250b.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8150.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8150b.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8150l.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8916.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8950.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8953.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8994.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8998.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pmi632.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pmi8950.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pmp8074.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pms405.dtsi | 2 +-
arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 4 ++--
arch/arm64/boot/dts/qcom/sc7280-idp.dts | 2 +-
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi | 2 +-
.../arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 6 +++---
arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 2 +-
arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 8 ++++----
drivers/iio/adc/qcom-spmi-adc5.c | 2 +-
drivers/iio/adc/qcom-spmi-vadc.c | 2 +-
include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pm7325.h | 2 +-
include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pm8350.h | 2 +-
.../dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pm8350b.h | 2 +-
.../dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pmk8350.h | 2 +-
.../dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pmr735a.h | 2 +-
.../dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pmr735b.h | 0
.../dt-bindings/iio/{ => adc}/qcom,spmi-adc7-smb139x.h | 0
include/dt-bindings/iio/{ => adc}/qcom,spmi-vadc.h | 0
42 files changed, 49 insertions(+), 49 deletions(-)
rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pm7325.h (98%)
rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pm8350.h (98%)
rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pm8350b.h (99%)
rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pmk8350.h (97%)
rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pmr735a.h (95%)
rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pmr735b.h (100%)
rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-smb139x.h (100%)
rename include/dt-bindings/iio/{ => adc}/qcom,spmi-vadc.h (100%)

diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
index 40fa0710f1f0..6e2ce30fe0ce 100644
--- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
@@ -277,8 +277,8 @@ examples:
};

- |
- #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
- #include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
+ #include <dt-bindings/iio/adc/qcom,spmi-adc7-pmk8350.h>
+ #include <dt-bindings/iio/adc/qcom,spmi-adc7-pm8350.h>
#include <dt-bindings/interrupt-controller/irq.h>

pmic {
diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
index 8103fb61a16c..0c2394301ca0 100644
--- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
+++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
@@ -268,7 +268,7 @@ examples:
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/iio/qcom,spmi-vadc.h>
+ #include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/spmi/spmi.h>

pmic@0 {
diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm-hc.yaml b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm-hc.yaml
index 7541e27704ca..147126c6a564 100644
--- a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm-hc.yaml
+++ b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm-hc.yaml
@@ -112,7 +112,7 @@ additionalProperties: false

examples:
- |
- #include <dt-bindings/iio/qcom,spmi-vadc.h>
+ #include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>

pmic {
diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml
index d9d2657287cb..e1b4a9fdd6af 100644
--- a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml
+++ b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml
@@ -165,7 +165,7 @@ additionalProperties: false

examples:
- |
- #include <dt-bindings/iio/qcom,spmi-vadc.h>
+ #include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>

pmic {
@@ -206,8 +206,8 @@ examples:
};

- |
- #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
- #include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
+ #include <dt-bindings/iio/adc/qcom,spmi-adc7-pmk8350.h>
+ #include <dt-bindings/iio/adc/qcom,spmi-adc7-pm8350.h>
#include <dt-bindings/interrupt-controller/irq.h>

pmic {
diff --git a/arch/arm64/boot/dts/qcom/pm2250.dtsi b/arch/arm64/boot/dts/qcom/pm2250.dtsi
index 5f1d15db5c99..a26466de03ad 100644
--- a/arch/arm64/boot/dts/qcom/pm2250.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm2250.dtsi
@@ -3,7 +3,7 @@
* Copyright (c) 2023, Linaro Ltd
*/

-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pm6125.dtsi b/arch/arm64/boot/dts/qcom/pm6125.dtsi
index 99369a0cdb61..c10625728d23 100644
--- a/arch/arm64/boot/dts/qcom/pm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm6125.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause

-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi
index ddbaf7280b03..844e77de1fa0 100644
--- a/arch/arm64/boot/dts/qcom/pm6150.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi
@@ -3,7 +3,7 @@
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*/

-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi
index d13a1ab7c20b..208b5ec8dca6 100644
--- a/arch/arm64/boot/dts/qcom/pm6150l.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm6150l.dtsi
@@ -3,7 +3,7 @@
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*/

-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>

diff --git a/arch/arm64/boot/dts/qcom/pm660.dtsi b/arch/arm64/boot/dts/qcom/pm660.dtsi
index 98dc04962fe3..bc5ce1ae9920 100644
--- a/arch/arm64/boot/dts/qcom/pm660.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm660.dtsi
@@ -3,7 +3,7 @@
* Copyright (c) 2020, Konrad Dybcio
*/

-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pm660l.dtsi b/arch/arm64/boot/dts/qcom/pm660l.dtsi
index 6fdbf507c262..c16dc3c4a6a3 100644
--- a/arch/arm64/boot/dts/qcom/pm660l.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm660l.dtsi
@@ -3,7 +3,7 @@
* Copyright (c) 2020, Konrad Dybcio
*/

-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pm7250b.dtsi b/arch/arm64/boot/dts/qcom/pm7250b.dtsi
index 3bf7cf5d1700..e5ea669795a3 100644
--- a/arch/arm64/boot/dts/qcom/pm7250b.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm7250b.dtsi
@@ -3,7 +3,7 @@
* Copyright (C) 2022 Luca Weiss <[email protected]>
*/

-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>

diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi
index 3ba3ba5d8fce..5dbfebc43847 100644
--- a/arch/arm64/boot/dts/qcom/pm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi
@@ -7,7 +7,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>

/ {
thermal-zones {
diff --git a/arch/arm64/boot/dts/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/pm8150b.dtsi
index 1aee3270ce7b..68d612d4277d 100644
--- a/arch/arm64/boot/dts/qcom/pm8150b.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8150b.dtsi
@@ -4,7 +4,7 @@
* Copyright (c) 2019, Linaro Limited
*/

-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>

diff --git a/arch/arm64/boot/dts/qcom/pm8150l.dtsi b/arch/arm64/boot/dts/qcom/pm8150l.dtsi
index ac08a09c64c2..a0b89a43baf0 100644
--- a/arch/arm64/boot/dts/qcom/pm8150l.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8150l.dtsi
@@ -4,7 +4,7 @@
* Copyright (c) 2019, Linaro Limited
*/

-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>

diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi
index 4b2e8fb47d2d..79059b263e5f 100644
--- a/arch/arm64/boot/dts/qcom/pm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pm8950.dtsi b/arch/arm64/boot/dts/qcom/pm8950.dtsi
index f03095779de0..33b401c9e70d 100644
--- a/arch/arm64/boot/dts/qcom/pm8950.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8950.dtsi
@@ -5,7 +5,7 @@
* Copyright (c) 2022, Marijn Suijten <[email protected]>
*/

-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
diff --git a/arch/arm64/boot/dts/qcom/pm8953.dtsi b/arch/arm64/boot/dts/qcom/pm8953.dtsi
index 1067e141be6c..5e2a7a3783b5 100644
--- a/arch/arm64/boot/dts/qcom/pm8953.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8953.dtsi
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/* Copyright (c) 2022, The Linux Foundation. All rights reserved. */

-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi
index d44a95caf04a..cfa4eb5723a6 100644
--- a/arch/arm64/boot/dts/qcom/pm8994.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi
index 3f82715392c6..26f46f898eb6 100644
--- a/arch/arm64/boot/dts/qcom/pm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/* Copyright 2018 Google LLC. */

-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pmi632.dtsi b/arch/arm64/boot/dts/qcom/pmi632.dtsi
index 4eb79e0ce40a..09f7af85d39b 100644
--- a/arch/arm64/boot/dts/qcom/pmi632.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmi632.dtsi
@@ -3,7 +3,7 @@
* Copyright (C) 2023 Luca Weiss <[email protected]>
*/

-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>

diff --git a/arch/arm64/boot/dts/qcom/pmi8950.dtsi b/arch/arm64/boot/dts/qcom/pmi8950.dtsi
index 1029f3b1bb9a..6fd1acdab640 100644
--- a/arch/arm64/boot/dts/qcom/pmi8950.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmi8950.dtsi
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2019, AngeloGioacchino Del Regno <[email protected]>

-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>

diff --git a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi
index dbd4b91dfe06..6d95a1352db1 100644
--- a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi
@@ -6,7 +6,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>

/ {
thermal-zones {
diff --git a/arch/arm64/boot/dts/qcom/pmp8074.dtsi b/arch/arm64/boot/dts/qcom/pmp8074.dtsi
index 0d0a846ac8d9..9f3e4121d834 100644
--- a/arch/arm64/boot/dts/qcom/pmp8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmp8074.dtsi
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause

#include <dt-bindings/spmi/spmi.h>
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>

&spmi_bus {
pmic@0 {
diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi
index 461ad97032f7..673a8ea5b64d 100644
--- a/arch/arm64/boot/dts/qcom/pms405.dtsi
+++ b/arch/arm64/boot/dts/qcom/pms405.dtsi
@@ -5,7 +5,7 @@

#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/thermal/thermal.h>

/ {
diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts
index 176898c9dbbd..58d4abbd3275 100644
--- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts
+++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts
@@ -9,8 +9,8 @@
#define PM7250B_SID 8
#define PM7250B_SID1 9

-#include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pm7325.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pmk8350.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
index b5fe7356be48..1dd4aa300f7f 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
@@ -7,7 +7,7 @@

/dts-v1/;

-#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pmr735a.h>
#include "sc7280-idp.dtsi"
#include "pmr735a.dtsi"

diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index a0059527d9e4..ba853a881616 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -5,7 +5,7 @@
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/

-#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pmk8350.h>
#include <dt-bindings/input/linux-event-codes.h>
#include "sc7280.dtsi"
#include "pm7325.dtsi"
diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
index f9b96bd2477e..ecd17cbaa966 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
@@ -11,8 +11,8 @@
* Copyright 2022 Google LLC.
*/

-#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pmk8350.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pmr735a.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>

diff --git a/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi
index ddc84282f142..931a8d911229 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi
@@ -7,7 +7,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>

/ {
thermal-zones {
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
index def3976bd5bb..4e4f276aebd5 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
@@ -7,9 +7,9 @@
/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pm8350.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pmk8350.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pmr735a.h>
#include <dt-bindings/input/gpio-keys.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
index ade619805519..c20abdf34eb7 100644
--- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
+++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
@@ -14,7 +14,7 @@

#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pmk8350.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
index a20d5d76af35..aff019dccd46 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
@@ -6,10 +6,10 @@
/dts-v1/;

#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pm8350b.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pm8350.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pm8350b.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pmk8350.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pmr735a.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include "sm8450.dtsi"
#include "pm8350.dtsi"
diff --git a/drivers/iio/adc/qcom-spmi-adc5.c b/drivers/iio/adc/qcom-spmi-adc5.c
index b6b612d733ff..4225952001f3 100644
--- a/drivers/iio/adc/qcom-spmi-adc5.c
+++ b/drivers/iio/adc/qcom-spmi-adc5.c
@@ -20,7 +20,7 @@
#include <linux/regmap.h>
#include <linux/slab.h>

-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>

#define ADC5_USR_REVISION1 0x0
#define ADC5_USR_STATUS1 0x8
diff --git a/drivers/iio/adc/qcom-spmi-vadc.c b/drivers/iio/adc/qcom-spmi-vadc.c
index f5c6f1f27b2c..c3602c53968a 100644
--- a/drivers/iio/adc/qcom-spmi-vadc.c
+++ b/drivers/iio/adc/qcom-spmi-vadc.c
@@ -20,7 +20,7 @@
#include <linux/slab.h>
#include <linux/log2.h>

-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>

/* VADC register and bit definitions */
#define VADC_REVISION2 0x1
diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pm7325.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pm7325.h
similarity index 98%
rename from include/dt-bindings/iio/qcom,spmi-adc7-pm7325.h
rename to include/dt-bindings/iio/adc/qcom,spmi-adc7-pm7325.h
index 96908014e09e..f0ab57078ca4 100644
--- a/include/dt-bindings/iio/qcom,spmi-adc7-pm7325.h
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pm7325.h
@@ -10,7 +10,7 @@
#define PM7325_SID 1
#endif

-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>

/* ADC channels for PM7325_ADC for PMIC7 */
#define PM7325_ADC7_REF_GND (PM7325_SID << 8 | ADC7_REF_GND)
diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pm8350.h
similarity index 98%
rename from include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h
rename to include/dt-bindings/iio/adc/qcom,spmi-adc7-pm8350.h
index 5d98f7d48a1e..ef818248ec8c 100644
--- a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pm8350.h
@@ -6,7 +6,7 @@
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H

-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>

/* ADC channels for PM8350_ADC for PMIC7 */
#define PM8350_ADC7_REF_GND(sid) ((sid) << 8 | ADC7_REF_GND)
diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pm8350b.h
similarity index 99%
rename from include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h
rename to include/dt-bindings/iio/adc/qcom,spmi-adc7-pm8350b.h
index 57c7977666d3..d841bf00b7b0 100644
--- a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pm8350b.h
@@ -10,7 +10,7 @@
#define PM8350B_SID 3
#endif

-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>

/* ADC channels for PM8350B_ADC for PMIC7 */
#define PM8350B_ADC7_REF_GND (PM8350B_SID << 8 | ADC7_REF_GND)
diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmk8350.h
similarity index 97%
rename from include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h
rename to include/dt-bindings/iio/adc/qcom,spmi-adc7-pmk8350.h
index 3d1a41a22cef..161b211ec126 100644
--- a/include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmk8350.h
@@ -10,7 +10,7 @@
#define PMK8350_SID 0
#endif

-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>

/* ADC channels for PMK8350_ADC for PMIC7 */
#define PMK8350_ADC7_REF_GND (PMK8350_SID << 8 | ADC7_REF_GND)
diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735a.h
similarity index 95%
rename from include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h
rename to include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735a.h
index c5adfa82b20d..fedc9e3882b8 100644
--- a/include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735a.h
@@ -10,7 +10,7 @@
#define PMR735A_SID 4
#endif

-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>

/* ADC channels for PMR735A_ADC for PMIC7 */
#define PMR735A_ADC7_REF_GND (PMR735A_SID << 8 | ADC7_REF_GND)
diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735b.h
similarity index 100%
rename from include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h
rename to include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735b.h
diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-smb139x.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h
similarity index 100%
rename from include/dt-bindings/iio/qcom,spmi-adc7-smb139x.h
rename to include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h
diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h
similarity index 100%
rename from include/dt-bindings/iio/qcom,spmi-vadc.h
rename to include/dt-bindings/iio/adc/qcom,spmi-vadc.h
--
2.25.1

2023-12-31 17:14:43

[permalink] [raw]

Subject: [PATCH v3 2/3] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC

For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the
following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs.

It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs
going through PBS(Programmable Boot Sequence) firmware through a single
register interface. This interface is implemented on an SDAM (Shared
Direct Access Memory) peripheral on the master PMIC PMK8550 rather
than a dedicated ADC peripheral.

Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC
channels and virtual channels (combination of ADC channel number and
PMIC SID number) per PMIC, to be used by clients of this device.

Changes since v2:
- Moved ADC5 Gen3 documentation into a separate new file.

Changes since v1:
- Updated properties separately for all compatibles to clarify usage
of new properties and updates in usage of old properties for ADC5 Gen3.
- Avoided updating 'adc7' name to 'adc5 gen2' and just left a comment
mentioning this convention.
- Used predefined channel IDs in individual PMIC channel definitions
instead of numeric IDs.
- Addressed other comments from reviewers.

Co-developed-by: Anjelique Melendez <[email protected]>
Signed-off-by: Anjelique Melendez <[email protected]>
Signed-off-by: Jishnu Prakash <[email protected]>
---
.../bindings/iio/adc/qcom,spmi-adc5-gen3.yaml | 212 ++++++++++++++++++
.../iio/adc/qcom,spmi-adc5-gen3-pm8550.h | 50 +++++
.../iio/adc/qcom,spmi-adc5-gen3-pm8550b.h | 89 ++++++++
.../iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h | 22 ++
.../iio/adc/qcom,spmi-adc5-gen3-pmk8550.h | 56 +++++
.../iio/adc/qcom,spmi-adc7-pmr735b.h | 2 +-
.../iio/adc/qcom,spmi-adc7-smb139x.h | 2 +-
include/dt-bindings/iio/adc/qcom,spmi-vadc.h | 81 +++++++
8 files changed, 512 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h

diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml
new file mode 100644
index 000000000000..ed5bb53e7628
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml
@@ -0,0 +1,212 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-adc5-gen3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm's SPMI PMIC ADC5 Gen3
+
+maintainers:
+ - Jishnu Prakash <[email protected]>
+
+description: |
+ SPMI PMIC5 Gen3 voltage ADC (ADC) provides interface to
+ clients to read voltage. It is a 16-bit sigma-delta ADC.
+ It also performs the same thermal monitoring function as
+ the existing ADC_TM devices.
+
+properties:
+ compatible:
+ const: qcom,spmi-adc5-gen3
+
+ reg:
+ description: |
+ - Each reg corresponds to an SDAM peripheral base address that is being used for ADC.
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ "#thermal-sensor-cells":
+ const: 1
+ description:
+ Number of cells required to uniquely identify the thermal sensors. Since
+ we have multiple sensors this is set to 1. This property is required for
+ ADC devices with channels used for TM (thermal monitoring) functionality.
+
+ '#io-channel-cells':
+ const: 1
+
+ interrupts:
+ description: |
+ End of conversion interrupt. Interrupts are defined for each SDAM being used.
+
+ interrupt-names:
+ minItems: 1
+ maxItems: 10
+ items:
+ pattern: "^adc-sdam[0-9]+$"
+ description: |
+ Names should be defined as "adc-sdam<N>" where <N> represents the SDAM index.
+
+required:
+ - compatible
+ - reg
+ - '#address-cells'
+ - '#size-cells'
+ - '#io-channel-cells'
+ - interrupts
+ - interrupt-names
+
+patternProperties:
+ "^channel@[0-9a-f]+$":
+ type: object
+ additionalProperties: false
+ description: |
+ Represents the external channels which are connected to the ADC.
+
+ properties:
+ reg:
+ maxItems: 1
+ description: |
+ ADC channel number.
+ See include/dt-bindings/iio/adc/qcom,spmi-vadc.h
+ For PMIC5 Gen3 ADC, the channel numbers are specified separately
+ per PMIC in the PMIC-specific files in include/dt-bindings/iio/adc.
+
+ label:
+ $ref: /schemas/types.yaml#/definitions/string
+ description: |
+ ADC input of the platform as seen in the schematics.
+ For thermistor inputs connected to generic AMUX or GPIO inputs
+ these can vary across platform for the same pins. Hence select
+ the platform schematics name for this channel.
+
+ qcom,decimation:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ This parameter is used to decrease ADC sampling rate.
+ Quicker measurements can be made by reducing decimation ratio.
+ enum: [ 85, 340, 1360 ]
+ default: 1360
+
+ qcom,pre-scaling:
+ description: |
+ Used for scaling the channel input signal before the signal is
+ fed to VADC. The configuration for this node is to know the
+ pre-determined ratio and use it for post scaling. It is a pair of
+ integers, denoting the numerator and denominator of the fraction by which
+ input signal is multiplied. For example, <1 3> indicates the signal is scaled
+ down to 1/3 of its value before ADC measurement.
+ If property is not found default value depending on chip will be used.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - const: 1
+ - enum: [ 1, 3, 6, 16 ]
+
+ qcom,ratiometric:
+ description: |
+ Channel calibration type.
+ - If this property is specified VADC will use the VDD reference (1.875V)
+ and GND for channel calibration. If property is not found, channel will be
+ calibrated with 0V and 1.25V reference channels, also known as
+ absolute calibration.
+ type: boolean
+
+ qcom,hw-settle-time:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Time between AMUX getting configured and the ADC starting
+ conversion. The 'hw_settle_time' is an index used from valid values
+ and programmed in hardware to achieve the hardware settling delay.
+ enum: [ 15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000,
+ 8000, 16000, 32000, 64000, 128000 ]
+ default: 15
+
+ qcom,avg-samples:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Number of samples to be used for measurement.
+ Averaging provides the option to obtain a single measurement
+ from the ADC that is an average of multiple samples. The value
+ selected is 2^(value).
+ enum: [ 1, 2, 4, 8, 16 ]
+ default: 1
+
+ qcom,adc-tm:
+ description: |
+ Indicates if ADC_TM monitoring is done on this channel.
+ Defined for compatible property "qcom,spmi-adc5-gen3".
+ This is the same functionality as in the existing QCOM ADC_TM
+ device, documented at devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml.
+ type: boolean
+
+ required:
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h>
+ #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h>
+ #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h>
+ #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ pmic {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* VADC node */
+ pmk8550_vadc: vadc@9000 {
+ compatible = "qcom,spmi-adc5-gen3";
+ reg = <0x9000>, <0x9100>;
+ interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "adc-sdam0", "adc-sdam1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+ #thermal-sensor-cells = <1>;
+
+ /* PMK8550 Channel nodes */
+ channel@3 {
+ reg = <PMK8550_ADC5_GEN3_DIE_TEMP>;
+ label = "pmk8550_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@44 {
+ reg = <PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU>;
+ label = "pmk8550_xo_therm";
+ qcom,pre-scaling = <1 1>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,adc-tm;
+ };
+
+ /* PM8550 Channel nodes */
+ channel@103 {
+ reg = <PM8550_ADC5_GEN3_DIE_TEMP>;
+ label = "pm8550_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ /* PM8550B Channel nodes */
+ channel@78f {
+ reg = <PM8550B_ADC5_GEN3_VBAT_SNS_QBG>;
+ label = "pm8550b_vbat_sns_qbg";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ /* PM8550VS_C Channel nodes */
+ channel@203 {
+ reg = <PM8550VS_ADC5_GEN3_DIE_TEMP(2)>;
+ label = "pm8550vs_c_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+ };
+ };
diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h
new file mode 100644
index 000000000000..0f25ef87ed5c
--- /dev/null
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H
+
+#ifndef PM8550_SID
+#define PM8550_SID 1
+#endif
+
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
+
+/* ADC channels for PM8550_ADC for PMIC5 Gen3 */
+#define PM8550_ADC5_GEN3_REF_GND (PM8550_SID << 8 | ADC5_GEN3_REF_GND)
+#define PM8550_ADC5_GEN3_1P25VREF (PM8550_SID << 8 | ADC5_GEN3_1P25VREF)
+#define PM8550_ADC5_GEN3_VREF_VADC (PM8550_SID << 8 | ADC5_GEN3_VREF_VADC)
+#define PM8550_ADC5_GEN3_DIE_TEMP (PM8550_SID << 8 | ADC5_GEN3_DIE_TEMP)
+
+#define PM8550_ADC5_GEN3_AMUX_THM1 (PM8550_SID << 8 | ADC5_GEN3_AMUX1_THM)
+#define PM8550_ADC5_GEN3_AMUX_THM2 (PM8550_SID << 8 | ADC5_GEN3_AMUX2_THM)
+#define PM8550_ADC5_GEN3_AMUX_THM3 (PM8550_SID << 8 | ADC5_GEN3_AMUX3_THM)
+#define PM8550_ADC5_GEN3_AMUX_THM4 (PM8550_SID << 8 | ADC5_GEN3_AMUX4_THM)
+#define PM8550_ADC5_GEN3_AMUX_THM5 (PM8550_SID << 8 | ADC5_GEN3_AMUX5_THM)
+#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2 (PM8550_SID << 8 | ADC5_GEN3_AMUX6_THM)
+#define PM8550_ADC5_GEN3_AMUX1_GPIO3 (PM8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO)
+#define PM8550_ADC5_GEN3_AMUX2_GPIO4 (PM8550_SID << 8 | ADC5_GEN3_AMUX2_GPIO)
+#define PM8550_ADC5_GEN3_AMUX3_GPIO7 (PM8550_SID << 8 | ADC5_GEN3_AMUX3_GPIO)
+#define PM8550_ADC5_GEN3_AMUX4_GPIO12 (PM8550_SID << 8 | ADC5_GEN3_AMUX4_GPIO)
+
+/* 100k pull-up */
+#define PM8550_ADC5_GEN3_AMUX_THM1_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX1_THM_100K_PU)
+#define PM8550_ADC5_GEN3_AMUX_THM2_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX2_THM_100K_PU)
+#define PM8550_ADC5_GEN3_AMUX_THM3_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX3_THM_100K_PU)
+#define PM8550_ADC5_GEN3_AMUX_THM4_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX4_THM_100K_PU)
+#define PM8550_ADC5_GEN3_AMUX_THM5_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX5_THM_100K_PU)
+#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX6_THM_100K_PU)
+#define PM8550_ADC5_GEN3_AMUX1_GPIO3_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO_100K_PU)
+#define PM8550_ADC5_GEN3_AMUX2_GPIO4_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX2_GPIO_100K_PU)
+#define PM8550_ADC5_GEN3_AMUX3_GPIO7_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX3_GPIO_100K_PU)
+#define PM8550_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX4_GPIO_100K_PU)
+
+/* 1/3 Divider */
+#define PM8550_ADC5_GEN3_AMUX3_GPIO7_DIV3 (PM8550_SID << 8 | ADC5_GEN3_AMUX3_GPIO_DIV3)
+#define PM8550_ADC5_GEN3_AMUX4_GPIO12_DIV3 (PM8550_SID << 8 | ADC5_GEN3_AMUX4_GPIO_DIV3)
+
+#define PM8550_ADC5_GEN3_VPH_PWR (PM8550_SID << 8 | ADC5_GEN3_VPH_PWR)
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H */
diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h
new file mode 100644
index 000000000000..47116bbe45de
--- /dev/null
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H
+
+#ifndef PM8550B_SID
+#define PM8550B_SID 7
+#endif
+
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
+
+/* ADC channels for PM8550B_ADC for PMIC5 Gen3 */
+#define PM8550B_ADC5_GEN3_REF_GND (PM8550B_SID << 8 | ADC5_GEN3_REF_GND)
+#define PM8550B_ADC5_GEN3_1P25VREF (PM8550B_SID << 8 | ADC5_GEN3_1P25VREF)
+#define PM8550B_ADC5_GEN3_VREF_VADC (PM8550B_SID << 8 | ADC5_GEN3_VREF_VADC)
+#define PM8550B_ADC5_GEN3_DIE_TEMP (PM8550B_SID << 8 | ADC5_GEN3_DIE_TEMP)
+
+#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_THM)
+#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_THM)
+#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_THM)
+#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_THM)
+#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION (PM8550B_SID << 8 | ADC5_GEN3_AMUX5_THM)
+#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10 (PM8550B_SID << 8 | ADC5_GEN3_AMUX6_THM)
+#define PM8550B_ADC5_GEN3_AMUX1_GPIO1 (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_GPIO)
+#define PM8550B_ADC5_GEN3_AMUX2_GPIO5 (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_GPIO)
+#define PM8550B_ADC5_GEN3_AMUX3_GPIO6 (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_GPIO)
+#define PM8550B_ADC5_GEN3_AMUX4_GPIO12 (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_GPIO)
+
+#define PM8550B_ADC5_GEN3_CHG_TEMP (PM8550B_SID << 8 | ADC5_GEN3_CHG_TEMP)
+#define PM8550B_ADC5_GEN3_USB_SNS_V_16 (PM8550B_SID << 8 | ADC5_GEN3_USB_SNS_V_16)
+#define PM8550B_ADC5_GEN3_VIN_DIV16_MUX (PM8550B_SID << 8 | ADC5_GEN3_VIN_DIV16_MUX)
+#define PM8550B_ADC5_GEN3_VREF_BAT_THERM (PM8550B_SID << 8 | ADC5_GEN3_VREF_BAT_THERM)
+#define PM8550B_ADC5_GEN3_IIN_FB (PM8550B_SID << 8 | ADC5_GEN3_IIN_FB)
+#define PM8550B_ADC5_GEN3_TEMP_ALARM_LITE (PM8550B_SID << 8 | ADC5_GEN3_TEMP_ALARM_LITE)
+#define PM8550B_ADC5_GEN3_SMB_IIN (PM8550B_SID << 8 | ADC5_GEN3_IIN_SMB)
+#define PM8550B_ADC5_GEN3_SMB_ICHG (PM8550B_SID << 8 | ADC5_GEN3_ICHG_SMB)
+#define PM8550B_ADC5_GEN3_ICHG_FB (PM8550B_SID << 8 | ADC5_GEN3_ICHG_FB)
+
+/* 30k pull-up */
+#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_THM_30K_PU)
+#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_THM_30K_PU)
+#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_THM_30K_PU)
+#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_THM_30K_PU)
+#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX5_THM_30K_PU)
+#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX6_THM_30K_PU)
+#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_GPIO_30K_PU)
+#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_GPIO_30K_PU)
+#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_GPIO_30K_PU)
+#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_GPIO_30K_PU)
+
+/* 100k pull-up */
+#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_THM_100K_PU)
+#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_THM_100K_PU)
+#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_THM_100K_PU)
+#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_THM_100K_PU)
+#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX5_THM_100K_PU)
+#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX6_THM_100K_PU)
+#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_GPIO_100K_PU)
+#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_GPIO_100K_PU)
+#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_GPIO_100K_PU)
+#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_GPIO_100K_PU)
+
+/* 400k pull-up */
+#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_THM_400K_PU)
+#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_THM_400K_PU)
+#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_THM_400K_PU)
+#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_THM_400K_PU)
+#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX5_THM_400K_PU)
+#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX6_THM_400K_PU)
+#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_GPIO_400K_PU)
+#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_GPIO_400K_PU)
+#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_GPIO_400K_PU)
+#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_GPIO_400K_PU)
+
+/* 1/3 Divider */
+#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_DIV3 (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_GPIO_DIV3)
+#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_DIV3 (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_GPIO_DIV3)
+#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_DIV3 (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_GPIO_DIV3)
+
+#define PM8550B_ADC5_GEN3_VPH_PWR (PM8550B_SID << 8 | ADC5_GEN3_VPH_PWR)
+#define PM8550B_ADC5_GEN3_VBAT_SNS_QBG (PM8550B_SID << 8 | ADC5_GEN3_VBAT_SNS_QBG)
+#define PM8550B_ADC5_GEN3_VBAT_SNS_CHGR (PM8550B_SID << 8 | ADC5_GEN3_VBAT_SNS_CHGR)
+#define PM8550B_ADC5_GEN3_VBAT_2S_MID_QBG (PM8550B_SID << 8 | ADC5_GEN3_VBAT_2S_MID_QBG)
+#define PM8550B_ADC5_GEN3_VBAT_2S_MID_CHGR (PM8550B_SID << 8 | ADC5_GEN3_VBAT_2S_MID_CHGR)
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H */
diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h
new file mode 100644
index 000000000000..360f2245d582
--- /dev/null
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H
+
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
+
+/* ADC channels for PM8550VX_ADC for PMIC5 Gen3 */
+#define PM8550VS_ADC5_GEN3_REF_GND(sid) ((sid) << 8 | ADC5_GEN3_REF_GND)
+#define PM8550VS_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | ADC5_GEN3_1P25VREF)
+#define PM8550VS_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | ADC5_GEN3_VREF_VADC)
+#define PM8550VS_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | ADC5_GEN3_DIE_TEMP)
+
+#define PM8550VE_ADC5_GEN3_OFFSET_REF(sid) ((sid) << 8 | ADC5_GEN3_REF_GND)
+#define PM8550VE_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | ADC5_GEN3_1P25VREF)
+#define PM8550VE_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | ADC5_GEN3_VREF_VADC)
+#define PM8550VE_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | ADC5_GEN3_DIE_TEMP)
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H */
diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h
new file mode 100644
index 000000000000..3fc829ebdf6d
--- /dev/null
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H
+
+#ifndef PMK8550_SID
+#define PMK8550_SID 0
+#endif
+
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
+
+/* ADC channels for PMK8550_ADC for PMIC5 Gen3 */
+#define PMK8550_ADC5_GEN3_REF_GND (PMK8550_SID << 8 | ADC5_GEN3_REF_GND)
+#define PMK8550_ADC5_GEN3_1P25VREF (PMK8550_SID << 8 | ADC5_GEN3_1P25VREF)
+#define PMK8550_ADC5_GEN3_VREF_VADC (PMK8550_SID << 8 | ADC5_GEN3_VREF_VADC)
+#define PMK8550_ADC5_GEN3_DIE_TEMP (PMK8550_SID << 8 | ADC5_GEN3_DIE_TEMP)
+
+#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_THM)
+#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1 (PMK8550_SID << 8 | ADC5_GEN3_AMUX2_THM)
+#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2 (PMK8550_SID << 8 | ADC5_GEN3_AMUX3_THM)
+#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3 (PMK8550_SID << 8 | ADC5_GEN3_AMUX4_THM)
+#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4 (PMK8550_SID << 8 | ADC5_GEN3_AMUX5_THM)
+#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5 (PMK8550_SID << 8 | ADC5_GEN3_AMUX6_THM)
+#define PMK8550_ADC5_GEN3_AMUX1_GPIO6 (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO)
+
+/* 30k pull-up */
+#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_THM_30K_PU)
+#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX2_THM_30K_PU)
+#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX3_THM_30K_PU)
+#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX4_THM_30K_PU)
+#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX5_THM_30K_PU)
+#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX6_THM_30K_PU)
+#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO_30K_PU)
+
+/* 100k pull-up */
+#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_THM_100K_PU)
+#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX2_THM_100K_PU)
+#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX3_THM_100K_PU)
+#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX4_THM_100K_PU)
+#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX5_THM_100K_PU)
+#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX6_THM_100K_PU)
+#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO_100K_PU)
+
+/* 400k pull-up */
+#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_THM_400K_PU)
+#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX2_THM_400K_PU)
+#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX3_THM_400K_PU)
+#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX4_THM_400K_PU)
+#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX5_THM_400K_PU)
+#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX6_THM_400K_PU)
+#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO_400K_PU)
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H */
diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735b.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735b.h
index fdb8dd9ae541..812f33872e5e 100644
--- a/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735b.h
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735b.h
@@ -10,7 +10,7 @@
#define PMR735B_SID 5
#endif

-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>

/* ADC channels for PMR735B_ADC for PMIC7 */
#define PMR735B_ADC7_REF_GND (PMR735B_SID << 8 | ADC7_REF_GND)
diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h
index c0680d1285cf..750a526af2c1 100644
--- a/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h
@@ -6,7 +6,7 @@
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_SMB139X_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_SMB139X_H

-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>

#define SMB139x_1_ADC7_SMB_TEMP (SMB139x_1_SID << 8 | ADC7_SMB_TEMP)
#define SMB139x_1_ADC7_ICHG_SMB (SMB139x_1_SID << 8 | ADC7_ICHG_SMB)
diff --git a/include/dt-bindings/iio/adc/qcom,spmi-vadc.h b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h
index ef07ecd4d585..cfe653d945a4 100644
--- a/include/dt-bindings/iio/adc/qcom,spmi-vadc.h
+++ b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h
@@ -1,6 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/

#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H
@@ -300,4 +302,83 @@
#define ADC7_SBUx 0x94
#define ADC7_VBAT_2S_MID 0x96

+/* ADC channels for PMIC5 Gen3 */
+
+#define ADC5_GEN3_REF_GND 0x00
+#define ADC5_GEN3_1P25VREF 0x01
+#define ADC5_GEN3_VREF_VADC 0x02
+#define ADC5_GEN3_DIE_TEMP 0x03
+
+#define ADC5_GEN3_AMUX1_THM 0x04
+#define ADC5_GEN3_AMUX2_THM 0x05
+#define ADC5_GEN3_AMUX3_THM 0x06
+#define ADC5_GEN3_AMUX4_THM 0x07
+#define ADC5_GEN3_AMUX5_THM 0x08
+#define ADC5_GEN3_AMUX6_THM 0x09
+#define ADC5_GEN3_AMUX1_GPIO 0x0a
+#define ADC5_GEN3_AMUX2_GPIO 0x0b
+#define ADC5_GEN3_AMUX3_GPIO 0x0c
+#define ADC5_GEN3_AMUX4_GPIO 0x0d
+
+#define ADC5_GEN3_CHG_TEMP 0x10
+#define ADC5_GEN3_USB_SNS_V_16 0x11
+#define ADC5_GEN3_VIN_DIV16_MUX 0x12
+#define ADC5_GEN3_VREF_BAT_THERM 0x15
+#define ADC5_GEN3_IIN_FB 0x17
+#define ADC5_GEN3_TEMP_ALARM_LITE 0x18
+#define ADC5_GEN3_IIN_SMB 0x19
+#define ADC5_GEN3_ICHG_SMB 0x1b
+#define ADC5_GEN3_ICHG_FB 0xa1
+
+/* 30k pull-up1 */
+#define ADC5_GEN3_AMUX1_THM_30K_PU 0x24
+#define ADC5_GEN3_AMUX2_THM_30K_PU 0x25
+#define ADC5_GEN3_AMUX3_THM_30K_PU 0x26
+#define ADC5_GEN3_AMUX4_THM_30K_PU 0x27
+#define ADC5_GEN3_AMUX5_THM_30K_PU 0x28
+#define ADC5_GEN3_AMUX6_THM_30K_PU 0x29
+#define ADC5_GEN3_AMUX1_GPIO_30K_PU 0x2a
+#define ADC5_GEN3_AMUX2_GPIO_30K_PU 0x2b
+#define ADC5_GEN3_AMUX3_GPIO_30K_PU 0x2c
+#define ADC5_GEN3_AMUX4_GPIO_30K_PU 0x2d
+
+/* 100k pull-up2 */
+#define ADC5_GEN3_AMUX1_THM_100K_PU 0x44
+#define ADC5_GEN3_AMUX2_THM_100K_PU 0x45
+#define ADC5_GEN3_AMUX3_THM_100K_PU 0x46
+#define ADC5_GEN3_AMUX4_THM_100K_PU 0x47
+#define ADC5_GEN3_AMUX5_THM_100K_PU 0x48
+#define ADC5_GEN3_AMUX6_THM_100K_PU 0x49
+#define ADC5_GEN3_AMUX1_GPIO_100K_PU 0x4a
+#define ADC5_GEN3_AMUX2_GPIO_100K_PU 0x4b
+#define ADC5_GEN3_AMUX3_GPIO_100K_PU 0x4c
+#define ADC5_GEN3_AMUX4_GPIO_100K_PU 0x4d
+
+/* 400k pull-up3 */
+#define ADC5_GEN3_AMUX1_THM_400K_PU 0x64
+#define ADC5_GEN3_AMUX2_THM_400K_PU 0x65
+#define ADC5_GEN3_AMUX3_THM_400K_PU 0x66
+#define ADC5_GEN3_AMUX4_THM_400K_PU 0x67
+#define ADC5_GEN3_AMUX5_THM_400K_PU 0x68
+#define ADC5_GEN3_AMUX6_THM_400K_PU 0x69
+#define ADC5_GEN3_AMUX1_GPIO_400K_PU 0x6a
+#define ADC5_GEN3_AMUX2_GPIO_400K_PU 0x6b
+#define ADC5_GEN3_AMUX3_GPIO_400K_PU 0x6c
+#define ADC5_GEN3_AMUX4_GPIO_400K_PU 0x6d
+
+/* 1/3 Divider */
+#define ADC5_GEN3_AMUX1_GPIO_DIV3 0x8a
+#define ADC5_GEN3_AMUX2_GPIO_DIV3 0x8b
+#define ADC5_GEN3_AMUX3_GPIO_DIV3 0x8c
+#define ADC5_GEN3_AMUX4_GPIO_DIV3 0x8d
+
+#define ADC5_GEN3_VPH_PWR 0x8e
+#define ADC5_GEN3_VBAT_SNS_QBG 0x8f
+
+#define ADC5_GEN3_VBAT_SNS_CHGR 0x94
+#define ADC5_GEN3_VBAT_2S_MID_QBG 0x96
+#define ADC5_GEN3_VBAT_2S_MID_CHGR 0x9d
+
+#define ADC5_GEN3_OFFSET_EXT2 0xf8
+
#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */
--
2.25.1

2023-12-31 17:15:09

[permalink] [raw]

Subject: [PATCH v3 3/3] iio: adc: Add support for QCOM PMIC5 Gen3 ADC

The ADC architecture on PMIC5 Gen3 is similar to that on PMIC5 Gen2,
with all SW communication to ADC going through PMK8550 which
communicates with other PMICs through PBS.

One major difference is that the register interface used here is that
of an SDAM (Shared Direct Access Memory) peripheral present on PMK8550.
There may be more than one SDAM used for ADC5 Gen3 and each has eight
channels, which may be used for either immediate reads (same functionality
as previous PMIC5 and PMIC5 Gen2 ADC peripherals) or recurring measurements
(same as ADC_TM functionality).

In this case, we have VADC and ADC_TM functionality combined into the
same driver. By convention, we reserve the first channel of the first
SDAM for all immediate reads and use the remaining channels across all
SDAMs for ADC_TM monitoring functionality.

Changes since v1:
- Removed datashet_name usage and implemented read_label() function
- In probe, updated channel property in iio_chan_spec from individual
channel to virtual channel and set indexed property to 1, due to the
above change.
- Updated order of checks in ISR
- Removed the driver remove callback and replaced with callbacks in a
devm_add_action call in probe.
- Addressed other comments from reviewers.

Signed-off-by: Jishnu Prakash <[email protected]>
---
drivers/iio/adc/Kconfig | 25 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/qcom-spmi-adc5-gen3.c | 1198 +++++++++++++++++++++++++
3 files changed, 1224 insertions(+)
create mode 100644 drivers/iio/adc/qcom-spmi-adc5-gen3.c

diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 4eebd5161419..4bdd5bb5b3fc 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -997,6 +997,31 @@ config QCOM_SPMI_ADC5
To compile this driver as a module, choose M here: the module will
be called qcom-spmi-adc5.

+config QCOM_SPMI_ADC5_GEN3
+ tristate "Qualcomm Technologies Inc. SPMI PMIC5 GEN3 ADC"
+ depends on SPMI && THERMAL
+ select REGMAP_SPMI
+ select QCOM_VADC_COMMON
+ help
+ This is the IIO Voltage PMIC5 Gen3 ADC driver for Qualcomm Technologies Inc. PMICs.
+
+ The driver supports reading multiple channels. The ADC is a 16-bit
+ sigma-delta ADC. The hardware supports calibrated results for
+ conversion requests and clients include reading phone power supply
+ voltage, on board system thermistors connected to the PMIC ADC,
+ PMIC die temperature, charger temperature, battery current, USB voltage
+ input and voltage signals connected to supported PMIC GPIO pins. The
+ hardware supports internal pull-up for thermistors and can choose between
+ a 30k, 100k or 400k ohm pull up using the ADC channels.
+
+ In addition, the same driver supports ADC thermal monitoring devices too.
+ They appear as thermal zones with multiple trip points. A thermal client sets
+ threshold temperature for both warm and cool trips and gets updated when a
+ threshold is reached.
+
+ To compile this driver as a module, choose M here: the module will
+ be called qcom-spmi-adc5-gen3.
+
config RCAR_GYRO_ADC
tristate "Renesas R-Car GyroADC driver"
depends on ARCH_RCAR_GEN2 || COMPILE_TEST
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index c0803383a7cc..539af17a668f 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -86,6 +86,7 @@ obj-$(CONFIG_NAU7802) += nau7802.o
obj-$(CONFIG_NPCM_ADC) += npcm_adc.o
obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
obj-$(CONFIG_QCOM_SPMI_ADC5) += qcom-spmi-adc5.o
+obj-$(CONFIG_QCOM_SPMI_ADC5_GEN3) += qcom-spmi-adc5-gen3.o
obj-$(CONFIG_QCOM_SPMI_IADC) += qcom-spmi-iadc.o
obj-$(CONFIG_QCOM_SPMI_RRADC) += qcom-spmi-rradc.o
obj-$(CONFIG_QCOM_VADC_COMMON) += qcom-vadc-common.o
diff --git a/drivers/iio/adc/qcom-spmi-adc5-gen3.c b/drivers/iio/adc/qcom-spmi-adc5-gen3.c
new file mode 100644
index 000000000000..5b5848492245
--- /dev/null
+++ b/drivers/iio/adc/qcom-spmi-adc5-gen3.c
@@ -0,0 +1,1198 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <asm/unaligned.h>
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/iio/iio.h>
+#include <linux/iio/adc/qcom-vadc-common.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/log2.h>
+#include <linux/math64.h>
+#include <linux/module.h>
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <linux/thermal.h>
+
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
+
+#define ADC5_GEN3_HS 0x45
+#define ADC5_GEN3_HS_BUSY BIT(7)
+#define ADC5_GEN3_HS_READY BIT(0)
+
+#define ADC5_GEN3_STATUS1 0x46
+#define ADC5_GEN3_STATUS1_CONV_FAULT BIT(7)
+#define ADC5_GEN3_STATUS1_THR_CROSS BIT(6)
+#define ADC5_GEN3_STATUS1_EOC BIT(0)
+
+#define ADC5_GEN3_TM_EN_STS 0x47
+#define ADC5_GEN3_TM_HIGH_STS 0x48
+#define ADC5_GEN3_TM_LOW_STS 0x49
+
+#define ADC5_GEN3_EOC_STS 0x4a
+#define ADC5_GEN3_EOC_CHAN_0 BIT(0)
+
+#define ADC5_GEN3_EOC_CLR 0x4b
+#define ADC5_GEN3_TM_HIGH_STS_CLR 0x4c
+#define ADC5_GEN3_TM_LOW_STS_CLR 0x4d
+#define ADC5_GEN3_CONV_ERR_CLR 0x4e
+#define ADC5_GEN3_CONV_ERR_CLR_REQ BIT(0)
+
+#define ADC5_GEN3_SID 0x4f
+#define ADC5_GEN3_SID_MASK GENMASK(3, 0)
+
+#define ADC5_GEN3_PERPH_CH 0x50
+#define ADC5_GEN3_CHAN_CONV_REQ BIT(7)
+
+#define ADC5_GEN3_TIMER_SEL 0x51
+#define ADC5_GEN3_TIME_IMMEDIATE 0x1
+
+#define ADC5_GEN3_DIG_PARAM 0x52
+#define ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK GENMASK(5, 4)
+#define ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK GENMASK(3, 2)
+
+#define ADC5_GEN3_FAST_AVG 0x53
+#define ADC5_GEN3_FAST_AVG_CTL_EN BIT(7)
+#define ADC5_GEN3_FAST_AVG_CTL_SAMPLES_MASK GENMASK(2, 0)
+
+#define ADC5_GEN3_ADC_CH_SEL_CTL 0x54
+#define ADC5_GEN3_DELAY_CTL 0x55
+#define ADC5_GEN3_HW_SETTLE_DELAY_MASK GENMASK(3, 0)
+
+#define ADC5_GEN3_CH_EN 0x56
+#define ADC5_GEN3_HIGH_THR_INT_EN BIT(1)
+#define ADC5_GEN3_LOW_THR_INT_EN BIT(0)
+
+#define ADC5_GEN3_LOW_THR0 0x57
+#define ADC5_GEN3_LOW_THR1 0x58
+#define ADC5_GEN3_HIGH_THR0 0x59
+#define ADC5_GEN3_HIGH_THR1 0x5a
+
+#define ADC5_GEN3_CH_DATA0(channel) (0x5c + (channel) * 2)
+#define ADC5_GEN3_CH_DATA1(channel) (0x5d + (channel) * 2)
+
+#define ADC5_GEN3_CONV_REQ 0xe5
+#define ADC5_GEN3_CONV_REQ_REQ BIT(0)
+
+#define ADC5_GEN3_VIRTUAL_SID_MASK GENMASK(15, 8)
+#define ADC5_GEN3_CHANNEL_MASK GENMASK(7, 0)
+#define V_CHAN(x) \
+ (FIELD_PREP(ADC5_GEN3_VIRTUAL_SID_MASK, (x).sid) | (x).channel) \
+
+enum adc5_cal_method {
+ ADC5_NO_CAL = 0,
+ ADC5_RATIOMETRIC_CAL,
+ ADC5_ABSOLUTE_CAL
+};
+
+enum adc5_time_select {
+ MEAS_INT_DISABLE = 0,
+ MEAS_INT_IMMEDIATE,
+ MEAS_INT_50MS,
+ MEAS_INT_100MS,
+ MEAS_INT_1S,
+ MEAS_INT_NONE,
+};
+
+struct adc5_sdam_data {
+ u16 base_addr;
+ const char *irq_name;
+ int irq;
+};
+
+/**
+ * struct adc5_channel_prop - ADC channel property.
+ * @channel: channel number, refer to the channel list.
+ * @cal_method: calibration method.
+ * @decimation: sampling rate supported for the channel.
+ * @sid: slave id of PMIC owning the channel.
+ * @prescale: channel scaling performed on the input signal.
+ * @hw_settle_time: the time between AMUX being configured and the
+ * start of conversion.
+ * @avg_samples: ability to provide single result from the ADC
+ * that is an average of multiple measurements.
+ * @sdam_index: Index for which SDAM this channel is on.
+ * @scale_fn_type: Represents the scaling function to convert voltage
+ * physical units desired by the client for the channel.
+ * @label: Channel name used in device tree.
+ * @chip: pointer to top-level ADC device structure.
+ * @adc_tm: indicates if the channel is used for TM measurements.
+ * @tm_chan_index: TM channel number used (ranging from 1-7).
+ * @timer: time period of recurring TM measurement.
+ * @tzd: pointer to thermal device corresponding to TM channel.
+ * @high_thr_en: TM high threshold crossing detection enabled.
+ * @low_thr_en: TM low threshold crossing detection enabled.
+ * @last_temp: last temperature that caused threshold violation,
+ * or a thermal TM channel.
+ * @last_temp_set: indicates if last_temp is stored.
+ */
+struct adc5_channel_prop {
+ unsigned int channel;
+ enum adc5_cal_method cal_method;
+ unsigned int decimation;
+ unsigned int sid;
+ unsigned int prescale;
+ unsigned int hw_settle_time;
+ unsigned int avg_samples;
+ unsigned int sdam_index;
+
+ enum vadc_scale_fn_type scale_fn_type;
+ const char *label;
+
+ struct adc5_chip *chip;
+ /* TM(thermal monitoring related) properties */
+ bool adc_tm;
+ unsigned int tm_chan_index;
+ unsigned int timer;
+ struct thermal_zone_device *tzd;
+ bool high_thr_en;
+ bool low_thr_en;
+ int last_temp;
+ bool last_temp_set;
+};
+
+/**
+ * struct adc5_chip - ADC private structure.
+ * @regmap: SPMI ADC5 Gen3 peripheral register map field.
+ * @dev: SPMI ADC5 Gen3 device.
+ * @base: pointer to array of ADC peripheral base and interrupt.
+ * @num_sdams: number of SDAMs (Shared Direct Access Memory Module) being used.
+ * @nchannels: number of ADC channels.
+ * @chan_props: array of ADC channel properties.
+ * @iio_chans: array of IIO channels specification.
+ * @complete: ADC result notification after interrupt is received.
+ * @lock: ADC lock for access to the peripheral, to prevent concurrent
+ * requests from multiple clients.
+ * @data: software configuration data.
+ * @n_tm_channels: number of ADC channels used for TM measurements.
+ * @tm_handler_work: scheduled work for handling TM threshold violation.
+ */
+struct adc5_chip {
+ struct regmap *regmap;
+ struct device *dev;
+ struct adc5_sdam_data *base;
+ unsigned int num_sdams;
+ unsigned int nchannels;
+ struct adc5_channel_prop *chan_props;
+ struct iio_chan_spec *iio_chans;
+ struct completion complete;
+ struct mutex lock;
+ const struct adc5_data *data;
+ /* TM properties */
+ unsigned int n_tm_channels;
+ struct work_struct tm_handler_work;
+};
+
+static int adc5_gen3_read(struct adc5_chip *adc, unsigned int sdam_index,
+ u16 offset, u8 *data, int len)
+{
+ return regmap_bulk_read(adc->regmap, adc->base[sdam_index].base_addr + offset, data, len);
+}
+
+static int adc5_gen3_write(struct adc5_chip *adc, unsigned int sdam_index,
+ u16 offset, u8 *data, int len)
+{
+ return regmap_bulk_write(adc->regmap, adc->base[sdam_index].base_addr + offset, data, len);
+}
+
+static int adc5_gen3_read_voltage_data(struct adc5_chip *adc, u16 *data, u8 sdam_index)
+{
+ int ret;
+ u8 rslt[2];
+
+ ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_CH_DATA0(0), rslt, 2);
+ if (ret)
+ return ret;
+
+ *data = get_unaligned_le16(rslt);
+
+ if (*data == ADC5_USR_DATA_CHECK) {
+ dev_err(adc->dev, "Invalid data:%#x\n", *data);
+ return -EINVAL;
+ }
+
+ dev_dbg(adc->dev, "voltage raw code:%#x\n", *data);
+
+ return 0;
+}
+
+static void adc5_gen3_update_dig_param(struct adc5_chip *adc,
+ struct adc5_channel_prop *prop, u8 *data)
+{
+ /* Update calibration select and decimation ratio select*/
+ *data &= ~(ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK | ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK);
+ *data |= FIELD_PREP(ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK, prop->cal_method);
+ *data |= FIELD_PREP(ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK, prop->decimation);
+}
+
+# define ADC5_GEN3_READ_CONFIG_REGS 7
+
+static int adc5_gen3_configure(struct adc5_chip *adc,
+ struct adc5_channel_prop *prop)
+{
+ u8 sdam_index = prop->sdam_index;
+ u8 conv_req = 0;
+ u8 buf[ADC5_GEN3_READ_CONFIG_REGS];
+ int ret;
+
+ /* Reserve channel 0 of first SDAM for immediate conversions */
+ if (prop->adc_tm)
+ sdam_index = 0;
+
+ ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_SID, buf, sizeof(buf));
+ if (ret)
+ return ret;
+
+ /* Write SID */
+ buf[0] = FIELD_PREP(ADC5_GEN3_SID_MASK, prop->sid);
+
+ /*
+ * Use channel 0 by default for immediate conversion and
+ * to indicate there is an actual conversion request
+ */
+ buf[1] = ADC5_GEN3_CHAN_CONV_REQ | 0;
+
+ buf[2] = ADC5_GEN3_TIME_IMMEDIATE;
+
+ /* Digital param selection */
+ adc5_gen3_update_dig_param(adc, prop, &buf[3]);
+
+ /* Update fast average sample value */
+ buf[4] &= ~ADC5_GEN3_FAST_AVG_CTL_SAMPLES_MASK;
+ buf[4] |= prop->avg_samples | ADC5_GEN3_FAST_AVG_CTL_EN;
+
+ /* Select ADC channel */
+ buf[5] = prop->channel;
+
+ /* Select HW settle delay for channel */
+ buf[6] = FIELD_PREP(ADC5_GEN3_HW_SETTLE_DELAY_MASK, prop->hw_settle_time);
+
+ reinit_completion(&adc->complete);
+
+ ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_SID, buf, sizeof(buf));
+ if (ret)
+ return ret;
+
+ conv_req = ADC5_GEN3_CONV_REQ_REQ;
+ return adc5_gen3_write(adc, sdam_index, ADC5_GEN3_CONV_REQ, &conv_req, 1);
+}
+
+/**
+ * Worst case delay from PBS in readying handshake bit
+ * can be up to 15ms, when PBS is busy running other
+ * simultaneous transactions, while in the best case, it is
+ * already ready at this point. Assigning polling delay and
+ * retry count accordingly.
+ */
+
+#define ADC5_GEN3_HS_DELAY_MIN_US 100
+#define ADC5_GEN3_HS_DELAY_MAX_US 110
+#define ADC5_GEN3_HS_RETRY_COUNT 150
+
+static int adc5_gen3_poll_wait_hs(struct adc5_chip *adc,
+ unsigned int sdam_index)
+{
+ u8 conv_req = ADC5_GEN3_CONV_REQ_REQ;
+ u8 status = 0;
+ int ret, count;
+
+ for (count = 0; count < ADC5_GEN3_HS_RETRY_COUNT; count++) {
+ ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_HS, &status, 1);
+ if (ret)
+ return ret;
+
+ if (status == ADC5_GEN3_HS_READY) {
+ ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_CONV_REQ,
+ &conv_req, 1);
+ if (ret)
+ return ret;
+
+ if (!conv_req)
+ return 0;
+ }
+
+ usleep_range(ADC5_GEN3_HS_DELAY_MIN_US,
+ ADC5_GEN3_HS_DELAY_MAX_US);
+ }
+
+ dev_err(adc->dev, "Setting HS ready bit timed out, status:%#x\n", status);
+ return -ETIMEDOUT;
+}
+
+/**
+ * Worst case delay from PBS for conversion time can be
+ * up to 500ms, when PBS has timed out twice, once for
+ * the initial attempt and once for a retry of the same
+ * transaction.
+ */
+
+#define ADC5_GEN3_CONV_TIMEOUT_MS 501
+
+static int adc5_gen3_do_conversion(struct adc5_chip *adc,
+ struct adc5_channel_prop *prop,
+ u16 *data_volt)
+{
+ u8 val, sdam_index = prop->sdam_index;
+ unsigned long rc;
+ int ret;
+
+ /* Reserve channel 0 of first SDAM for immediate conversions */
+ if (prop->adc_tm)
+ sdam_index = 0;
+
+ mutex_lock(&adc->lock);
+ ret = adc5_gen3_poll_wait_hs(adc, 0);
+ if (ret)
+ goto unlock;
+
+ ret = adc5_gen3_configure(adc, prop);
+ if (ret) {
+ dev_err(adc->dev, "ADC configure failed with %d\n", ret);
+ goto unlock;
+ }
+
+ /* No support for polling mode at present*/
+ rc = wait_for_completion_timeout(&adc->complete,
+ msecs_to_jiffies(ADC5_GEN3_CONV_TIMEOUT_MS));
+ if (!rc) {
+ dev_err(adc->dev, "Reading ADC channel %s timed out\n",
+ prop->label);
+ ret = -ETIMEDOUT;
+ goto unlock;
+ }
+
+ ret = adc5_gen3_read_voltage_data(adc, data_volt, sdam_index);
+ if (ret)
+ goto unlock;
+
+ val = BIT(0);
+ ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_EOC_CLR, &val, 1);
+ if (ret)
+ goto unlock;
+
+ /* To indicate conversion request is only to clear a status */
+ val = 0;
+ ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_PERPH_CH, &val, 1);
+ if (ret)
+ goto unlock;
+
+ val = ADC5_GEN3_CONV_REQ_REQ;
+ ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_CONV_REQ, &val, 1);
+
+unlock:
+ mutex_unlock(&adc->lock);
+
+ return ret;
+}
+
+static int get_sdam_from_irq(struct adc5_chip *adc, int irq)
+{
+ int i;
+
+ for (i = 0; i < adc->num_sdams; i++) {
+ if (adc->base[i].irq == irq)
+ return i;
+ }
+ return -ENOENT;
+}
+
+static irqreturn_t adc5_gen3_isr(int irq, void *dev_id)
+{
+ struct adc5_chip *adc = dev_id;
+ u8 status, tm_status[2], eoc_status, val;
+ int ret, sdam_num;
+
+ sdam_num = get_sdam_from_irq(adc, irq);
+ if (sdam_num < 0) {
+ dev_err(adc->dev, "adc irq %d not associated with an sdam\n", irq);
+ return IRQ_HANDLED;
+ }
+
+ ret = adc5_gen3_read(adc, sdam_num, ADC5_GEN3_STATUS1, &status, 1);
+ if (ret) {
+ dev_err(adc->dev, "adc read status1 failed with %d\n", ret);
+ return IRQ_HANDLED;
+ }
+
+ ret = adc5_gen3_read(adc, sdam_num, ADC5_GEN3_EOC_STS, &eoc_status, 1);
+ if (ret) {
+ dev_err(adc->dev, "adc read eoc status failed with %d\n", ret);
+ return IRQ_HANDLED;
+ }
+
+ if (status & ADC5_GEN3_STATUS1_CONV_FAULT) {
+ dev_err_ratelimited(adc->dev, "Unexpected conversion fault, status:%#x, eoc_status:%#x\n",
+ status, eoc_status);
+ val = ADC5_GEN3_CONV_ERR_CLR_REQ;
+ ret = adc5_gen3_write(adc, sdam_num, ADC5_GEN3_CONV_ERR_CLR, &val, 1);
+ if (ret < 0)
+ return IRQ_HANDLED;
+
+ /* To indicate conversion request is only to clear a status */
+ val = 0;
+ ret = adc5_gen3_write(adc, sdam_num, ADC5_GEN3_PERPH_CH, &val, 1);
+ if (ret < 0)
+ return IRQ_HANDLED;
+
+ val = ADC5_GEN3_CONV_REQ_REQ;
+ ret = adc5_gen3_write(adc, sdam_num, ADC5_GEN3_CONV_REQ, &val, 1);
+
+ return IRQ_HANDLED;
+ }
+
+ /* CHAN0 is the preconfigured channel for immediate conversion */
+ if (eoc_status & ADC5_GEN3_EOC_CHAN_0)
+ complete(&adc->complete);
+
+ ret = adc5_gen3_read(adc, sdam_num, ADC5_GEN3_TM_HIGH_STS, tm_status, 2);
+ if (ret) {
+ dev_err(adc->dev, "adc read TM status failed with %d\n", ret);
+ return IRQ_HANDLED;
+ }
+
+ if (tm_status[0] || tm_status[1])
+ schedule_work(&adc->tm_handler_work);
+
+ dev_dbg(adc->dev, "Interrupt status:%#x, EOC status:%#x, high:%#x, low:%#x\n",
+ status, eoc_status, tm_status[0], tm_status[1]);
+
+ return IRQ_HANDLED;
+}
+
+static void tm_handler_work(struct work_struct *work)
+{
+ struct adc5_chip *adc = container_of(work, struct adc5_chip, tm_handler_work);
+ struct adc5_channel_prop *chan_prop;
+ u8 tm_status[2] = {0};
+ u8 buf[16] = {0};
+ u8 val;
+ int ret, i, sdam_index = -1;
+
+ for (i = 0; i < adc->nchannels; i++) {
+ bool upper_set = false, lower_set = false;
+ int temp, offset;
+ u16 code = 0;
+
+ chan_prop = &adc->chan_props[i];
+ offset = chan_prop->tm_chan_index;
+
+ if (!chan_prop->adc_tm)
+ continue;
+
+ mutex_lock(&adc->lock);
+ if (chan_prop->sdam_index != sdam_index) {
+ sdam_index = chan_prop->sdam_index;
+ ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_TM_HIGH_STS,
+ tm_status, 2);
+ if (ret) {
+ dev_err(adc->dev, "adc read TM status failed with %d\n", ret);
+ goto out;
+ }
+
+ ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_TM_HIGH_STS_CLR,
+ tm_status, 2);
+ if (ret) {
+ dev_err(adc->dev, "adc write TM status failed with %d\n", ret);
+ goto out;
+ }
+
+ /* To indicate conversion request is only to clear a status */
+ val = 0;
+ ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_PERPH_CH, &val, 1);
+ if (ret) {
+ dev_err(adc->dev, "adc write status clear conv_req failed with %d\n",
+ ret);
+ goto out;
+ }
+
+ val = ADC5_GEN3_CONV_REQ_REQ;
+ ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_CONV_REQ, &val, 1);
+ if (ret) {
+ dev_err(adc->dev, "adc write conv_req failed with %d\n", ret);
+ goto out;
+ }
+
+ ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_CH_DATA0(0), buf,
+ sizeof(buf));
+ if (ret < 0) {
+ dev_err(adc->dev, "adc read data failed with %d\n", ret);
+ goto out;
+ }
+ }
+
+ if ((tm_status[0] & BIT(offset)) && (chan_prop->high_thr_en))
+ upper_set = true;
+
+ if ((tm_status[1] & BIT(offset)) && (chan_prop->low_thr_en))
+ lower_set = true;
+
+ mutex_unlock(&adc->lock);
+
+ if (!(upper_set || lower_set))
+ continue;
+
+ code = get_unaligned_le16(&buf[2 * offset]);
+ pr_debug("ADC_TM threshold code:%#x\n", code);
+
+ ret = qcom_adc5_hw_scale(chan_prop->scale_fn_type,
+ chan_prop->prescale, adc->data, code, &temp);
+ if (ret) {
+ dev_err(adc->dev, "Invalid temperature reading, ret = %d, code=%#x\n",
+ ret, code);
+ continue;
+ }
+
+ chan_prop->last_temp = temp;
+ chan_prop->last_temp_set = true;
+ thermal_zone_device_update(chan_prop->tzd, THERMAL_TRIP_VIOLATED);
+ }
+
+ return;
+
+out:
+ mutex_unlock(&adc->lock);
+}
+
+static int adc5_gen3_fwnode_xlate(struct iio_dev *indio_dev,
+ const struct fwnode_reference_args *iiospec)
+{
+ struct adc5_chip *adc = iio_priv(indio_dev);
+ int i, v_channel;
+
+ for (i = 0; i < adc->nchannels; i++) {
+ v_channel = V_CHAN(adc->chan_props[i]);
+ if (v_channel == iiospec->args[0])
+ return i;
+ }
+
+ return -ENOENT;
+}
+
+static int adc5_gen3_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan, int *val, int *val2,
+ long mask)
+{
+ struct adc5_chip *adc = iio_priv(indio_dev);
+ struct adc5_channel_prop *prop;
+ u16 adc_code_volt;
+ int ret;
+
+ prop = &adc->chan_props[chan->address];
+
+ switch (mask) {
+ case IIO_CHAN_INFO_PROCESSED:
+ ret = adc5_gen3_do_conversion(adc, prop,
+ &adc_code_volt);
+ if (ret)
+ return ret;
+
+ ret = qcom_adc5_hw_scale(prop->scale_fn_type,
+ prop->prescale, adc->data,
+ adc_code_volt, val);
+ if (ret)
+ return ret;
+
+ return IIO_VAL_INT;
+ case IIO_CHAN_INFO_RAW:
+ ret = adc5_gen3_do_conversion(adc, prop,
+ &adc_code_volt);
+ if (ret)
+ return ret;
+ *val = (int)adc_code_volt;
+ return IIO_VAL_INT;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int adc5_gen3_read_label(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan, char *label)
+{
+ struct adc5_chip *adc = iio_priv(indio_dev);
+ struct adc5_channel_prop *prop;
+
+ prop = &adc->chan_props[chan->address];
+ return sprintf(label, "%s\n", prop->label);
+}
+
+static const struct iio_info adc5_gen3_info = {
+ .read_raw = adc5_gen3_read_raw,
+ .read_label = adc5_gen3_read_label,
+ .fwnode_xlate = adc5_gen3_fwnode_xlate,
+};
+
+static int adc_tm_gen3_get_temp(struct thermal_zone_device *tz, int *temp)
+{
+ struct adc5_channel_prop *prop = tz->devdata;
+ struct adc5_chip *adc;
+ u16 adc_code_volt;
+ int ret;
+
+ if (!prop || !prop->chip)
+ return -EINVAL;
+
+ adc = prop->chip;
+
+ if (prop->last_temp_set) {
+ pr_debug("last_temp: %d\n", prop->last_temp);
+ prop->last_temp_set = false;
+ *temp = prop->last_temp;
+ return 0;
+ }
+
+ ret = adc5_gen3_do_conversion(adc, prop, &adc_code_volt);
+ if (ret < 0)
+ return ret;
+
+ return qcom_adc5_hw_scale(prop->scale_fn_type,
+ prop->prescale, adc->data,
+ adc_code_volt, temp);
+}
+
+static int _adc_tm5_gen3_disable_channel(struct adc5_channel_prop *prop)
+{
+ struct adc5_chip *adc = prop->chip;
+ int ret;
+ u8 val;
+
+ prop->high_thr_en = false;
+ prop->low_thr_en = false;
+
+ val = MEAS_INT_DISABLE;
+ ret = adc5_gen3_write(adc, prop->sdam_index, ADC5_GEN3_TIMER_SEL, &val, 1);
+ if (ret)
+ return ret;
+
+ /* To indicate there is an actual conversion request */
+ val = ADC5_GEN3_CHAN_CONV_REQ | prop->tm_chan_index;
+ ret = adc5_gen3_write(adc, prop->sdam_index, ADC5_GEN3_PERPH_CH, &val, 1);
+ if (ret)
+ return ret;
+
+ val = ADC5_GEN3_CONV_REQ_REQ;
+ return adc5_gen3_write(adc, prop->sdam_index, ADC5_GEN3_CONV_REQ, &val, 1);
+}
+
+static int adc_tm5_gen3_disable_channel(struct adc5_channel_prop *prop)
+{
+ return _adc_tm5_gen3_disable_channel(prop);
+}
+
+# define ADC_TM5_GEN3_CONFIG_REGS 12
+
+static int adc_tm5_gen3_configure(struct adc5_channel_prop *prop,
+ int low_temp, int high_temp)
+{
+ struct adc5_chip *adc = prop->chip;
+ u8 conv_req = 0, buf[ADC_TM5_GEN3_CONFIG_REGS];
+ u16 adc_code;
+ int ret;
+
+ ret = adc5_gen3_poll_wait_hs(adc, prop->sdam_index);
+ if (ret < 0)
+ return ret;
+
+ ret = adc5_gen3_read(adc, prop->sdam_index, ADC5_GEN3_SID, buf, sizeof(buf));
+ if (ret < 0)
+ return ret;
+
+ /* Write SID */
+ buf[0] = FIELD_PREP(ADC5_GEN3_SID_MASK, prop->sid);
+
+ /*
+ * Select TM channel and indicate there is an actual
+ * conversion request
+ */
+ buf[1] = ADC5_GEN3_CHAN_CONV_REQ | prop->tm_chan_index;
+
+ buf[2] = prop->timer;
+
+ /* Digital param selection */
+ adc5_gen3_update_dig_param(adc, prop, &buf[3]);
+
+ /* Update fast average sample value */
+ buf[4] &= ~ADC5_GEN3_FAST_AVG_CTL_SAMPLES_MASK;
+ buf[4] |= prop->avg_samples | ADC5_GEN3_FAST_AVG_CTL_EN;
+
+ /* Select ADC channel */
+ buf[5] = prop->channel;
+
+ /* Select HW settle delay for channel */
+ buf[6] = FIELD_PREP(ADC5_GEN3_HW_SETTLE_DELAY_MASK, prop->hw_settle_time);
+
+ /* High temperature corresponds to low voltage threshold */
+ if (high_temp != INT_MAX) {
+ prop->low_thr_en = true;
+ adc_code = qcom_adc_tm5_gen2_temp_res_scale(high_temp);
+ put_unaligned_le16(adc_code, &buf[8]);
+ } else {
+ prop->low_thr_en = false;
+ }
+
+ /* Low temperature corresponds to high voltage threshold */
+ if (low_temp != -INT_MAX) {
+ prop->high_thr_en = true;
+ adc_code = qcom_adc_tm5_gen2_temp_res_scale(low_temp);
+ put_unaligned_le16(adc_code, &buf[10]);
+ } else {
+ prop->high_thr_en = false;
+ }
+
+ buf[7] = 0;
+ if (prop->high_thr_en)
+ buf[7] |= ADC5_GEN3_HIGH_THR_INT_EN;
+ if (prop->low_thr_en)
+ buf[7] |= ADC5_GEN3_LOW_THR_INT_EN;
+
+ ret = adc5_gen3_write(adc, prop->sdam_index, ADC5_GEN3_SID, buf, sizeof(buf));
+ if (ret < 0)
+ return ret;
+
+ conv_req = ADC5_GEN3_CONV_REQ_REQ;
+ return adc5_gen3_write(adc, prop->sdam_index, ADC5_GEN3_CONV_REQ, &conv_req, 1);
+}
+
+static int adc_tm5_gen3_set_trip_temp(struct thermal_zone_device *tz,
+ int low_temp, int high_temp)
+{
+ struct adc5_channel_prop *prop = tz->devdata;
+ struct adc5_chip *adc;
+ int ret;
+
+ if (!prop || !prop->chip)
+ return -EINVAL;
+
+ adc = prop->chip;
+
+ dev_dbg(adc->dev, "channel:%s, low_temp(mdegC):%d, high_temp(mdegC):%d\n",
+ prop->label, low_temp, high_temp);
+
+ mutex_lock(&adc->lock);
+ if (high_temp == INT_MAX && low_temp <= -INT_MAX)
+ ret = adc_tm5_gen3_disable_channel(prop);
+ else
+ ret = adc_tm5_gen3_configure(prop, low_temp, high_temp);
+ mutex_unlock(&adc->lock);
+
+ return ret;
+}
+
+static const struct thermal_zone_device_ops adc_tm_ops = {
+ .get_temp = adc_tm_gen3_get_temp,
+ .set_trips = adc_tm5_gen3_set_trip_temp,
+};
+
+static int adc_tm_register_tzd(struct adc5_chip *adc)
+{
+ unsigned int i, channel;
+ struct thermal_zone_device *tzd;
+
+ for (i = 0; i < adc->nchannels; i++) {
+ channel = V_CHAN(adc->chan_props[i]);
+
+ if (!adc->chan_props[i].adc_tm)
+ continue;
+ tzd = devm_thermal_of_zone_register(adc->dev, channel,
+ &adc->chan_props[i], &adc_tm_ops);
+
+ if (IS_ERR(tzd)) {
+ if (PTR_ERR(tzd) == -ENODEV) {
+ dev_warn(adc->dev, "thermal sensor on channel %d is not used\n",
+ channel);
+ continue;
+ }
+
+ dev_err(adc->dev, "Error registering TZ zone:%ld for channel:%d\n",
+ PTR_ERR(tzd), adc->chan_props[i].channel);
+ return PTR_ERR(tzd);
+ }
+ adc->chan_props[i].tzd = tzd;
+ }
+
+ return 0;
+}
+
+static void adc5_gen3_disable(void *data)
+{
+ struct adc5_chip *adc = data;
+ int i;
+
+ if (adc->n_tm_channels)
+ cancel_work_sync(&adc->tm_handler_work);
+
+ for (i = 0; i < adc->num_sdams; i++)
+ free_irq(adc->base[i].irq, adc);
+
+ mutex_lock(&adc->lock);
+ /* Disable all available TM channels */
+ for (i = 0; i < adc->nchannels; i++) {
+ if (!adc->chan_props[i].adc_tm)
+ continue;
+ adc5_gen3_poll_wait_hs(adc, adc->chan_props[i].sdam_index);
+ _adc_tm5_gen3_disable_channel(&adc->chan_props[i]);
+ }
+
+ mutex_unlock(&adc->lock);
+}
+
+struct adc5_channels {
+ unsigned int prescale_index;
+ enum iio_chan_type type;
+ long info_mask;
+ enum vadc_scale_fn_type scale_fn_type;
+};
+
+/* In these definitions, _pre refers to an index into adc5_prescale_ratios. */
+#define ADC5_CHAN(_type, _mask, _pre, _scale) \
+ { \
+ .prescale_index = _pre, \
+ .type = _type, \
+ .info_mask = _mask, \
+ .scale_fn_type = _scale, \
+ }, \
+
+#define ADC5_CHAN_TEMP(_pre, _scale) \
+ ADC5_CHAN(IIO_TEMP, BIT(IIO_CHAN_INFO_PROCESSED), _pre, _scale) \
+
+#define ADC5_CHAN_VOLT(_pre, _scale) \
+ ADC5_CHAN(IIO_VOLTAGE, BIT(IIO_CHAN_INFO_PROCESSED), _pre, _scale) \
+
+#define ADC5_CHAN_CUR(_pre, _scale) \
+ ADC5_CHAN(IIO_CURRENT, BIT(IIO_CHAN_INFO_PROCESSED), _pre, _scale) \
+
+static const struct adc5_channels adc5_gen3_chans_pmic[ADC5_MAX_CHANNEL] = {
+ [ADC5_GEN3_REF_GND] = ADC5_CHAN_VOLT(0, SCALE_HW_CALIB_DEFAULT)
+ [ADC5_GEN3_1P25VREF] = ADC5_CHAN_VOLT(0, SCALE_HW_CALIB_DEFAULT)
+ [ADC5_GEN3_VPH_PWR] = ADC5_CHAN_VOLT(1, SCALE_HW_CALIB_DEFAULT)
+ [ADC5_GEN3_VBAT_SNS_QBG] = ADC5_CHAN_VOLT(1, SCALE_HW_CALIB_DEFAULT)
+ [ADC5_GEN3_USB_SNS_V_16] = ADC5_CHAN_TEMP(8, SCALE_HW_CALIB_DEFAULT)
+ [ADC5_GEN3_VIN_DIV16_MUX] = ADC5_CHAN_TEMP(8, SCALE_HW_CALIB_DEFAULT)
+ [ADC5_GEN3_DIE_TEMP] = ADC5_CHAN_TEMP(0,
+ SCALE_HW_CALIB_PMIC_THERM_PM7)
+ [ADC5_GEN3_TEMP_ALARM_LITE] = ADC5_CHAN_TEMP(0,
+ SCALE_HW_CALIB_PMIC_THERM_PM7)
+ [ADC5_GEN3_AMUX1_THM_100K_PU] = ADC5_CHAN_TEMP(0,
+ SCALE_HW_CALIB_THERM_100K_PU_PM7)
+ [ADC5_GEN3_AMUX2_THM_100K_PU] = ADC5_CHAN_TEMP(0,
+ SCALE_HW_CALIB_THERM_100K_PU_PM7)
+ [ADC5_GEN3_AMUX3_THM_100K_PU] = ADC5_CHAN_TEMP(0,
+ SCALE_HW_CALIB_THERM_100K_PU_PM7)
+ [ADC5_GEN3_AMUX4_THM_100K_PU] = ADC5_CHAN_TEMP(0,
+ SCALE_HW_CALIB_THERM_100K_PU_PM7)
+ [ADC5_GEN3_AMUX5_THM_100K_PU] = ADC5_CHAN_TEMP(0,
+ SCALE_HW_CALIB_THERM_100K_PU_PM7)
+ [ADC5_GEN3_AMUX6_THM_100K_PU] = ADC5_CHAN_TEMP(0,
+ SCALE_HW_CALIB_THERM_100K_PU_PM7)
+ [ADC5_GEN3_AMUX1_GPIO_100K_PU] = ADC5_CHAN_TEMP(0,
+ SCALE_HW_CALIB_THERM_100K_PU_PM7)
+ [ADC5_GEN3_AMUX2_GPIO_100K_PU] = ADC5_CHAN_TEMP(0,
+ SCALE_HW_CALIB_THERM_100K_PU_PM7)
+ [ADC5_GEN3_AMUX3_GPIO_100K_PU] = ADC5_CHAN_TEMP(0,
+ SCALE_HW_CALIB_THERM_100K_PU_PM7)
+ [ADC5_GEN3_AMUX4_GPIO_100K_PU] = ADC5_CHAN_TEMP(0,
+ SCALE_HW_CALIB_THERM_100K_PU_PM7)
+};
+
+static int adc5_gen3_get_fw_channel_data(struct adc5_chip *adc,
+ struct adc5_channel_prop *prop,
+ struct fwnode_handle *fwnode,
+ const struct adc5_data *data)
+{
+ const char *name = fwnode_get_name(fwnode);
+ const char *channel_name;
+ struct device *dev = adc->dev;
+ u32 chan, value, varr[2], sid = 0;
+ int ret, val;
+
+ ret = fwnode_property_read_u32(fwnode, "reg", &chan);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "invalid channel number %s\n", name);
+
+ /*
+ * Value read from "reg" is virtual channel number
+ * virtual channel number = sid << 8 | channel number
+ */
+
+ sid = FIELD_GET(ADC5_GEN3_VIRTUAL_SID_MASK, chan);
+ chan = FIELD_GET(ADC5_GEN3_CHANNEL_MASK, chan);
+
+ if (chan > ADC5_GEN3_OFFSET_EXT2)
+ return dev_err_probe(dev, -EINVAL, "%s invalid channel number %d\n", name, chan);
+
+ prop->channel = chan;
+ prop->sid = sid;
+
+ ret = fwnode_property_read_string(fwnode, "label", &channel_name);
+ if (ret)
+ channel_name = name;
+ prop->label = channel_name;
+
+ prop->decimation = ADC5_DECIMATION_DEFAULT;
+ ret = fwnode_property_read_u32(fwnode, "qcom,decimation", &value);
+ if (!ret) {
+ ret = qcom_adc5_decimation_from_dt(value, data->decimation);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "%#x invalid decimation %d\n",
+ chan, value);
+ prop->decimation = ret;
+ }
+
+ prop->prescale = adc->data->adc_chans[prop->channel].prescale_index;
+ ret = fwnode_property_read_u32_array(fwnode, "qcom,pre-scaling", varr, 2);
+ if (!ret) {
+ ret = qcom_adc5_prescaling_from_dt(varr[0], varr[1]);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "%#x invalid pre-scaling <%d %d>\n",
+ chan, varr[0], varr[1]);
+ prop->prescale = ret;
+ }
+
+ prop->hw_settle_time = VADC_DEF_HW_SETTLE_TIME;
+ ret = fwnode_property_read_u32(fwnode, "qcom,hw-settle-time", &value);
+ if (!ret) {
+ ret = qcom_adc5_hw_settle_time_from_dt(value,
+ data->hw_settle_1);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "%#x invalid hw-settle-time %d us\n",
+ chan, value);
+ prop->hw_settle_time = ret;
+ }
+
+ prop->avg_samples = VADC_DEF_AVG_SAMPLES;
+ ret = fwnode_property_read_u32(fwnode, "qcom,avg-samples", &value);
+ if (!ret) {
+ ret = qcom_adc5_avg_samples_from_dt(value);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "%#x invalid avg-samples %d\n",
+ chan, value);
+ prop->avg_samples = ret;
+ }
+
+ if (fwnode_property_read_bool(fwnode, "qcom,ratiometric"))
+ prop->cal_method = ADC5_RATIOMETRIC_CAL;
+ else
+ prop->cal_method = ADC5_ABSOLUTE_CAL;
+
+ prop->timer = MEAS_INT_IMMEDIATE;
+
+ prop->adc_tm = fwnode_property_read_bool(fwnode, "qcom,adc-tm");
+
+ if (prop->adc_tm) {
+ adc->n_tm_channels++;
+ if (adc->n_tm_channels > ((adc->num_sdams * 8) - 1))
+ return dev_err_probe(adc->dev, -EINVAL,
+ "Number of TM nodes %u greater than channels supported:%u\n",
+ adc->n_tm_channels, (adc->num_sdams * 8) - 1);
+
+ val = adc->n_tm_channels / 8;
+ prop->sdam_index = val;
+ prop->tm_chan_index = adc->n_tm_channels - (8*val);
+
+ prop->timer = MEAS_INT_1S;
+ }
+
+ return 0;
+}
+
+static const struct adc5_data adc5_gen3_data_pmic = {
+ .full_scale_code_volt = 0x70e4,
+ .adc_chans = adc5_gen3_chans_pmic,
+ .info = &adc5_gen3_info,
+ .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX])
+ {85, 340, 1360},
+ .hw_settle_1 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
+ {15, 100, 200, 300, 400, 500, 600, 700,
+ 1000, 2000, 4000, 8000, 16000, 32000,
+ 64000, 128000},
+};
+
+static const struct of_device_id adc5_match_table[] = {
+ {
+ .compatible = "qcom,spmi-adc5-gen3",
+ .data = &adc5_gen3_data_pmic,
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, adc5_match_table);
+
+static int adc5_get_fw_data(struct adc5_chip *adc)
+{
+ const struct adc5_channels *adc_chan;
+ struct iio_chan_spec *iio_chan;
+ struct adc5_channel_prop *chan_props;
+ struct fwnode_handle *child;
+ unsigned int index = 0;
+ int ret;
+
+ adc->nchannels = device_get_child_node_count(adc->dev);
+ if (!adc->nchannels)
+ return -EINVAL;
+
+ adc->iio_chans = devm_kcalloc(adc->dev, adc->nchannels,
+ sizeof(*adc->iio_chans), GFP_KERNEL);
+ if (!adc->iio_chans)
+ return -ENOMEM;
+
+ adc->chan_props = devm_kcalloc(adc->dev, adc->nchannels,
+ sizeof(*adc->chan_props), GFP_KERNEL);
+ if (!adc->chan_props)
+ return -ENOMEM;
+
+ chan_props = adc->chan_props;
+ adc->n_tm_channels = 0;
+ iio_chan = adc->iio_chans;
+ adc->data = device_get_match_data(adc->dev);
+ if (!adc->data)
+ adc->data = &adc5_gen3_data_pmic;
+
+ device_for_each_child_node(adc->dev, child) {
+ ret = adc5_gen3_get_fw_channel_data(adc, chan_props, child, adc->data);
+ if (ret < 0) {
+ fwnode_handle_put(child);
+ return ret;
+ }
+
+ chan_props->chip = adc;
+ chan_props->scale_fn_type =
+ adc->data->adc_chans[chan_props->channel].scale_fn_type;
+ adc_chan = &adc->data->adc_chans[chan_props->channel];
+ iio_chan->channel = V_CHAN(*chan_props);
+ iio_chan->info_mask_separate = adc_chan->info_mask;
+ iio_chan->type = adc_chan->type;
+ iio_chan->address = index;
+ iio_chan->indexed = 1;
+ iio_chan++;
+ chan_props++;
+ index++;
+ }
+
+ return 0;
+}
+
+static int adc5_gen3_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct iio_dev *indio_dev;
+ struct adc5_chip *adc;
+ struct regmap *regmap;
+ int ret, i;
+ u32 *reg;
+
+ regmap = dev_get_regmap(dev->parent, NULL);
+ if (!regmap)
+ return -ENODEV;
+
+ indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
+ if (!indio_dev)
+ return -ENOMEM;
+
+ adc = iio_priv(indio_dev);
+ adc->regmap = regmap;
+ adc->dev = dev;
+
+ ret = device_property_count_u32(dev, "reg");
+ if (ret < 0)
+ return ret;
+
+ adc->num_sdams = ret;
+
+ reg = kcalloc(adc->num_sdams, sizeof(u32), GFP_KERNEL);
+ if (!reg)
+ return -ENOMEM;
+
+ ret = device_property_read_u32_array(dev, "reg", reg, adc->num_sdams);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to read reg property, ret = %d\n", ret);
+
+ adc->base = devm_kcalloc(dev, adc->num_sdams, sizeof(*adc->base), GFP_KERNEL);
+ if (!adc->base)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, indio_dev);
+ init_completion(&adc->complete);
+ mutex_init(&adc->lock);
+
+ for (i = 0; i < adc->num_sdams; i++) {
+ adc->base[i].base_addr = reg[i];
+
+ adc->base[i].irq_name = devm_kasprintf(dev, GFP_KERNEL, "adc-sdam%d", i);
+ if (!adc->base[i].irq_name) {
+ kfree(reg);
+ ret = -ENOMEM;
+ goto err_irq;
+ }
+
+ ret = platform_get_irq_byname(pdev, adc->base[i].irq_name);
+ if (ret < 0) {
+ kfree(reg);
+ dev_err(dev, "Getting IRQ %d by name failed, ret = %d\n",
+ adc->base[i].irq, ret);
+ goto err_irq;
+ }
+ adc->base[i].irq = ret;
+
+ ret = request_irq(adc->base[i].irq, adc5_gen3_isr, 0, adc->base[i].irq_name, adc);
+ if (ret < 0) {
+ kfree(reg);
+ dev_err(dev, "Failed to request SDAM%d irq, ret = %d\n", i, ret);
+ goto err_irq;
+ }
+ }
+ kfree(reg);
+
+ ret = devm_add_action(dev, adc5_gen3_disable, adc);
+ if (ret < 0) {
+ dev_err(dev, "failed to register adc disablement devm action, %d\n", ret);
+ goto err_irq;
+ }
+
+ ret = adc5_get_fw_data(adc);
+ if (ret < 0) {
+ dev_err(dev, "adc get dt data failed, ret = %d\n", ret);
+ goto err_irq;
+ }
+
+ ret = adc_tm_register_tzd(adc);
+ if (ret < 0)
+ goto err_irq;
+
+ if (adc->n_tm_channels)
+ INIT_WORK(&adc->tm_handler_work, tm_handler_work);
+
+ indio_dev->name = pdev->name;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->info = &adc5_gen3_info;
+ indio_dev->channels = adc->iio_chans;
+ indio_dev->num_channels = adc->nchannels;
+
+ ret = devm_iio_device_register(dev, indio_dev);
+ if (!ret)
+ return 0;
+
+err_irq:
+ for (i = 0; i < adc->num_sdams; i++)
+ free_irq(adc->base[i].irq, adc);
+
+ return ret;
+}
+
+static struct platform_driver adc5_gen3_driver = {
+ .driver = {
+ .name = "qcom-spmi-adc5-gen3",
+ .of_match_table = adc5_match_table,
+ },
+ .probe = adc5_gen3_probe,
+};
+module_platform_driver(adc5_gen3_driver);
+
+MODULE_DESCRIPTION("Qualcomm Technologies Inc. PMIC5 Gen3 ADC driver");
+MODULE_LICENSE("GPL");
--
2.25.1

2023-12-31 17:41:50

[permalink] [raw]

Subject: Re: [PATCH v3 2/3] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC

On Sun, 31 Dec 2023 at 19:13, Jishnu Prakash <[email protected]> wrote:
>
> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the
> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs.
>
> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs
> going through PBS(Programmable Boot Sequence) firmware through a single
> register interface. This interface is implemented on an SDAM (Shared
> Direct Access Memory) peripheral on the master PMIC PMK8550 rather
> than a dedicated ADC peripheral.
>
> Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC
> channels and virtual channels (combination of ADC channel number and
> PMIC SID number) per PMIC, to be used by clients of this device.
>
> Changes since v2:
> - Moved ADC5 Gen3 documentation into a separate new file.
>
> Changes since v1:
> - Updated properties separately for all compatibles to clarify usage
> of new properties and updates in usage of old properties for ADC5 Gen3.
> - Avoided updating 'adc7' name to 'adc5 gen2' and just left a comment
> mentioning this convention.
> - Used predefined channel IDs in individual PMIC channel definitions
> instead of numeric IDs.
> - Addressed other comments from reviewers.
>
> Co-developed-by: Anjelique Melendez <[email protected]>
> Signed-off-by: Anjelique Melendez <[email protected]>
> Signed-off-by: Jishnu Prakash <[email protected]>
> ---
> .../bindings/iio/adc/qcom,spmi-adc5-gen3.yaml | 212 ++++++++++++++++++
> .../iio/adc/qcom,spmi-adc5-gen3-pm8550.h | 50 +++++
> .../iio/adc/qcom,spmi-adc5-gen3-pm8550b.h | 89 ++++++++
> .../iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h | 22 ++
> .../iio/adc/qcom,spmi-adc5-gen3-pmk8550.h | 56 +++++
> .../iio/adc/qcom,spmi-adc7-pmr735b.h | 2 +-
> .../iio/adc/qcom,spmi-adc7-smb139x.h | 2 +-
> include/dt-bindings/iio/adc/qcom,spmi-vadc.h | 81 +++++++
> 8 files changed, 512 insertions(+), 2 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml
> create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h
> create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h
> create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h
> create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml
> new file mode 100644
> index 000000000000..ed5bb53e7628
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml
> @@ -0,0 +1,212 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-adc5-gen3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm's SPMI PMIC ADC5 Gen3
> +
> +maintainers:
> + - Jishnu Prakash <[email protected]>
> +
> +description: |
> + SPMI PMIC5 Gen3 voltage ADC (ADC) provides interface to
> + clients to read voltage. It is a 16-bit sigma-delta ADC.
> + It also performs the same thermal monitoring function as
> + the existing ADC_TM devices.
> +
> +properties:
> + compatible:
> + const: qcom,spmi-adc5-gen3
> +
> + reg:
> + description: |
> + - Each reg corresponds to an SDAM peripheral base address that is being used for ADC.
> +
> + '#address-cells':
> + const: 1
> +
> + '#size-cells':
> + const: 0
> +
> + "#thermal-sensor-cells":
> + const: 1
> + description:
> + Number of cells required to uniquely identify the thermal sensors. Since
> + we have multiple sensors this is set to 1. This property is required for
> + ADC devices with channels used for TM (thermal monitoring) functionality.
> +
> + '#io-channel-cells':
> + const: 1
> +
> + interrupts:
> + description: |
> + End of conversion interrupt. Interrupts are defined for each SDAM being used.
> +
> + interrupt-names:
> + minItems: 1
> + maxItems: 10
> + items:
> + pattern: "^adc-sdam[0-9]+$"
> + description: |
> + Names should be defined as "adc-sdam<N>" where <N> represents the SDAM index.
> +
> +required:
> + - compatible
> + - reg
> + - '#address-cells'
> + - '#size-cells'
> + - '#io-channel-cells'
> + - interrupts
> + - interrupt-names
> +
> +patternProperties:
> + "^channel@[0-9a-f]+$":
> + type: object
> + additionalProperties: false
> + description: |
> + Represents the external channels which are connected to the ADC.
> +
> + properties:
> + reg:
> + maxItems: 1
> + description: |
> + ADC channel number.
> + See include/dt-bindings/iio/adc/qcom,spmi-vadc.h
> + For PMIC5 Gen3 ADC, the channel numbers are specified separately
> + per PMIC in the PMIC-specific files in include/dt-bindings/iio/adc.
> +
> + label:
> + $ref: /schemas/types.yaml#/definitions/string
> + description: |
> + ADC input of the platform as seen in the schematics.
> + For thermistor inputs connected to generic AMUX or GPIO inputs
> + these can vary across platform for the same pins. Hence select
> + the platform schematics name for this channel.
> +
> + qcom,decimation:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + This parameter is used to decrease ADC sampling rate.
> + Quicker measurements can be made by reducing decimation ratio.
> + enum: [ 85, 340, 1360 ]
> + default: 1360
> +
> + qcom,pre-scaling:
> + description: |
> + Used for scaling the channel input signal before the signal is
> + fed to VADC. The configuration for this node is to know the
> + pre-determined ratio and use it for post scaling. It is a pair of
> + integers, denoting the numerator and denominator of the fraction by which
> + input signal is multiplied. For example, <1 3> indicates the signal is scaled
> + down to 1/3 of its value before ADC measurement.
> + If property is not found default value depending on chip will be used.
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + items:
> + - const: 1
> + - enum: [ 1, 3, 6, 16 ]
> +
> + qcom,ratiometric:
> + description: |
> + Channel calibration type.
> + - If this property is specified VADC will use the VDD reference (1.875V)
> + and GND for channel calibration. If property is not found, channel will be
> + calibrated with 0V and 1.25V reference channels, also known as
> + absolute calibration.
> + type: boolean
> +
> + qcom,hw-settle-time:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + Time between AMUX getting configured and the ADC starting
> + conversion. The 'hw_settle_time' is an index used from valid values
> + and programmed in hardware to achieve the hardware settling delay.
> + enum: [ 15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000,
> + 8000, 16000, 32000, 64000, 128000 ]
> + default: 15
> +
> + qcom,avg-samples:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + Number of samples to be used for measurement.
> + Averaging provides the option to obtain a single measurement
> + from the ADC that is an average of multiple samples. The value
> + selected is 2^(value).
> + enum: [ 1, 2, 4, 8, 16 ]
> + default: 1
> +
> + qcom,adc-tm:
> + description: |
> + Indicates if ADC_TM monitoring is done on this channel.
> + Defined for compatible property "qcom,spmi-adc5-gen3".
> + This is the same functionality as in the existing QCOM ADC_TM
> + device, documented at devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml.
> + type: boolean
> +
> + required:
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h>
> + #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h>
> + #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h>
> + #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + pmic {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* VADC node */
> + pmk8550_vadc: vadc@9000 {
> + compatible = "qcom,spmi-adc5-gen3";
> + reg = <0x9000>, <0x9100>;
> + interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>,
> + <0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "adc-sdam0", "adc-sdam1";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #io-channel-cells = <1>;
> + #thermal-sensor-cells = <1>;
> +
> + /* PMK8550 Channel nodes */
> + channel@3 {
> + reg = <PMK8550_ADC5_GEN3_DIE_TEMP>;
> + label = "pmk8550_die_temp";
> + qcom,pre-scaling = <1 1>;
> + };
> +
> + channel@44 {
> + reg = <PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU>;
> + label = "pmk8550_xo_therm";
> + qcom,pre-scaling = <1 1>;
> + qcom,ratiometric;
> + qcom,hw-settle-time = <200>;
> + qcom,adc-tm;
> + };
> +
> + /* PM8550 Channel nodes */
> + channel@103 {
> + reg = <PM8550_ADC5_GEN3_DIE_TEMP>;
> + label = "pm8550_die_temp";
> + qcom,pre-scaling = <1 1>;
> + };
> +
> + /* PM8550B Channel nodes */
> + channel@78f {
> + reg = <PM8550B_ADC5_GEN3_VBAT_SNS_QBG>;
> + label = "pm8550b_vbat_sns_qbg";
> + qcom,pre-scaling = <1 3>;
> + };
> +
> + /* PM8550VS_C Channel nodes */
> + channel@203 {
> + reg = <PM8550VS_ADC5_GEN3_DIE_TEMP(2)>;
> + label = "pm8550vs_c_die_temp";
> + qcom,pre-scaling = <1 1>;
> + };
> + };
> + };
> diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h
> new file mode 100644
> index 000000000000..0f25ef87ed5c
> --- /dev/null
> +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h
> @@ -0,0 +1,50 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H
> +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H
> +
> +#ifndef PM8550_SID
> +#define PM8550_SID 1
> +#endif

Please drop these defaults.
We should drop them from the existing binding files too...

> +
> +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
>

--
With best wishes
Dmitry

2023-12-31 17:47:31

[permalink] [raw]

Subject: Re: [PATCH v3 3/3] iio: adc: Add support for QCOM PMIC5 Gen3 ADC

On Sun, 31 Dec 2023 at 19:13, Jishnu Prakash <[email protected]> wrote:
>
> The ADC architecture on PMIC5 Gen3 is similar to that on PMIC5 Gen2,
> with all SW communication to ADC going through PMK8550 which
> communicates with other PMICs through PBS.
>
> One major difference is that the register interface used here is that
> of an SDAM (Shared Direct Access Memory) peripheral present on PMK8550.
> There may be more than one SDAM used for ADC5 Gen3 and each has eight
> channels, which may be used for either immediate reads (same functionality
> as previous PMIC5 and PMIC5 Gen2 ADC peripherals) or recurring measurements
> (same as ADC_TM functionality).
>
> In this case, we have VADC and ADC_TM functionality combined into the
> same driver. By convention, we reserve the first channel of the first
> SDAM for all immediate reads and use the remaining channels across all
> SDAMs for ADC_TM monitoring functionality.
>
> Changes since v1:
> - Removed datashet_name usage and implemented read_label() function
> - In probe, updated channel property in iio_chan_spec from individual
> channel to virtual channel and set indexed property to 1, due to the
> above change.
> - Updated order of checks in ISR
> - Removed the driver remove callback and replaced with callbacks in a
> devm_add_action call in probe.
> - Addressed other comments from reviewers.
>
> Signed-off-by: Jishnu Prakash <[email protected]>
> ---
> drivers/iio/adc/Kconfig | 25 +
> drivers/iio/adc/Makefile | 1 +
> drivers/iio/adc/qcom-spmi-adc5-gen3.c | 1198 +++++++++++++++++++++++++
> 3 files changed, 1224 insertions(+)
> create mode 100644 drivers/iio/adc/qcom-spmi-adc5-gen3.c
>
> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> index 4eebd5161419..4bdd5bb5b3fc 100644
> --- a/drivers/iio/adc/Kconfig
> +++ b/drivers/iio/adc/Kconfig
> @@ -997,6 +997,31 @@ config QCOM_SPMI_ADC5
> To compile this driver as a module, choose M here: the module will
> be called qcom-spmi-adc5.
>
> +config QCOM_SPMI_ADC5_GEN3
> + tristate "Qualcomm Technologies Inc. SPMI PMIC5 GEN3 ADC"
> + depends on SPMI && THERMAL
> + select REGMAP_SPMI
> + select QCOM_VADC_COMMON
> + help
> + This is the IIO Voltage PMIC5 Gen3 ADC driver for Qualcomm Technologies Inc. PMICs.
> +
> + The driver supports reading multiple channels. The ADC is a 16-bit
> + sigma-delta ADC. The hardware supports calibrated results for
> + conversion requests and clients include reading phone power supply
> + voltage, on board system thermistors connected to the PMIC ADC,
> + PMIC die temperature, charger temperature, battery current, USB voltage
> + input and voltage signals connected to supported PMIC GPIO pins. The
> + hardware supports internal pull-up for thermistors and can choose between
> + a 30k, 100k or 400k ohm pull up using the ADC channels.
> +
> + In addition, the same driver supports ADC thermal monitoring devices too.
> + They appear as thermal zones with multiple trip points. A thermal client sets
> + threshold temperature for both warm and cool trips and gets updated when a
> + threshold is reached.
> +
> + To compile this driver as a module, choose M here: the module will
> + be called qcom-spmi-adc5-gen3.
> +
> config RCAR_GYRO_ADC
> tristate "Renesas R-Car GyroADC driver"
> depends on ARCH_RCAR_GEN2 || COMPILE_TEST
> diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
> index c0803383a7cc..539af17a668f 100644
> --- a/drivers/iio/adc/Makefile
> +++ b/drivers/iio/adc/Makefile
> @@ -86,6 +86,7 @@ obj-$(CONFIG_NAU7802) += nau7802.o
> obj-$(CONFIG_NPCM_ADC) += npcm_adc.o
> obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
> obj-$(CONFIG_QCOM_SPMI_ADC5) += qcom-spmi-adc5.o
> +obj-$(CONFIG_QCOM_SPMI_ADC5_GEN3) += qcom-spmi-adc5-gen3.o
> obj-$(CONFIG_QCOM_SPMI_IADC) += qcom-spmi-iadc.o
> obj-$(CONFIG_QCOM_SPMI_RRADC) += qcom-spmi-rradc.o
> obj-$(CONFIG_QCOM_VADC_COMMON) += qcom-vadc-common.o
> diff --git a/drivers/iio/adc/qcom-spmi-adc5-gen3.c b/drivers/iio/adc/qcom-spmi-adc5-gen3.c
> new file mode 100644
> index 000000000000..5b5848492245
> --- /dev/null
> +++ b/drivers/iio/adc/qcom-spmi-adc5-gen3.c
> @@ -0,0 +1,1198 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <asm/unaligned.h>
> +#include <linux/bitfield.h>
> +#include <linux/bitops.h>
> +#include <linux/completion.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/iio/iio.h>
> +#include <linux/iio/adc/qcom-vadc-common.h>
> +#include <linux/interrupt.h>
> +#include <linux/kernel.h>
> +#include <linux/log2.h>
> +#include <linux/math64.h>
> +#include <linux/module.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/platform_device.h>
> +#include <linux/property.h>
> +#include <linux/regmap.h>
> +#include <linux/slab.h>
> +#include <linux/thermal.h>
> +
> +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
> +
> +#define ADC5_GEN3_HS 0x45
> +#define ADC5_GEN3_HS_BUSY BIT(7)
> +#define ADC5_GEN3_HS_READY BIT(0)
> +
> +#define ADC5_GEN3_STATUS1 0x46
> +#define ADC5_GEN3_STATUS1_CONV_FAULT BIT(7)
> +#define ADC5_GEN3_STATUS1_THR_CROSS BIT(6)
> +#define ADC5_GEN3_STATUS1_EOC BIT(0)
> +
> +#define ADC5_GEN3_TM_EN_STS 0x47
> +#define ADC5_GEN3_TM_HIGH_STS 0x48
> +#define ADC5_GEN3_TM_LOW_STS 0x49
> +
> +#define ADC5_GEN3_EOC_STS 0x4a
> +#define ADC5_GEN3_EOC_CHAN_0 BIT(0)
> +
> +#define ADC5_GEN3_EOC_CLR 0x4b
> +#define ADC5_GEN3_TM_HIGH_STS_CLR 0x4c
> +#define ADC5_GEN3_TM_LOW_STS_CLR 0x4d
> +#define ADC5_GEN3_CONV_ERR_CLR 0x4e
> +#define ADC5_GEN3_CONV_ERR_CLR_REQ BIT(0)
> +
> +#define ADC5_GEN3_SID 0x4f
> +#define ADC5_GEN3_SID_MASK GENMASK(3, 0)
> +
> +#define ADC5_GEN3_PERPH_CH 0x50
> +#define ADC5_GEN3_CHAN_CONV_REQ BIT(7)
> +
> +#define ADC5_GEN3_TIMER_SEL 0x51
> +#define ADC5_GEN3_TIME_IMMEDIATE 0x1
> +
> +#define ADC5_GEN3_DIG_PARAM 0x52
> +#define ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK GENMASK(5, 4)
> +#define ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK GENMASK(3, 2)
> +
> +#define ADC5_GEN3_FAST_AVG 0x53
> +#define ADC5_GEN3_FAST_AVG_CTL_EN BIT(7)
> +#define ADC5_GEN3_FAST_AVG_CTL_SAMPLES_MASK GENMASK(2, 0)
> +
> +#define ADC5_GEN3_ADC_CH_SEL_CTL 0x54
> +#define ADC5_GEN3_DELAY_CTL 0x55
> +#define ADC5_GEN3_HW_SETTLE_DELAY_MASK GENMASK(3, 0)
> +
> +#define ADC5_GEN3_CH_EN 0x56
> +#define ADC5_GEN3_HIGH_THR_INT_EN BIT(1)
> +#define ADC5_GEN3_LOW_THR_INT_EN BIT(0)
> +
> +#define ADC5_GEN3_LOW_THR0 0x57
> +#define ADC5_GEN3_LOW_THR1 0x58
> +#define ADC5_GEN3_HIGH_THR0 0x59
> +#define ADC5_GEN3_HIGH_THR1 0x5a
> +
> +#define ADC5_GEN3_CH_DATA0(channel) (0x5c + (channel) * 2)
> +#define ADC5_GEN3_CH_DATA1(channel) (0x5d + (channel) * 2)
> +
> +#define ADC5_GEN3_CONV_REQ 0xe5
> +#define ADC5_GEN3_CONV_REQ_REQ BIT(0)
> +
> +#define ADC5_GEN3_VIRTUAL_SID_MASK GENMASK(15, 8)
> +#define ADC5_GEN3_CHANNEL_MASK GENMASK(7, 0)
> +#define V_CHAN(x) \
> + (FIELD_PREP(ADC5_GEN3_VIRTUAL_SID_MASK, (x).sid) | (x).channel) \
> +
> +enum adc5_cal_method {
> + ADC5_NO_CAL = 0,
> + ADC5_RATIOMETRIC_CAL,
> + ADC5_ABSOLUTE_CAL
> +};
> +
> +enum adc5_time_select {
> + MEAS_INT_DISABLE = 0,
> + MEAS_INT_IMMEDIATE,
> + MEAS_INT_50MS,
> + MEAS_INT_100MS,
> + MEAS_INT_1S,
> + MEAS_INT_NONE,
> +};
> +
> +struct adc5_sdam_data {
> + u16 base_addr;
> + const char *irq_name;
> + int irq;
> +};
> +
> +/**
> + * struct adc5_channel_prop - ADC channel property.
> + * @channel: channel number, refer to the channel list.
> + * @cal_method: calibration method.
> + * @decimation: sampling rate supported for the channel.
> + * @sid: slave id of PMIC owning the channel.
> + * @prescale: channel scaling performed on the input signal.
> + * @hw_settle_time: the time between AMUX being configured and the
> + * start of conversion.
> + * @avg_samples: ability to provide single result from the ADC
> + * that is an average of multiple measurements.
> + * @sdam_index: Index for which SDAM this channel is on.
> + * @scale_fn_type: Represents the scaling function to convert voltage
> + * physical units desired by the client for the channel.
> + * @label: Channel name used in device tree.
> + * @chip: pointer to top-level ADC device structure.
> + * @adc_tm: indicates if the channel is used for TM measurements.
> + * @tm_chan_index: TM channel number used (ranging from 1-7).
> + * @timer: time period of recurring TM measurement.
> + * @tzd: pointer to thermal device corresponding to TM channel.
> + * @high_thr_en: TM high threshold crossing detection enabled.
> + * @low_thr_en: TM low threshold crossing detection enabled.
> + * @last_temp: last temperature that caused threshold violation,
> + * or a thermal TM channel.
> + * @last_temp_set: indicates if last_temp is stored.
> + */
> +struct adc5_channel_prop {
> + unsigned int channel;
> + enum adc5_cal_method cal_method;
> + unsigned int decimation;
> + unsigned int sid;
> + unsigned int prescale;
> + unsigned int hw_settle_time;
> + unsigned int avg_samples;
> + unsigned int sdam_index;
> +
> + enum vadc_scale_fn_type scale_fn_type;
> + const char *label;
> +
> + struct adc5_chip *chip;
> + /* TM(thermal monitoring related) properties */
> + bool adc_tm;
> + unsigned int tm_chan_index;
> + unsigned int timer;
> + struct thermal_zone_device *tzd;
> + bool high_thr_en;
> + bool low_thr_en;
> + int last_temp;
> + bool last_temp_set;
> +};
> +
> +/**
> + * struct adc5_chip - ADC private structure.
> + * @regmap: SPMI ADC5 Gen3 peripheral register map field.
> + * @dev: SPMI ADC5 Gen3 device.
> + * @base: pointer to array of ADC peripheral base and interrupt.
> + * @num_sdams: number of SDAMs (Shared Direct Access Memory Module) being used.
> + * @nchannels: number of ADC channels.
> + * @chan_props: array of ADC channel properties.
> + * @iio_chans: array of IIO channels specification.
> + * @complete: ADC result notification after interrupt is received.
> + * @lock: ADC lock for access to the peripheral, to prevent concurrent
> + * requests from multiple clients.
> + * @data: software configuration data.
> + * @n_tm_channels: number of ADC channels used for TM measurements.
> + * @tm_handler_work: scheduled work for handling TM threshold violation.
> + */
> +struct adc5_chip {
> + struct regmap *regmap;
> + struct device *dev;
> + struct adc5_sdam_data *base;
> + unsigned int num_sdams;
> + unsigned int nchannels;
> + struct adc5_channel_prop *chan_props;
> + struct iio_chan_spec *iio_chans;
> + struct completion complete;
> + struct mutex lock;
> + const struct adc5_data *data;
> + /* TM properties */
> + unsigned int n_tm_channels;
> + struct work_struct tm_handler_work;
> +};
> +
> +static int adc5_gen3_read(struct adc5_chip *adc, unsigned int sdam_index,
> + u16 offset, u8 *data, int len)
> +{
> + return regmap_bulk_read(adc->regmap, adc->base[sdam_index].base_addr + offset, data, len);
> +}
> +
> +static int adc5_gen3_write(struct adc5_chip *adc, unsigned int sdam_index,
> + u16 offset, u8 *data, int len)
> +{
> + return regmap_bulk_write(adc->regmap, adc->base[sdam_index].base_addr + offset, data, len);
> +}
> +
> +static int adc5_gen3_read_voltage_data(struct adc5_chip *adc, u16 *data, u8 sdam_index)
> +{
> + int ret;
> + u8 rslt[2];
> +
> + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_CH_DATA0(0), rslt, 2);
> + if (ret)
> + return ret;
> +
> + *data = get_unaligned_le16(rslt);
> +
> + if (*data == ADC5_USR_DATA_CHECK) {
> + dev_err(adc->dev, "Invalid data:%#x\n", *data);
> + return -EINVAL;
> + }
> +
> + dev_dbg(adc->dev, "voltage raw code:%#x\n", *data);
> +
> + return 0;
> +}
> +
> +static void adc5_gen3_update_dig_param(struct adc5_chip *adc,
> + struct adc5_channel_prop *prop, u8 *data)
> +{
> + /* Update calibration select and decimation ratio select*/
> + *data &= ~(ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK | ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK);
> + *data |= FIELD_PREP(ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK, prop->cal_method);
> + *data |= FIELD_PREP(ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK, prop->decimation);
> +}
> +
> +# define ADC5_GEN3_READ_CONFIG_REGS 7
> +
> +static int adc5_gen3_configure(struct adc5_chip *adc,
> + struct adc5_channel_prop *prop)
> +{
> + u8 sdam_index = prop->sdam_index;
> + u8 conv_req = 0;
> + u8 buf[ADC5_GEN3_READ_CONFIG_REGS];
> + int ret;
> +
> + /* Reserve channel 0 of first SDAM for immediate conversions */
> + if (prop->adc_tm)
> + sdam_index = 0;
> +
> + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_SID, buf, sizeof(buf));
> + if (ret)
> + return ret;
> +
> + /* Write SID */
> + buf[0] = FIELD_PREP(ADC5_GEN3_SID_MASK, prop->sid);
> +
> + /*
> + * Use channel 0 by default for immediate conversion and
> + * to indicate there is an actual conversion request
> + */
> + buf[1] = ADC5_GEN3_CHAN_CONV_REQ | 0;
> +
> + buf[2] = ADC5_GEN3_TIME_IMMEDIATE;
> +
> + /* Digital param selection */
> + adc5_gen3_update_dig_param(adc, prop, &buf[3]);
> +
> + /* Update fast average sample value */
> + buf[4] &= ~ADC5_GEN3_FAST_AVG_CTL_SAMPLES_MASK;
> + buf[4] |= prop->avg_samples | ADC5_GEN3_FAST_AVG_CTL_EN;
> +
> + /* Select ADC channel */
> + buf[5] = prop->channel;
> +
> + /* Select HW settle delay for channel */
> + buf[6] = FIELD_PREP(ADC5_GEN3_HW_SETTLE_DELAY_MASK, prop->hw_settle_time);
> +
> + reinit_completion(&adc->complete);
> +
> + ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_SID, buf, sizeof(buf));
> + if (ret)
> + return ret;
> +
> + conv_req = ADC5_GEN3_CONV_REQ_REQ;
> + return adc5_gen3_write(adc, sdam_index, ADC5_GEN3_CONV_REQ, &conv_req, 1);
> +}
> +
> +/**
> + * Worst case delay from PBS in readying handshake bit
> + * can be up to 15ms, when PBS is busy running other
> + * simultaneous transactions, while in the best case, it is
> + * already ready at this point. Assigning polling delay and
> + * retry count accordingly.
> + */
> +
> +#define ADC5_GEN3_HS_DELAY_MIN_US 100
> +#define ADC5_GEN3_HS_DELAY_MAX_US 110
> +#define ADC5_GEN3_HS_RETRY_COUNT 150
> +
> +static int adc5_gen3_poll_wait_hs(struct adc5_chip *adc,
> + unsigned int sdam_index)
> +{
> + u8 conv_req = ADC5_GEN3_CONV_REQ_REQ;
> + u8 status = 0;
> + int ret, count;
> +
> + for (count = 0; count < ADC5_GEN3_HS_RETRY_COUNT; count++) {
> + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_HS, &status, 1);
> + if (ret)
> + return ret;
> +
> + if (status == ADC5_GEN3_HS_READY) {
> + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_CONV_REQ,
> + &conv_req, 1);
> + if (ret)
> + return ret;
> +
> + if (!conv_req)
> + return 0;
> + }
> +
> + usleep_range(ADC5_GEN3_HS_DELAY_MIN_US,
> + ADC5_GEN3_HS_DELAY_MAX_US);
> + }
> +
> + dev_err(adc->dev, "Setting HS ready bit timed out, status:%#x\n", status);
> + return -ETIMEDOUT;
> +}
> +
> +/**
> + * Worst case delay from PBS for conversion time can be
> + * up to 500ms, when PBS has timed out twice, once for
> + * the initial attempt and once for a retry of the same
> + * transaction.
> + */
> +
> +#define ADC5_GEN3_CONV_TIMEOUT_MS 501
> +
> +static int adc5_gen3_do_conversion(struct adc5_chip *adc,
> + struct adc5_channel_prop *prop,
> + u16 *data_volt)
> +{
> + u8 val, sdam_index = prop->sdam_index;
> + unsigned long rc;
> + int ret;
> +
> + /* Reserve channel 0 of first SDAM for immediate conversions */
> + if (prop->adc_tm)
> + sdam_index = 0;
> +
> + mutex_lock(&adc->lock);
> + ret = adc5_gen3_poll_wait_hs(adc, 0);
> + if (ret)
> + goto unlock;
> +
> + ret = adc5_gen3_configure(adc, prop);
> + if (ret) {
> + dev_err(adc->dev, "ADC configure failed with %d\n", ret);
> + goto unlock;
> + }
> +
> + /* No support for polling mode at present*/
> + rc = wait_for_completion_timeout(&adc->complete,
> + msecs_to_jiffies(ADC5_GEN3_CONV_TIMEOUT_MS));
> + if (!rc) {
> + dev_err(adc->dev, "Reading ADC channel %s timed out\n",
> + prop->label);
> + ret = -ETIMEDOUT;
> + goto unlock;
> + }
> +
> + ret = adc5_gen3_read_voltage_data(adc, data_volt, sdam_index);
> + if (ret)
> + goto unlock;
> +
> + val = BIT(0);
> + ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_EOC_CLR, &val, 1);
> + if (ret)
> + goto unlock;
> +
> + /* To indicate conversion request is only to clear a status */
> + val = 0;
> + ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_PERPH_CH, &val, 1);
> + if (ret)
> + goto unlock;
> +
> + val = ADC5_GEN3_CONV_REQ_REQ;
> + ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_CONV_REQ, &val, 1);
> +
> +unlock:
> + mutex_unlock(&adc->lock);
> +
> + return ret;
> +}
> +
> +static int get_sdam_from_irq(struct adc5_chip *adc, int irq)
> +{
> + int i;
> +
> + for (i = 0; i < adc->num_sdams; i++) {
> + if (adc->base[i].irq == irq)
> + return i;
> + }
> + return -ENOENT;
> +}
> +
> +static irqreturn_t adc5_gen3_isr(int irq, void *dev_id)
> +{
> + struct adc5_chip *adc = dev_id;
> + u8 status, tm_status[2], eoc_status, val;
> + int ret, sdam_num;
> +
> + sdam_num = get_sdam_from_irq(adc, irq);
> + if (sdam_num < 0) {
> + dev_err(adc->dev, "adc irq %d not associated with an sdam\n", irq);
> + return IRQ_HANDLED;
> + }
> +
> + ret = adc5_gen3_read(adc, sdam_num, ADC5_GEN3_STATUS1, &status, 1);
> + if (ret) {
> + dev_err(adc->dev, "adc read status1 failed with %d\n", ret);
> + return IRQ_HANDLED;
> + }
> +
> + ret = adc5_gen3_read(adc, sdam_num, ADC5_GEN3_EOC_STS, &eoc_status, 1);
> + if (ret) {
> + dev_err(adc->dev, "adc read eoc status failed with %d\n", ret);
> + return IRQ_HANDLED;
> + }
> +
> + if (status & ADC5_GEN3_STATUS1_CONV_FAULT) {
> + dev_err_ratelimited(adc->dev, "Unexpected conversion fault, status:%#x, eoc_status:%#x\n",
> + status, eoc_status);
> + val = ADC5_GEN3_CONV_ERR_CLR_REQ;
> + ret = adc5_gen3_write(adc, sdam_num, ADC5_GEN3_CONV_ERR_CLR, &val, 1);
> + if (ret < 0)
> + return IRQ_HANDLED;
> +
> + /* To indicate conversion request is only to clear a status */
> + val = 0;
> + ret = adc5_gen3_write(adc, sdam_num, ADC5_GEN3_PERPH_CH, &val, 1);
> + if (ret < 0)
> + return IRQ_HANDLED;
> +
> + val = ADC5_GEN3_CONV_REQ_REQ;
> + ret = adc5_gen3_write(adc, sdam_num, ADC5_GEN3_CONV_REQ, &val, 1);
> +
> + return IRQ_HANDLED;
> + }
> +
> + /* CHAN0 is the preconfigured channel for immediate conversion */
> + if (eoc_status & ADC5_GEN3_EOC_CHAN_0)
> + complete(&adc->complete);
> +
> + ret = adc5_gen3_read(adc, sdam_num, ADC5_GEN3_TM_HIGH_STS, tm_status, 2);
> + if (ret) {
> + dev_err(adc->dev, "adc read TM status failed with %d\n", ret);
> + return IRQ_HANDLED;
> + }
> +
> + if (tm_status[0] || tm_status[1])
> + schedule_work(&adc->tm_handler_work);
> +
> + dev_dbg(adc->dev, "Interrupt status:%#x, EOC status:%#x, high:%#x, low:%#x\n",
> + status, eoc_status, tm_status[0], tm_status[1]);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static void tm_handler_work(struct work_struct *work)
> +{
> + struct adc5_chip *adc = container_of(work, struct adc5_chip, tm_handler_work);
> + struct adc5_channel_prop *chan_prop;
> + u8 tm_status[2] = {0};
> + u8 buf[16] = {0};
> + u8 val;
> + int ret, i, sdam_index = -1;
> +
> + for (i = 0; i < adc->nchannels; i++) {
> + bool upper_set = false, lower_set = false;
> + int temp, offset;
> + u16 code = 0;
> +
> + chan_prop = &adc->chan_props[i];
> + offset = chan_prop->tm_chan_index;
> +
> + if (!chan_prop->adc_tm)
> + continue;
> +
> + mutex_lock(&adc->lock);
> + if (chan_prop->sdam_index != sdam_index) {
> + sdam_index = chan_prop->sdam_index;
> + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_TM_HIGH_STS,
> + tm_status, 2);
> + if (ret) {
> + dev_err(adc->dev, "adc read TM status failed with %d\n", ret);
> + goto out;
> + }
> +
> + ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_TM_HIGH_STS_CLR,
> + tm_status, 2);
> + if (ret) {
> + dev_err(adc->dev, "adc write TM status failed with %d\n", ret);
> + goto out;
> + }
> +
> + /* To indicate conversion request is only to clear a status */
> + val = 0;
> + ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_PERPH_CH, &val, 1);
> + if (ret) {
> + dev_err(adc->dev, "adc write status clear conv_req failed with %d\n",
> + ret);
> + goto out;
> + }
> +
> + val = ADC5_GEN3_CONV_REQ_REQ;
> + ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_CONV_REQ, &val, 1);
> + if (ret) {
> + dev_err(adc->dev, "adc write conv_req failed with %d\n", ret);
> + goto out;
> + }
> +
> + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_CH_DATA0(0), buf,
> + sizeof(buf));
> + if (ret < 0) {
> + dev_err(adc->dev, "adc read data failed with %d\n", ret);
> + goto out;
> + }
> + }
> +
> + if ((tm_status[0] & BIT(offset)) && (chan_prop->high_thr_en))
> + upper_set = true;
> +
> + if ((tm_status[1] & BIT(offset)) && (chan_prop->low_thr_en))
> + lower_set = true;
> +
> + mutex_unlock(&adc->lock);
> +
> + if (!(upper_set || lower_set))
> + continue;
> +
> + code = get_unaligned_le16(&buf[2 * offset]);
> + pr_debug("ADC_TM threshold code:%#x\n", code);
> +
> + ret = qcom_adc5_hw_scale(chan_prop->scale_fn_type,
> + chan_prop->prescale, adc->data, code, &temp);
> + if (ret) {
> + dev_err(adc->dev, "Invalid temperature reading, ret = %d, code=%#x\n",
> + ret, code);
> + continue;
> + }
> +
> + chan_prop->last_temp = temp;
> + chan_prop->last_temp_set = true;
> + thermal_zone_device_update(chan_prop->tzd, THERMAL_TRIP_VIOLATED);
> + }
> +
> + return;
> +
> +out:
> + mutex_unlock(&adc->lock);
> +}
> +
> +static int adc5_gen3_fwnode_xlate(struct iio_dev *indio_dev,
> + const struct fwnode_reference_args *iiospec)
> +{
> + struct adc5_chip *adc = iio_priv(indio_dev);
> + int i, v_channel;
> +
> + for (i = 0; i < adc->nchannels; i++) {
> + v_channel = V_CHAN(adc->chan_props[i]);
> + if (v_channel == iiospec->args[0])
> + return i;
> + }
> +
> + return -ENOENT;
> +}
> +
> +static int adc5_gen3_read_raw(struct iio_dev *indio_dev,
> + struct iio_chan_spec const *chan, int *val, int *val2,
> + long mask)
> +{
> + struct adc5_chip *adc = iio_priv(indio_dev);
> + struct adc5_channel_prop *prop;
> + u16 adc_code_volt;
> + int ret;
> +
> + prop = &adc->chan_props[chan->address];
> +
> + switch (mask) {
> + case IIO_CHAN_INFO_PROCESSED:
> + ret = adc5_gen3_do_conversion(adc, prop,
> + &adc_code_volt);
> + if (ret)
> + return ret;
> +
> + ret = qcom_adc5_hw_scale(prop->scale_fn_type,
> + prop->prescale, adc->data,
> + adc_code_volt, val);
> + if (ret)
> + return ret;
> +
> + return IIO_VAL_INT;
> + case IIO_CHAN_INFO_RAW:
> + ret = adc5_gen3_do_conversion(adc, prop,
> + &adc_code_volt);
> + if (ret)
> + return ret;
> + *val = (int)adc_code_volt;
> + return IIO_VAL_INT;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static int adc5_gen3_read_label(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan, char *label)
> +{
> + struct adc5_chip *adc = iio_priv(indio_dev);
> + struct adc5_channel_prop *prop;
> +
> + prop = &adc->chan_props[chan->address];
> + return sprintf(label, "%s\n", prop->label);
> +}
> +
> +static const struct iio_info adc5_gen3_info = {
> + .read_raw = adc5_gen3_read_raw,
> + .read_label = adc5_gen3_read_label,
> + .fwnode_xlate = adc5_gen3_fwnode_xlate,
> +};
> +
> +static int adc_tm_gen3_get_temp(struct thermal_zone_device *tz, int *temp)
> +{
> + struct adc5_channel_prop *prop = tz->devdata;
> + struct adc5_chip *adc;
> + u16 adc_code_volt;
> + int ret;
> +
> + if (!prop || !prop->chip)
> + return -EINVAL;
> +
> + adc = prop->chip;
> +
> + if (prop->last_temp_set) {
> + pr_debug("last_temp: %d\n", prop->last_temp);
> + prop->last_temp_set = false;
> + *temp = prop->last_temp;
> + return 0;
> + }
> +
> + ret = adc5_gen3_do_conversion(adc, prop, &adc_code_volt);
> + if (ret < 0)
> + return ret;
> +
> + return qcom_adc5_hw_scale(prop->scale_fn_type,
> + prop->prescale, adc->data,
> + adc_code_volt, temp);
> +}
> +
> +static int _adc_tm5_gen3_disable_channel(struct adc5_channel_prop *prop)
> +{
> + struct adc5_chip *adc = prop->chip;
> + int ret;
> + u8 val;
> +
> + prop->high_thr_en = false;
> + prop->low_thr_en = false;
> +
> + val = MEAS_INT_DISABLE;
> + ret = adc5_gen3_write(adc, prop->sdam_index, ADC5_GEN3_TIMER_SEL, &val, 1);
> + if (ret)
> + return ret;
> +
> + /* To indicate there is an actual conversion request */
> + val = ADC5_GEN3_CHAN_CONV_REQ | prop->tm_chan_index;
> + ret = adc5_gen3_write(adc, prop->sdam_index, ADC5_GEN3_PERPH_CH, &val, 1);
> + if (ret)
> + return ret;
> +
> + val = ADC5_GEN3_CONV_REQ_REQ;
> + return adc5_gen3_write(adc, prop->sdam_index, ADC5_GEN3_CONV_REQ, &val, 1);
> +}
> +
> +static int adc_tm5_gen3_disable_channel(struct adc5_channel_prop *prop)
> +{
> + return _adc_tm5_gen3_disable_channel(prop);
> +}
> +
> +# define ADC_TM5_GEN3_CONFIG_REGS 12
> +
> +static int adc_tm5_gen3_configure(struct adc5_channel_prop *prop,
> + int low_temp, int high_temp)
> +{
> + struct adc5_chip *adc = prop->chip;
> + u8 conv_req = 0, buf[ADC_TM5_GEN3_CONFIG_REGS];
> + u16 adc_code;
> + int ret;
> +
> + ret = adc5_gen3_poll_wait_hs(adc, prop->sdam_index);
> + if (ret < 0)
> + return ret;
> +
> + ret = adc5_gen3_read(adc, prop->sdam_index, ADC5_GEN3_SID, buf, sizeof(buf));
> + if (ret < 0)
> + return ret;
> +
> + /* Write SID */
> + buf[0] = FIELD_PREP(ADC5_GEN3_SID_MASK, prop->sid);
> +
> + /*
> + * Select TM channel and indicate there is an actual
> + * conversion request
> + */
> + buf[1] = ADC5_GEN3_CHAN_CONV_REQ | prop->tm_chan_index;
> +
> + buf[2] = prop->timer;
> +
> + /* Digital param selection */
> + adc5_gen3_update_dig_param(adc, prop, &buf[3]);
> +
> + /* Update fast average sample value */
> + buf[4] &= ~ADC5_GEN3_FAST_AVG_CTL_SAMPLES_MASK;
> + buf[4] |= prop->avg_samples | ADC5_GEN3_FAST_AVG_CTL_EN;
> +
> + /* Select ADC channel */
> + buf[5] = prop->channel;
> +
> + /* Select HW settle delay for channel */
> + buf[6] = FIELD_PREP(ADC5_GEN3_HW_SETTLE_DELAY_MASK, prop->hw_settle_time);
> +
> + /* High temperature corresponds to low voltage threshold */
> + if (high_temp != INT_MAX) {
> + prop->low_thr_en = true;
> + adc_code = qcom_adc_tm5_gen2_temp_res_scale(high_temp);
> + put_unaligned_le16(adc_code, &buf[8]);
> + } else {
> + prop->low_thr_en = false;
> + }
> +
> + /* Low temperature corresponds to high voltage threshold */
> + if (low_temp != -INT_MAX) {
> + prop->high_thr_en = true;
> + adc_code = qcom_adc_tm5_gen2_temp_res_scale(low_temp);
> + put_unaligned_le16(adc_code, &buf[10]);
> + } else {
> + prop->high_thr_en = false;
> + }
> +
> + buf[7] = 0;
> + if (prop->high_thr_en)
> + buf[7] |= ADC5_GEN3_HIGH_THR_INT_EN;
> + if (prop->low_thr_en)
> + buf[7] |= ADC5_GEN3_LOW_THR_INT_EN;
> +
> + ret = adc5_gen3_write(adc, prop->sdam_index, ADC5_GEN3_SID, buf, sizeof(buf));
> + if (ret < 0)
> + return ret;
> +
> + conv_req = ADC5_GEN3_CONV_REQ_REQ;
> + return adc5_gen3_write(adc, prop->sdam_index, ADC5_GEN3_CONV_REQ, &conv_req, 1);
> +}
> +
> +static int adc_tm5_gen3_set_trip_temp(struct thermal_zone_device *tz,
> + int low_temp, int high_temp)
> +{
> + struct adc5_channel_prop *prop = tz->devdata;
> + struct adc5_chip *adc;
> + int ret;
> +
> + if (!prop || !prop->chip)
> + return -EINVAL;
> +
> + adc = prop->chip;
> +
> + dev_dbg(adc->dev, "channel:%s, low_temp(mdegC):%d, high_temp(mdegC):%d\n",
> + prop->label, low_temp, high_temp);
> +
> + mutex_lock(&adc->lock);
> + if (high_temp == INT_MAX && low_temp <= -INT_MAX)
> + ret = adc_tm5_gen3_disable_channel(prop);
> + else
> + ret = adc_tm5_gen3_configure(prop, low_temp, high_temp);
> + mutex_unlock(&adc->lock);
> +
> + return ret;
> +}
> +
> +static const struct thermal_zone_device_ops adc_tm_ops = {
> + .get_temp = adc_tm_gen3_get_temp,
> + .set_trips = adc_tm5_gen3_set_trip_temp,
> +};
> +
> +static int adc_tm_register_tzd(struct adc5_chip *adc)
> +{
> + unsigned int i, channel;
> + struct thermal_zone_device *tzd;
> +
> + for (i = 0; i < adc->nchannels; i++) {
> + channel = V_CHAN(adc->chan_props[i]);
> +
> + if (!adc->chan_props[i].adc_tm)
> + continue;
> + tzd = devm_thermal_of_zone_register(adc->dev, channel,
> + &adc->chan_props[i], &adc_tm_ops);

It is _very_ useful to register a hwmon too by calling
devm_thermal_add_hwmon_sysfs(). However this becomes tricky, as this
function is not defined in one of the global headers.

This actually points out an issue. You have the ADC driver fused
together with the thermal driver. Can I suggest using the aux device
to split the thermal functionality to the separate driver?

This way it would be possible to use the ADC without any thermal
monitoring in place.

> +
> + if (IS_ERR(tzd)) {
> + if (PTR_ERR(tzd) == -ENODEV) {
> + dev_warn(adc->dev, "thermal sensor on channel %d is not used\n",
> + channel);
> + continue;
> + }
> +
> + dev_err(adc->dev, "Error registering TZ zone:%ld for channel:%d\n",
> + PTR_ERR(tzd), adc->chan_props[i].channel);
> + return PTR_ERR(tzd);
> + }
> + adc->chan_props[i].tzd = tzd;
> + }
> +
> + return 0;
> +}
> +
> +static void adc5_gen3_disable(void *data)
> +{
> + struct adc5_chip *adc = data;
> + int i;
> +
> + if (adc->n_tm_channels)
> + cancel_work_sync(&adc->tm_handler_work);
> +
> + for (i = 0; i < adc->num_sdams; i++)
> + free_irq(adc->base[i].irq, adc);
> +
> + mutex_lock(&adc->lock);
> + /* Disable all available TM channels */
> + for (i = 0; i < adc->nchannels; i++) {
> + if (!adc->chan_props[i].adc_tm)
> + continue;
> + adc5_gen3_poll_wait_hs(adc, adc->chan_props[i].sdam_index);
> + _adc_tm5_gen3_disable_channel(&adc->chan_props[i]);
> + }
> +
> + mutex_unlock(&adc->lock);
> +}
> +
> +struct adc5_channels {
> + unsigned int prescale_index;
> + enum iio_chan_type type;
> + long info_mask;
> + enum vadc_scale_fn_type scale_fn_type;
> +};
> +
> +/* In these definitions, _pre refers to an index into adc5_prescale_ratios. */
> +#define ADC5_CHAN(_type, _mask, _pre, _scale) \
> + { \
> + .prescale_index = _pre, \
> + .type = _type, \
> + .info_mask = _mask, \
> + .scale_fn_type = _scale, \
> + }, \
> +
> +#define ADC5_CHAN_TEMP(_pre, _scale) \
> + ADC5_CHAN(IIO_TEMP, BIT(IIO_CHAN_INFO_PROCESSED), _pre, _scale) \
> +
> +#define ADC5_CHAN_VOLT(_pre, _scale) \
> + ADC5_CHAN(IIO_VOLTAGE, BIT(IIO_CHAN_INFO_PROCESSED), _pre, _scale) \
> +
> +#define ADC5_CHAN_CUR(_pre, _scale) \
> + ADC5_CHAN(IIO_CURRENT, BIT(IIO_CHAN_INFO_PROCESSED), _pre, _scale) \
> +
> +static const struct adc5_channels adc5_gen3_chans_pmic[ADC5_MAX_CHANNEL] = {
> + [ADC5_GEN3_REF_GND] = ADC5_CHAN_VOLT(0, SCALE_HW_CALIB_DEFAULT)
> + [ADC5_GEN3_1P25VREF] = ADC5_CHAN_VOLT(0, SCALE_HW_CALIB_DEFAULT)
> + [ADC5_GEN3_VPH_PWR] = ADC5_CHAN_VOLT(1, SCALE_HW_CALIB_DEFAULT)
> + [ADC5_GEN3_VBAT_SNS_QBG] = ADC5_CHAN_VOLT(1, SCALE_HW_CALIB_DEFAULT)
> + [ADC5_GEN3_USB_SNS_V_16] = ADC5_CHAN_TEMP(8, SCALE_HW_CALIB_DEFAULT)
> + [ADC5_GEN3_VIN_DIV16_MUX] = ADC5_CHAN_TEMP(8, SCALE_HW_CALIB_DEFAULT)
> + [ADC5_GEN3_DIE_TEMP] = ADC5_CHAN_TEMP(0,
> + SCALE_HW_CALIB_PMIC_THERM_PM7)
> + [ADC5_GEN3_TEMP_ALARM_LITE] = ADC5_CHAN_TEMP(0,
> + SCALE_HW_CALIB_PMIC_THERM_PM7)
> + [ADC5_GEN3_AMUX1_THM_100K_PU] = ADC5_CHAN_TEMP(0,
> + SCALE_HW_CALIB_THERM_100K_PU_PM7)
> + [ADC5_GEN3_AMUX2_THM_100K_PU] = ADC5_CHAN_TEMP(0,
> + SCALE_HW_CALIB_THERM_100K_PU_PM7)
> + [ADC5_GEN3_AMUX3_THM_100K_PU] = ADC5_CHAN_TEMP(0,
> + SCALE_HW_CALIB_THERM_100K_PU_PM7)
> + [ADC5_GEN3_AMUX4_THM_100K_PU] = ADC5_CHAN_TEMP(0,
> + SCALE_HW_CALIB_THERM_100K_PU_PM7)
> + [ADC5_GEN3_AMUX5_THM_100K_PU] = ADC5_CHAN_TEMP(0,
> + SCALE_HW_CALIB_THERM_100K_PU_PM7)
> + [ADC5_GEN3_AMUX6_THM_100K_PU] = ADC5_CHAN_TEMP(0,
> + SCALE_HW_CALIB_THERM_100K_PU_PM7)
> + [ADC5_GEN3_AMUX1_GPIO_100K_PU] = ADC5_CHAN_TEMP(0,
> + SCALE_HW_CALIB_THERM_100K_PU_PM7)
> + [ADC5_GEN3_AMUX2_GPIO_100K_PU] = ADC5_CHAN_TEMP(0,
> + SCALE_HW_CALIB_THERM_100K_PU_PM7)
> + [ADC5_GEN3_AMUX3_GPIO_100K_PU] = ADC5_CHAN_TEMP(0,
> + SCALE_HW_CALIB_THERM_100K_PU_PM7)
> + [ADC5_GEN3_AMUX4_GPIO_100K_PU] = ADC5_CHAN_TEMP(0,
> + SCALE_HW_CALIB_THERM_100K_PU_PM7)
> +};
> +
> +static int adc5_gen3_get_fw_channel_data(struct adc5_chip *adc,
> + struct adc5_channel_prop *prop,
> + struct fwnode_handle *fwnode,
> + const struct adc5_data *data)
> +{
> + const char *name = fwnode_get_name(fwnode);
> + const char *channel_name;
> + struct device *dev = adc->dev;
> + u32 chan, value, varr[2], sid = 0;
> + int ret, val;
> +
> + ret = fwnode_property_read_u32(fwnode, "reg", &chan);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "invalid channel number %s\n", name);
> +
> + /*
> + * Value read from "reg" is virtual channel number
> + * virtual channel number = sid << 8 | channel number
> + */
> +
> + sid = FIELD_GET(ADC5_GEN3_VIRTUAL_SID_MASK, chan);
> + chan = FIELD_GET(ADC5_GEN3_CHANNEL_MASK, chan);
> +
> + if (chan > ADC5_GEN3_OFFSET_EXT2)
> + return dev_err_probe(dev, -EINVAL, "%s invalid channel number %d\n", name, chan);
> +
> + prop->channel = chan;
> + prop->sid = sid;
> +
> + ret = fwnode_property_read_string(fwnode, "label", &channel_name);
> + if (ret)
> + channel_name = name;
> + prop->label = channel_name;
> +
> + prop->decimation = ADC5_DECIMATION_DEFAULT;
> + ret = fwnode_property_read_u32(fwnode, "qcom,decimation", &value);
> + if (!ret) {
> + ret = qcom_adc5_decimation_from_dt(value, data->decimation);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "%#x invalid decimation %d\n",
> + chan, value);
> + prop->decimation = ret;
> + }
> +
> + prop->prescale = adc->data->adc_chans[prop->channel].prescale_index;
> + ret = fwnode_property_read_u32_array(fwnode, "qcom,pre-scaling", varr, 2);
> + if (!ret) {
> + ret = qcom_adc5_prescaling_from_dt(varr[0], varr[1]);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "%#x invalid pre-scaling <%d %d>\n",
> + chan, varr[0], varr[1]);
> + prop->prescale = ret;
> + }
> +
> + prop->hw_settle_time = VADC_DEF_HW_SETTLE_TIME;
> + ret = fwnode_property_read_u32(fwnode, "qcom,hw-settle-time", &value);
> + if (!ret) {
> + ret = qcom_adc5_hw_settle_time_from_dt(value,
> + data->hw_settle_1);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "%#x invalid hw-settle-time %d us\n",
> + chan, value);
> + prop->hw_settle_time = ret;
> + }
> +
> + prop->avg_samples = VADC_DEF_AVG_SAMPLES;
> + ret = fwnode_property_read_u32(fwnode, "qcom,avg-samples", &value);
> + if (!ret) {
> + ret = qcom_adc5_avg_samples_from_dt(value);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "%#x invalid avg-samples %d\n",
> + chan, value);
> + prop->avg_samples = ret;
> + }
> +
> + if (fwnode_property_read_bool(fwnode, "qcom,ratiometric"))
> + prop->cal_method = ADC5_RATIOMETRIC_CAL;
> + else
> + prop->cal_method = ADC5_ABSOLUTE_CAL;
> +
> + prop->timer = MEAS_INT_IMMEDIATE;
> +
> + prop->adc_tm = fwnode_property_read_bool(fwnode, "qcom,adc-tm");
> +
> + if (prop->adc_tm) {
> + adc->n_tm_channels++;
> + if (adc->n_tm_channels > ((adc->num_sdams * 8) - 1))
> + return dev_err_probe(adc->dev, -EINVAL,
> + "Number of TM nodes %u greater than channels supported:%u\n",
> + adc->n_tm_channels, (adc->num_sdams * 8) - 1);
> +
> + val = adc->n_tm_channels / 8;
> + prop->sdam_index = val;
> + prop->tm_chan_index = adc->n_tm_channels - (8*val);
> +
> + prop->timer = MEAS_INT_1S;
> + }
> +
> + return 0;
> +}
> +
> +static const struct adc5_data adc5_gen3_data_pmic = {
> + .full_scale_code_volt = 0x70e4,
> + .adc_chans = adc5_gen3_chans_pmic,
> + .info = &adc5_gen3_info,
> + .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX])
> + {85, 340, 1360},
> + .hw_settle_1 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
> + {15, 100, 200, 300, 400, 500, 600, 700,
> + 1000, 2000, 4000, 8000, 16000, 32000,
> + 64000, 128000},
> +};
> +
> +static const struct of_device_id adc5_match_table[] = {
> + {
> + .compatible = "qcom,spmi-adc5-gen3",
> + .data = &adc5_gen3_data_pmic,
> + },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, adc5_match_table);
> +
> +static int adc5_get_fw_data(struct adc5_chip *adc)
> +{
> + const struct adc5_channels *adc_chan;
> + struct iio_chan_spec *iio_chan;
> + struct adc5_channel_prop *chan_props;
> + struct fwnode_handle *child;
> + unsigned int index = 0;
> + int ret;
> +
> + adc->nchannels = device_get_child_node_count(adc->dev);
> + if (!adc->nchannels)
> + return -EINVAL;
> +
> + adc->iio_chans = devm_kcalloc(adc->dev, adc->nchannels,
> + sizeof(*adc->iio_chans), GFP_KERNEL);
> + if (!adc->iio_chans)
> + return -ENOMEM;
> +
> + adc->chan_props = devm_kcalloc(adc->dev, adc->nchannels,
> + sizeof(*adc->chan_props), GFP_KERNEL);
> + if (!adc->chan_props)
> + return -ENOMEM;
> +
> + chan_props = adc->chan_props;
> + adc->n_tm_channels = 0;
> + iio_chan = adc->iio_chans;
> + adc->data = device_get_match_data(adc->dev);
> + if (!adc->data)
> + adc->data = &adc5_gen3_data_pmic;
> +
> + device_for_each_child_node(adc->dev, child) {
> + ret = adc5_gen3_get_fw_channel_data(adc, chan_props, child, adc->data);
> + if (ret < 0) {
> + fwnode_handle_put(child);
> + return ret;
> + }
> +
> + chan_props->chip = adc;
> + chan_props->scale_fn_type =
> + adc->data->adc_chans[chan_props->channel].scale_fn_type;
> + adc_chan = &adc->data->adc_chans[chan_props->channel];
> + iio_chan->channel = V_CHAN(*chan_props);
> + iio_chan->info_mask_separate = adc_chan->info_mask;
> + iio_chan->type = adc_chan->type;
> + iio_chan->address = index;
> + iio_chan->indexed = 1;
> + iio_chan++;
> + chan_props++;
> + index++;
> + }
> +
> + return 0;
> +}
> +
> +static int adc5_gen3_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct iio_dev *indio_dev;
> + struct adc5_chip *adc;
> + struct regmap *regmap;
> + int ret, i;
> + u32 *reg;
> +
> + regmap = dev_get_regmap(dev->parent, NULL);
> + if (!regmap)
> + return -ENODEV;
> +
> + indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
> + if (!indio_dev)
> + return -ENOMEM;
> +
> + adc = iio_priv(indio_dev);
> + adc->regmap = regmap;
> + adc->dev = dev;
> +
> + ret = device_property_count_u32(dev, "reg");
> + if (ret < 0)
> + return ret;
> +
> + adc->num_sdams = ret;
> +
> + reg = kcalloc(adc->num_sdams, sizeof(u32), GFP_KERNEL);
> + if (!reg)
> + return -ENOMEM;
> +
> + ret = device_property_read_u32_array(dev, "reg", reg, adc->num_sdams);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to read reg property, ret = %d\n", ret);
> +
> + adc->base = devm_kcalloc(dev, adc->num_sdams, sizeof(*adc->base), GFP_KERNEL);
> + if (!adc->base)
> + return -ENOMEM;
> +
> + platform_set_drvdata(pdev, indio_dev);
> + init_completion(&adc->complete);
> + mutex_init(&adc->lock);
> +
> + for (i = 0; i < adc->num_sdams; i++) {
> + adc->base[i].base_addr = reg[i];
> +
> + adc->base[i].irq_name = devm_kasprintf(dev, GFP_KERNEL, "adc-sdam%d", i);
> + if (!adc->base[i].irq_name) {
> + kfree(reg);
> + ret = -ENOMEM;
> + goto err_irq;
> + }
> +
> + ret = platform_get_irq_byname(pdev, adc->base[i].irq_name);
> + if (ret < 0) {
> + kfree(reg);
> + dev_err(dev, "Getting IRQ %d by name failed, ret = %d\n",
> + adc->base[i].irq, ret);
> + goto err_irq;
> + }
> + adc->base[i].irq = ret;
> +
> + ret = request_irq(adc->base[i].irq, adc5_gen3_isr, 0, adc->base[i].irq_name, adc);
> + if (ret < 0) {
> + kfree(reg);
> + dev_err(dev, "Failed to request SDAM%d irq, ret = %d\n", i, ret);
> + goto err_irq;
> + }
> + }
> + kfree(reg);
> +
> + ret = devm_add_action(dev, adc5_gen3_disable, adc);
> + if (ret < 0) {
> + dev_err(dev, "failed to register adc disablement devm action, %d\n", ret);
> + goto err_irq;
> + }
> +
> + ret = adc5_get_fw_data(adc);
> + if (ret < 0) {
> + dev_err(dev, "adc get dt data failed, ret = %d\n", ret);
> + goto err_irq;
> + }
> +
> + ret = adc_tm_register_tzd(adc);
> + if (ret < 0)
> + goto err_irq;
> +
> + if (adc->n_tm_channels)
> + INIT_WORK(&adc->tm_handler_work, tm_handler_work);
> +
> + indio_dev->name = pdev->name;
> + indio_dev->modes = INDIO_DIRECT_MODE;
> + indio_dev->info = &adc5_gen3_info;
> + indio_dev->channels = adc->iio_chans;
> + indio_dev->num_channels = adc->nchannels;
> +
> + ret = devm_iio_device_register(dev, indio_dev);
> + if (!ret)
> + return 0;
> +
> +err_irq:
> + for (i = 0; i < adc->num_sdams; i++)
> + free_irq(adc->base[i].irq, adc);
> +
> + return ret;
> +}
> +
> +static struct platform_driver adc5_gen3_driver = {
> + .driver = {
> + .name = "qcom-spmi-adc5-gen3",
> + .of_match_table = adc5_match_table,
> + },
> + .probe = adc5_gen3_probe,
> +};
> +module_platform_driver(adc5_gen3_driver);
> +
> +MODULE_DESCRIPTION("Qualcomm Technologies Inc. PMIC5 Gen3 ADC driver");
> +MODULE_LICENSE("GPL");
> --
> 2.25.1
>

--
With best wishes
Dmitry

2023-12-31 19:56:05

by kernel test robot

[permalink] [raw]

Subject: Re: [PATCH v3 3/3] iio: adc: Add support for QCOM PMIC5 Gen3 ADC

Hi Jishnu,

kernel test robot noticed the following build warnings:

[auto build test WARNING on next-20231222]
[cannot apply to robh/for-next jic23-iio/togreg rafael-pm/thermal v6.7-rc7 v6.7-rc6 v6.7-rc5 linus/master v6.7-rc7]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url: https://github.com/intel-lab-lkp/linux/commits/Jishnu-Prakash/dt-bindings-iio-adc-Move-QCOM-ADC-bindings-to-iio-adc-folder/20240101-011705
base: next-20231222
patch link: https://lore.kernel.org/r/20231231171237.3322376-4-quic_jprakash%40quicinc.com
patch subject: [PATCH v3 3/3] iio: adc: Add support for QCOM PMIC5 Gen3 ADC
config: m68k-allyesconfig (https://download.01.org/0day-ci/archive/20240101/[email protected]/config)
compiler: m68k-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240101/[email protected]/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/

All warnings (new ones prefixed by >>):

>> drivers/iio/adc/qcom-spmi-adc5-gen3.c:290: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* Worst case delay from PBS in readying handshake bit
drivers/iio/adc/qcom-spmi-adc5-gen3.c:332: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* Worst case delay from PBS for conversion time can be

vim +290 drivers/iio/adc/qcom-spmi-adc5-gen3.c

288
289 /**
> 290 * Worst case delay from PBS in readying handshake bit
291 * can be up to 15ms, when PBS is busy running other
292 * simultaneous transactions, while in the best case, it is
293 * already ready at this point. Assigning polling delay and
294 * retry count accordingly.
295 */
296

--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

2024-01-01 10:37:22

by kernel test robot

[permalink] [raw]

Subject: Re: [PATCH v3 1/3] dt-bindings: iio/adc: Move QCOM ADC bindings to iio/adc folder

Hi Jishnu,

kernel test robot noticed the following build errors:

[auto build test ERROR on next-20231222]
[cannot apply to robh/for-next jic23-iio/togreg rafael-pm/thermal v6.7-rc7 v6.7-rc6 v6.7-rc5 linus/master v6.7-rc8]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url: https://github.com/intel-lab-lkp/linux/commits/Jishnu-Prakash/dt-bindings-iio-adc-Move-QCOM-ADC-bindings-to-iio-adc-folder/20240101-011705
base: next-20231222
patch link: https://lore.kernel.org/r/20231231171237.3322376-2-quic_jprakash%40quicinc.com
patch subject: [PATCH v3 1/3] dt-bindings: iio/adc: Move QCOM ADC bindings to iio/adc folder
config: arm-defconfig (https://download.01.org/0day-ci/archive/20240101/[email protected]/config)
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project.git f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240101/[email protected]/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/

All errors (new ones prefixed by >>):

In file included from arch/arm/boot/dts/qcom/qcom-apq8026-asus-sparrow.dts:9:
>> arch/arm/boot/dts/qcom/pm8226.dtsi:2:10: fatal error: 'dt-bindings/iio/qcom,spmi-vadc.h' file not found
#include <dt-bindings/iio/qcom,spmi-vadc.h>
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1 error generated.
--
In file included from arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts:8:
>> arch/arm/boot/dts/qcom/pm8941.dtsi:2:10: fatal error: 'dt-bindings/iio/qcom,spmi-vadc.h' file not found
#include <dt-bindings/iio/qcom,spmi-vadc.h>
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1 error generated.
--
In file included from arch/arm/boot/dts/qcom/qcom-apq8084-ifc6540.dts:3:
>> arch/arm/boot/dts/qcom/pma8084.dtsi:2:10: fatal error: 'dt-bindings/iio/qcom,spmi-vadc.h' file not found
#include <dt-bindings/iio/qcom,spmi-vadc.h>
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1 error generated.
--
In file included from arch/arm/boot/dts/qcom/qcom-sdx55-mtp.dts:12:
>> arch/arm/boot/dts/qcom/pmx55.dtsi:8:10: fatal error: 'dt-bindings/iio/qcom,spmi-vadc.h' file not found
#include <dt-bindings/iio/qcom,spmi-vadc.h>
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1 error generated.

vim +2 arch/arm/boot/dts/qcom/pm8226.dtsi

bc6ecf993b1023 arch/arm/boot/dts/qcom-pm8226.dtsi Rayyan Ansari 2022-12-23 @2 #include <dt-bindings/iio/qcom,spmi-vadc.h>
79ca56c11e9004 arch/arm/boot/dts/qcom-pm8226.dtsi Rayyan Ansari 2022-12-23 3 #include <dt-bindings/input/linux-event-codes.h>
266a1139ec1762 arch/arm/boot/dts/qcom-pm8226.dtsi Luca Weiss 2021-09-12 4 #include <dt-bindings/interrupt-controller/irq.h>
266a1139ec1762 arch/arm/boot/dts/qcom-pm8226.dtsi Luca Weiss 2021-09-12 5 #include <dt-bindings/spmi/spmi.h>
266a1139ec1762 arch/arm/boot/dts/qcom-pm8226.dtsi Luca Weiss 2021-09-12 6

--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

2024-01-01 17:55:19

[permalink] [raw]

Subject: Re: [PATCH v3 3/3] iio: adc: Add support for QCOM PMIC5 Gen3 ADC

On Sun, 31 Dec 2023 22:42:37 +0530
Jishnu Prakash <[email protected]> wrote:

> The ADC architecture on PMIC5 Gen3 is similar to that on PMIC5 Gen2,
> with all SW communication to ADC going through PMK8550 which
> communicates with other PMICs through PBS.
>
> One major difference is that the register interface used here is that
> of an SDAM (Shared Direct Access Memory) peripheral present on PMK8550.
> There may be more than one SDAM used for ADC5 Gen3 and each has eight
> channels, which may be used for either immediate reads (same functionality
> as previous PMIC5 and PMIC5 Gen2 ADC peripherals) or recurring measurements
> (same as ADC_TM functionality).
>
> In this case, we have VADC and ADC_TM functionality combined into the
> same driver. By convention, we reserve the first channel of the first
> SDAM for all immediate reads and use the remaining channels across all
> SDAMs for ADC_TM monitoring functionality.
>
> Changes since v1:

Move below the --- we don't want this in the eventual git commit as it
is just noise.

> - Removed datashet_name usage and implemented read_label() function
> - In probe, updated channel property in iio_chan_spec from individual
> channel to virtual channel and set indexed property to 1, due to the
> above change.
> - Updated order of checks in ISR
> - Removed the driver remove callback and replaced with callbacks in a
> devm_add_action call in probe.
> - Addressed other comments from reviewers.
>
> Signed-off-by: Jishnu Prakash <[email protected]>
> ---

A few quick comments inline because you already have a request for a substantial
change. Main one is the devm handling tries to do too much with one callback and
I think introduces various bugs as a result. Use the appropriate number of callbacks
so each action has it's own undo registered thus they will happen in the correct order
and no unnecessary ones will occur.

Jonathan

> diff --git a/drivers/iio/adc/qcom-spmi-adc5-gen3.c b/drivers/iio/adc/qcom-spmi-adc5-gen3.c
> new file mode 100644
> index 000000000000..5b5848492245
> --- /dev/null
> +++ b/drivers/iio/adc/qcom-spmi-adc5-gen3.c
> @@ -0,0 +1,1198 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <asm/unaligned.h>

Whilst it isn't alphabetical order, general convention is
to put asm includes in a block after linux ones.

> +#include <linux/bitfield.h>
> +#include <linux/bitops.h>
> +#include <linux/completion.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/iio/iio.h>
> +#include <linux/iio/adc/qcom-vadc-common.h>
> +#include <linux/interrupt.h>
> +#include <linux/kernel.h>
> +#include <linux/log2.h>
> +#include <linux/math64.h>
> +#include <linux/module.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/platform_device.h>
> +#include <linux/property.h>
> +#include <linux/regmap.h>
> +#include <linux/slab.h>
> +#include <linux/thermal.h>
> +
> +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>

> +
> +/**
> + * Worst case delay from PBS for conversion time can be
> + * up to 500ms, when PBS has timed out twice, once for
> + * the initial attempt and once for a retry of the same
> + * transaction.
> + */
> +
> +#define ADC5_GEN3_CONV_TIMEOUT_MS 501
> +
> +static int adc5_gen3_do_conversion(struct adc5_chip *adc,
> + struct adc5_channel_prop *prop,
> + u16 *data_volt)
> +{
> + u8 val, sdam_index = prop->sdam_index;
> + unsigned long rc;
> + int ret;
> +
> + /* Reserve channel 0 of first SDAM for immediate conversions */
> + if (prop->adc_tm)
> + sdam_index = 0;
> +
> + mutex_lock(&adc->lock);
> + ret = adc5_gen3_poll_wait_hs(adc, 0);
> + if (ret)
> + goto unlock;
> +
> + ret = adc5_gen3_configure(adc, prop);
> + if (ret) {
> + dev_err(adc->dev, "ADC configure failed with %d\n", ret);
> + goto unlock;
> + }
> +
> + /* No support for polling mode at present*/
> + rc = wait_for_completion_timeout(&adc->complete,
> + msecs_to_jiffies(ADC5_GEN3_CONV_TIMEOUT_MS));
> + if (!rc) {
> + dev_err(adc->dev, "Reading ADC channel %s timed out\n",
> + prop->label);
> + ret = -ETIMEDOUT;
> + goto unlock;
> + }
> +
> + ret = adc5_gen3_read_voltage_data(adc, data_volt, sdam_index);
> + if (ret)
> + goto unlock;
> +
> + val = BIT(0);
> + ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_EOC_CLR, &val, 1);
> + if (ret)
> + goto unlock;
> +
> + /* To indicate conversion request is only to clear a status */
> + val = 0;
> + ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_PERPH_CH, &val, 1);
> + if (ret)
> + goto unlock;
> +
> + val = ADC5_GEN3_CONV_REQ_REQ;
> + ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_CONV_REQ, &val, 1);
> +
> +unlock:
> + mutex_unlock(&adc->lock);

guard(mutex)(&adc->lock); when you take the lock will simplify this funciton
as you can return directly then.

> +
> + return ret;
> +}

> +static void tm_handler_work(struct work_struct *work)
> +{
> + struct adc5_chip *adc = container_of(work, struct adc5_chip, tm_handler_work);
> + struct adc5_channel_prop *chan_prop;
> + u8 tm_status[2] = {0};
> + u8 buf[16] = {0};
> + u8 val;
> + int ret, i, sdam_index = -1;
> +
> + for (i = 0; i < adc->nchannels; i++) {
> + bool upper_set = false, lower_set = false;
> + int temp, offset;
> + u16 code = 0;
> +
> + chan_prop = &adc->chan_props[i];
> + offset = chan_prop->tm_chan_index;
> +
> + if (!chan_prop->adc_tm)
> + continue;
> +
> + mutex_lock(&adc->lock);
> + if (chan_prop->sdam_index != sdam_index) {

Perhaps factor this block out as indent already high and adding scoped_guard would
make it worse.

> + sdam_index = chan_prop->sdam_index;
> + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_TM_HIGH_STS,
> + tm_status, 2);
> + if (ret) {
> + dev_err(adc->dev, "adc read TM status failed with %d\n", ret);
> + goto out;
> + }
> +
> + ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_TM_HIGH_STS_CLR,
> + tm_status, 2);
> + if (ret) {
> + dev_err(adc->dev, "adc write TM status failed with %d\n", ret);
> + goto out;
> + }
> +
> + /* To indicate conversion request is only to clear a status */
> + val = 0;
> + ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_PERPH_CH, &val, 1);
> + if (ret) {
> + dev_err(adc->dev, "adc write status clear conv_req failed with %d\n",
> + ret);
> + goto out;
> + }
> +
> + val = ADC5_GEN3_CONV_REQ_REQ;
> + ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_CONV_REQ, &val, 1);
> + if (ret) {
> + dev_err(adc->dev, "adc write conv_req failed with %d\n", ret);
> + goto out;
> + }
> +
> + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_CH_DATA0(0), buf,
> + sizeof(buf));
> + if (ret < 0) {
> + dev_err(adc->dev, "adc read data failed with %d\n", ret);
> + goto out;
> + }
> + }
> +
> + if ((tm_status[0] & BIT(offset)) && (chan_prop->high_thr_en))
> + upper_set = true;
> +
> + if ((tm_status[1] & BIT(offset)) && (chan_prop->low_thr_en))
> + lower_set = true;
> +
> + mutex_unlock(&adc->lock);
> +
> + if (!(upper_set || lower_set))
> + continue;
> +
> + code = get_unaligned_le16(&buf[2 * offset]);
> + pr_debug("ADC_TM threshold code:%#x\n", code);
> +
> + ret = qcom_adc5_hw_scale(chan_prop->scale_fn_type,
> + chan_prop->prescale, adc->data, code, &temp);
> + if (ret) {
> + dev_err(adc->dev, "Invalid temperature reading, ret = %d, code=%#x\n",
> + ret, code);
> + continue;
> + }
> +
> + chan_prop->last_temp = temp;
> + chan_prop->last_temp_set = true;
> + thermal_zone_device_update(chan_prop->tzd, THERMAL_TRIP_VIOLATED);
> + }
> +
> + return;
> +
> +out:
> + mutex_unlock(&adc->lock);

Messy to do this. Can you use scoped_guard(mutex, &adc->lock) to handle it more
cleanly?

> +}
> +

> +
> +static int adc5_gen3_read_raw(struct iio_dev *indio_dev,
> + struct iio_chan_spec const *chan, int *val, int *val2,
> + long mask)
> +{
> + struct adc5_chip *adc = iio_priv(indio_dev);
> + struct adc5_channel_prop *prop;
> + u16 adc_code_volt;
> + int ret;
> +
> + prop = &adc->chan_props[chan->address];
> +
> + switch (mask) {
> + case IIO_CHAN_INFO_PROCESSED:
> + ret = adc5_gen3_do_conversion(adc, prop,
> + &adc_code_volt);
> + if (ret)
> + return ret;
> +
> + ret = qcom_adc5_hw_scale(prop->scale_fn_type,
> + prop->prescale, adc->data,
> + adc_code_volt, val);
> + if (ret)
> + return ret;
> +
> + return IIO_VAL_INT;
> + case IIO_CHAN_INFO_RAW:
> + ret = adc5_gen3_do_conversion(adc, prop,
> + &adc_code_volt);
Very short line wrap. Will be under 80 chars without it.
Please check for similar cases.

> + if (ret)
> + return ret;
> + *val = (int)adc_code_volt;
> + return IIO_VAL_INT;
> + default:
> + return -EINVAL;
> + }
> +}

> +
> +static void adc5_gen3_disable(void *data)
> +{
> + struct adc5_chip *adc = data;
> + int i;
> +
> + if (adc->n_tm_channels)
> + cancel_work_sync(&adc->tm_handler_work);
If this is required before the place where a simple
devm_request_irq() will result in the irqs being cleaned up
them register this callback earlier to avoid problems there.

> +
> + for (i = 0; i < adc->num_sdams; i++)
> + free_irq(adc->base[i].irq, adc);
> +
> + mutex_lock(&adc->lock);
> + /* Disable all available TM channels */
> + for (i = 0; i < adc->nchannels; i++) {
> + if (!adc->chan_props[i].adc_tm)
> + continue;
> + adc5_gen3_poll_wait_hs(adc, adc->chan_props[i].sdam_index);
> + _adc_tm5_gen3_disable_channel(&adc->chan_props[i]);
> + }
> +
> + mutex_unlock(&adc->lock);
> +}

> +static int adc5_gen3_get_fw_channel_data(struct adc5_chip *adc,
> + struct adc5_channel_prop *prop,
> + struct fwnode_handle *fwnode,
> + const struct adc5_data *data)
> +{
> + const char *name = fwnode_get_name(fwnode);
> + const char *channel_name;
> + struct device *dev = adc->dev;
> + u32 chan, value, varr[2], sid = 0;
> + int ret, val;
> +
> + ret = fwnode_property_read_u32(fwnode, "reg", &chan);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "invalid channel number %s\n", name);
> +
> + /*
> + * Value read from "reg" is virtual channel number
> + * virtual channel number = sid << 8 | channel number
> + */
> +
> + sid = FIELD_GET(ADC5_GEN3_VIRTUAL_SID_MASK, chan);
> + chan = FIELD_GET(ADC5_GEN3_CHANNEL_MASK, chan);
> +
> + if (chan > ADC5_GEN3_OFFSET_EXT2)
> + return dev_err_probe(dev, -EINVAL, "%s invalid channel number %d\n", name, chan);
> +
> + prop->channel = chan;
> + prop->sid = sid;
> +
> + ret = fwnode_property_read_string(fwnode, "label", &channel_name);
> + if (ret)
> + channel_name = name;
Set this first then don't check ret

channel_name = name;
fwnode_property_read_string()

do similar for any other cases with a default.

> + prop->label = channel_name;
> +
> + prop->decimation = ADC5_DECIMATION_DEFAULT;
> + ret = fwnode_property_read_u32(fwnode, "qcom,decimation", &value);
> + if (!ret) {
> + ret = qcom_adc5_decimation_from_dt(value, data->decimation);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "%#x invalid decimation %d\n",
> + chan, value);
> + prop->decimation = ret;
> + }
> +
> + prop->prescale = adc->data->adc_chans[prop->channel].prescale_index;
> + ret = fwnode_property_read_u32_array(fwnode, "qcom,pre-scaling", varr, 2);
> + if (!ret) {
> + ret = qcom_adc5_prescaling_from_dt(varr[0], varr[1]);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "%#x invalid pre-scaling <%d %d>\n",
> + chan, varr[0], varr[1]);
> + prop->prescale = ret;
> + }
> +
> + prop->hw_settle_time = VADC_DEF_HW_SETTLE_TIME;

I'd prefer to see you has through the value that maps to this after qcom_adc5_hw_settle_time_from_dt
so then you can just set a default in value and call the rest of the code unconditionally.
Same for the cases that follow.

> + ret = fwnode_property_read_u32(fwnode, "qcom,hw-settle-time", &value);
> + if (!ret) {
> + ret = qcom_adc5_hw_settle_time_from_dt(value,
> + data->hw_settle_1);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "%#x invalid hw-settle-time %d us\n",
> + chan, value);
> + prop->hw_settle_time = ret;
> + }
> +
> + prop->avg_samples = VADC_DEF_AVG_SAMPLES;
> + ret = fwnode_property_read_u32(fwnode, "qcom,avg-samples", &value);
> + if (!ret) {
> + ret = qcom_adc5_avg_samples_from_dt(value);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "%#x invalid avg-samples %d\n",
> + chan, value);
> + prop->avg_samples = ret;
> + }
> +
> + if (fwnode_property_read_bool(fwnode, "qcom,ratiometric"))
> + prop->cal_method = ADC5_RATIOMETRIC_CAL;
> + else
> + prop->cal_method = ADC5_ABSOLUTE_CAL;
> +
> + prop->timer = MEAS_INT_IMMEDIATE;
> +
> + prop->adc_tm = fwnode_property_read_bool(fwnode, "qcom,adc-tm");
> +
> + if (prop->adc_tm) {
> + adc->n_tm_channels++;
> + if (adc->n_tm_channels > ((adc->num_sdams * 8) - 1))
> + return dev_err_probe(adc->dev, -EINVAL,
> + "Number of TM nodes %u greater than channels supported:%u\n",
> + adc->n_tm_channels, (adc->num_sdams * 8) - 1);
> +
> + val = adc->n_tm_channels / 8;
> + prop->sdam_index = val;
> + prop->tm_chan_index = adc->n_tm_channels - (8*val);
> +
> + prop->timer = MEAS_INT_1S;
> + }
> +
> + return 0;
> +}
>
> +static const struct of_device_id adc5_match_table[] = {
> + {
> + .compatible = "qcom,spmi-adc5-gen3",
> + .data = &adc5_gen3_data_pmic,
> + },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, adc5_match_table);
> +
> +static int adc5_get_fw_data(struct adc5_chip *adc)
> +{
> + const struct adc5_channels *adc_chan;
> + struct iio_chan_spec *iio_chan;
> + struct adc5_channel_prop *chan_props;
> + struct fwnode_handle *child;
> + unsigned int index = 0;
> + int ret;
> +
> + adc->nchannels = device_get_child_node_count(adc->dev);
> + if (!adc->nchannels)
> + return -EINVAL;
> +
> + adc->iio_chans = devm_kcalloc(adc->dev, adc->nchannels,
> + sizeof(*adc->iio_chans), GFP_KERNEL);
> + if (!adc->iio_chans)
> + return -ENOMEM;
> +
> + adc->chan_props = devm_kcalloc(adc->dev, adc->nchannels,
> + sizeof(*adc->chan_props), GFP_KERNEL);
> + if (!adc->chan_props)
> + return -ENOMEM;
> +
> + chan_props = adc->chan_props;
> + adc->n_tm_channels = 0;
> + iio_chan = adc->iio_chans;
> + adc->data = device_get_match_data(adc->dev);
> + if (!adc->data)
> + adc->data = &adc5_gen3_data_pmic;

Why do you need a default? Add a comment so we remember the reasoning.

> +
> + device_for_each_child_node(adc->dev, child) {
> + ret = adc5_gen3_get_fw_channel_data(adc, chan_props, child, adc->data);
> + if (ret < 0) {
> + fwnode_handle_put(child);
I've just sent out automated cleanup handling for this. Not a huge
saving here, but if you want to:
https://lore.kernel.org/linux-iio/[email protected]/T/#t

> + return ret;
> + }
> +
> + chan_props->chip = adc;
> + chan_props->scale_fn_type =
> + adc->data->adc_chans[chan_props->channel].scale_fn_type;
> + adc_chan = &adc->data->adc_chans[chan_props->channel];
> + iio_chan->channel = V_CHAN(*chan_props);
> + iio_chan->info_mask_separate = adc_chan->info_mask;
> + iio_chan->type = adc_chan->type;
> + iio_chan->address = index;
> + iio_chan->indexed = 1;
> + iio_chan++;
> + chan_props++;
> + index++;
> + }
> +
> + return 0;
> +}
> +
> +static int adc5_gen3_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct iio_dev *indio_dev;
> + struct adc5_chip *adc;
> + struct regmap *regmap;
> + int ret, i;
> + u32 *reg;
> +
> + regmap = dev_get_regmap(dev->parent, NULL);
> + if (!regmap)
> + return -ENODEV;
> +
> + indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
> + if (!indio_dev)
> + return -ENOMEM;
> +
> + adc = iio_priv(indio_dev);
> + adc->regmap = regmap;
> + adc->dev = dev;
> +
> + ret = device_property_count_u32(dev, "reg");
> + if (ret < 0)
> + return ret;
> +
> + adc->num_sdams = ret;
> +
> + reg = kcalloc(adc->num_sdams, sizeof(u32), GFP_KERNEL);

> + if (!reg)
> + return -ENOMEM;
> +
> + ret = device_property_read_u32_array(dev, "reg", reg, adc->num_sdams);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to read reg property, ret = %d\n", ret);
> +
> + adc->base = devm_kcalloc(dev, adc->num_sdams, sizeof(*adc->base), GFP_KERNEL);
> + if (!adc->base)
> + return -ENOMEM;
> +
> + platform_set_drvdata(pdev, indio_dev);
> + init_completion(&adc->complete);
> + mutex_init(&adc->lock);
> +
> + for (i = 0; i < adc->num_sdams; i++) {
> + adc->base[i].base_addr = reg[i];
> +
> + adc->base[i].irq_name = devm_kasprintf(dev, GFP_KERNEL, "adc-sdam%d", i);
> + if (!adc->base[i].irq_name) {
> + kfree(reg);
> + ret = -ENOMEM;
> + goto err_irq;
> + }
> +
> + ret = platform_get_irq_byname(pdev, adc->base[i].irq_name);
> + if (ret < 0) {
> + kfree(reg);
> + dev_err(dev, "Getting IRQ %d by name failed, ret = %d\n",
> + adc->base[i].irq, ret);
> + goto err_irq;
> + }
> + adc->base[i].irq = ret;
> +
> + ret = request_irq(adc->base[i].irq, adc5_gen3_isr, 0, adc->base[i].irq_name, adc);

Don't mix devm and non dev calls. And don't group up multiple things in one devm callback
as it almost always leads to bugs where for example only some irqs are allocated.

> + if (ret < 0) {
> + kfree(reg);
> + dev_err(dev, "Failed to request SDAM%d irq, ret = %d\n", i, ret);
> + goto err_irq;
> + }
> + }
> + kfree(reg);

I would factor out this code and allocation of reg so you can easily use scope
based cleanup (see linux/cleanup.h) to avoid the kfree(reg) entries that
make for awkward code flow.

> +
> + ret = devm_add_action(dev, adc5_gen3_disable, adc);
As above, this action does multiple things. Also use devm_add_action_or_reset() to cleanup
if the devm registration fails without needing to do it manually.

> + if (ret < 0) {
> + dev_err(dev, "failed to register adc disablement devm action, %d\n", ret);
> + goto err_irq;
> + }
> +
> + ret = adc5_get_fw_data(adc);
> + if (ret < 0) {
> + dev_err(dev, "adc get dt data failed, ret = %d\n", ret);
> + goto err_irq;

Fairly sure this results in a double free of the irqs.
Use devm_request_irq() in the first place and let the normal handling clean them
up both in the error path and in the remove path.

> + }
> +
> + ret = adc_tm_register_tzd(adc);
> + if (ret < 0)
> + goto err_irq;
> +
> + if (adc->n_tm_channels)
> + INIT_WORK(&adc->tm_handler_work, tm_handler_work);

Until this init work seems unlikely you should be calling the cancel
work in gen3_disable()

> +
> + indio_dev->name = pdev->name;
> + indio_dev->modes = INDIO_DIRECT_MODE;
> + indio_dev->info = &adc5_gen3_info;
> + indio_dev->channels = adc->iio_chans;
> + indio_dev->num_channels = adc->nchannels;
> +
> + ret = devm_iio_device_register(dev, indio_dev);
> + if (!ret)
> + return 0;
Please keep error conditions as the out of line path.

if (ret)
goto err_irq;

return 0;

> +
> +err_irq:
> + for (i = 0; i < adc->num_sdams; i++)
> + free_irq(adc->base[i].irq, adc);

Already freed by a devm cleanup handler.

> +
> + return ret;
> +}

2024-01-01 18:02:36

[permalink] [raw]

Subject: Re: [PATCH v3 2/3] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC

On Sun, 31 Dec 2023 22:42:36 +0530
Jishnu Prakash <[email protected]> wrote:

> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the
> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs.
>
> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs
> going through PBS(Programmable Boot Sequence) firmware through a single
> register interface. This interface is implemented on an SDAM (Shared
> Direct Access Memory) peripheral on the master PMIC PMK8550 rather
> than a dedicated ADC peripheral.
>
> Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC
> channels and virtual channels (combination of ADC channel number and
> PMIC SID number) per PMIC, to be used by clients of this device.
>
> Changes since v2:
> - Moved ADC5 Gen3 documentation into a separate new file.
>
> Changes since v1:
> - Updated properties separately for all compatibles to clarify usage
> of new properties and updates in usage of old properties for ADC5 Gen3.
> - Avoided updating 'adc7' name to 'adc5 gen2' and just left a comment
> mentioning this convention.
> - Used predefined channel IDs in individual PMIC channel definitions
> instead of numeric IDs.
> - Addressed other comments from reviewers.
change log below the ---

Comments inline.

Jonathan

>
> Co-developed-by: Anjelique Melendez <[email protected]>
> Signed-off-by: Anjelique Melendez <[email protected]>
> Signed-off-by: Jishnu Prakash <[email protected]>
> ---
> .../bindings/iio/adc/qcom,spmi-adc5-gen3.yaml | 212 ++++++++++++++++++
> .../iio/adc/qcom,spmi-adc5-gen3-pm8550.h | 50 +++++
> .../iio/adc/qcom,spmi-adc5-gen3-pm8550b.h | 89 ++++++++
> .../iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h | 22 ++
> .../iio/adc/qcom,spmi-adc5-gen3-pmk8550.h | 56 +++++
> .../iio/adc/qcom,spmi-adc7-pmr735b.h | 2 +-
> .../iio/adc/qcom,spmi-adc7-smb139x.h | 2 +-
> include/dt-bindings/iio/adc/qcom,spmi-vadc.h | 81 +++++++
> 8 files changed, 512 insertions(+), 2 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml
> create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h
> create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h
> create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h
> create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml
> new file mode 100644
> index 000000000000..ed5bb53e7628
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml
> @@ -0,0 +1,212 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-adc5-gen3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm's SPMI PMIC ADC5 Gen3
> +
> +maintainers:
> + - Jishnu Prakash <[email protected]>
> +
> +description: |
> + SPMI PMIC5 Gen3 voltage ADC (ADC) provides interface to
> + clients to read voltage. It is a 16-bit sigma-delta ADC.
> + It also performs the same thermal monitoring function as

Line wrap is too short.

> + the existing ADC_TM devices.
> +
> +properties:
> + compatible:
> + const: qcom,spmi-adc5-gen3
> +
> + reg:
> + description: |
> + - Each reg corresponds to an SDAM peripheral base address that is being used for ADC.
Formatted text / bullet point seems unnecessary as only one entyr.
description:
Each reg corresponds to an ...

> +
> + '#address-cells':
> + const: 1
> +
> + '#size-cells':
> + const: 0
> +
> + "#thermal-sensor-cells":
> + const: 1
> + description:
> + Number of cells required to uniquely identify the thermal sensors. Since
> + we have multiple sensors this is set to 1. This property is required for
> + ADC devices with channels used for TM (thermal monitoring) functionality.
> +
> + '#io-channel-cells':
> + const: 1
> +
> + interrupts:
> + description: |
> + End of conversion interrupt. Interrupts are defined for each SDAM being used.

As before - no need to preserve formatting for a simple one line statement.

> +
> + interrupt-names:
> + minItems: 1
> + maxItems: 10
> + items:
> + pattern: "^adc-sdam[0-9]+$"
> + description: |
> + Names should be defined as "adc-sdam<N>" where <N> represents the SDAM index.
> +
> +required:
> + - compatible
> + - reg
> + - '#address-cells'
> + - '#size-cells'
> + - '#io-channel-cells'
> + - interrupts
> + - interrupt-names
> +
> +patternProperties:
> + "^channel@[0-9a-f]+$":
> + type: object
> + additionalProperties: false
> + description: |
> + Represents the external channels which are connected to the ADC.
> +
> + properties:
> + reg:
> + maxItems: 1
> + description: |
> + ADC channel number.
> + See include/dt-bindings/iio/adc/qcom,spmi-vadc.h
> + For PMIC5 Gen3 ADC, the channel numbers are specified separately
> + per PMIC in the PMIC-specific files in include/dt-bindings/iio/adc.
> +
> + label:
> + $ref: /schemas/types.yaml#/definitions/string
> + description: |
> + ADC input of the platform as seen in the schematics.
> + For thermistor inputs connected to generic AMUX or GPIO inputs
> + these can vary across platform for the same pins. Hence select
> + the platform schematics name for this channel.

defined in adc.yaml, so should just have a reference to that here.

> +
> + qcom,decimation:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + This parameter is used to decrease ADC sampling rate.
> + Quicker measurements can be made by reducing decimation ratio.

Why is this in DT rather than as a userspace control?

> + enum: [ 85, 340, 1360 ]
> + default: 1360
> +
> + qcom,pre-scaling:
> + description: |
> + Used for scaling the channel input signal before the signal is
> + fed to VADC. The configuration for this node is to know the
> + pre-determined ratio and use it for post scaling. It is a pair of
> + integers, denoting the numerator and denominator of the fraction by which
> + input signal is multiplied. For example, <1 3> indicates the signal is scaled
> + down to 1/3 of its value before ADC measurement.
> + If property is not found default value depending on chip will be used.
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + items:
> + - const: 1
> + - enum: [ 1, 3, 6, 16 ]
> +
> + qcom,ratiometric:
> + description: |
> + Channel calibration type.
> + - If this property is specified VADC will use the VDD reference (1.875V)
> + and GND for channel calibration. If property is not found, channel will be
> + calibrated with 0V and 1.25V reference channels, also known as
> + absolute calibration.
> + type: boolean
> +
> + qcom,hw-settle-time:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + Time between AMUX getting configured and the ADC starting
> + conversion. The 'hw_settle_time' is an index used from valid values
> + and programmed in hardware to achieve the hardware settling delay.
> + enum: [ 15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000,
> + 8000, 16000, 32000, 64000, 128000 ]
> + default: 15

only currently defined for muxes but we have settle-time-us which has benefit of
providing the units (which are missing here from the description as well)

> +
> + qcom,avg-samples:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + Number of samples to be used for measurement.
> + Averaging provides the option to obtain a single measurement
> + from the ADC that is an average of multiple samples. The value
> + selected is 2^(value).
Why is this in dt? Why not just userspace control (in_voltageX_oversampling_ratio

If it needs to be, we do have standard DT bindings for it in adc.yaml

> + enum: [ 1, 2, 4, 8, 16 ]
> + default: 1
> +
> + qcom,adc-tm:
> + description: |
> + Indicates if ADC_TM monitoring is done on this channel.
> + Defined for compatible property "qcom,spmi-adc5-gen3".
> + This is the same functionality as in the existing QCOM ADC_TM
> + device, documented at devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml.
> + type: boolean
> +
> + required:
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h>
> + #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h>
> + #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h>
> + #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + pmic {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* VADC node */
> + pmk8550_vadc: vadc@9000 {
> + compatible = "qcom,spmi-adc5-gen3";
> + reg = <0x9000>, <0x9100>;
> + interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>,
> + <0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "adc-sdam0", "adc-sdam1";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #io-channel-cells = <1>;
> + #thermal-sensor-cells = <1>;
> +
> + /* PMK8550 Channel nodes */
> + channel@3 {
> + reg = <PMK8550_ADC5_GEN3_DIE_TEMP>;
> + label = "pmk8550_die_temp";
> + qcom,pre-scaling = <1 1>;
> + };
> +
> + channel@44 {
> + reg = <PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU>;
> + label = "pmk8550_xo_therm";
> + qcom,pre-scaling = <1 1>;
> + qcom,ratiometric;
> + qcom,hw-settle-time = <200>;
> + qcom,adc-tm;
> + };
> +
> + /* PM8550 Channel nodes */
> + channel@103 {
> + reg = <PM8550_ADC5_GEN3_DIE_TEMP>;
> + label = "pm8550_die_temp";
> + qcom,pre-scaling = <1 1>;
> + };
> +
> + /* PM8550B Channel nodes */
> + channel@78f {
> + reg = <PM8550B_ADC5_GEN3_VBAT_SNS_QBG>;
> + label = "pm8550b_vbat_sns_qbg";
> + qcom,pre-scaling = <1 3>;
> + };
> +
> + /* PM8550VS_C Channel nodes */
> + channel@203 {
> + reg = <PM8550VS_ADC5_GEN3_DIE_TEMP(2)>;
> + label = "pm8550vs_c_die_temp";
> + qcom,pre-scaling = <1 1>;
> + };
> + };
> + };
> diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h
> new file mode 100644
> index 000000000000..0f25ef87ed5c
> --- /dev/null
> +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h
> @@ -0,0 +1,50 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H
> +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H
> +
> +#ifndef PM8550_SID
> +#define PM8550_SID 1
> +#endif
> +
> +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
> +
> +/* ADC channels for PM8550_ADC for PMIC5 Gen3 */
> +#define PM8550_ADC5_GEN3_REF_GND (PM8550_SID << 8 | ADC5_GEN3_REF_GND)
> +#define PM8550_ADC5_GEN3_1P25VREF (PM8550_SID << 8 | ADC5_GEN3_1P25VREF)
> +#define PM8550_ADC5_GEN3_VREF_VADC (PM8550_SID << 8 | ADC5_GEN3_VREF_VADC)
> +#define PM8550_ADC5_GEN3_DIE_TEMP (PM8550_SID << 8 | ADC5_GEN3_DIE_TEMP)
> +
> +#define PM8550_ADC5_GEN3_AMUX_THM1 (PM8550_SID << 8 | ADC5_GEN3_AMUX1_THM)
> +#define PM8550_ADC5_GEN3_AMUX_THM2 (PM8550_SID << 8 | ADC5_GEN3_AMUX2_THM)
> +#define PM8550_ADC5_GEN3_AMUX_THM3 (PM8550_SID << 8 | ADC5_GEN3_AMUX3_THM)
> +#define PM8550_ADC5_GEN3_AMUX_THM4 (PM8550_SID << 8 | ADC5_GEN3_AMUX4_THM)
> +#define PM8550_ADC5_GEN3_AMUX_THM5 (PM8550_SID << 8 | ADC5_GEN3_AMUX5_THM)
> +#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2 (PM8550_SID << 8 | ADC5_GEN3_AMUX6_THM)
> +#define PM8550_ADC5_GEN3_AMUX1_GPIO3 (PM8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO)
> +#define PM8550_ADC5_GEN3_AMUX2_GPIO4 (PM8550_SID << 8 | ADC5_GEN3_AMUX2_GPIO)
> +#define PM8550_ADC5_GEN3_AMUX3_GPIO7 (PM8550_SID << 8 | ADC5_GEN3_AMUX3_GPIO)
> +#define PM8550_ADC5_GEN3_AMUX4_GPIO12 (PM8550_SID << 8 | ADC5_GEN3_AMUX4_GPIO)
> +
> +/* 100k pull-up */
> +#define PM8550_ADC5_GEN3_AMUX_THM1_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX1_THM_100K_PU)
> +#define PM8550_ADC5_GEN3_AMUX_THM2_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX2_THM_100K_PU)
> +#define PM8550_ADC5_GEN3_AMUX_THM3_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX3_THM_100K_PU)
> +#define PM8550_ADC5_GEN3_AMUX_THM4_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX4_THM_100K_PU)
> +#define PM8550_ADC5_GEN3_AMUX_THM5_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX5_THM_100K_PU)
> +#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX6_THM_100K_PU)
> +#define PM8550_ADC5_GEN3_AMUX1_GPIO3_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO_100K_PU)
> +#define PM8550_ADC5_GEN3_AMUX2_GPIO4_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX2_GPIO_100K_PU)
> +#define PM8550_ADC5_GEN3_AMUX3_GPIO7_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX3_GPIO_100K_PU)
> +#define PM8550_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX4_GPIO_100K_PU)
> +
> +/* 1/3 Divider */
> +#define PM8550_ADC5_GEN3_AMUX3_GPIO7_DIV3 (PM8550_SID << 8 | ADC5_GEN3_AMUX3_GPIO_DIV3)
> +#define PM8550_ADC5_GEN3_AMUX4_GPIO12_DIV3 (PM8550_SID << 8 | ADC5_GEN3_AMUX4_GPIO_DIV3)
> +
> +#define PM8550_ADC5_GEN3_VPH_PWR (PM8550_SID << 8 | ADC5_GEN3_VPH_PWR)
> +
> +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H */
> diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h
> new file mode 100644
> index 000000000000..47116bbe45de
> --- /dev/null
> +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h
> @@ -0,0 +1,89 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H
> +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H
> +
> +#ifndef PM8550B_SID
> +#define PM8550B_SID 7
> +#endif
> +
> +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
> +
> +/* ADC channels for PM8550B_ADC for PMIC5 Gen3 */
> +#define PM8550B_ADC5_GEN3_REF_GND (PM8550B_SID << 8 | ADC5_GEN3_REF_GND)
> +#define PM8550B_ADC5_GEN3_1P25VREF (PM8550B_SID << 8 | ADC5_GEN3_1P25VREF)
> +#define PM8550B_ADC5_GEN3_VREF_VADC (PM8550B_SID << 8 | ADC5_GEN3_VREF_VADC)
> +#define PM8550B_ADC5_GEN3_DIE_TEMP (PM8550B_SID << 8 | ADC5_GEN3_DIE_TEMP)
> +
> +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_THM)
> +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_THM)
> +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_THM)
> +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_THM)
> +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION (PM8550B_SID << 8 | ADC5_GEN3_AMUX5_THM)
> +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10 (PM8550B_SID << 8 | ADC5_GEN3_AMUX6_THM)
> +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1 (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_GPIO)
> +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5 (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_GPIO)
> +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6 (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_GPIO)
> +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12 (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_GPIO)
> +
> +#define PM8550B_ADC5_GEN3_CHG_TEMP (PM8550B_SID << 8 | ADC5_GEN3_CHG_TEMP)
> +#define PM8550B_ADC5_GEN3_USB_SNS_V_16 (PM8550B_SID << 8 | ADC5_GEN3_USB_SNS_V_16)
> +#define PM8550B_ADC5_GEN3_VIN_DIV16_MUX (PM8550B_SID << 8 | ADC5_GEN3_VIN_DIV16_MUX)
> +#define PM8550B_ADC5_GEN3_VREF_BAT_THERM (PM8550B_SID << 8 | ADC5_GEN3_VREF_BAT_THERM)
> +#define PM8550B_ADC5_GEN3_IIN_FB (PM8550B_SID << 8 | ADC5_GEN3_IIN_FB)
> +#define PM8550B_ADC5_GEN3_TEMP_ALARM_LITE (PM8550B_SID << 8 | ADC5_GEN3_TEMP_ALARM_LITE)
> +#define PM8550B_ADC5_GEN3_SMB_IIN (PM8550B_SID << 8 | ADC5_GEN3_IIN_SMB)
> +#define PM8550B_ADC5_GEN3_SMB_ICHG (PM8550B_SID << 8 | ADC5_GEN3_ICHG_SMB)
> +#define PM8550B_ADC5_GEN3_ICHG_FB (PM8550B_SID << 8 | ADC5_GEN3_ICHG_FB)
> +
> +/* 30k pull-up */
> +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_THM_30K_PU)
> +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_THM_30K_PU)
> +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_THM_30K_PU)
> +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_THM_30K_PU)
> +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX5_THM_30K_PU)
> +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX6_THM_30K_PU)
> +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_GPIO_30K_PU)
> +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_GPIO_30K_PU)
> +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_GPIO_30K_PU)
> +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_30K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_GPIO_30K_PU)
> +
> +/* 100k pull-up */
> +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_THM_100K_PU)
> +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_THM_100K_PU)
> +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_THM_100K_PU)
> +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_THM_100K_PU)
> +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX5_THM_100K_PU)
> +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX6_THM_100K_PU)
> +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_GPIO_100K_PU)
> +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_GPIO_100K_PU)
> +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_GPIO_100K_PU)
> +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_GPIO_100K_PU)
> +
> +/* 400k pull-up */
> +#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_THM_400K_PU)
> +#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_THM_400K_PU)
> +#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_THM_400K_PU)
> +#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_THM_400K_PU)
> +#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX5_THM_400K_PU)
> +#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX6_THM_400K_PU)
> +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_GPIO_400K_PU)
> +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_GPIO_400K_PU)
> +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_GPIO_400K_PU)
> +#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_400K_PU (PM8550B_SID << 8 | ADC5_GEN3_AMUX4_GPIO_400K_PU)
> +
> +/* 1/3 Divider */
> +#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_DIV3 (PM8550B_SID << 8 | ADC5_GEN3_AMUX1_GPIO_DIV3)
> +#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_DIV3 (PM8550B_SID << 8 | ADC5_GEN3_AMUX2_GPIO_DIV3)
> +#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_DIV3 (PM8550B_SID << 8 | ADC5_GEN3_AMUX3_GPIO_DIV3)
> +
> +#define PM8550B_ADC5_GEN3_VPH_PWR (PM8550B_SID << 8 | ADC5_GEN3_VPH_PWR)
> +#define PM8550B_ADC5_GEN3_VBAT_SNS_QBG (PM8550B_SID << 8 | ADC5_GEN3_VBAT_SNS_QBG)
> +#define PM8550B_ADC5_GEN3_VBAT_SNS_CHGR (PM8550B_SID << 8 | ADC5_GEN3_VBAT_SNS_CHGR)
> +#define PM8550B_ADC5_GEN3_VBAT_2S_MID_QBG (PM8550B_SID << 8 | ADC5_GEN3_VBAT_2S_MID_QBG)
> +#define PM8550B_ADC5_GEN3_VBAT_2S_MID_CHGR (PM8550B_SID << 8 | ADC5_GEN3_VBAT_2S_MID_CHGR)
> +
> +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H */
> diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h
> new file mode 100644
> index 000000000000..360f2245d582
> --- /dev/null
> +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h
> @@ -0,0 +1,22 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H
> +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H
> +
> +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
> +
> +/* ADC channels for PM8550VX_ADC for PMIC5 Gen3 */
> +#define PM8550VS_ADC5_GEN3_REF_GND(sid) ((sid) << 8 | ADC5_GEN3_REF_GND)
> +#define PM8550VS_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | ADC5_GEN3_1P25VREF)
> +#define PM8550VS_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | ADC5_GEN3_VREF_VADC)
> +#define PM8550VS_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | ADC5_GEN3_DIE_TEMP)
> +
> +#define PM8550VE_ADC5_GEN3_OFFSET_REF(sid) ((sid) << 8 | ADC5_GEN3_REF_GND)
> +#define PM8550VE_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | ADC5_GEN3_1P25VREF)
> +#define PM8550VE_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | ADC5_GEN3_VREF_VADC)
> +#define PM8550VE_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | ADC5_GEN3_DIE_TEMP)
> +
> +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H */
> diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h
> new file mode 100644
> index 000000000000..3fc829ebdf6d
> --- /dev/null
> +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h
> @@ -0,0 +1,56 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H
> +#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H
> +
> +#ifndef PMK8550_SID
> +#define PMK8550_SID 0
> +#endif
> +
> +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
> +
> +/* ADC channels for PMK8550_ADC for PMIC5 Gen3 */
> +#define PMK8550_ADC5_GEN3_REF_GND (PMK8550_SID << 8 | ADC5_GEN3_REF_GND)
> +#define PMK8550_ADC5_GEN3_1P25VREF (PMK8550_SID << 8 | ADC5_GEN3_1P25VREF)
> +#define PMK8550_ADC5_GEN3_VREF_VADC (PMK8550_SID << 8 | ADC5_GEN3_VREF_VADC)
> +#define PMK8550_ADC5_GEN3_DIE_TEMP (PMK8550_SID << 8 | ADC5_GEN3_DIE_TEMP)
> +
> +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_THM)
> +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1 (PMK8550_SID << 8 | ADC5_GEN3_AMUX2_THM)
> +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2 (PMK8550_SID << 8 | ADC5_GEN3_AMUX3_THM)
> +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3 (PMK8550_SID << 8 | ADC5_GEN3_AMUX4_THM)
> +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4 (PMK8550_SID << 8 | ADC5_GEN3_AMUX5_THM)
> +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5 (PMK8550_SID << 8 | ADC5_GEN3_AMUX6_THM)
> +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6 (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO)
> +
> +/* 30k pull-up */
> +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_THM_30K_PU)
> +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX2_THM_30K_PU)
> +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX3_THM_30K_PU)
> +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX4_THM_30K_PU)
> +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX5_THM_30K_PU)
> +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX6_THM_30K_PU)
> +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_30K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO_30K_PU)
> +
> +/* 100k pull-up */
> +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_THM_100K_PU)
> +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX2_THM_100K_PU)
> +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX3_THM_100K_PU)
> +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX4_THM_100K_PU)
> +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX5_THM_100K_PU)
> +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX6_THM_100K_PU)
> +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_100K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO_100K_PU)
> +
> +/* 400k pull-up */
> +#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_THM_400K_PU)
> +#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX2_THM_400K_PU)
> +#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX3_THM_400K_PU)
> +#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX4_THM_400K_PU)
> +#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX5_THM_400K_PU)
> +#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX6_THM_400K_PU)
> +#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_400K_PU (PMK8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO_400K_PU)
> +
> +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H */
> diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735b.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735b.h
> index fdb8dd9ae541..812f33872e5e 100644
> --- a/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735b.h
> +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735b.h
> @@ -10,7 +10,7 @@
> #define PMR735B_SID 5
> #endif
>
> -#include <dt-bindings/iio/qcom,spmi-vadc.h>
> +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
>
> /* ADC channels for PMR735B_ADC for PMIC7 */
> #define PMR735B_ADC7_REF_GND (PMR735B_SID << 8 | ADC7_REF_GND)
> diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h
> index c0680d1285cf..750a526af2c1 100644
> --- a/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h
> +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h
> @@ -6,7 +6,7 @@
> #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_SMB139X_H
> #define _DT_BINDINGS_QCOM_SPMI_VADC_SMB139X_H
>
> -#include <dt-bindings/iio/qcom,spmi-vadc.h>
> +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
>
> #define SMB139x_1_ADC7_SMB_TEMP (SMB139x_1_SID << 8 | ADC7_SMB_TEMP)
> #define SMB139x_1_ADC7_ICHG_SMB (SMB139x_1_SID << 8 | ADC7_ICHG_SMB)
> diff --git a/include/dt-bindings/iio/adc/qcom,spmi-vadc.h b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h
> index ef07ecd4d585..cfe653d945a4 100644
> --- a/include/dt-bindings/iio/adc/qcom,spmi-vadc.h
> +++ b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h
> @@ -1,6 +1,8 @@
> /* SPDX-License-Identifier: GPL-2.0 */
> /*
> * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved.
> + *
> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
> */
>
> #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H
> @@ -300,4 +302,83 @@
> #define ADC7_SBUx 0x94
> #define ADC7_VBAT_2S_MID 0x96
>
> +/* ADC channels for PMIC5 Gen3 */
> +
> +#define ADC5_GEN3_REF_GND 0x00
> +#define ADC5_GEN3_1P25VREF 0x01
> +#define ADC5_GEN3_VREF_VADC 0x02
> +#define ADC5_GEN3_DIE_TEMP 0x03
> +
> +#define ADC5_GEN3_AMUX1_THM 0x04
> +#define ADC5_GEN3_AMUX2_THM 0x05
> +#define ADC5_GEN3_AMUX3_THM 0x06
> +#define ADC5_GEN3_AMUX4_THM 0x07
> +#define ADC5_GEN3_AMUX5_THM 0x08
> +#define ADC5_GEN3_AMUX6_THM 0x09
> +#define ADC5_GEN3_AMUX1_GPIO 0x0a
> +#define ADC5_GEN3_AMUX2_GPIO 0x0b
> +#define ADC5_GEN3_AMUX3_GPIO 0x0c
> +#define ADC5_GEN3_AMUX4_GPIO 0x0d
> +
> +#define ADC5_GEN3_CHG_TEMP 0x10
> +#define ADC5_GEN3_USB_SNS_V_16 0x11
> +#define ADC5_GEN3_VIN_DIV16_MUX 0x12
> +#define ADC5_GEN3_VREF_BAT_THERM 0x15
> +#define ADC5_GEN3_IIN_FB 0x17
> +#define ADC5_GEN3_TEMP_ALARM_LITE 0x18
> +#define ADC5_GEN3_IIN_SMB 0x19
> +#define ADC5_GEN3_ICHG_SMB 0x1b
> +#define ADC5_GEN3_ICHG_FB 0xa1
> +
> +/* 30k pull-up1 */
> +#define ADC5_GEN3_AMUX1_THM_30K_PU 0x24
> +#define ADC5_GEN3_AMUX2_THM_30K_PU 0x25
> +#define ADC5_GEN3_AMUX3_THM_30K_PU 0x26
> +#define ADC5_GEN3_AMUX4_THM_30K_PU 0x27
> +#define ADC5_GEN3_AMUX5_THM_30K_PU 0x28
> +#define ADC5_GEN3_AMUX6_THM_30K_PU 0x29
> +#define ADC5_GEN3_AMUX1_GPIO_30K_PU 0x2a
> +#define ADC5_GEN3_AMUX2_GPIO_30K_PU 0x2b
> +#define ADC5_GEN3_AMUX3_GPIO_30K_PU 0x2c
> +#define ADC5_GEN3_AMUX4_GPIO_30K_PU 0x2d
> +
> +/* 100k pull-up2 */
> +#define ADC5_GEN3_AMUX1_THM_100K_PU 0x44
> +#define ADC5_GEN3_AMUX2_THM_100K_PU 0x45
> +#define ADC5_GEN3_AMUX3_THM_100K_PU 0x46
> +#define ADC5_GEN3_AMUX4_THM_100K_PU 0x47
> +#define ADC5_GEN3_AMUX5_THM_100K_PU 0x48
> +#define ADC5_GEN3_AMUX6_THM_100K_PU 0x49
> +#define ADC5_GEN3_AMUX1_GPIO_100K_PU 0x4a
> +#define ADC5_GEN3_AMUX2_GPIO_100K_PU 0x4b
> +#define ADC5_GEN3_AMUX3_GPIO_100K_PU 0x4c
> +#define ADC5_GEN3_AMUX4_GPIO_100K_PU 0x4d
> +
> +/* 400k pull-up3 */
> +#define ADC5_GEN3_AMUX1_THM_400K_PU 0x64
> +#define ADC5_GEN3_AMUX2_THM_400K_PU 0x65
> +#define ADC5_GEN3_AMUX3_THM_400K_PU 0x66
> +#define ADC5_GEN3_AMUX4_THM_400K_PU 0x67
> +#define ADC5_GEN3_AMUX5_THM_400K_PU 0x68
> +#define ADC5_GEN3_AMUX6_THM_400K_PU 0x69
> +#define ADC5_GEN3_AMUX1_GPIO_400K_PU 0x6a
> +#define ADC5_GEN3_AMUX2_GPIO_400K_PU 0x6b
> +#define ADC5_GEN3_AMUX3_GPIO_400K_PU 0x6c
> +#define ADC5_GEN3_AMUX4_GPIO_400K_PU 0x6d
> +
> +/* 1/3 Divider */
> +#define ADC5_GEN3_AMUX1_GPIO_DIV3 0x8a
> +#define ADC5_GEN3_AMUX2_GPIO_DIV3 0x8b
> +#define ADC5_GEN3_AMUX3_GPIO_DIV3 0x8c
> +#define ADC5_GEN3_AMUX4_GPIO_DIV3 0x8d
> +
> +#define ADC5_GEN3_VPH_PWR 0x8e
> +#define ADC5_GEN3_VBAT_SNS_QBG 0x8f
> +
> +#define ADC5_GEN3_VBAT_SNS_CHGR 0x94
> +#define ADC5_GEN3_VBAT_2S_MID_QBG 0x96
> +#define ADC5_GEN3_VBAT_2S_MID_CHGR 0x9d
> +
> +#define ADC5_GEN3_OFFSET_EXT2 0xf8
> +
> #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */

2024-01-04 08:08:43

[permalink] [raw]

Subject: Re: [PATCH v3 1/3] dt-bindings: iio/adc: Move QCOM ADC bindings to iio/adc folder

On 31/12/2023 18:12, Jishnu Prakash wrote:
> There are several files containing QCOM ADC macros for channel names
> right now in the include/dt-bindings/iio folder. Since all of these
> are specifically for adc, move the files to the
> include/dt-bindings/iio/adc folder.
>
> Also update all affected devicetree and driver files to fix compilation
> errors seen with this move and update documentation files to fix
> dtbinding check errors for the same.
>
> Changes since v2:
> - Updated some more new devicetree files requiring this change.

Changelog goes under ---

>
> Acked-by: Lee Jones <[email protected]>
> Acked-by: Rob Herring <[email protected]>
> Signed-off-by: Jishnu Prakash <[email protected]>

No dependencies mentioned and this has build failures. Please test your
patches before sending.

Best regards,
Krzysztof

2024-01-04 08:18:33

[permalink] [raw]

Subject: Re: [PATCH v3 2/3] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC

On 31/12/2023 18:12, Jishnu Prakash wrote:
> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the
> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs.
>
> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs
> going through PBS(Programmable Boot Sequence) firmware through a single
> register interface. This interface is implemented on an SDAM (Shared
> Direct Access Memory) peripheral on the master PMIC PMK8550 rather
> than a dedicated ADC peripheral.
>
> Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC
> channels and virtual channels (combination of ADC channel number and
> PMIC SID number) per PMIC, to be used by clients of this device.
>
> Changes since v2:
> - Moved ADC5 Gen3 documentation into a separate new file.

Changelog goes under ---.

Why did you do this? What is the rationale? Sorry, this patchset goes
nowhere.

>
> Changes since v1:
> - Updated properties separately for all compatibles to clarify usage
> of new properties and updates in usage of old properties for ADC5 Gen3.
> - Avoided updating 'adc7' name to 'adc5 gen2' and just left a comment
> mentioning this convention.
> - Used predefined channel IDs in individual PMIC channel definitions
> instead of numeric IDs.
> - Addressed other comments from reviewers.
>
> Co-developed-by: Anjelique Melendez <[email protected]>
> Signed-off-by: Anjelique Melendez <[email protected]>
> Signed-off-by: Jishnu Prakash <[email protected]>
> ---
> .../bindings/iio/adc/qcom,spmi-adc5-gen3.yaml | 212 ++++++++++++++++++
> .../iio/adc/qcom,spmi-adc5-gen3-pm8550.h | 50 +++++
> .../iio/adc/qcom,spmi-adc5-gen3-pm8550b.h | 89 ++++++++
> .../iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h | 22 ++
> .../iio/adc/qcom,spmi-adc5-gen3-pmk8550.h | 56 +++++
> .../iio/adc/qcom,spmi-adc7-pmr735b.h | 2 +-
> .../iio/adc/qcom,spmi-adc7-smb139x.h | 2 +-
> include/dt-bindings/iio/adc/qcom,spmi-vadc.h | 81 +++++++
> 8 files changed, 512 insertions(+), 2 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml
> create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h
> create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h
> create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h
> create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml
> new file mode 100644
> index 000000000000..ed5bb53e7628
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml
> @@ -0,0 +1,212 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-adc5-gen3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm's SPMI PMIC ADC5 Gen3
> +
> +maintainers:
> + - Jishnu Prakash <[email protected]>
> +
> +description: |

Do not need '|' unless you need to preserve formatting.

> + SPMI PMIC5 Gen3 voltage ADC (ADC) provides interface to
> + clients to read voltage. It is a 16-bit sigma-delta ADC.
> + It also performs the same thermal monitoring function as
> + the existing ADC_TM devices.
> +
> +properties:
> + compatible:
> + const: qcom,spmi-adc5-gen3
> +
> + reg:
> + description: |
> + - Each reg corresponds to an SDAM peripheral base address that is being used for ADC.

Missing constraints, weird formatting and not wrapped according to
coding style (read Linux coding style).

> +
> + '#address-cells':
> + const: 1
> +
> + '#size-cells':
> + const: 0
> +
> + "#thermal-sensor-cells":
> + const: 1
> + description:
> + Number of cells required to uniquely identify the thermal sensors. Since
> + we have multiple sensors this is set to 1. This property is required for
> + ADC devices with channels used for TM (thermal monitoring) functionality.
> +
> + '#io-channel-cells':
> + const: 1
> +
> + interrupts:
> + description: |
> + End of conversion interrupt. Interrupts are defined for each SDAM being used.

Same problemns.

You already got comments on this in v2.

> +
> + interrupt-names:
> + minItems: 1
> + maxItems: 10
> + items:
> + pattern: "^adc-sdam[0-9]+$"
> + description: |
> + Names should be defined as "adc-sdam<N>" where <N> represents the SDAM index.

Don't repeat constraints in free form text.

> +
> +required:

required: goes after all properties.

> + - compatible
> + - reg
> + - '#address-cells'
> + - '#size-cells'
> + - '#io-channel-cells'
> + - interrupts
> + - interrupt-names
> +
> +patternProperties:
> + "^channel@[0-9a-f]+$":
> + type: object
> + additionalProperties: false
> + description: |

Do not need '|' unless you need to preserve formatting.

> + Represents the external channels which are connected to the ADC.
> +
> + properties:
> + reg:
> + maxItems: 1
> + description: |
> + ADC channel number.
> + See include/dt-bindings/iio/adc/qcom,spmi-vadc.h
> + For PMIC5 Gen3 ADC, the channel numbers are specified separately
> + per PMIC in the PMIC-specific files in include/dt-bindings/iio/adc.
> +
> + label:
> + $ref: /schemas/types.yaml#/definitions/string

Why do you need it in the first place? Don't you miss some $ref?

> + description: |

Do not need '|' unless you need to preserve formatting. Applies everywhere.

> + ADC input of the platform as seen in the schematics.
> + For thermistor inputs connected to generic AMUX or GPIO inputs
> + these can vary across platform for the same pins. Hence select
> + the platform schematics name for this channel.
> +
> + qcom,decimation:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + This parameter is used to decrease ADC sampling rate.
> + Quicker measurements can be made by reducing decimation ratio.
> + enum: [ 85, 340, 1360 ]
> + default: 1360
> +
> + qcom,pre-scaling:
> + description: |
> + Used for scaling the channel input signal before the signal is
> + fed to VADC. The configuration for this node is to know the
> + pre-determined ratio and use it for post scaling. It is a pair of
> + integers, denoting the numerator and denominator of the fraction by which
> + input signal is multiplied. For example, <1 3> indicates the signal is scaled
> + down to 1/3 of its value before ADC measurement.
> + If property is not found default value depending on chip will be used.
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + items:
> + - const: 1
> + - enum: [ 1, 3, 6, 16 ]
> +
> + qcom,ratiometric:
> + description: |
> + Channel calibration type.
> + - If this property is specified VADC will use the VDD reference (1.875V)
> + and GND for channel calibration. If property is not found, channel will be
> + calibrated with 0V and 1.25V reference channels, also known as
> + absolute calibration.
> + type: boolean
> +
> + qcom,hw-settle-time:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + Time between AMUX getting configured and the ADC starting
> + conversion. The 'hw_settle_time' is an index used from valid values
> + and programmed in hardware to achieve the hardware settling delay.
> + enum: [ 15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000,
> + 8000, 16000, 32000, 64000, 128000 ]
> + default: 15
> +
> + qcom,avg-samples:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + Number of samples to be used for measurement.
> + Averaging provides the option to obtain a single measurement
> + from the ADC that is an average of multiple samples. The value
> + selected is 2^(value).
> + enum: [ 1, 2, 4, 8, 16 ]
> + default: 1
> +
> + qcom,adc-tm:
> + description: |
> + Indicates if ADC_TM monitoring is done on this channel.
> + Defined for compatible property "qcom,spmi-adc5-gen3".
> + This is the same functionality as in the existing QCOM ADC_TM
> + device, documented at devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml.
> + type: boolean
> +

Why do you duplicate entire vadc file? Why it cannot be part of that
file? Oh wait, it was in v2.

You now duplicated a lot of property definitions without clear reason.
If this is intention, then you need to put them in common schema.

> + required:
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h>
> + #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h>
> + #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h>
> + #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + pmic {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* VADC node */
> + pmk8550_vadc: vadc@9000 {

Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation

Really, duplicating entire file and adding mistakes? Just open the
original file which you changed in v2 and look how it is done there.

> + compatible = "qcom,spmi-adc5-gen3";
> + reg = <0x9000>, <0x9100>;
> + interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>,
> + <0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>;

wrong alignment.

> + interrupt-names = "adc-sdam0", "adc-sdam1";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #io-channel-cells = <1>;
> + #thermal-sensor-cells = <1>;
> +
> + /* PMK8550 Channel nodes */
> + channel@3 {
> + reg = <PMK8550_ADC5_GEN3_DIE_TEMP>;
> + label = "pmk8550_die_temp";
> + qcom,pre-scaling = <1 1>;
> + };
> +
> + channel@44 {
> + reg = <PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU>;
> + label = "pmk8550_xo_therm";
> + qcom,pre-scaling = <1 1>;
> + qcom,ratiometric;
> + qcom,hw-settle-time = <200>;
> + qcom,adc-tm;
> + };
> +
> + /* PM8550 Channel nodes */
> + channel@103 {
> + reg = <PM8550_ADC5_GEN3_DIE_TEMP>;
> + label = "pm8550_die_temp";
> + qcom,pre-scaling = <1 1>;
> + };
> +
> + /* PM8550B Channel nodes */
> + channel@78f {
> + reg = <PM8550B_ADC5_GEN3_VBAT_SNS_QBG>;
> + label = "pm8550b_vbat_sns_qbg";
> + qcom,pre-scaling = <1 3>;
> + };
> +
> + /* PM8550VS_C Channel nodes */
> + channel@203 {
> + reg = <PM8550VS_ADC5_GEN3_DIE_TEMP(2)>;
> + label = "pm8550vs_c_die_temp";
> + qcom,pre-scaling = <1 1>;
> + };
> + };
> + };
> diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h
> new file mode 100644
> index 000000000000..0f25ef87ed5c
> --- /dev/null
> +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h
> @@ -0,0 +1,50 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H
> +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H
> +
> +#ifndef PM8550_SID
> +#define PM8550_SID 1
> +#endif

Drop

> +
> +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
> +
> +/* ADC channels for PM8550_ADC for PMIC5 Gen3 */
> +#define PM8550_ADC5_GEN3_REF_GND (PM8550_SID << 8 | ADC5_GEN3_REF_GND)
> +#define PM8550_ADC5_GEN3_1P25VREF (PM8550_SID << 8 | ADC5_GEN3_1P25VREF)
> +#define PM8550_ADC5_GEN3_VREF_VADC (PM8550_SID << 8 | ADC5_GEN3_VREF_VADC)
> +#define PM8550_ADC5_GEN3_DIE_TEMP (PM8550_SID << 8 | ADC5_GEN3_DIE_TEMP)
> +
> +#define PM8550_ADC5_GEN3_AMUX_THM1 (PM8550_SID << 8 | ADC5_GEN3_AMUX1_THM)
> +#define PM8550_ADC5_GEN3_AMUX_THM2 (PM8550_SID << 8 | ADC5_GEN3_AMUX2_THM)
> +#define PM8550_ADC5_GEN3_AMUX_THM3 (PM8550_SID << 8 | ADC5_GEN3_AMUX3_THM)
> +#define PM8550_ADC5_GEN3_AMUX_THM4 (PM8550_SID << 8 | ADC5_GEN3_AMUX4_THM)
> +#define PM8550_ADC5_GEN3_AMUX_THM5 (PM8550_SID << 8 | ADC5_GEN3_AMUX5_THM)
> +#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2 (PM8550_SID << 8 | ADC5_GEN3_AMUX6_THM)
> +#define PM8550_ADC5_GEN3_AMUX1_GPIO3 (PM8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO)
> +#define PM8550_ADC5_GEN3_AMUX2_GPIO4 (PM8550_SID << 8 | ADC5_GEN3_AMUX2_GPIO)
> +#define PM8550_ADC5_GEN3_AMUX3_GPIO7 (PM8550_SID << 8 | ADC5_GEN3_AMUX3_GPIO)
> +#define PM8550_ADC5_GEN3_AMUX4_GPIO12 (PM8550_SID << 8 | ADC5_GEN3_AMUX4_GPIO)
> +
> +/* 100k pull-up */
> +#define PM8550_ADC5_GEN3_AMUX_THM1_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX1_THM_100K_PU)
> +#define PM8550_ADC5_GEN3_AMUX_THM2_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX2_THM_100K_PU)
> +#define PM8550_ADC5_GEN3_AMUX_THM3_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX3_THM_100K_PU)
> +#define PM8550_ADC5_GEN3_AMUX_THM4_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX4_THM_100K_PU)
> +#define PM8550_ADC5_GEN3_AMUX_THM5_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX5_THM_100K_PU)
> +#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX6_THM_100K_PU)
> +#define PM8550_ADC5_GEN3_AMUX1_GPIO3_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX1_GPIO_100K_PU)
> +#define PM8550_ADC5_GEN3_AMUX2_GPIO4_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX2_GPIO_100K_PU)
> +#define PM8550_ADC5_GEN3_AMUX3_GPIO7_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX3_GPIO_100K_PU)
> +#define PM8550_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550_SID << 8 | ADC5_GEN3_AMUX4_GPIO_100K_PU)
> +
> +/* 1/3 Divider */
> +#define PM8550_ADC5_GEN3_AMUX3_GPIO7_DIV3 (PM8550_SID << 8 | ADC5_GEN3_AMUX3_GPIO_DIV3)
> +#define PM8550_ADC5_GEN3_AMUX4_GPIO12_DIV3 (PM8550_SID << 8 | ADC5_GEN3_AMUX4_GPIO_DIV3)
> +
> +#define PM8550_ADC5_GEN3_VPH_PWR (PM8550_SID << 8 | ADC5_GEN3_VPH_PWR)
> +
> +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H */
> diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h
> new file mode 100644
> index 000000000000..47116bbe45de
> --- /dev/null
> +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h
> @@ -0,0 +1,89 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H
> +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H
> +
> +#ifndef PM8550B_SID
> +#define PM8550B_SID 7

Drop

> +#endif
> +

...

> +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H */
> diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h
> new file mode 100644
> index 000000000000..3fc829ebdf6d
> --- /dev/null
> +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h
> @@ -0,0 +1,56 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H
> +#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H
> +
> +#ifndef PMK8550_SID
> +#define PMK8550_SID 0
> +#endif

Drop

>
> /* ADC channels for PMR735B_ADC for PMIC7 */
> #define PMR735B_ADC7_REF_GND (PMR735B_SID << 8 | ADC7_REF_GND)
> diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h
> index c0680d1285cf..750a526af2c1 100644
> --- a/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h
> +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h
> @@ -6,7 +6,7 @@
> #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_SMB139X_H
> #define _DT_BINDINGS_QCOM_SPMI_VADC_SMB139X_H
>
> -#include <dt-bindings/iio/qcom,spmi-vadc.h>
> +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>

? How is it related?

>
> #define SMB139x_1_ADC7_SMB_TEMP (SMB139x_1_SID << 8 | ADC7_SMB_TEMP)
> #define SMB139x_1_ADC7_ICHG_SMB (SMB139x_1_SID << 8 | ADC7_ICHG_SMB)
> diff --git a/include/dt-bindings/iio/adc/qcom,spmi-vadc.h b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h
> index ef07ecd4d585..cfe653d945a4 100644
> --- a/include/dt-bindings/iio/adc/qcom,spmi-vadc.h
> +++ b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h
> @@ -1,6 +1,8 @@
> /* SPDX-License-Identifier: GPL-2.0 */
> /*
> * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved.
> + *

Drop stray blank line

Best regards,
Krzysztof

2024-02-14 14:04:20

[permalink] [raw]

Subject: Re: [PATCH v3 3/3] iio: adc: Add support for QCOM PMIC5 Gen3 ADC

Hi Dmitry,

On 12/31/2023 11:16 PM, Dmitry Baryshkov wrote:
> On Sun, 31 Dec 2023 at 19:13, Jishnu Prakash <[email protected]> wrote:
>> The ADC architecture on PMIC5 Gen3 is similar to that on PMIC5 Gen2,
>> with all SW communication to ADC going through PMK8550 which
>> communicates with other PMICs through PBS.

>> +static int adc_tm_register_tzd(struct adc5_chip *adc)
>> +{
>> + unsigned int i, channel;
>> + struct thermal_zone_device *tzd;
>> +
>> + for (i = 0; i < adc->nchannels; i++) {
>> + channel = V_CHAN(adc->chan_props[i]);
>> +
>> + if (!adc->chan_props[i].adc_tm)
>> + continue;
>> + tzd = devm_thermal_of_zone_register(adc->dev, channel,
>> + &adc->chan_props[i], &adc_tm_ops);
> It is _very_ useful to register a hwmon too by calling
> devm_thermal_add_hwmon_sysfs(). However this becomes tricky, as this
> function is not defined in one of the global headers.
>
> This actually points out an issue. You have the ADC driver fused
> together with the thermal driver. Can I suggest using the aux device
> to split the thermal functionality to the separate driver?
>
> This way it would be possible to use the ADC without any thermal
> monitoring in place.

There are a couple of issues which may make it harder to split the
thermal functionality from this driver into an auxiliary driver as you
mentioned.

For one, we use the same set of registers (offsets 0x4f-0x55) for both
VADC function(requesting an immediate channel reading) and ADC_TM
function (setting upper/lower thermal thresholds on a channel). To avoid
any race conditions, we would need to share a mutex between the
top-level ADC driver and the auxiliary ADC_TM thermal driver to avoid
concurrently accessing these or any other shared registers.

In addition, the device has only one interrupt with one interrupt
handler, and it gets triggered for both VADC and ADC_TM events (end of
conversion and threshold violation, respectively). The handler checks
for both types of event and handles it as required.

For the shared interrupt, we may be able to keep the interrupt handler
in the top-level driver and just notify the auxiliary TM driver if a
threshold violation is detected. For the shared mutex, I think the
auxiliary driver may be able to access the parent driver's mutex, but
I'll need to check more for the implementation in both of these cases.

Please let me know if you see any problems with this kind of
implementation or if you have any additional comments.

Thanks,

Jishnu

>> +
>> + if (IS_ERR(tzd)) {
>> + if (PTR_ERR(tzd) == -ENODEV) {
>> + dev_warn(adc->dev, "thermal sensor on channel %d is not used\n",
>> + channel);
>> + continue;
>> + }
>> +
>>
>

2024-02-16 10:40:30

[permalink] [raw]

Subject: Re: [PATCH v3 2/3] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC

Hi Jonathan,

On 1/1/2024 11:32 PM, Jonathan Cameron wrote:
> On Sun, 31 Dec 2023 22:42:36 +0530
> Jishnu Prakash <[email protected]> wrote:
>
>> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the

>> +
>> + label:
>> + $ref: /schemas/types.yaml#/definitions/string
>> + description: |
>> + ADC input of the platform as seen in the schematics.
>> + For thermistor inputs connected to generic AMUX or GPIO inputs
>> + these can vary across platform for the same pins. Hence select
>> + the platform schematics name for this channel.
> defined in adc.yaml, so should just have a reference to that here.
>
>> +
>> + qcom,decimation:
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> + description: |
>> + This parameter is used to decrease ADC sampling rate.
>> + Quicker measurements can be made by reducing decimation ratio.
> Why is this in DT rather than as a userspace control?

We don't intend this property to be something that can be controlled
from userspace - if a client wants to read an ADC channel from
userspace, we only intend to provide them the processed value,
calculated with a fixed set of ADC properties mentioned in the
corresponding channel node in DT.

>> + enum: [ 85, 340, 1360 ]
>> + default: 1360
>> +

>> +
>> + qcom,hw-settle-time:
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> + description: |
>> + Time between AMUX getting configured and the ADC starting
>> + conversion. The 'hw_settle_time' is an index used from valid values
>> + and programmed in hardware to achieve the hardware settling delay.
>> + enum: [ 15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000,
>> + 8000, 16000, 32000, 64000, 128000 ]
>> + default: 15
> only currently defined for muxes but we have settle-time-us which has benefit of
> providing the units (which are missing here from the description as well)
>
>> +
>> + qcom,avg-samples:
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> + description: |
>> + Number of samples to be used for measurement.
>> + Averaging provides the option to obtain a single measurement
>> + from the ADC that is an average of multiple samples. The value
>> + selected is 2^(value).
> Why is this in dt? Why not just userspace control (in_voltageX_oversampling_ratio
>
> If it needs to be, we do have standard DT bindings for it in adc.yaml

avg-samples is also something we don't want the client to modify from
userspace. As for using adc.yaml, I think I could use settling-time-us
and oversampling-ratio from it for the above two properties.

However, Krzysztof has mentioned in another comment that I should put
properties common to ADC5 Gen3 and older QCOM VADC devices in a common
schema. If I now try replacing the existing qcom,hw-settle-time and
qcom,avg-samples properties with settling-time-us and oversampling-ratio
for older devices too, I would have to make several DT changes for
existing devices...are you fine with this? Or should I just replace
these two properties for ADC5 Gen3?

I'll address your other comments in the next patchset.

Thanks,

Jishnu

2024-02-16 10:48:52

[permalink] [raw]

Subject: Re: [PATCH v3 2/3] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC

Hi Jishnu,

On Fri, 16 Feb 2024 at 12:39, Jishnu Prakash <[email protected]> wrote:

Please disable sending HTML emails in your email client. It is
generally frowned upon, it complicates replying, it breaks quotations,
etc.

>
> Hi Krzysztof,
>
> On 1/4/2024 1:48 PM, Krzysztof Kozlowski wrote:
>
> On 31/12/2023 18:12, Jishnu Prakash wrote:
>
> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the
> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs.
>
> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs
> going through PBS(Programmable Boot Sequence) firmware through a single
> register interface. This interface is implemented on an SDAM (Shared
> Direct Access Memory) peripheral on the master PMIC PMK8550 rather
> than a dedicated ADC peripheral.
>
> Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC
> channels and virtual channels (combination of ADC channel number and
> PMIC SID number) per PMIC, to be used by clients of this device.
>
> Changes since v2:
> - Moved ADC5 Gen3 documentation into a separate new file.
>
> Changelog goes under ---.
>
> Why did you do this? What is the rationale? Sorry, this patchset goes
> nowhere.
>
>
> I'll elaborate this more in the next patchset. There are two main reasons for adding this documentation in a new file:
>
> 1.This device is not exactly like the existing QCOM VADC drivers as it now combines VADC functionality (reading ADC channel on client request) with ADC_TM functionality (thermal threshold monitoring).
>
> 2.Adding this device's bindings in the existing qcom,spmi-vadc.yaml file is not possible as it would require updating some of the existing top-level constraints. (for the older devices in that file, "reg" and "interrupts" can have at most one item, while this device can have more than one item under these properties.)
>
>
> Changes since v1:
> - Updated properties separately for all compatibles to clarify usage
> of new properties and updates in usage of old properties for ADC5 Gen3.
> - Avoided updating 'adc7' name to 'adc5 gen2' and just left a comment
> mentioning this convention.
> - Used predefined channel IDs in individual PMIC channel definitions
> instead of numeric IDs.
> - Addressed other comments from reviewers.
>
>
> + per PMIC in the PMIC-specific files in include/dt-bindings/iio/adc.
> +
> + label:
> + $ref: /schemas/types.yaml#/definitions/string
>
> Why do you need it in the first place? Don't you miss some $ref?
>
>
> This is just meant to show the ADC channel name in DT for our reference. I'll check if I can use adc.yaml, which includes this property already, as a reference in this case.
>
>
> + description: |
>
> Do not need '|' unless you need to preserve formatting. Applies everywhere.
>
>
>
> + ADC input of the platform as seen in the schematics.
> + For thermistor inputs connected to generic AMUX or GPIO inputs
> + these can vary across platform for the same pins. Hence select
> + the platform schematics name for this channel.
> +
>
> + qcom,adc-tm:
> + description: |
> + Indicates if ADC_TM monitoring is done on this channel.
> + Defined for compatible property "qcom,spmi-adc5-gen3".

You are describing qcom,spmi-adc5-gen3, are you not? So this phrase
adds nothing.

> + This is the same functionality as in the existing QCOM ADC_TM
> + device, documented at devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml.
> + type: boolean
> +
>
> Why do you duplicate entire vadc file? Why it cannot be part of that
> file? Oh wait, it was in v2.
>
> You now duplicated a lot of property definitions without clear reason.
> If this is intention, then you need to put them in common schema.
>
>
> Many of the properties used for earlier QCOM VADC devices will be used for this device too.....do you mean I can add a new schema file (named something like qcom,vadc.yaml) and move common properties into it (like qcom,hw-settle-time, qcom,decimation, etc) from this file and qcom,spmi-vadc.yaml?
>
> Can I do it in the same patch or should it be a separate patch coming before this one ?

I'd say, separate patch. Move first, extend later.

>
>
>
> diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h
>
> index c0680d1285cf..750a526af2c1 100644
> --- a/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h
> +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h
> @@ -6,7 +6,7 @@
> #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_SMB139X_H
> #define _DT_BINDINGS_QCOM_SPMI_VADC_SMB139X_H
>
> -#include <dt-bindings/iio/qcom,spmi-vadc.h>
> +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
>
> ? How is it related?
>
>
> This should have gone into patch 1, I'll fix it in the next patch series.
>
> I'll address all your other comments in the next patchset.
>
> Thanks,
>
> Jishnu
>
>
>
> #define SMB139x_1_ADC7_SMB_TEMP (SMB139x_1_SID << 8 | ADC7_SMB_TEMP)
> #define SMB139x_1_ADC7_ICHG_SMB (SMB139x_1_SID << 8 | ADC7_ICHG_SMB)
> diff --git a/include/dt-bindings/iio/adc/qcom,spmi-vadc.h b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h
> index ef07ecd4d585..cfe653d945a4 100644
> --- a/include/dt-bindings/iio/adc/qcom,spmi-vadc.h
> +++ b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h
> @@ -1,6 +1,8 @@
> /* SPDX-License-Identifier: GPL-2.0 */
> /*
> * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved.
> + *
>
> Drop stray blank line
>
> Best regards,
> Krzysztof
>

--
With best wishes
Dmitry

2024-02-16 10:53:22

[permalink] [raw]

Subject: Re: [PATCH v3 3/3] iio: adc: Add support for QCOM PMIC5 Gen3 ADC

On Wed, 14 Feb 2024 at 15:58, Jishnu Prakash <[email protected]> wrote:
>
> Hi Dmitry,
>
> On 12/31/2023 11:16 PM, Dmitry Baryshkov wrote:
> > On Sun, 31 Dec 2023 at 19:13, Jishnu Prakash <[email protected]> wrote:
> >> The ADC architecture on PMIC5 Gen3 is similar to that on PMIC5 Gen2,
> >> with all SW communication to ADC going through PMK8550 which
> >> communicates with other PMICs through PBS.
>
> >> +static int adc_tm_register_tzd(struct adc5_chip *adc)
> >> +{
> >> + unsigned int i, channel;
> >> + struct thermal_zone_device *tzd;
> >> +
> >> + for (i = 0; i < adc->nchannels; i++) {
> >> + channel = V_CHAN(adc->chan_props[i]);
> >> +
> >> + if (!adc->chan_props[i].adc_tm)
> >> + continue;
> >> + tzd = devm_thermal_of_zone_register(adc->dev, channel,
> >> + &adc->chan_props[i], &adc_tm_ops);
> > It is _very_ useful to register a hwmon too by calling
> > devm_thermal_add_hwmon_sysfs(). However this becomes tricky, as this
> > function is not defined in one of the global headers.
> >
> > This actually points out an issue. You have the ADC driver fused
> > together with the thermal driver. Can I suggest using the aux device
> > to split the thermal functionality to the separate driver?
> >
> > This way it would be possible to use the ADC without any thermal
> > monitoring in place.
>
>
> There are a couple of issues which may make it harder to split the
> thermal functionality from this driver into an auxiliary driver as you
> mentioned.
>
> For one, we use the same set of registers (offsets 0x4f-0x55) for both
> VADC function(requesting an immediate channel reading) and ADC_TM
> function (setting upper/lower thermal thresholds on a channel). To avoid
> any race conditions, we would need to share a mutex between the
> top-level ADC driver and the auxiliary ADC_TM thermal driver to avoid
> concurrently accessing these or any other shared registers.

Just export an API performing this access. No need to export data (aka mutex).

>
> In addition, the device has only one interrupt with one interrupt
> handler, and it gets triggered for both VADC and ADC_TM events (end of
> conversion and threshold violation, respectively). The handler checks
> for both types of event and handles it as required.

You can extend auxiliary drivers with the custom callbacks, see
drivers/base/auxiliary.c .
I think you can call a callback from ADC_TM driver from your ADC driver.

>
> For the shared interrupt, we may be able to keep the interrupt handler
> in the top-level driver and just notify the auxiliary TM driver if a
> threshold violation is detected. For the shared mutex, I think the
> auxiliary driver may be able to access the parent driver's mutex, but
> I'll need to check more for the implementation in both of these cases.
>
> Please let me know if you see any problems with this kind of
> implementation or if you have any additional comments.
>
> Thanks,
>
> Jishnu
>
> >> +
> >> + if (IS_ERR(tzd)) {
> >> + if (PTR_ERR(tzd) == -ENODEV) {
> >> + dev_warn(adc->dev, "thermal sensor on channel %d is not used\n",
> >> + channel);
> >> + continue;
> >> + }
> >> +
> >>
> >

--
With best wishes
Dmitry

2024-02-16 11:19:29

[permalink] [raw]

Subject: Re: [PATCH v3 2/3] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC

Hi Dmitry,

On 2/16/2024 4:18 PM, Dmitry Baryshkov wrote:
> Hi Jishnu,
>
>
> On Fri, 16 Feb 2024 at 12:39, Jishnu Prakash <[email protected]> wrote:
>
> Please disable sending HTML emails in your email client. It is
> generally frowned upon, it complicates replying, it breaks quotations,
> etc.

Sorry, I'm not sure how that happened, but I have fixed it now.

>
>>
>> Hi Krzysztof,
>>
>> On 1/4/2024 1:48 PM, Krzysztof Kozlowski wrote:
>>
>> On 31/12/2023 18:12, Jishnu Prakash wrote:
>>
>> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the
>> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs.
>>

>> +
>>
>> + qcom,adc-tm:
>> + description: |
>> + Indicates if ADC_TM monitoring is done on this channel.
>> + Defined for compatible property "qcom,spmi-adc5-gen3".
>
> You are describing qcom,spmi-adc5-gen3, are you not? So this phrase
> adds nothing.

Yes, I'll remove this.

>
>> + This is the same functionality as in the existing QCOM ADC_TM
>> + device, documented at devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml.
>> + type: boolean
>> +
>>
>> Why do you duplicate entire vadc file? Why it cannot be part of that
>> file? Oh wait, it was in v2.
>>
>> You now duplicated a lot of property definitions without clear reason.
>> If this is intention, then you need to put them in common schema.
>>
>>
>> Many of the properties used for earlier QCOM VADC devices will be used for this device too.....do you mean I can add a new schema file (named something like qcom,vadc.yaml) and move common properties into it (like qcom,hw-settle-time, qcom,decimation, etc) from this file and qcom,spmi-vadc.yaml?
>>
>> Can I do it in the same patch or should it be a separate patch coming before this one ?
>
> I'd say, separate patch. Move first, extend later.

OK, I'll make it this way if no one else has any objections.

Thanks,
Jishnu

>
>>
>>
>>

2024-02-16 11:45:07

[permalink] [raw]

Subject: Re: [PATCH v3 2/3] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC

Hi Krzysztof,

(Resending this mail for tracking on mailing lists, as it got rejected
from lists the first time due to HTML)

On 1/4/2024 1:48 PM, Krzysztof Kozlowski wrote:
> On 31/12/2023 18:12, Jishnu Prakash wrote:
>> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the
>> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs.
>>
>> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs
>> going through PBS(Programmable Boot Sequence) firmware through a single
>> register interface. This interface is implemented on an SDAM (Shared
>> Direct Access Memory) peripheral on the master PMIC PMK8550 rather
>> than a dedicated ADC peripheral.
>>
>> Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC
>> channels and virtual channels (combination of ADC channel number and
>> PMIC SID number) per PMIC, to be used by clients of this device.
>>
>> Changes since v2:
>> - Moved ADC5 Gen3 documentation into a separate new file.
>
> Changelog goes under ---.
>
> Why did you do this? What is the rationale? Sorry, this patchset goes
> nowhere.

I'll elaborate this more in the next patchset. There are two main
reasons for adding this documentation in a new file:

1.This device is not exactly like the existing QCOM VADC drivers as it
now combines VADC functionality (reading ADC channel on client request)
with ADC_TM functionality (thermal threshold monitoring).

2.Adding this device's bindings in the existing qcom,spmi-vadc.yaml file
is not possible as it would require updating some of the existing
top-level constraints. (for the older devices in that file, "reg" and
"interrupts" can have at most one item, while this device can have more
than one item under these properties.)

>
>>
>> Changes since v1:
>> - Updated properties separately for all compatibles to clarify usage
>> of new properties and updates in usage of old properties for ADC5 Gen3.
>> - Avoided updating 'adc7' name to 'adc5 gen2' and just left a comment
>> mentioning this convention.
>> - Used predefined channel IDs in individual PMIC channel definitions
>> instead of numeric IDs.
>> - Addressed other comments from reviewers.
>>

>> + per PMIC in the PMIC-specific files in include/dt-bindings/iio/adc.
>> +
>> + label:
>> + $ref: /schemas/types.yaml#/definitions/string
>
> Why do you need it in the first place? Don't you miss some $ref?

This is just meant to show the ADC channel name in DT for our reference.
I'll check if I can use adc.yaml, which includes this property already,
as a reference in this case.

>
>> + description: |
>
> Do not need '|' unless you need to preserve formatting. Applies everywhere.
>
>
>
>> + ADC input of the platform as seen in the schematics.
>> + For thermistor inputs connected to generic AMUX or GPIO inputs
>> + these can vary across platform for the same pins. Hence select
>> + the platform schematics name for this channel.
>> +

>> +
>> + qcom,adc-tm:
>> + description: |
>> + Indicates if ADC_TM monitoring is done on this channel.
>> + Defined for compatible property "qcom,spmi-adc5-gen3".
>> + This is the same functionality as in the existing QCOM ADC_TM
>> + device, documented at devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml.
>> + type: boolean
>> +
>
> Why do you duplicate entire vadc file? Why it cannot be part of that
> file? Oh wait, it was in v2.
>
> You now duplicated a lot of property definitions without clear reason.
> If this is intention, then you need to put them in common schema.

Many of the properties used for earlier QCOM VADC devices will be used
for this device too.....do you mean I can add a new schema file (named
something like qcom,vadc.yaml) and move common properties into it (like
qcom,hw-settle-time, qcom,decimation, etc) from this file and
qcom,spmi-vadc.yaml?

Dmitry suggests doing it in a separate patch, I'll follow his suggestion
if there's no issue.

>> diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h
>> index c0680d1285cf..750a526af2c1 100644
>> --- a/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h
>> +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h
>> @@ -6,7 +6,7 @@
>> #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_SMB139X_H
>> #define _DT_BINDINGS_QCOM_SPMI_VADC_SMB139X_H
>>
>> -#include <dt-bindings/iio/qcom,spmi-vadc.h>
>> +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
>
> ? How is it related?

This should have gone into patch 1, I'll fix it in the next patch series.

I'll address all your other comments in the next patchset.

Thanks,

Jishnu

>
>>
>> #define SMB139x_1_ADC7_SMB_TEMP (SMB139x_1_SID << 8 | ADC7_SMB_TEMP)
>> #define SMB139x_1_ADC7_ICHG_SMB (SMB139x_1_SID << 8 | ADC7_ICHG_SMB)
>> diff --git a/include/dt-bindings/iio/adc/qcom,spmi-vadc.h b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h
>> index ef07ecd4d585..cfe653d945a4 100644
>> --- a/include/dt-bindings/iio/adc/qcom,spmi-vadc.h
>> +++ b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h
>> @@ -1,6 +1,8 @@
>> /* SPDX-License-Identifier: GPL-2.0 */
>> /*
>> * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved.
>> + *
>
> Drop stray blank line
>
> Best regards,
> Krzysztof
>

2024-02-16 11:45:28

[permalink] [raw]

Subject: Re: [PATCH v3 3/3] iio: adc: Add support for QCOM PMIC5 Gen3 ADC

Hi Jonathan,

(Resending this mail for tracking on mailing lists, as it got rejected
from lists the first time due to HTML)

On 1/1/2024 11:24 PM, Jonathan Cameron wrote:
> On Sun, 31 Dec 2023 22:42:37 +0530
> Jishnu Prakash <[email protected]> wrote:
>
>> The ADC architecture on PMIC5 Gen3 is similar to that on PMIC5 Gen2,
>> with all SW communication to ADC going through PMK8550 which
>> communicates with other PMICs through PBS.
>>

>> +
>> + for (i = 0; i < adc->nchannels; i++) {
>> + bool upper_set = false, lower_set = false;
>> + int temp, offset;
>> + u16 code = 0;
>> +
>> + chan_prop = &adc->chan_props[i];
>> + offset = chan_prop->tm_chan_index;
>> +
>> + if (!chan_prop->adc_tm)
>> + continue;
>> +
>> + mutex_lock(&adc->lock);
>> + if (chan_prop->sdam_index != sdam_index) {
>
> Perhaps factor this block out as indent already high and adding scoped_guard would
> make it worse.

I don't think I can completely factor it out, as we need to update
several local variables here (sdam_index, tm_status, buf, also chan_prop
above), but I'll try to reduce it as much as possible.

>
>> + sdam_index = chan_prop->sdam_index;
>> + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_TM_HIGH_STS,
>> + tm_status, 2);
>> + if (ret) {
>> + dev_err(adc->dev, "adc read TM status failed with %d\n", ret);
>> + goto out;
>> + }

>> +
>> +static void adc5_gen3_disable(void *data)
>> +{
>> + struct adc5_chip *adc = data;
>> + int i;
>> +
>> + if (adc->n_tm_channels)
>> + cancel_work_sync(&adc->tm_handler_work);
> If this is required before the place where a simple
> devm_request_irq() will result in the irqs being cleaned up
> them register this callback earlier to avoid problems there.
>

On checking again, it looks like I can just use devm_request_irq() and
avoid having to free irqs explicitly here and elsewhere. I'll still
need to call cancel_work_sync() and I think you have also asked me to
keep this call in another comment below. I have another question for it
below.

>> +
>> + for (i = 0; i < adc->num_sdams; i++)
>> + free_irq(adc->base[i].irq, adc);
>> +
>> + mutex_lock(&adc->lock);
>> + /* Disable all available TM channels */
>> + for (i = 0; i < adc->nchannels; i++) {
>> + if (!adc->chan_props[i].adc_tm)
>> + continue;
>> + adc5_gen3_poll_wait_hs(adc, adc->chan_props[i].sdam_index);
>> + _adc_tm5_gen3_disable_channel(&adc->chan_props[i]);
>> + }
>> +
>> + mutex_unlock(&adc->lock);
>> +}
>

>> +
>> + prop->hw_settle_time = VADC_DEF_HW_SETTLE_TIME;
>
> I'd prefer to see you has through the value that maps to this after qcom_adc5_hw_settle_time_from_dt
> so then you can just set a default in value and call the rest of the code unconditionally.
> Same for the cases that follow.

I can remove the return check for fwnode_property_read_u32() as you
suggested, but I think we still need to keep the return check for
qcom_adc5_hw_settle_time_from_dt(), to check in case values unsupported
in this ADC HW are set in DT. Same for the other properties.

>
>> + ret = fwnode_property_read_u32(fwnode, "qcom,hw-settle-time", &value);
>> + if (!ret) {
>> + ret = qcom_adc5_hw_settle_time_from_dt(value,
>> + data->hw_settle_1);
>> + if (ret < 0)
>> + return dev_err_probe(dev, ret, "%#x invalid hw-settle-time %d us\n",
>> + chan, value);
>> + prop->hw_settle_time = ret;
>> + }
>> +

>> +
>> + chan_props = adc->chan_props;
>> + adc->n_tm_channels = 0;
>> + iio_chan = adc->iio_chans;
>> + adc->data = device_get_match_data(adc->dev);
>> + if (!adc->data)
>> + adc->data = &adc5_gen3_data_pmic;
>
> Why do you need a default? Add a comment so we remember the reasoning.

On second thought, this may not be needed, I'll remove this.

>
>
>> +
>> + device_for_each_child_node(adc->dev, child) {
>> + ret = adc5_gen3_get_fw_channel_data(adc, chan_props, child, adc->data);
>> + if (ret < 0) {

>> +
>> + ret = platform_get_irq_byname(pdev, adc->base[i].irq_name);
>> + if (ret < 0) {
>> + kfree(reg);
>> + dev_err(dev, "Getting IRQ %d by name failed, ret = %d\n",
>> + adc->base[i].irq, ret);
>> + goto err_irq;
>> + }
>> + adc->base[i].irq = ret;
>> +
>> + ret = request_irq(adc->base[i].irq, adc5_gen3_isr, 0, adc->base[i].irq_name, adc);
>
> Don't mix devm and non dev calls. And don't group up multiple things in one devm callback
> as it almost always leads to bugs where for example only some irqs are allocated.

I can replace request_irq() with devm_request_irq(). But when you say
not to group up multiple things in one devm callback, do you mean the
devm_add_action() callback I added below or something else right here?

>
>> + if (ret < 0) {
>> + kfree(reg);
>> + dev_err(dev, "Failed to request SDAM%d irq, ret = %d\n", i, ret);
>> + goto err_irq;
>> + }
>> + }
>> + kfree(reg);
>
> I would factor out this code and allocation of reg so you can easily use scope
> based cleanup (see linux/cleanup.h) to avoid the kfree(reg) entries that
> make for awkward code flow.
>

The kfrees are not really needed, I'll just use devm_kcalloc to allocate
memory for the "reg" variable. With this and devm_request_irq, I think a
scoped guard would not be needed here.

>
>
>> +
>> + ret = devm_add_action(dev, adc5_gen3_disable, adc);
> As above, this action does multiple things. Also use devm_add_action_or_reset() to cleanup
> if the devm registration fails without needing to do it manually.

I'll change it to devm_add_action_or_reset(), but do you mean I should
call devm_add_action_or_reset() twice to register two separate callbacks
instead of just adc5_gen3_disable? Like one for calling
cancel_work_sync() alone and the other for the loop where we disable all
TM channels?

>
>> + if (ret < 0) {
>> + dev_err(dev, "failed to register adc disablement devm action, %d\n", ret);
>> + goto err_irq;
>> + }
>> +

>> +
>> + if (adc->n_tm_channels)
>> + INIT_WORK(&adc->tm_handler_work, tm_handler_work);
>
> Until this init work seems unlikely you should be calling the cancel
> work in gen3_disable()

We are already calling cancel_work_sync() in adc5_gen3_disable....is
there any change needed?

I'll address all your other comments in the next patchset.

Thanks,

Jishnu

>
>
>> +
>> + indio_dev->name = pdev->name;
>> + indio_dev->modes = INDIO_DIRECT_MODE;
>> + indio_dev->info = &adc5_gen3_info;
>> + indio_dev->channels = adc->iio_chans;
>> + indio_dev->num_channels = adc->nchannels;
>> +
>> + ret = devm_iio_device_register(dev, indio_dev);
>> + if (!ret)
>> + return 0;
> Please keep error conditions as the out of line path.
>
> if (ret)
> goto err_irq;
>
> return 0;
>
>
>> +
>> +err_irq:
>> + for (i = 0; i < adc->num_sdams; i++)
>> + free_irq(adc->base[i].irq, adc);
>
> Already freed by a devm cleanup handler.
>
>> +
>> + return ret;
>> +}
>

2024-02-16 13:53:03

[permalink] [raw]

Subject: Re: [PATCH v3 2/3] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC

On Fri, 16 Feb 2024 16:09:38 +0530
Jishnu Prakash <[email protected]> wrote:

> Hi Jonathan,
>
> On 1/1/2024 11:32 PM, Jonathan Cameron wrote:
> > On Sun, 31 Dec 2023 22:42:36 +0530
> > Jishnu Prakash <[email protected]> wrote:
> >
> >> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the
>
> >> +
> >> + label:
> >> + $ref: /schemas/types.yaml#/definitions/string
> >> + description: |
> >> + ADC input of the platform as seen in the schematics.
> >> + For thermistor inputs connected to generic AMUX or GPIO inputs
> >> + these can vary across platform for the same pins. Hence select
> >> + the platform schematics name for this channel.
> > defined in adc.yaml, so should just have a reference to that here.
> >
> >> +
> >> + qcom,decimation:
> >> + $ref: /schemas/types.yaml#/definitions/uint32
> >> + description: |
> >> + This parameter is used to decrease ADC sampling rate.
> >> + Quicker measurements can be made by reducing decimation ratio.
> > Why is this in DT rather than as a userspace control?
>
>
> We don't intend this property to be something that can be controlled
> from userspace - if a client wants to read an ADC channel from
> userspace, we only intend to provide them the processed value,
> calculated with a fixed set of ADC properties mentioned in the
> corresponding channel node in DT.

Why? This is a way to control precision of an ADC channel read out.
That's policy rather than dependent on the hardware.
To be in DT we (mostly) need it to be related to the hardware configuration
(i.e. what it is wired to etc).

>
>
> >> + enum: [ 85, 340, 1360 ]
> >> + default: 1360
> >> +
>
> >> +
> >> + qcom,hw-settle-time:
> >> + $ref: /schemas/types.yaml#/definitions/uint32
> >> + description: |
> >> + Time between AMUX getting configured and the ADC starting
> >> + conversion. The 'hw_settle_time' is an index used from valid values
> >> + and programmed in hardware to achieve the hardware settling delay.
> >> + enum: [ 15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000,
> >> + 8000, 16000, 32000, 64000, 128000 ]
> >> + default: 15
> > only currently defined for muxes but we have settle-time-us which has benefit of
> > providing the units (which are missing here from the description as well)
> >
> >> +
> >> + qcom,avg-samples:
> >> + $ref: /schemas/types.yaml#/definitions/uint32
> >> + description: |
> >> + Number of samples to be used for measurement.
> >> + Averaging provides the option to obtain a single measurement
> >> + from the ADC that is an average of multiple samples. The value
> >> + selected is 2^(value).
> > Why is this in dt? Why not just userspace control (in_voltageX_oversampling_ratio
> >
> > If it needs to be, we do have standard DT bindings for it in adc.yaml
>
>
> avg-samples is also something we don't want the client to modify from
> userspace. As for using adc.yaml, I think I could use settling-time-us
> and oversampling-ratio from it for the above two properties.

Same as for above. This is policy. If you want to control it that belongs
in a udev script or similar, not the DT bindings.
We tend to resist defining such policy in DT because it isn't a characteristic
of the hardware and depending on the usecase userspace may have good reason
to tweak the settings (or consumer drivers if you have those as sometimes
these numbers are about getting a particular precision needed for what
we are measuring to be useful for another driver).

There is some legacy for this though as you point out. So that may be a
strong enough argument for why we should make an exception this time.
If so make that clear in the patch description.

>
> However, Krzysztof has mentioned in another comment that I should put
> properties common to ADC5 Gen3 and older QCOM VADC devices in a common
> schema. If I now try replacing the existing qcom,hw-settle-time and
> qcom,avg-samples properties with settling-time-us and oversampling-ratio
> for older devices too, I would have to make several DT changes for
> existing devices...are you fine with this? Or should I just replace
> these two properties for ADC5 Gen3?

If you change DT binding for older devices, you will need to maintain
backwards compatibility. It's fine to deprecate them in the binding
docs etc, but not the driver (as there may be old DT on devices that
can't be easily updated).

>
>
> I'll address your other comments in the next patchset.
>
>
> Thanks,
>
> Jishnu
>

2024-02-16 13:55:52

[permalink] [raw]

Subject: Re: [PATCH v3 3/3] iio: adc: Add support for QCOM PMIC5 Gen3 ADC

On Fri, 16 Feb 2024 16:10:18 +0530
Jishnu Prakash <[email protected]> wrote:

> Hi Jonathan,
>
> On 1/1/2024 11:24 PM, Jonathan Cameron wrote:
> > On Sun, 31 Dec 2023 22:42:37 +0530
> > Jishnu Prakash<[email protected]> wrote:
> >
> >> The ADC architecture on PMIC5 Gen3 is similar to that on PMIC5 Gen2,
> >> with all SW communication to ADC going through PMK8550 which
> >> communicates with other PMICs through PBS.
> >>
>
> >> +
> >> + for (i = 0; i < adc->nchannels; i++) {
> >> + bool upper_set = false, lower_set = false;
> >> + int temp, offset;
> >> + u16 code = 0;
> >> +
> >> + chan_prop = &adc->chan_props[i];
> >> + offset = chan_prop->tm_chan_index;
> >> +
> >> + if (!chan_prop->adc_tm)
> >> + continue;
> >> +
> >> + mutex_lock(&adc->lock);
> >> + if (chan_prop->sdam_index != sdam_index) {
> > Perhaps factor this block out as indent already high and adding scoped_guard would
> > make it worse.
>
>
> I don't think I can completely factor it out, as we need to update
> several local variables here (sdam_index, tm_status, buf, also chan_prop
> above), but I'll try to reduce it as much as possible.
>
>
> >> + sdam_index = chan_prop->sdam_index;
> >> + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_TM_HIGH_STS,
> >> + tm_status, 2);
> >> + if (ret) {
> >> + dev_err(adc->dev, "adc read TM status failed with %d\n", ret);
> >> + goto out;
> >> + }
> >> +
>
> >> +
> >> +static void adc5_gen3_disable(void *data)
> >> +{
> >> + struct adc5_chip *adc = data;
> >> + int i;
> >> +
> >> + if (adc->n_tm_channels)
> >> + cancel_work_sync(&adc->tm_handler_work);
> > If this is required before the place where a simple
> > devm_request_irq() will result in the irqs being cleaned up
> > them register this callback earlier to avoid problems there.
>
>
> On checking again, it looks like I can just use devm_request_irq() and
> avoid having to free irqs explicitly here and elsewhere. I'll still
> need to call cancel_work_sync() and I think you have also asked me to
> keep this call in another comment below. I have another question for it
> below.

Keeping it is fine, just make sure it's registered in the right location
to ensure it is taken down after we are sure it can't get scheduled again
(I think that is what I was getting at - been a while!)
>
>
> >> +
> >> + for (i = 0; i < adc->num_sdams; i++)
> >> + free_irq(adc->base[i].irq, adc);
> >> +
> >> + mutex_lock(&adc->lock);
> >> + /* Disable all available TM channels */
> >> + for (i = 0; i < adc->nchannels; i++) {
> >> + if (!adc->chan_props[i].adc_tm)
> >> + continue;
> >> + adc5_gen3_poll_wait_hs(adc, adc->chan_props[i].sdam_index);
> >> + _adc_tm5_gen3_disable_channel(&adc->chan_props[i]);
> >> + }
> >> +
> >> + mutex_unlock(&adc->lock);
> >> +}
>
> > +
> >> + prop->hw_settle_time = VADC_DEF_HW_SETTLE_TIME;
> > I'd prefer to see you has through the value that maps to this after qcom_adc5_hw_settle_time_from_dt
> > so then you can just set a default in value and call the rest of the code unconditionally.
> > Same for the cases that follow.
>
>
> I can remove the return check for fwnode_property_read_u32() as you
> suggested, but I think we still need to keep the return check for
> qcom_adc5_hw_settle_time_from_dt(), to check in case values unsupported
> in this ADC HW are set in DT. Same for the other properties.

Sure, you can check for errors in using the property. Just do it unconditionally
so that you call the same code for the default (even though you know that will
be fine). Should simplify the code.

>
>
> >> + ret = fwnode_property_read_u32(fwnode, "qcom,hw-settle-time", &value);
> >> + if (!ret) {
> >> + ret = qcom_adc5_hw_settle_time_from_dt(value,
> >> + data->hw_settle_1);
> >> + if (ret < 0)
> >> + return dev_err_probe(dev, ret, "%#x invalid hw-settle-time %d us\n",
> >> + chan, value);
> >> + prop->hw_settle_time = ret;
> >> + }
> >> +

> >
> >> +
> >> + device_for_each_child_node(adc->dev, child) {
> >> + ret = adc5_gen3_get_fw_channel_data(adc, chan_props, child, adc->data);
> >> + if (ret < 0) {
>
> >> + ret = platform_get_irq_byname(pdev, adc->base[i].irq_name);
> >> + if (ret < 0) {
> >> + kfree(reg);
> >> + dev_err(dev, "Getting IRQ %d by name failed, ret = %d\n",
> >> + adc->base[i].irq, ret);
> >> + goto err_irq;
> >> + }
> >> + adc->base[i].irq = ret;
> >> +
> >> + ret = request_irq(adc->base[i].irq, adc5_gen3_isr, 0, adc->base[i].irq_name, adc);
> > Don't mix devm and non dev calls. And don't group up multiple things in one devm callback
> > as it almost always leads to bugs where for example only some irqs are allocated.
>
>
> I can replace request_irq() with devm_request_irq(). But when you say
> not to group up multiple things in one devm callback, do you mean the
> devm_add_action() callback I added below or something else right here?

Yes, I meant the devm_add_action() callback.

>
>
> >> + if (ret < 0) {
> >> + kfree(reg);
> >> + dev_err(dev, "Failed to request SDAM%d irq, ret = %d\n", i, ret);
> >> + goto err_irq;
> >> + }
> >> + }
> >> + kfree(reg);
> > I would factor out this code and allocation of reg so you can easily use scope
> > based cleanup (see linux/cleanup.h) to avoid the kfree(reg) entries that
> > make for awkward code flow.
>
>
> The kfrees are not really needed, I'll just use devm_kcalloc to allocate
> memory for the "reg" variable. With this and devm_request_irq, I think a
> scoped guard would not be needed here.

If you don't need it after this function, then better to clean it up.

>
>
> >
> >
> >> +
> >> + ret = devm_add_action(dev, adc5_gen3_disable, adc);
> > As above, this action does multiple things. Also use devm_add_action_or_reset() to cleanup
> > if the devm registration fails without needing to do it manually.
>
>
> I'll change it to devm_add_action_or_reset(), but do you mean I should
> call devm_add_action_or_reset() twice to register two separate callbacks
> instead of just adc5_gen3_disable? Like one for calling
> cancel_work_sync() alone and the other for the loop where we disable all
> TM channels?

yes

>
>
> >> + if (ret < 0) {
> >> + dev_err(dev, "failed to register adc disablement devm action, %d\n", ret);
> >> + goto err_irq;
> >> + }
> >> +
>
> >> +
> >> + if (adc->n_tm_channels)
> >> + INIT_WORK(&adc->tm_handler_work, tm_handler_work);
> > Until this init work seems unlikely you should be calling the cancel
> > work in gen3_disable()
>
>
> We are already calling cancel_work_sync() in adc5_gen3_disable....is
> there any change needed?
Yes - add a devm_add_action() here (not need for reset in this case as nothing
can have queued any work yet) and handle this on it's own.

Each cleanup action should match with a setup action.

Jonathan

2024-02-17 14:14:14

[permalink] [raw]

Subject: Re: [PATCH v3 2/3] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC

On 16/02/2024 11:39, Jishnu Prakash wrote:
> Hi Krzysztof,
>
> On 1/4/2024 1:48 PM, Krzysztof Kozlowski wrote:
>> On 31/12/2023 18:12, Jishnu Prakash wrote:
>>> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the
>>> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs.
>>>
>>> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs
>>> going through PBS(Programmable Boot Sequence) firmware through a single
>>> register interface. This interface is implemented on an SDAM (Shared
>>> Direct Access Memory) peripheral on the master PMIC PMK8550 rather
>>> than a dedicated ADC peripheral.
>>>
>>> Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC
>>> channels and virtual channels (combination of ADC channel number and
>>> PMIC SID number) per PMIC, to be used by clients of this device.
>>>
>>> Changes since v2:
>>> - Moved ADC5 Gen3 documentation into a separate new file.
>> Changelog goes under ---.
>>
>> Why did you do this? What is the rationale? Sorry, this patchset goes
>> nowhere.
>
>
> I'll elaborate this more in the next patchset. There are two main
> reasons for adding this documentation in a new file:

This was more than a month ago? You reply to my comment with 1.5 months
delay?

Sorry, I am not in the context and I am not going back to it. I have
many other emails where my questions are addressed faster than 1.5 months.

The patch is not even in my mailbox, long gone.
Why you are making it so difficult for reviewers?

You will get answers like I am not in context, sorry. Next time don't
respond after 1.5 months.

>
> 1.This device is not exactly like the existing QCOM VADC drivers as it
> now combines VADC functionality (reading ADC channel on client request)
> with ADC_TM functionality (thermal threshold monitoring).

Does no explain touching bindings. Your drivers don't matter for bindings.

>
> 2.Adding this device's bindings in the existing qcom,spmi-vadc.yaml file

No rationale was provided in commit msg.

> is not possible as it would require updating some of the existing
> top-level constraints. (for the older devices in that file, "reg" and
> "interrupts" can have at most one item, while this device can have more
> than one item under these properties.)

How is this a problem?

Best regards,
Krzysztof

2024-02-17 14:15:20

[permalink] [raw]

Subject: Re: [PATCH v3 2/3] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC

On 16/02/2024 12:44, Jishnu Prakash wrote:
> Hi Krzysztof,
>
> (Resending this mail for tracking on mailing lists, as it got rejected
> from lists the first time due to HTML)

I already responded to some other email of yours and I am not going to
respond twice.

Best regards,
Krzysztof

2024-02-21 05:37:17

[permalink] [raw]

Subject: Re: [PATCH v3 2/3] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC

Hi Krzysztof,

On 2/17/2024 7:43 PM, Krzysztof Kozlowski wrote:
> On 16/02/2024 11:39, Jishnu Prakash wrote:
>> Hi Krzysztof,
>>
>> On 1/4/2024 1:48 PM, Krzysztof Kozlowski wrote:
>>> On 31/12/2023 18:12, Jishnu Prakash wrote:
>>>> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the
>>>> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs.
>>>>
>>>> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs
>>>> going through PBS(Programmable Boot Sequence) firmware through a single
>>>> register interface. This interface is implemented on an SDAM (Shared
>>>> Direct Access Memory) peripheral on the master PMIC PMK8550 rather
>>>> than a dedicated ADC peripheral.
>>>>
>>>> Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC
>>>> channels and virtual channels (combination of ADC channel number and
>>>> PMIC SID number) per PMIC, to be used by clients of this device.
>>>>
>>>> Changes since v2:
>>>> - Moved ADC5 Gen3 documentation into a separate new file.
>>> Changelog goes under ---.
>>>
>>> Why did you do this? What is the rationale? Sorry, this patchset goes
>>> nowhere.
>>
>>
>> I'll elaborate this more in the next patchset. There are two main
>> reasons for adding this documentation in a new file:
>
> This was more than a month ago? You reply to my comment with 1.5 months
> delay?
>
> Sorry, I am not in the context and I am not going back to it. I have
> many other emails where my questions are addressed faster than 1.5 months.
>
> The patch is not even in my mailbox, long gone.
> Why you are making it so difficult for reviewers?
>
> You will get answers like I am not in context, sorry. Next time don't
> respond after 1.5 months.
>

You're right - I'll do my best to get back to review comments in a
reasonable time frame.

>
>>
>> 1.This device is not exactly like the existing QCOM VADC drivers as it
>> now combines VADC functionality (reading ADC channel on client request)
>> with ADC_TM functionality (thermal threshold monitoring).
>
> Does no explain touching bindings. Your drivers don't matter for bindings.
>
>>
>> 2.Adding this device's bindings in the existing qcom,spmi-vadc.yaml file
>
> No rationale was provided in commit msg.
>
>> is not possible as it would require updating some of the existing
>> top-level constraints. (for the older devices in that file, "reg" and
>> "interrupts" can have at most one item, while this device can have more
>> than one item under these properties.)
>

> How is this a problem?

In qcom,spmi-vadc.yaml, we have the following top-level constraints for
the "reg" and "interrupts" properties:

reg:
maxItems: 1

interrupts:
maxItems: 1

For the ADC5 Gen3 device being added now, these constraints cannot be
followed always, as there may be more than one peripheral under one
device instance, each with a corresponding interrupt. For example, the
above properties could be like this for a ADC5 Gen3 device:

reg = <0x9000>, <0x9100>;
interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>,
<0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>;

I could not overwrite the top-level constraints for the new device
"qcom,spmi-adc5-gen3" alone in qcom,spmi-vadc.yaml, so I tried to remove
the constraints from the top level and add them back conditionally for
all the device types separately, but you told me not to remove them
(full message:
https://lore.kernel.org/linux-iio/[email protected]/)

Since these constraints cannot be modified for a specific new device or
removed, I think the only way to accommodate this new device is to add
it in its own new file.

Is this a sufficient justification for adding this documentation in a
new file or do you have any other suggestions?

Thanks,
Jishnu

>
>
> Best regards,
> Krzysztof
>

2024-02-21 07:19:43

[permalink] [raw]

Subject: Re: [PATCH v3 2/3] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC

On 21/02/2024 06:36, Jishnu Prakash wrote:
> Hi Krzysztof,
>
> On 2/17/2024 7:43 PM, Krzysztof Kozlowski wrote:
>> On 16/02/2024 11:39, Jishnu Prakash wrote:
>>> Hi Krzysztof,
>>>
>>> On 1/4/2024 1:48 PM, Krzysztof Kozlowski wrote:
>>>> On 31/12/2023 18:12, Jishnu Prakash wrote:
>>>>> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the
>>>>> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs.
>>>>>
>>>>> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs
>>>>> going through PBS(Programmable Boot Sequence) firmware through a single
>>>>> register interface. This interface is implemented on an SDAM (Shared
>>>>> Direct Access Memory) peripheral on the master PMIC PMK8550 rather
>>>>> than a dedicated ADC peripheral.
>>>>>
>>>>> Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC
>>>>> channels and virtual channels (combination of ADC channel number and
>>>>> PMIC SID number) per PMIC, to be used by clients of this device.
>>>>>
>>>>> Changes since v2:
>>>>> - Moved ADC5 Gen3 documentation into a separate new file.
>>>> Changelog goes under ---.
>>>>
>>>> Why did you do this? What is the rationale? Sorry, this patchset goes
>>>> nowhere.
>>>
>>>
>>> I'll elaborate this more in the next patchset. There are two main
>>> reasons for adding this documentation in a new file:
>>
>> This was more than a month ago? You reply to my comment with 1.5 months
>> delay?
>>
>> Sorry, I am not in the context and I am not going back to it. I have
>> many other emails where my questions are addressed faster than 1.5 months.
>>
>> The patch is not even in my mailbox, long gone.
>> Why you are making it so difficult for reviewers?
>>
>> You will get answers like I am not in context, sorry. Next time don't
>> respond after 1.5 months.
>>
>
> You're right - I'll do my best to get back to review comments in a
> reasonable time frame.
>
>>
>>>
>>> 1.This device is not exactly like the existing QCOM VADC drivers as it
>>> now combines VADC functionality (reading ADC channel on client request)
>>> with ADC_TM functionality (thermal threshold monitoring).
>>
>> Does no explain touching bindings. Your drivers don't matter for bindings.
>>
>>>
>>> 2.Adding this device's bindings in the existing qcom,spmi-vadc.yaml file
>>
>> No rationale was provided in commit msg.
>>
>>> is not possible as it would require updating some of the existing
>>> top-level constraints. (for the older devices in that file, "reg" and
>>> "interrupts" can have at most one item, while this device can have more
>>> than one item under these properties.)
>>
>
>> How is this a problem?
>
> In qcom,spmi-vadc.yaml, we have the following top-level constraints for
> the "reg" and "interrupts" properties:
>
> reg:
> maxItems: 1
>
> interrupts:
> maxItems: 1
>
> For the ADC5 Gen3 device being added now, these constraints cannot be
> followed always, as there may be more than one peripheral under one
> device instance, each with a corresponding interrupt. For example, the
> above properties could be like this for a ADC5 Gen3 device:
>
> reg = <0x9000>, <0x9100>;
> interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>,
> <0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>;
>
>
> I could not overwrite the top-level constraints for the new device
> "qcom,spmi-adc5-gen3" alone in qcom,spmi-vadc.yaml, so I tried to remove
> the constraints from the top level and add them back conditionally for
> all the device types separately, but you told me not to remove them
> (full message:
> https://lore.kernel.org/linux-iio/[email protected]/)

Because top-level widest constraints must stay, but it is not a problem.
Most of the multi-device bindings work like this. Dozen of Qualcomm. Why
you cannot do this the same way we do for all Qualcomm devices?

>
> Since these constraints cannot be modified for a specific new device or

???

> removed, I think the only way to accommodate this new device is to add
> it in its own new file.
>
> Is this a sufficient justification for adding this documentation in a
> new file or do you have any other suggestions?

I already gave you the suggestions and you ignored them. Do like we are
doing for all other drivers. Don't re-invent stuff. Either this fits to
existing schema or come with common schema (and then provide rationale
why it does not fit to existing one).

Best regards,
Krzysztof

2024-03-14 08:29:16

[permalink] [raw]

Subject: Re: [PATCH v3 2/3] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC

Hi Krzysztof,

On 2/21/2024 12:49 PM, Krzysztof Kozlowski wrote:
> On 21/02/2024 06:36, Jishnu Prakash wrote:
>> Hi Krzysztof,
>>
>> On 2/17/2024 7:43 PM, Krzysztof Kozlowski wrote:
>>> On 16/02/2024 11:39, Jishnu Prakash wrote:
>>>> Hi Krzysztof,
>>>>

>>
>>> How is this a problem?
>>
>> In qcom,spmi-vadc.yaml, we have the following top-level constraints for
>> the "reg" and "interrupts" properties:
>>
>> reg:
>> maxItems: 1
>>
>> interrupts:
>> maxItems: 1
>>
>> For the ADC5 Gen3 device being added now, these constraints cannot be
>> followed always, as there may be more than one peripheral under one
>> device instance, each with a corresponding interrupt. For example, the
>> above properties could be like this for a ADC5 Gen3 device:
>>
>> reg = <0x9000>, <0x9100>;
>> interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>,
>> <0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>;
>>
>>
>> I could not overwrite the top-level constraints for the new device
>> "qcom,spmi-adc5-gen3" alone in qcom,spmi-vadc.yaml, so I tried to remove
>> the constraints from the top level and add them back conditionally for
>> all the device types separately, but you told me not to remove them
>> (full message:
>> https://lore.kernel.org/linux-iio/[email protected]/)
>
> Because top-level widest constraints must stay, but it is not a problem.
> Most of the multi-device bindings work like this. Dozen of Qualcomm. Why
> you cannot do this the same way we do for all Qualcomm devices?
>

I would like to clarify a point with you related to the top-level
constraints, as I think I have not asked this exact question earlier.

For these top-level constraints in qcom,spmi-vadc.yaml:

reg:
maxItems: 1

interrupts:
maxItems: 1

If we add ADC5 Gen3 bindings in the same file, is it acceptable to
update the top-level constraints to something like this:

reg:
minItems: 1
maxItems: 2

interrupts:
minItems: 1
maxItems: 2

followed by updating maxItems back to 1 for all the earlier existing
compatibles, using if:then: conditions, like the below example?

- if:
properties:
compatible:
contains:
const: qcom,spmi-adc5

then:
properties:
reg:
maxItems: 1
interrupts:
maxItems: 1

If this is acceptable, I'll add ADC5 Gen3 bindings in the same file with
changes like the above, else I'll add them in a new file after first
creating a common schema file as you suggested.

Thanks,
Jishnu

>>
>> Since these constraints cannot be modified for a specific new device or
>
> ???
>
>> removed, I think the only way to accommodate this new device is to add
>> it in its own new file.
>>
>> Is this a sufficient justification for adding this documentation in a
>> new file or do you have any other suggestions?
>
> I already gave you the suggestions and you ignored them. Do like we are
> doing for all other drivers. Don't re-invent stuff. Either this fits to
> existing schema or come with common schema (and then provide rationale
> why it does not fit to existing one).
>
> Best regards,
> Krzysztof
>

2024-03-14 08:36:29