Hi everyone,
Here's a (pretty long) series to introduce support in the VC4 DRM driver
for the display pipeline found in the BCM2711 (and thus the RaspberryPi 4).
The main differences are that there's two HDMI controllers and that there's
more pixelvalve now. Those pixelvalve come with a mux in the HVS that still
have only 3 FIFOs. Both of those differences are breaking a bunch of
expectations in the driver, so we first need a good bunch of cleanup and
reworks to introduce support for the new controllers.
Similarly, the HDMI controller has all its registers shuffled and split in
multiple controllers now, so we need a bunch of changes to support this as
well.
Only the HDMI support is enabled for now (even though the DPI output has
been tested too). There's a couple of rough edges still that should be
addressed in the next versions:
- After a modeset, it's likely that the pixels will be shifted by one.
- Dual output doesn't work
- The transposer (and thus writeback) doesn't work either and conflicts
with the output mux too.
Let me know if you have any comments
Maxime
Cc: [email protected]
Cc: [email protected]
Cc: Kamal Dasu <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: Michael Turquette <[email protected]>
Cc: Philipp Zabel <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Wolfram Sang <[email protected]>
Changes from v1:
- Rebased on top of 5.7-rc1
- Run checkpatch
- Added audio support
- Fixed some HDMI timeouts
- Swiched to clk_hw_register_gate_parent_data
- Reorder Kconfig symbols in drivers/i2c/busses
- Make the firmware clocks a child of the firmware node
- Switch DVP clock driver to clk_hw interface
- constify raspberrypi_clk_data in raspberrypi_clock_property
- Don't mark firmware clocks as IGNORE_UNUSED
- Change from reset_ms to reset_us in reset-simple, and add a bit more
comments
- Remove generic clk patch to test if a NULL pointer is returned
- Removed misleading message in the is_prepared renaming patch commit
message
- Constify HDMI controller variants
- Fix a bug in the allocation size of the clk data array
- Added a mention in the DT binding conversion patches about the breakage
- Merged a few fixes from kbuild
- Fixed a few bisection and CEC build issues
- Collected Acked-by and Reviewed-by
- Change Dave email address to raspberrypi.com
Dave Stevenson (6):
drm/vc4: Add support for the BCM2711 HVS5
drm/vc4: plane: Improve LBM usage
drm/vc4: hdmi: Use reg-names to retrieve the HDMI audio registers
drm/vc4: hdmi: Reset audio infoframe on encoder_enable if previously streaming
drm/vc4: hdmi: Set the b-frame marker to the match ALSA's default.
drm/vc4: hdmi: Add audio-related callbacks
Florian Fainelli (1):
dt-bindings: arm: bcm: Convert BCM2835 firmware binding to YAML
Maxime Ripard (84):
i2c: brcmstb: Allow to compile it on BCM2835
dt-bindings: clock: Add a binding for the RPi Firmware clocks
firmware: rpi: Only create clocks device if we don't have a node for it
clk: bcm: rpi: Allow the driver to be probed by DT
clk: bcm: rpi: Statically init clk_init_data
clk: bcm: rpi: Use clk_hw_register for pllb_arm
clk: bcm: rpi: Remove global pllb_arm clock pointer
clk: bcm: rpi: Make sure pllb_arm is removed
clk: bcm: rpi: Remove pllb_arm_lookup global pointer
clk: bcm: rpi: Switch to clk_hw_register_clkdev
clk: bcm: rpi: Make sure the clkdev lookup is removed
clk: bcm: rpi: Create a data structure for the clocks
clk: bcm: rpi: Add clock id to data
clk: bcm: rpi: Pass the clocks data to the firmware function
clk: bcm: rpi: Rename is_prepared function
clk: bcm: rpi: Split pllb clock hooks
clk: bcm: rpi: Make the PLLB registration function return a clk_hw
clk: bcm: rpi: Add DT provider for the clocks
clk: bcm: rpi: Discover the firmware clocks
ARM: dts: bcm2711: Add firmware clocks node
reset: Move reset-simple header out of drivers/reset
reset: simple: Add reset callback
dt-bindings: clock: Add BCM2711 DVP binding
clk: bcm: Add BCM2711 DVP driver
ARM: dts: bcm2711: Add HDMI DVP
dt-bindings: display: Convert VC4 bindings to schemas
dt-bindings: display: vc4: dpi: Add missing clock-names property
dt-bindings: display: vc4: dsi: Add missing clock properties
dt-bindings: display: vc4: hdmi: Add missing clock-names property
dt-bindings: display: vc4: Document BCM2711 VC5
drm/vc4: drv: Add include guards
drm/vc4: drv: Support BCM2711
dt-bindings: display: Add support for the BCM2711 HVS
drm/vc4: hvs: Boost the core clock during modeset
drm/vc4: plane: Move planes creation to its own function
drm/vc4: plane: Move additional planes creation to driver
drm/vc4: plane: Register all the planes at once
drm/vc4: plane: Create overlays for any CRTC
drm/vc4: plane: Create more planes
drm/vc4: crtc: Rename SoC data structures
drm/vc4: crtc: Move crtc state to common header
drm/vc4: crtc: Deal with different number of pixel per clock
drm/vc4: crtc: Use a shared interrupt
drm/vc4: crtc: Turn static const variable into a define
drm/vc4: crtc: Move the cob allocation outside of bind
drm/vc4: crtc: Rename HVS channel to output
drm/vc4: crtc: Use local chan variable
drm/vc4: crtc: Enable and disable the PV in atomic_enable / disable
drm/vc4: crtc: Assign output to channel automatically
drm/vc4: crtc: Add FIFO depth to vc4_crtc_data
drm/vc4: crtc: Add function to compute FIFO level bits
drm/vc4: crtc: Rename HDMI encoder type to HDMI0
drm/vc4: crtc: Add HDMI1 encoder type
drm/vc4: crtc: Remove redundant call to drm_crtc_enable_color_mgmt
drm/vc4: crtc: Disable color management for HVS5
dt-bindings: display: vc4: pv: Add BCM2711 pixel valves
drm/vc4: crtc: Add BCM2711 pixelvalves
drm/vc4: hdmi: Use debugfs private field
drm/vc4: hdmi: Move structure to header
drm/vc4: hdmi: rework connectors and encoders
drm/vc4: hdmi: Remove DDC argument to connector_init
drm/vc4: hdmi: Rename hdmi to vc4_hdmi
drm/vc4: hdmi: Move accessors to vc4_hdmi
drm/vc4: hdmi: Use local vc4_hdmi directly
drm/vc4: hdmi: Add container_of macros for encoders and connectors
drm/vc4: hdmi: Pass vc4_hdmi to CEC code
drm/vc4: hdmi: Remove vc4_dev hdmi pointer
drm/vc4: hdmi: Remove vc4_hdmi_connector
drm/vc4: hdmi: Introduce resource init and variant
drm/vc4: hdmi: Implement a register layout abstraction
drm/vc4: hdmi: Add reset callback
drm/vc4: hdmi: Add PHY init and disable function
drm/vc4: hdmi: Add PHY RNG enable / disable function
drm/vc4: hdmi: Add a CSC setup callback
drm/vc4: hdmi: Store the encoder type in the variant structure
drm/vc4: hdmi: Deal with multiple debugfs files
drm/vc4: hdmi: Move CEC init to its own function
drm/vc4: hdmi: Add CEC support flag
drm/vc4: hdmi: Remove unused CEC_CLOCK_DIV define
drm/vc4: hdmi: Rename drm_encoder pointer in mode_valid
drm/vc4: hdmi: Adjust HSM clock rate depending on pixel rate
drm/vc4: hdmi: Support the BCM2711 HDMI controllers
dt-bindings: display: vc4: hdmi: Add BCM2711 HDMI controllers bindings
ARM: dts: bcm2711: Enable the display pipeline
Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.txt | 14 +-
Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml | 59 +++-
Documentation/devicetree/bindings/clock/brcm,bcm2711-dvp.yaml | 47 ++-
Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt | 174 +--------
Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml | 109 +++++-
Documentation/devicetree/bindings/display/brcm,bcm2835-dpi.yaml | 72 +++-
Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml | 84 ++++-
Documentation/devicetree/bindings/display/brcm,bcm2835-hdmi.yaml | 80 ++++-
Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yaml | 53 ++-
Documentation/devicetree/bindings/display/brcm,bcm2835-pixelvalve0.yaml | 45 ++-
Documentation/devicetree/bindings/display/brcm,bcm2835-txp.yaml | 37 ++-
Documentation/devicetree/bindings/display/brcm,bcm2835-v3d.yaml | 42 ++-
Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml | 35 ++-
Documentation/devicetree/bindings/display/brcm,bcm2835-vec.yaml | 44 ++-
MAINTAINERS | 2 +-
arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 51 ++-
arch/arm/boot/dts/bcm2711.dtsi | 130 +++++-
drivers/clk/bcm/Kconfig | 1 +-
drivers/clk/bcm/Makefile | 1 +-
drivers/clk/bcm/clk-bcm2711-dvp.c | 127 ++++++-
drivers/clk/bcm/clk-raspberrypi.c | 280 +++++++++----
drivers/firmware/raspberrypi.c | 17 +-
drivers/gpu/drm/vc4/Makefile | 1 +-
drivers/gpu/drm/vc4/vc4_crtc.c | 328 +++++++++------
drivers/gpu/drm/vc4/vc4_drv.c | 5 +-
drivers/gpu/drm/vc4/vc4_drv.h | 58 ++-
drivers/gpu/drm/vc4/vc4_hdmi.c | 1536 ++++++++++++++++++++++++++++++++++++++++++------------------------------
drivers/gpu/drm/vc4/vc4_hdmi.h | 179 ++++++++-
drivers/gpu/drm/vc4/vc4_hdmi_phy.c | 508 ++++++++++++++++++++++++-
drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 451 +++++++++++++++++++++-
drivers/gpu/drm/vc4/vc4_hvs.c | 25 +-
drivers/gpu/drm/vc4/vc4_kms.c | 181 +++++++-
drivers/gpu/drm/vc4/vc4_plane.c | 271 +++++++++----
drivers/gpu/drm/vc4/vc4_regs.h | 173 +++-----
drivers/i2c/busses/Kconfig | 4 +-
drivers/reset/reset-simple.c | 27 +-
drivers/reset/reset-simple.h | 41 +--
drivers/reset/reset-socfpga.c | 3 +-
drivers/reset/reset-sunxi.c | 3 +-
drivers/reset/reset-uniphier-glue.c | 3 +-
include/linux/reset/reset-simple.h | 47 ++-
include/soc/bcm2835/raspberrypi-firmware.h | 5 +-
42 files changed, 4109 insertions(+), 1244 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.txt
create mode 100644 Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml
create mode 100644 Documentation/devicetree/bindings/clock/brcm,bcm2711-dvp.yaml
delete mode 100644 Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt
create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml
create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-dpi.yaml
create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml
create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-hdmi.yaml
create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yaml
create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-pixelvalve0.yaml
create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-txp.yaml
create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-v3d.yaml
create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml
create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-vec.yaml
create mode 100644 drivers/clk/bcm/clk-bcm2711-dvp.c
create mode 100644 drivers/gpu/drm/vc4/vc4_hdmi.h
create mode 100644 drivers/gpu/drm/vc4/vc4_hdmi_phy.c
create mode 100644 drivers/gpu/drm/vc4/vc4_hdmi_regs.h
delete mode 100644 drivers/reset/reset-simple.h
create mode 100644 include/linux/reset/reset-simple.h
base-commit: cb3692197b5da2fb898335eec1640db14d92e52e
--
git-series 0.9.1
For the upcoming registration of the clocks provided by the firmware, make
sure it's exposed to the device tree providers.
Cc: Michael Turquette <[email protected]>
Cc: [email protected]
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
---
drivers/clk/bcm/clk-raspberrypi.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/clk/bcm/clk-raspberrypi.c b/drivers/clk/bcm/clk-raspberrypi.c
index 677d7f3e8d2e..1a9027169a2a 100644
--- a/drivers/clk/bcm/clk-raspberrypi.c
+++ b/drivers/clk/bcm/clk-raspberrypi.c
@@ -31,6 +31,8 @@
#define A2W_PLL_FRAC_BITS 20
+#define NUM_FW_CLKS 16
+
struct raspberrypi_clk {
struct device *dev;
struct rpi_firmware *firmware;
@@ -285,11 +287,13 @@ static struct clk_hw *raspberrypi_register_pllb_arm(struct raspberrypi_clk *rpi)
static int raspberrypi_clk_probe(struct platform_device *pdev)
{
+ struct clk_hw_onecell_data *clk_data;
struct device_node *firmware_node;
struct device *dev = &pdev->dev;
struct rpi_firmware *firmware;
struct raspberrypi_clk *rpi;
struct clk_hw *hw;
+ int ret;
/*
* We can be probed either through the an old-fashioned
@@ -318,6 +322,11 @@ static int raspberrypi_clk_probe(struct platform_device *pdev)
rpi->firmware = firmware;
platform_set_drvdata(pdev, rpi);
+ clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, NUM_FW_CLKS),
+ GFP_KERNEL);
+ if (!clk_data)
+ return -ENOMEM;
+
hw = raspberrypi_register_pllb(rpi);
if (IS_ERR(hw)) {
dev_err(dev, "Failed to initialize pllb, %ld\n", PTR_ERR(hw));
@@ -327,6 +336,13 @@ static int raspberrypi_clk_probe(struct platform_device *pdev)
hw = raspberrypi_register_pllb_arm(rpi);
if (IS_ERR(hw))
return PTR_ERR(hw);
+ clk_data->hws[RPI_FIRMWARE_ARM_CLK_ID] = hw;
+ clk_data->num = RPI_FIRMWARE_ARM_CLK_ID + 1;
+
+ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
+ clk_data);
+ if (ret)
+ return ret;
rpi->cpufreq = platform_device_register_data(dev, "raspberrypi-cpufreq",
-1, NULL, 0);
--
git-series 0.9.1
The pllb_arm clock was created at probe time, but was never removed if
something went wrong later in probe, or if the driver was ever removed from
the system.
Now that we are using clk_hw_register, we can just use its managed variant
to take care of that for us.
Cc: Michael Turquette <[email protected]>
Cc: [email protected]
Acked-by: Nicolas Saenz Julienne <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
---
drivers/clk/bcm/clk-raspberrypi.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/clk/bcm/clk-raspberrypi.c b/drivers/clk/bcm/clk-raspberrypi.c
index a99e8189311f..859eac020122 100644
--- a/drivers/clk/bcm/clk-raspberrypi.c
+++ b/drivers/clk/bcm/clk-raspberrypi.c
@@ -240,7 +240,7 @@ static int raspberrypi_register_pllb_arm(struct raspberrypi_clk *rpi)
{
int ret;
- ret = clk_hw_register(rpi->dev, &raspberrypi_clk_pllb_arm.hw);
+ ret = devm_clk_hw_register(rpi->dev, &raspberrypi_clk_pllb_arm.hw);
if (ret) {
dev_err(rpi->dev, "Failed to initialize pllb_arm\n");
return ret;
@@ -250,7 +250,6 @@ static int raspberrypi_register_pllb_arm(struct raspberrypi_clk *rpi)
NULL, "cpu0");
if (!rpi->pllb_arm_lookup) {
dev_err(rpi->dev, "Failed to initialize pllb_arm_lookup\n");
- clk_hw_unregister_fixed_factor(&raspberrypi_clk_pllb_arm.hw);
return -ENOMEM;
}
--
git-series 0.9.1
While the device tree and the driver expected a clock-names property, it
wasn't explicitly documented in the previous binding. Make sure it is now.
Cc: [email protected]
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
---
Documentation/devicetree/bindings/display/brcm,bcm2835-dpi.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/brcm,bcm2835-dpi.yaml b/Documentation/devicetree/bindings/display/brcm,bcm2835-dpi.yaml
index 288494b70e82..58213c564e03 100644
--- a/Documentation/devicetree/bindings/display/brcm,bcm2835-dpi.yaml
+++ b/Documentation/devicetree/bindings/display/brcm,bcm2835-dpi.yaml
@@ -21,6 +21,11 @@ properties:
- description: The core clock the unit runs on
- description: The pixel clock that feeds the pixelvalve
+ clock-names:
+ items:
+ - const: core
+ - const: pixel
+
port:
type: object
description: >
@@ -31,6 +36,7 @@ required:
- compatible
- reg
- clocks
+ - clock-names
- port
additionalProperties: false
--
git-series 0.9.1
The BCM2711, supported by ARCH_BCM2835, also has a controller by the
brcmstb driver so let's allow it to be compiled on that platform.
Cc: Kamal Dasu <[email protected]>
Cc: Wolfram Sang <[email protected]>
Cc: [email protected]
Cc: [email protected]
Acked-by: Florian Fainelli <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
---
drivers/i2c/busses/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 2ddca08f8a76..6644e0faa3df 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -475,8 +475,8 @@ config I2C_BCM_KONA
config I2C_BRCMSTB
tristate "BRCM Settop/DSL I2C controller"
- depends on ARCH_BRCMSTB || BMIPS_GENERIC || ARCH_BCM_63XX || \
- COMPILE_TEST
+ depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC || \
+ ARCH_BCM_63XX || COMPILE_TEST
default y
help
If you say yes to this option, support will be included for the
--
git-series 0.9.1
From: Florian Fainelli <[email protected]>
Convert the Raspberry Pi BCM2835 firmware binding document to YAML.
Verified with dt_binding_check and dtbs_check.
Signed-off-by: Florian Fainelli <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
---
Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.txt | 14 --------------
Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml | 35 +++++++++++++++++++++++++++++++++++
2 files changed, 35 insertions(+), 14 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.txt
create mode 100644 Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml
diff --git a/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.txt b/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.txt
deleted file mode 100644
index 6824b3180ffb..000000000000
--- a/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-Raspberry Pi VideoCore firmware driver
-
-Required properties:
-
-- compatible: Should be "raspberrypi,bcm2835-firmware"
-- mboxes: Phandle to the firmware device's Mailbox.
- (See: ../mailbox/mailbox.txt for more information)
-
-Example:
-
-firmware {
- compatible = "raspberrypi,bcm2835-firmware";
- mboxes = <&mailbox>;
-};
diff --git a/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml b/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml
new file mode 100644
index 000000000000..cec540c052b6
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/bcm/raspberrypi,bcm2835-firmware.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Raspberry Pi VideoCore firmware driver
+
+maintainers:
+ - Eric Anholt <[email protected]>
+ - Stefan Wahren <[email protected]>
+
+properties:
+ compatible:
+ items:
+ - const: raspberrypi,bcm2835-firmware
+ - const: simple-bus
+
+ mboxes:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: |
+ Phandle to the firmware device's Mailbox.
+ (See: ../mailbox/mailbox.txt for more information)
+
+required:
+ - compatible
+ - mboxes
+
+examples:
+ - |
+ firmware {
+ compatible = "raspberrypi,bcm2835-firmware", "simple-bus";
+ mboxes = <&mailbox>;
+ };
+...
--
git-series 0.9.1
Instead of declaring the clk_init_data and then calling memset on it, just
initialise properly.
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Acked-by: Nicolas Saenz Julienne <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
---
drivers/clk/bcm/clk-raspberrypi.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/clk/bcm/clk-raspberrypi.c b/drivers/clk/bcm/clk-raspberrypi.c
index aedeaaf2f66b..b6d2823c2882 100644
--- a/drivers/clk/bcm/clk-raspberrypi.c
+++ b/drivers/clk/bcm/clk-raspberrypi.c
@@ -175,11 +175,10 @@ static const struct clk_ops raspberrypi_firmware_pll_clk_ops = {
static int raspberrypi_register_pllb(struct raspberrypi_clk *rpi)
{
+ struct clk_init_data init = {};
u32 min_rate = 0, max_rate = 0;
- struct clk_init_data init;
int ret;
- memset(&init, 0, sizeof(init));
/* All of the PLLs derive from the external oscillator. */
init.parent_names = (const char *[]){ "osc" };
--
git-series 0.9.1
The HVS found in the BCM2711 has 6 outputs and 3 FIFOs, with each output
being connected to a pixelvalve, and some muxing between the FIFOs and
outputs.
Any output cannot feed from any FIFO though, and they all have a bunch of
constraints.
In order to support this, let's store the possible FIFOs each output can be
assigned to in the vc4_crtc_data, and use that information at atomic_check
time to iterate over all the CRTCs enabled and assign them FIFOs.
The channel assigned is then set in the vc4_crtc_state so that the rest of
the driver can use it.
Signed-off-by: Maxime Ripard <[email protected]>
---
drivers/gpu/drm/vc4/vc4_crtc.c | 37 +++++----
drivers/gpu/drm/vc4/vc4_drv.h | 7 +-
drivers/gpu/drm/vc4/vc4_kms.c | 142 ++++++++++++++++++++++++++++++++--
drivers/gpu/drm/vc4/vc4_regs.h | 10 ++-
4 files changed, 172 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 00e6ecf5a6d4..ea55d4ca2766 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -91,6 +91,7 @@ static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc,
struct drm_device *dev = crtc->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+ struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
unsigned int cob_size;
u32 val;
int fifo_lines;
@@ -107,7 +108,7 @@ static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc,
* Read vertical scanline which is currently composed for our
* pixelvalve by the HVS, and also the scaler status.
*/
- val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
+ val = HVS_READ(SCALER_DISPSTATX(vc4_crtc_state->assigned_channel));
/* Get optional system timestamp after query. */
if (etime)
@@ -127,7 +128,7 @@ static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc,
*hpos += mode->crtc_htotal / 2;
}
- cob_size = vc4_crtc_get_cob_allocation(vc4_crtc, vc4_crtc->channel);
+ cob_size = vc4_crtc_get_cob_allocation(vc4_crtc, vc4_crtc_state->assigned_channel);
/* This is the offset we need for translating hvs -> pv scanout pos. */
fifo_lines = cob_size / mode->crtc_hdisplay;
@@ -214,6 +215,7 @@ vc4_crtc_lut_load(struct drm_crtc *crtc)
struct drm_device *dev = crtc->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+ struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
u32 i;
/* The LUT memory is laid out with each HVS channel in order,
@@ -222,7 +224,7 @@ vc4_crtc_lut_load(struct drm_crtc *crtc)
*/
HVS_WRITE(SCALER_GAMADDR,
SCALER_GAMADDR_AUTOINC |
- (vc4_crtc->channel * 3 * crtc->gamma_size));
+ (vc4_crtc_state->assigned_channel * 3 * crtc->gamma_size));
for (i = 0; i < crtc->gamma_size; i++)
HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
@@ -394,7 +396,7 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
drm_print_regset32(&p, &vc4_crtc->regset);
}
- if (vc4_crtc->channel == 2) {
+ if (vc4_crtc->data->hvs_output == 2) {
u32 dispctrl;
u32 dsp3_mux;
@@ -421,7 +423,7 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
if (!vc4_state->feed_txp)
vc4_crtc_config_pv(crtc);
- HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
+ HVS_WRITE(SCALER_DISPBKGNDX(vc4_state->assigned_channel),
SCALER_DISPBKGND_AUTOHS |
SCALER_DISPBKGND_GAMMA |
(interlace ? SCALER_DISPBKGND_INTERLACE : 0));
@@ -453,7 +455,8 @@ static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
struct drm_device *dev = crtc->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
- u32 chan = vc4_crtc->channel;
+ struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(old_state);
+ u32 chan = vc4_crtc_state->assigned_channel;
int ret;
require_hvs_enabled(dev);
@@ -532,12 +535,12 @@ static void vc4_crtc_update_dlist(struct drm_crtc *crtc)
crtc->state->event = NULL;
}
- HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
+ HVS_WRITE(SCALER_DISPLISTX(vc4_state->assigned_channel),
vc4_state->mm.start);
spin_unlock_irqrestore(&dev->event_lock, flags);
} else {
- HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
+ HVS_WRITE(SCALER_DISPLISTX(vc4_state->assigned_channel),
vc4_state->mm.start);
}
}
@@ -586,7 +589,7 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
(vc4_state->feed_txp ?
SCALER5_DISPCTRLX_ONESHOT : 0);
- HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel), dispctrl);
+ HVS_WRITE(SCALER_DISPCTRLX(vc4_state->assigned_channel), dispctrl);
/* When feeding the transposer block the pixelvalve is unneeded and
* should not be enabled.
@@ -702,7 +705,6 @@ static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
{
struct drm_device *dev = crtc->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
- struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
struct drm_plane *plane;
struct vc4_plane_state *vc4_plane_state;
@@ -744,8 +746,8 @@ static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
/* This sets a black background color fill, as is the case
* with other DRM drivers.
*/
- HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
- HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel)) |
+ HVS_WRITE(SCALER_DISPBKGNDX(vc4_state->assigned_channel),
+ HVS_READ(SCALER_DISPBKGNDX(vc4_state->assigned_channel)) |
SCALER_DISPBKGND_FILL);
/* Only update DISPLIST if the CRTC was already running and is not
@@ -759,7 +761,7 @@ static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
vc4_crtc_update_dlist(crtc);
if (crtc->state->color_mgmt_changed) {
- u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel));
+ u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(vc4_state->assigned_channel));
if (crtc->state->gamma_lut) {
vc4_crtc_update_gamma_lut(crtc);
@@ -771,7 +773,7 @@ static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
*/
dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
}
- HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel), dispbkgndx);
+ HVS_WRITE(SCALER_DISPBKGNDX(vc4_state->assigned_channel), dispbkgndx);
}
if (debug_dump_regs) {
@@ -802,7 +804,7 @@ static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
struct drm_device *dev = crtc->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
- u32 chan = vc4_crtc->channel;
+ u32 chan = vc4_state->assigned_channel;
unsigned long flags;
spin_lock_irqsave(&dev->event_lock, flags);
@@ -1001,6 +1003,7 @@ static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
old_vc4_state = to_vc4_crtc_state(crtc->state);
vc4_state->feed_txp = old_vc4_state->feed_txp;
vc4_state->margins = old_vc4_state->margins;
+ vc4_state->assigned_channel = old_vc4_state->assigned_channel;
__drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
return &vc4_state->base;
@@ -1062,6 +1065,7 @@ static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
};
static const struct vc4_crtc_data bcm2835_pv0_data = {
+ .hvs_available_channels = BIT(0),
.hvs_output = 0,
.debugfs_name = "crtc0_regs",
.pixels_per_clock = 1,
@@ -1072,6 +1076,7 @@ static const struct vc4_crtc_data bcm2835_pv0_data = {
};
static const struct vc4_crtc_data bcm2835_pv1_data = {
+ .hvs_available_channels = BIT(2),
.hvs_output = 2,
.debugfs_name = "crtc1_regs",
.pixels_per_clock = 1,
@@ -1082,6 +1087,7 @@ static const struct vc4_crtc_data bcm2835_pv1_data = {
};
static const struct vc4_crtc_data bcm2835_pv2_data = {
+ .hvs_available_channels = BIT(1),
.hvs_output = 1,
.debugfs_name = "crtc2_regs",
.pixels_per_clock = 1,
@@ -1173,7 +1179,6 @@ static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
&vc4_crtc_funcs, NULL);
drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
- vc4_crtc->channel = vc4_crtc->data->hvs_output;
drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 6fe36a38a8b3..6468c6df20b6 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -450,6 +450,9 @@ to_vc4_encoder(struct drm_encoder *encoder)
}
struct vc4_crtc_data {
+ /* Which channels of the HVS can the output source from */
+ unsigned int hvs_available_channels;
+
/* Which output of the HVS this pixelvalve sources from. */
int hvs_output;
@@ -469,9 +472,6 @@ struct vc4_crtc {
/* Timestamp at start of vblank irq - unaffected by lock delays. */
ktime_t t_vblank;
- /* Which HVS channel we're using for our CRTC. */
- int channel;
-
u8 lut_r[256];
u8 lut_g[256];
u8 lut_b[256];
@@ -493,6 +493,7 @@ struct vc4_crtc_state {
struct drm_mm_node mm;
bool feed_txp;
bool txp_armed;
+ unsigned int assigned_channel;
struct {
unsigned int left;
diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index 851f0740b260..06afffe1c22b 100644
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -11,6 +11,8 @@
* crtc, HDMI encoder).
*/
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
#include <linux/clk.h>
#include <drm/drm_atomic.h>
@@ -146,6 +148,72 @@ vc4_ctm_commit(struct vc4_dev *vc4, struct drm_atomic_state *state)
VC4_SET_FIELD(ctm_state->fifo, SCALER_OLEDOFFS_DISPFIFO));
}
+static void vc4_hvs_pv_muxing_commit(struct vc4_dev *vc4,
+ struct drm_atomic_state *state)
+{
+ struct drm_crtc_state *crtc_state;
+ struct drm_crtc *crtc;
+ unsigned char dsp2_mux = 0;
+ unsigned char dsp3_mux = 3;
+ unsigned char dsp4_mux = 3;
+ unsigned char dsp5_mux = 3;
+ unsigned int i;
+ u32 reg;
+
+ for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
+ struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
+ struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+
+ if (!crtc_state->active)
+ continue;
+
+ switch (vc4_crtc->data->hvs_output) {
+ case 2:
+ dsp2_mux = (vc4_state->assigned_channel == 2) ? 1 : 0;
+ break;
+
+ case 3:
+ dsp3_mux = vc4_state->assigned_channel;
+ break;
+
+ case 4:
+ dsp4_mux = vc4_state->assigned_channel;
+ break;
+
+ case 5:
+ dsp5_mux = vc4_state->assigned_channel;
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ reg = HVS_READ(SCALER_DISPECTRL);
+ if (FIELD_GET(SCALER_DISPECTRL_DSP2_MUX_MASK, reg) != dsp2_mux)
+ HVS_WRITE(SCALER_DISPECTRL,
+ (reg & ~SCALER_DISPECTRL_DSP2_MUX_MASK) |
+ VC4_SET_FIELD(dsp2_mux, SCALER_DISPECTRL_DSP2_MUX));
+
+ reg = HVS_READ(SCALER_DISPCTRL);
+ if (FIELD_GET(SCALER_DISPCTRL_DSP3_MUX_MASK, reg) != dsp3_mux)
+ HVS_WRITE(SCALER_DISPCTRL,
+ (reg & ~SCALER_DISPCTRL_DSP3_MUX_MASK) |
+ VC4_SET_FIELD(dsp3_mux, SCALER_DISPCTRL_DSP3_MUX));
+
+ reg = HVS_READ(SCALER_DISPEOLN);
+ if (FIELD_GET(SCALER_DISPEOLN_DSP4_MUX_MASK, reg) != dsp4_mux)
+ HVS_WRITE(SCALER_DISPEOLN,
+ (reg & ~SCALER_DISPEOLN_DSP4_MUX_MASK) |
+ VC4_SET_FIELD(dsp4_mux, SCALER_DISPEOLN_DSP4_MUX));
+
+ reg = HVS_READ(SCALER_DISPDITHER);
+ if (FIELD_GET(SCALER_DISPDITHER_DSP5_MUX_MASK, reg) != dsp5_mux)
+ HVS_WRITE(SCALER_DISPDITHER,
+ (reg & ~SCALER_DISPDITHER_DSP5_MUX_MASK) |
+ VC4_SET_FIELD(dsp5_mux, SCALER_DISPDITHER_DSP5_MUX));
+}
+
static void
vc4_atomic_complete_commit(struct drm_atomic_state *state)
{
@@ -156,11 +224,15 @@ vc4_atomic_complete_commit(struct drm_atomic_state *state)
int i;
for (i = 0; i < dev->mode_config.num_crtc; i++) {
- if (!state->crtcs[i].ptr || !state->crtcs[i].commit)
+ struct __drm_crtcs_state *_state = &state->crtcs[i];
+ struct vc4_crtc_state *vc4_crtc_state;
+
+ if (!_state->ptr || !_state->commit)
continue;
- vc4_crtc = to_vc4_crtc(state->crtcs[i].ptr);
- vc4_hvs_mask_underrun(dev, vc4_crtc->channel);
+ vc4_crtc = to_vc4_crtc(_state->ptr);
+ vc4_crtc_state = to_vc4_crtc_state(_state->state);
+ vc4_hvs_mask_underrun(dev, vc4_crtc_state->assigned_channel);
}
clk_set_rate(hvs->core_clk, 500000000);
@@ -172,6 +244,7 @@ vc4_atomic_complete_commit(struct drm_atomic_state *state)
drm_atomic_helper_commit_modeset_disables(dev, state);
vc4_ctm_commit(vc4, state);
+ vc4_hvs_pv_muxing_commit(vc4, state);
drm_atomic_helper_commit_planes(dev, state, 0);
@@ -381,8 +454,11 @@ vc4_ctm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
/* CTM is being enabled or the matrix changed. */
if (new_crtc_state->ctm) {
+ struct vc4_crtc_state *vc4_crtc_state =
+ to_vc4_crtc_state(new_crtc_state);
+
/* fifo is 1-based since 0 disables CTM. */
- int fifo = to_vc4_crtc(crtc)->channel + 1;
+ int fifo = vc4_crtc_state->assigned_channel + 1;
/* Check userland isn't trying to turn on CTM for more
* than one CRTC at a time.
@@ -495,10 +571,66 @@ static const struct drm_private_state_funcs vc4_load_tracker_state_funcs = {
.atomic_destroy_state = vc4_load_tracker_destroy_state,
};
+#define NUM_OUTPUTS 6
+#define NUM_CHANNELS 3
+
static int
vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
{
- int ret;
+ unsigned long unassigned_channels = GENMASK(NUM_CHANNELS - 1, 0);
+ struct drm_crtc_state *crtc_state;
+ struct drm_crtc *crtc;
+ int i, ret;
+
+ for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
+ struct vc4_crtc_state *vc4_crtc_state =
+ to_vc4_crtc_state(crtc_state);
+ struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+ bool is_assigned = false;
+ unsigned int channel;
+
+ if (!crtc_state->active)
+ continue;
+
+ /*
+ * The problem we have to solve here is that we have
+ * up to 7 encoders, connected to up to 6 CRTCs.
+ *
+ * Those CRTCs, depending on the instance, can be
+ * routed to 1, 2 or 3 HVS FIFOs, and we need to set
+ * the change the muxing between FIFOs and outputs in
+ * the HVS accordingly.
+ *
+ * It would be pretty hard to come up with an
+ * algorithm that would generically solve
+ * this. However, the current routing trees we support
+ * allow us to simplify a bit the problem.
+ *
+ * Indeed, with the current supported layouts, if we
+ * try to assign in the ascending crtc index order the
+ * FIFOs, we can't fall into the situation where an
+ * earlier CRTC that had multiple routes is assigned
+ * one that was the only option for a later CRTC.
+ *
+ * If the layout changes and doesn't give us that in
+ * the future, we will need to have something smarter,
+ * but it works so far.
+ */
+ for_each_set_bit(channel, &unassigned_channels,
+ sizeof(unassigned_channels)) {
+
+ if (!(BIT(channel) & vc4_crtc->data->hvs_available_channels))
+ continue;
+
+ vc4_crtc_state->assigned_channel = channel;
+ unassigned_channels &= ~BIT(channel);
+ is_assigned = true;
+ break;
+ }
+
+ if (!is_assigned)
+ return -EINVAL;
+ }
ret = vc4_ctm_atomic_check(dev, state);
if (ret < 0)
diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index 8a51baf681fe..b96ebbb1354b 100644
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -287,9 +287,19 @@
#define SCALER_DISPID 0x00000008
#define SCALER_DISPECTRL 0x0000000c
+# define SCALER_DISPECTRL_DSP2_MUX_SHIFT 31
+# define SCALER_DISPECTRL_DSP2_MUX_MASK VC4_MASK(31, 31)
+
#define SCALER_DISPPROF 0x00000010
+
#define SCALER_DISPDITHER 0x00000014
+# define SCALER_DISPDITHER_DSP5_MUX_SHIFT 30
+# define SCALER_DISPDITHER_DSP5_MUX_MASK VC4_MASK(31, 30)
+
#define SCALER_DISPEOLN 0x00000018
+# define SCALER_DISPEOLN_DSP4_MUX_SHIFT 30
+# define SCALER_DISPEOLN_DSP4_MUX_MASK VC4_MASK(31, 30)
+
#define SCALER_DISPLIST0 0x00000020
#define SCALER_DISPLIST1 0x00000024
#define SCALER_DISPLIST2 0x00000028
--
git-series 0.9.1
Similarly to the previous patches, the CSC setup is slightly different in
the BCM2711 than in the previous generations. Let's add a callback for it.
Signed-off-by: Maxime Ripard <[email protected]>
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 142 +++++++++++++++++++---------------
drivers/gpu/drm/vc4/vc4_hdmi.h | 7 ++-
2 files changed, 89 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 189c88d3b06e..b3a98a17f8f8 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -336,12 +336,44 @@ static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
DRM_ERROR("Failed to release power domain: %d\n", ret);
}
-static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
+static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
+{
+ u32 csc_ctl;
+
+ csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
+ VC4_HD_CSC_CTL_ORDER);
+
+ if (enable) {
+ /* CEA VICs other than #1 requre limited range RGB
+ * output unless overridden by an AVI infoframe.
+ * Apply a colorspace conversion to squash 0-255 down
+ * to 16-235. The matrix here is:
+ *
+ * [ 0 0 0.8594 16]
+ * [ 0 0.8594 0 16]
+ * [ 0.8594 0 0 16]
+ * [ 0 0 0 1]
+ */
+ csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
+ csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
+ csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
+ VC4_HD_CSC_CTL_MODE);
+
+ HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
+ HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
+ HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
+ HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
+ HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
+ HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
+ }
+
+ /* The RGB order applies even when CSC is disabled. */
+ HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
+}
+
+static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
+ struct drm_display_mode *mode)
{
- struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
- struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
- struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
- bool debug_dump_regs = false;
bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
@@ -359,7 +391,41 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
mode->crtc_vsync_end -
interlaced,
VC4_HDMI_VERTB_VBP));
- u32 csc_ctl;
+
+ HDMI_WRITE(HDMI_HORZA,
+ (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
+ (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
+ VC4_SET_FIELD(mode->hdisplay * pixel_rep,
+ VC4_HDMI_HORZA_HAP));
+
+ HDMI_WRITE(HDMI_HORZB,
+ VC4_SET_FIELD((mode->htotal -
+ mode->hsync_end) * pixel_rep,
+ VC4_HDMI_HORZB_HBP) |
+ VC4_SET_FIELD((mode->hsync_end -
+ mode->hsync_start) * pixel_rep,
+ VC4_HDMI_HORZB_HSP) |
+ VC4_SET_FIELD((mode->hsync_start -
+ mode->hdisplay) * pixel_rep,
+ VC4_HDMI_HORZB_HFP));
+
+ HDMI_WRITE(HDMI_VERTA0, verta);
+ HDMI_WRITE(HDMI_VERTA1, verta);
+
+ HDMI_WRITE(HDMI_VERTB0, vertb_even);
+ HDMI_WRITE(HDMI_VERTB1, vertb);
+
+ HDMI_WRITE(HDMI_VID_CTL,
+ (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
+ (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
+}
+
+static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
+{
+ struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
+ struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
+ struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
+ bool debug_dump_regs = false;
int ret;
ret = pm_runtime_get_sync(&vc4_hdmi->pdev->dev);
@@ -403,68 +469,22 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
- HDMI_WRITE(HDMI_HORZA,
- (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
- (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
- VC4_SET_FIELD(mode->hdisplay * pixel_rep,
- VC4_HDMI_HORZA_HAP));
-
- HDMI_WRITE(HDMI_HORZB,
- VC4_SET_FIELD((mode->htotal -
- mode->hsync_end) * pixel_rep,
- VC4_HDMI_HORZB_HBP) |
- VC4_SET_FIELD((mode->hsync_end -
- mode->hsync_start) * pixel_rep,
- VC4_HDMI_HORZB_HSP) |
- VC4_SET_FIELD((mode->hsync_start -
- mode->hdisplay) * pixel_rep,
- VC4_HDMI_HORZB_HFP));
-
- HDMI_WRITE(HDMI_VERTA0, verta);
- HDMI_WRITE(HDMI_VERTA1, verta);
-
- HDMI_WRITE(HDMI_VERTB0, vertb_even);
- HDMI_WRITE(HDMI_VERTB1, vertb);
-
- HDMI_WRITE(HDMI_VID_CTL,
- (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
- (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
-
- csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
- VC4_HD_CSC_CTL_ORDER);
+ if (vc4_hdmi->variant->set_timings)
+ vc4_hdmi->variant->set_timings(vc4_hdmi, mode);
if (vc4_encoder->hdmi_monitor &&
- drm_default_rgb_quant_range(mode) ==
- HDMI_QUANTIZATION_RANGE_LIMITED) {
- /* CEA VICs other than #1 requre limited range RGB
- * output unless overridden by an AVI infoframe.
- * Apply a colorspace conversion to squash 0-255 down
- * to 16-235. The matrix here is:
- *
- * [ 0 0 0.8594 16]
- * [ 0 0.8594 0 16]
- * [ 0.8594 0 0 16]
- * [ 0 0 0 1]
- */
- csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
- csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
- csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
- VC4_HD_CSC_CTL_MODE);
+ drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) {
+ if (vc4_hdmi->variant->csc_setup)
+ vc4_hdmi->variant->csc_setup(vc4_hdmi, true);
- HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
- HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
- HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
- HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
- HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
- HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
vc4_encoder->limited_rgb_range = true;
} else {
+ if (vc4_hdmi->variant->csc_setup)
+ vc4_hdmi->variant->csc_setup(vc4_hdmi, false);
+
vc4_encoder->limited_rgb_range = false;
}
- /* The RGB order applies even when CSC is disabled. */
- HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
-
HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
if (debug_dump_regs) {
@@ -1423,7 +1443,9 @@ static const struct vc4_hdmi_variant bcm2835_variant = {
.num_registers = ARRAY_SIZE(vc4_hdmi_fields),
.init_resources = vc4_hdmi_init_resources,
+ .csc_setup = vc4_hdmi_csc_setup,
.reset = vc4_hdmi_reset,
+ .set_timings = vc4_hdmi_set_timings,
.phy_init = vc4_hdmi_phy_init,
.phy_disable = vc4_hdmi_phy_disable,
.phy_rng_enable = vc4_hdmi_phy_rng_enable,
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h
index 9ae4d2c5a4f0..4a67d62aef53 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
@@ -41,6 +41,13 @@ struct vc4_hdmi_variant {
/* Callback to reset the HDMI block */
void (*reset)(struct vc4_hdmi *vc4_hdmi);
+ /* Callback to enable / disable the CSC */
+ void (*csc_setup)(struct vc4_hdmi *vc4_hdmi, bool enable);
+
+ /* Callback to configure the video timings in the HDMI block */
+ void (*set_timings)(struct vc4_hdmi *vc4_hdmi,
+ struct drm_display_mode *mode);
+
/* Callback to initialize the PHY according to the mode */
void (*phy_init)(struct vc4_hdmi *vc4_hdmi,
struct drm_display_mode *mode);
--
git-series 0.9.1
We will need to share the vc4_hdmi and related structures with multiple
files, so let's create a header for it.
Signed-off-by: Maxime Ripard <[email protected]>
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 76 +-------------------------------
drivers/gpu/drm/vc4/vc4_hdmi.h | 86 +++++++++++++++++++++++++++++++++++-
2 files changed, 87 insertions(+), 75 deletions(-)
create mode 100644 drivers/gpu/drm/vc4/vc4_hdmi.h
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index a9e32ad7b0ab..4b21292072e4 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -48,87 +48,13 @@
#include <sound/soc.h>
#include "media/cec.h"
#include "vc4_drv.h"
+#include "vc4_hdmi.h"
#include "vc4_regs.h"
#define HSM_CLOCK_FREQ 163682864
#define CEC_CLOCK_FREQ 40000
#define CEC_CLOCK_DIV (HSM_CLOCK_FREQ / CEC_CLOCK_FREQ)
-/* HDMI audio information */
-struct vc4_hdmi_audio {
- struct snd_soc_card card;
- struct snd_soc_dai_link link;
- struct snd_soc_dai_link_component cpu;
- struct snd_soc_dai_link_component codec;
- struct snd_soc_dai_link_component platform;
- int samplerate;
- int channels;
- struct snd_dmaengine_dai_dma_data dma_data;
- struct snd_pcm_substream *substream;
-};
-
-/* General HDMI hardware state. */
-struct vc4_hdmi {
- struct platform_device *pdev;
-
- struct drm_encoder *encoder;
- struct drm_connector *connector;
-
- struct vc4_hdmi_audio audio;
-
- struct i2c_adapter *ddc;
- void __iomem *hdmicore_regs;
- void __iomem *hd_regs;
- int hpd_gpio;
- bool hpd_active_low;
-
- struct cec_adapter *cec_adap;
- struct cec_msg cec_rx_msg;
- bool cec_tx_ok;
- bool cec_irq_was_rx;
-
- struct clk *pixel_clock;
- struct clk *hsm_clock;
-
- struct debugfs_regset32 hdmi_regset;
- struct debugfs_regset32 hd_regset;
-};
-
-#define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset)
-#define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset)
-#define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset)
-#define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset)
-
-/* VC4 HDMI encoder KMS struct */
-struct vc4_hdmi_encoder {
- struct vc4_encoder base;
- bool hdmi_monitor;
- bool limited_rgb_range;
-};
-
-static inline struct vc4_hdmi_encoder *
-to_vc4_hdmi_encoder(struct drm_encoder *encoder)
-{
- return container_of(encoder, struct vc4_hdmi_encoder, base.base);
-}
-
-/* VC4 HDMI connector KMS struct */
-struct vc4_hdmi_connector {
- struct drm_connector base;
-
- /* Since the connector is attached to just the one encoder,
- * this is the reference to it so we can do the best_encoder()
- * hook.
- */
- struct drm_encoder *encoder;
-};
-
-static inline struct vc4_hdmi_connector *
-to_vc4_hdmi_connector(struct drm_connector *connector)
-{
- return container_of(connector, struct vc4_hdmi_connector, base);
-}
-
static const struct debugfs_reg32 hdmi_regs[] = {
VC4_REG32(VC4_HDMI_CORE_REV),
VC4_REG32(VC4_HDMI_SW_RESET_CONTROL),
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h
new file mode 100644
index 000000000000..5ec5d1f6b1e6
--- /dev/null
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
@@ -0,0 +1,86 @@
+#ifndef _VC4_HDMI_H_
+#define _VC4_HDMI_H_
+
+#include <drm/drm_connector.h>
+#include <media/cec.h>
+#include <sound/dmaengine_pcm.h>
+#include <sound/soc.h>
+
+#include "vc4_drv.h"
+
+/* HDMI audio information */
+struct vc4_hdmi_audio {
+ struct snd_soc_card card;
+ struct snd_soc_dai_link link;
+ struct snd_soc_dai_link_component cpu;
+ struct snd_soc_dai_link_component codec;
+ struct snd_soc_dai_link_component platform;
+ int samplerate;
+ int channels;
+ struct snd_dmaengine_dai_dma_data dma_data;
+ struct snd_pcm_substream *substream;
+};
+
+/* General HDMI hardware state. */
+struct vc4_hdmi {
+ struct platform_device *pdev;
+
+ struct drm_encoder *encoder;
+ struct drm_connector *connector;
+
+ struct vc4_hdmi_audio audio;
+
+ struct i2c_adapter *ddc;
+ void __iomem *hdmicore_regs;
+ void __iomem *hd_regs;
+ int hpd_gpio;
+ bool hpd_active_low;
+
+ struct cec_adapter *cec_adap;
+ struct cec_msg cec_rx_msg;
+ bool cec_tx_ok;
+ bool cec_irq_was_rx;
+
+ struct clk *pixel_clock;
+ struct clk *hsm_clock;
+
+ struct debugfs_regset32 hdmi_regset;
+ struct debugfs_regset32 hd_regset;
+};
+
+#define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset)
+#define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset)
+#define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset)
+#define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset)
+
+/* VC4 HDMI encoder KMS struct */
+struct vc4_hdmi_encoder {
+ struct vc4_encoder base;
+ bool hdmi_monitor;
+ bool limited_rgb_range;
+};
+
+static inline struct vc4_hdmi_encoder *
+to_vc4_hdmi_encoder(struct drm_encoder *encoder)
+{
+ return container_of(encoder, struct vc4_hdmi_encoder, base.base);
+}
+
+/* VC4 HDMI connector KMS struct */
+struct vc4_hdmi_connector {
+ struct drm_connector base;
+
+ /* Since the connector is attached to just the one encoder,
+ * this is the reference to it so we can do the best_encoder()
+ * hook.
+ */
+ struct drm_encoder *encoder;
+};
+
+static inline struct vc4_hdmi_connector *
+to_vc4_hdmi_connector(struct drm_connector *connector)
+{
+ return container_of(connector, struct vc4_hdmi_connector, base);
+}
+
+#endif /* _VC4_HDMI_H_ */
--
git-series 0.9.1
Now that we don't have any users anymore, we can kill that pointer.
Signed-off-by: Maxime Ripard <[email protected]>
---
drivers/gpu/drm/vc4/vc4_drv.h | 1 -
drivers/gpu/drm/vc4/vc4_hdmi.c | 14 ++++++--------
2 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 39b0d5ee1eba..d70421aab2d0 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -73,7 +73,6 @@ struct vc4_perfmon {
struct vc4_dev {
struct drm_device *dev;
- struct vc4_hdmi *hdmi;
struct vc4_hvs *hvs;
struct vc4_v3d *v3d;
struct vc4_dpi *dpi;
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index c3f97e833555..93c9ed7c16cf 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -1196,7 +1196,6 @@ static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
#endif
struct platform_device *pdev = to_platform_device(dev);
struct drm_device *drm = dev_get_drvdata(master);
- struct vc4_dev *vc4 = drm->dev_private;
struct vc4_hdmi *vc4_hdmi;
struct drm_encoder *encoder;
struct device_node *ddc_node;
@@ -1284,8 +1283,6 @@ static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
vc4_hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
}
- vc4->hdmi = vc4_hdmi;
-
/* HDMI core must be enabled. */
if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) {
HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST);
@@ -1366,9 +1363,12 @@ static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
static void vc4_hdmi_unbind(struct device *dev, struct device *master,
void *data)
{
- struct drm_device *drm = dev_get_drvdata(master);
- struct vc4_dev *vc4 = drm->dev_private;
- struct vc4_hdmi *vc4_hdmi = vc4->hdmi;
+ /*
+ * snd_soc_register_card will set the device drvdata pointer
+ * to the card being registered.
+ */
+ struct snd_soc_card *card = dev_get_drvdata(dev);
+ struct vc4_hdmi *vc4_hdmi = snd_soc_card_get_drvdata(card);
cec_unregister_adapter(vc4_hdmi->cec_adap);
vc4_hdmi_connector_destroy(&vc4_hdmi->connector.base);
@@ -1378,8 +1378,6 @@ static void vc4_hdmi_unbind(struct device *dev, struct device *master,
pm_runtime_disable(dev);
put_device(&vc4_hdmi->ddc->dev);
-
- vc4->hdmi = NULL;
}
static const struct component_ops vc4_hdmi_ops = {
--
git-series 0.9.1
Some of the HDMI pixelvalves in vc5 output two pixels per clock cycle.
Let's put the number of pixel output per clock cycle in the CRTC data and
update the various calculations to reflect that.
Signed-off-by: Maxime Ripard <[email protected]>
---
drivers/gpu/drm/vc4/vc4_crtc.c | 17 ++++++++++-------
drivers/gpu/drm/vc4/vc4_drv.h | 3 +++
2 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 9718df881fab..be264da1a13f 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -282,6 +282,7 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc)
bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
+ u8 ppc = vc4_crtc->data->pixels_per_clock;
/* Reset the PV fifo. */
CRTC_WRITE(PV_CONTROL, 0);
@@ -289,17 +290,16 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc)
CRTC_WRITE(PV_CONTROL, 0);
CRTC_WRITE(PV_HORZA,
- VC4_SET_FIELD((mode->htotal -
- mode->hsync_end) * pixel_rep,
+ VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,
PV_HORZA_HBP) |
- VC4_SET_FIELD((mode->hsync_end -
- mode->hsync_start) * pixel_rep,
+ VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc,
PV_HORZA_HSYNC));
+
CRTC_WRITE(PV_HORZB,
- VC4_SET_FIELD((mode->hsync_start -
- mode->hdisplay) * pixel_rep,
+ VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc,
PV_HORZB_HFP) |
- VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
+ VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc,
+ PV_HORZB_HACTIVE));
CRTC_WRITE(PV_VERTA,
VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
@@ -1040,6 +1040,7 @@ static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
static const struct vc4_crtc_data bcm2835_pv0_data = {
.hvs_channel = 0,
.debugfs_name = "crtc0_regs",
+ .pixels_per_clock = 1,
.encoder_types = {
[PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
@@ -1049,6 +1050,7 @@ static const struct vc4_crtc_data bcm2835_pv0_data = {
static const struct vc4_crtc_data bcm2835_pv1_data = {
.hvs_channel = 2,
.debugfs_name = "crtc1_regs",
+ .pixels_per_clock = 1,
.encoder_types = {
[PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
@@ -1058,6 +1060,7 @@ static const struct vc4_crtc_data bcm2835_pv1_data = {
static const struct vc4_crtc_data bcm2835_pv2_data = {
.hvs_channel = 1,
.debugfs_name = "crtc2_regs",
+ .pixels_per_clock = 1,
.encoder_types = {
[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
[PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 487ad72c284d..cda738dbd6c1 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -453,6 +453,9 @@ struct vc4_crtc_data {
/* Which channel of the HVS this pixelvalve sources from. */
int hvs_channel;
+ /* Number of pixels output per clock period */
+ u8 pixels_per_clock;
+
enum vc4_encoder_type encoder_types[4];
const char *debugfs_name;
};
--
git-series 0.9.1
From: Dave Stevenson <[email protected]>
The HVS found in the BCM2711 is slightly different from the previous
generations.
Most notably, the display list layout changes a bit, the LBM doesn't have
the same size and the formats ordering for some formats is swapped.
Signed-off-by: Dave Stevenson <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
---
drivers/gpu/drm/vc4/vc4_crtc.c | 24 +++-
drivers/gpu/drm/vc4/vc4_drv.h | 4 +-
drivers/gpu/drm/vc4/vc4_hvs.c | 16 ++-
drivers/gpu/drm/vc4/vc4_plane.c | 194 ++++++++++++++++++++++++---------
drivers/gpu/drm/vc4/vc4_regs.h | 67 +++++++++++-
5 files changed, 246 insertions(+), 59 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 1208258ad3b2..591a10ae1950 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -551,6 +551,7 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
struct drm_display_mode *mode = &crtc->state->adjusted_mode;
+ u32 dispctrl;
require_hvs_enabled(dev);
@@ -565,11 +566,24 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
* When feeding the transposer, we should operate in oneshot
* mode.
*/
- HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
- VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
- VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
- SCALER_DISPCTRLX_ENABLE |
- (vc4_state->feed_txp ? SCALER_DISPCTRLX_ONESHOT : 0));
+ dispctrl = SCALER_DISPCTRLX_ENABLE;
+
+ if (!vc4->hvs->hvs5)
+ dispctrl |= VC4_SET_FIELD(mode->hdisplay,
+ SCALER_DISPCTRLX_WIDTH) |
+ VC4_SET_FIELD(mode->vdisplay,
+ SCALER_DISPCTRLX_HEIGHT) |
+ (vc4_state->feed_txp ?
+ SCALER_DISPCTRLX_ONESHOT : 0);
+ else
+ dispctrl |= VC4_SET_FIELD(mode->hdisplay,
+ SCALER5_DISPCTRLX_WIDTH) |
+ VC4_SET_FIELD(mode->vdisplay,
+ SCALER5_DISPCTRLX_HEIGHT) |
+ (vc4_state->feed_txp ?
+ SCALER5_DISPCTRLX_ONESHOT : 0);
+
+ HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel), dispctrl);
/* When feeding the transposer block the pixelvalve is unneeded and
* should not be enabled.
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 6024de9ecd35..7da417feff5a 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -332,7 +332,11 @@ struct vc4_hvs {
spinlock_t mm_lock;
struct drm_mm_node mitchell_netravali_filter;
+
struct debugfs_regset32 regset;
+
+ /* HVS version 5 flag, therefore requires updated dlist structures */
+ bool hvs5;
};
struct vc4_plane {
diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c
index 5a43659da319..0fe4758de03a 100644
--- a/drivers/gpu/drm/vc4/vc4_hvs.c
+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
@@ -230,6 +230,9 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
hvs->pdev = pdev;
+ if (of_device_is_compatible(pdev->dev.of_node, "brcm,bcm2711-hvs"))
+ hvs->hvs5 = true;
+
hvs->regs = vc4_ioremap_regs(pdev, 0);
if (IS_ERR(hvs->regs))
return PTR_ERR(hvs->regs);
@@ -238,7 +241,10 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
hvs->regset.regs = hvs_regs;
hvs->regset.nregs = ARRAY_SIZE(hvs_regs);
- hvs->dlist = hvs->regs + SCALER_DLIST_START;
+ if (!hvs->hvs5)
+ hvs->dlist = hvs->regs + SCALER_DLIST_START;
+ else
+ hvs->dlist = hvs->regs + SCALER5_DLIST_START;
spin_lock_init(&hvs->mm_lock);
@@ -256,7 +262,12 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
* between planes when they don't overlap on the screen, but
* for now we just allocate globally.
*/
- drm_mm_init(&hvs->lbm_mm, 0, 96 * 1024);
+ if (!hvs->hvs5)
+ /* 96kB */
+ drm_mm_init(&hvs->lbm_mm, 0, 96 * 1024);
+ else
+ /* 70k words */
+ drm_mm_init(&hvs->lbm_mm, 0, 70 * 2 * 1024);
/* Upload filter kernels. We only have the one for now, so we
* keep it around for the lifetime of the driver.
@@ -341,6 +352,7 @@ static int vc4_hvs_dev_remove(struct platform_device *pdev)
}
static const struct of_device_id vc4_hvs_dt_match[] = {
+ { .compatible = "brcm,bcm2711-hvs" },
{ .compatible = "brcm,bcm2835-hvs" },
{}
};
diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index 57a73a2e2e5c..1575c05e3106 100644
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -32,45 +32,60 @@ static const struct hvs_format {
u32 drm; /* DRM_FORMAT_* */
u32 hvs; /* HVS_FORMAT_* */
u32 pixel_order;
+ u32 pixel_order_hvs5;
} hvs_formats[] = {
{
- .drm = DRM_FORMAT_XRGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
+ .drm = DRM_FORMAT_XRGB8888,
+ .hvs = HVS_PIXEL_FORMAT_RGBA8888,
.pixel_order = HVS_PIXEL_ORDER_ABGR,
+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB,
},
{
- .drm = DRM_FORMAT_ARGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
+ .drm = DRM_FORMAT_ARGB8888,
+ .hvs = HVS_PIXEL_FORMAT_RGBA8888,
.pixel_order = HVS_PIXEL_ORDER_ABGR,
+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB,
},
{
- .drm = DRM_FORMAT_ABGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
+ .drm = DRM_FORMAT_ABGR8888,
+ .hvs = HVS_PIXEL_FORMAT_RGBA8888,
.pixel_order = HVS_PIXEL_ORDER_ARGB,
+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_ABGR,
},
{
- .drm = DRM_FORMAT_XBGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
+ .drm = DRM_FORMAT_XBGR8888,
+ .hvs = HVS_PIXEL_FORMAT_RGBA8888,
.pixel_order = HVS_PIXEL_ORDER_ARGB,
+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_ABGR,
},
{
- .drm = DRM_FORMAT_RGB565, .hvs = HVS_PIXEL_FORMAT_RGB565,
+ .drm = DRM_FORMAT_RGB565,
+ .hvs = HVS_PIXEL_FORMAT_RGB565,
.pixel_order = HVS_PIXEL_ORDER_XRGB,
},
{
- .drm = DRM_FORMAT_BGR565, .hvs = HVS_PIXEL_FORMAT_RGB565,
+ .drm = DRM_FORMAT_BGR565,
+ .hvs = HVS_PIXEL_FORMAT_RGB565,
.pixel_order = HVS_PIXEL_ORDER_XBGR,
},
{
- .drm = DRM_FORMAT_ARGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
+ .drm = DRM_FORMAT_ARGB1555,
+ .hvs = HVS_PIXEL_FORMAT_RGBA5551,
.pixel_order = HVS_PIXEL_ORDER_ABGR,
},
{
- .drm = DRM_FORMAT_XRGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
+ .drm = DRM_FORMAT_XRGB1555,
+ .hvs = HVS_PIXEL_FORMAT_RGBA5551,
.pixel_order = HVS_PIXEL_ORDER_ABGR,
},
{
- .drm = DRM_FORMAT_RGB888, .hvs = HVS_PIXEL_FORMAT_RGB888,
+ .drm = DRM_FORMAT_RGB888,
+ .hvs = HVS_PIXEL_FORMAT_RGB888,
.pixel_order = HVS_PIXEL_ORDER_XRGB,
},
{
- .drm = DRM_FORMAT_BGR888, .hvs = HVS_PIXEL_FORMAT_RGB888,
+ .drm = DRM_FORMAT_BGR888,
+ .hvs = HVS_PIXEL_FORMAT_RGB888,
.pixel_order = HVS_PIXEL_ORDER_XBGR,
},
{
@@ -781,35 +796,6 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
return -EINVAL;
}
- /* Control word */
- vc4_dlist_write(vc4_state,
- SCALER_CTL0_VALID |
- (rotation & DRM_MODE_REFLECT_X ? SCALER_CTL0_HFLIP : 0) |
- (rotation & DRM_MODE_REFLECT_Y ? SCALER_CTL0_VFLIP : 0) |
- VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) |
- (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
- (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
- VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
- (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
- VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
- VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
-
- /* Position Word 0: Image Positions and Alpha Value */
- vc4_state->pos0_offset = vc4_state->dlist_count;
- vc4_dlist_write(vc4_state,
- VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) |
- VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
- VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
-
- /* Position Word 1: Scaled Image Dimensions. */
- if (!vc4_state->is_unity) {
- vc4_dlist_write(vc4_state,
- VC4_SET_FIELD(vc4_state->crtc_w,
- SCALER_POS1_SCL_WIDTH) |
- VC4_SET_FIELD(vc4_state->crtc_h,
- SCALER_POS1_SCL_HEIGHT));
- }
-
/* Don't waste cycles mixing with plane alpha if the set alpha
* is opaque or there is no per-pixel alpha information.
* In any case we use the alpha property value as the fixed alpha.
@@ -817,20 +803,120 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
mix_plane_alpha = state->alpha != DRM_BLEND_ALPHA_OPAQUE &&
fb->format->has_alpha;
- /* Position Word 2: Source Image Size, Alpha */
- vc4_state->pos2_offset = vc4_state->dlist_count;
- vc4_dlist_write(vc4_state,
- VC4_SET_FIELD(fb->format->has_alpha ?
- SCALER_POS2_ALPHA_MODE_PIPELINE :
- SCALER_POS2_ALPHA_MODE_FIXED,
- SCALER_POS2_ALPHA_MODE) |
- (mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) |
- (fb->format->has_alpha ? SCALER_POS2_ALPHA_PREMULT : 0) |
- VC4_SET_FIELD(vc4_state->src_w[0], SCALER_POS2_WIDTH) |
- VC4_SET_FIELD(vc4_state->src_h[0], SCALER_POS2_HEIGHT));
+ if (!vc4->hvs->hvs5) {
+ /* Control word */
+ vc4_dlist_write(vc4_state,
+ SCALER_CTL0_VALID |
+ (rotation & DRM_MODE_REFLECT_X ? SCALER_CTL0_HFLIP : 0) |
+ (rotation & DRM_MODE_REFLECT_Y ? SCALER_CTL0_VFLIP : 0) |
+ VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) |
+ (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
+ (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
+ VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
+ (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
+ VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
+ VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
+
+ /* Position Word 0: Image Positions and Alpha Value */
+ vc4_state->pos0_offset = vc4_state->dlist_count;
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) |
+ VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
+ VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
+
+ /* Position Word 1: Scaled Image Dimensions. */
+ if (!vc4_state->is_unity) {
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(vc4_state->crtc_w,
+ SCALER_POS1_SCL_WIDTH) |
+ VC4_SET_FIELD(vc4_state->crtc_h,
+ SCALER_POS1_SCL_HEIGHT));
+ }
+
+ /* Position Word 2: Source Image Size, Alpha */
+ vc4_state->pos2_offset = vc4_state->dlist_count;
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(fb->format->has_alpha ?
+ SCALER_POS2_ALPHA_MODE_PIPELINE :
+ SCALER_POS2_ALPHA_MODE_FIXED,
+ SCALER_POS2_ALPHA_MODE) |
+ (mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) |
+ (fb->format->has_alpha ?
+ SCALER_POS2_ALPHA_PREMULT : 0) |
+ VC4_SET_FIELD(vc4_state->src_w[0],
+ SCALER_POS2_WIDTH) |
+ VC4_SET_FIELD(vc4_state->src_h[0],
+ SCALER_POS2_HEIGHT));
+
+ /* Position Word 3: Context. Written by the HVS. */
+ vc4_dlist_write(vc4_state, 0xc0c0c0c0);
+
+ } else {
+ u32 hvs_pixel_order = format->pixel_order;
- /* Position Word 3: Context. Written by the HVS. */
- vc4_dlist_write(vc4_state, 0xc0c0c0c0);
+ if (format->pixel_order_hvs5)
+ hvs_pixel_order = format->pixel_order_hvs5;
+
+ /* Control word */
+ vc4_dlist_write(vc4_state,
+ SCALER_CTL0_VALID |
+ (hvs_pixel_order << SCALER_CTL0_ORDER_SHIFT) |
+ (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
+ VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
+ (vc4_state->is_unity ?
+ SCALER5_CTL0_UNITY : 0) |
+ VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
+ VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1) |
+ SCALER5_CTL0_ALPHA_EXPAND |
+ SCALER5_CTL0_RGB_EXPAND);
+
+ /* Position Word 0: Image Positions and Alpha Value */
+ vc4_state->pos0_offset = vc4_state->dlist_count;
+ vc4_dlist_write(vc4_state,
+ (rotation & DRM_MODE_REFLECT_Y ?
+ SCALER5_POS0_VFLIP : 0) |
+ VC4_SET_FIELD(vc4_state->crtc_x,
+ SCALER_POS0_START_X) |
+ (rotation & DRM_MODE_REFLECT_X ?
+ SCALER5_POS0_HFLIP : 0) |
+ VC4_SET_FIELD(vc4_state->crtc_y,
+ SCALER5_POS0_START_Y)
+ );
+
+ /* Control Word 2 */
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(state->alpha >> 4,
+ SCALER5_CTL2_ALPHA) |
+ fb->format->has_alpha ?
+ SCALER5_CTL2_ALPHA_PREMULT : 0 |
+ (mix_plane_alpha ?
+ SCALER5_CTL2_ALPHA_MIX : 0) |
+ VC4_SET_FIELD(fb->format->has_alpha ?
+ SCALER5_CTL2_ALPHA_MODE_PIPELINE :
+ SCALER5_CTL2_ALPHA_MODE_FIXED,
+ SCALER5_CTL2_ALPHA_MODE)
+ );
+
+ /* Position Word 1: Scaled Image Dimensions. */
+ if (!vc4_state->is_unity) {
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(vc4_state->crtc_w,
+ SCALER_POS1_SCL_WIDTH) |
+ VC4_SET_FIELD(vc4_state->crtc_h,
+ SCALER_POS1_SCL_HEIGHT));
+ }
+
+ /* Position Word 2: Source Image Size */
+ vc4_state->pos2_offset = vc4_state->dlist_count;
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(vc4_state->src_w[0],
+ SCALER5_POS2_WIDTH) |
+ VC4_SET_FIELD(vc4_state->src_h[0],
+ SCALER5_POS2_HEIGHT));
+
+ /* Position Word 3: Context. Written by the HVS. */
+ vc4_dlist_write(vc4_state, 0xc0c0c0c0);
+ }
/* Pointer Word 0/1/2: RGB / Y / Cb / Cr Pointers
@@ -1208,6 +1294,10 @@ static bool vc4_format_mod_supported(struct drm_plane *plane,
default:
return false;
}
+ case DRM_FORMAT_RGBX1010102:
+ case DRM_FORMAT_BGRX1010102:
+ case DRM_FORMAT_RGBA1010102:
+ case DRM_FORMAT_BGRA1010102:
case DRM_FORMAT_YUV422:
case DRM_FORMAT_YVU422:
case DRM_FORMAT_YUV420:
diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index b5a6b4cdd332..8a51baf681fe 100644
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -328,6 +328,20 @@
# define SCALER_DISPCTRLX_HEIGHT_MASK VC4_MASK(11, 0)
# define SCALER_DISPCTRLX_HEIGHT_SHIFT 0
+# define SCALER5_DISPCTRLX_WIDTH_MASK VC4_MASK(28, 16)
+# define SCALER5_DISPCTRLX_WIDTH_SHIFT 16
+/* Generates a single frame when VSTART is seen and stops at the last
+ * pixel read from the FIFO.
+ */
+# define SCALER5_DISPCTRLX_ONESHOT BIT(15)
+/* Processes a single context in the dlist and then task switch,
+ * instead of an entire line.
+ */
+# define SCALER5_DISPCTRLX_ONECTX_MASK VC4_MASK(14, 13)
+# define SCALER5_DISPCTRLX_ONECTX_SHIFT 13
+# define SCALER5_DISPCTRLX_HEIGHT_MASK VC4_MASK(12, 0)
+# define SCALER5_DISPCTRLX_HEIGHT_SHIFT 0
+
#define SCALER_DISPBKGND0 0x00000044
# define SCALER_DISPBKGND_AUTOHS BIT(31)
# define SCALER_DISPBKGND_INTERLACE BIT(30)
@@ -461,6 +475,8 @@
#define SCALER_DLIST_START 0x00002000
#define SCALER_DLIST_SIZE 0x00004000
+#define SCALER5_DLIST_START 0x00004000
+
#define VC4_HDMI_CORE_REV 0x000
#define VC4_HDMI_SW_RESET_CONTROL 0x004
@@ -826,6 +842,8 @@ enum hvs_pixel_format {
HVS_PIXEL_FORMAT_PALETTE = 13,
HVS_PIXEL_FORMAT_YUV444_RGB = 14,
HVS_PIXEL_FORMAT_AYUV444_RGB = 15,
+ HVS_PIXEL_FORMAT_RGBA1010102 = 16,
+ HVS_PIXEL_FORMAT_YCBCR_10BIT = 17,
};
/* Note: the LSB is the rightmost character shown. Only valid for
@@ -880,6 +898,10 @@ enum hvs_pixel_format {
#define SCALER_CTL0_RGBA_EXPAND_MSB 2
#define SCALER_CTL0_RGBA_EXPAND_ROUND 3
+#define SCALER5_CTL0_ALPHA_EXPAND BIT(12)
+
+#define SCALER5_CTL0_RGB_EXPAND BIT(11)
+
#define SCALER_CTL0_SCL1_MASK VC4_MASK(10, 8)
#define SCALER_CTL0_SCL1_SHIFT 8
@@ -897,10 +919,13 @@ enum hvs_pixel_format {
/* Set to indicate no scaling. */
#define SCALER_CTL0_UNITY BIT(4)
+#define SCALER5_CTL0_UNITY BIT(15)
#define SCALER_CTL0_PIXEL_FORMAT_MASK VC4_MASK(3, 0)
#define SCALER_CTL0_PIXEL_FORMAT_SHIFT 0
+#define SCALER5_CTL0_PIXEL_FORMAT_MASK VC4_MASK(4, 0)
+
#define SCALER_POS0_FIXED_ALPHA_MASK VC4_MASK(31, 24)
#define SCALER_POS0_FIXED_ALPHA_SHIFT 24
@@ -910,12 +935,48 @@ enum hvs_pixel_format {
#define SCALER_POS0_START_X_MASK VC4_MASK(11, 0)
#define SCALER_POS0_START_X_SHIFT 0
+#define SCALER5_POS0_START_Y_MASK VC4_MASK(27, 16)
+#define SCALER5_POS0_START_Y_SHIFT 16
+
+#define SCALER5_POS0_START_X_MASK VC4_MASK(13, 0)
+#define SCALER5_POS0_START_X_SHIFT 0
+
+#define SCALER5_POS0_VFLIP BIT(31)
+#define SCALER5_POS0_HFLIP BIT(15)
+
+#define SCALER5_CTL2_ALPHA_MODE_MASK VC4_MASK(31, 30)
+#define SCALER5_CTL2_ALPHA_MODE_SHIFT 30
+#define SCALER5_CTL2_ALPHA_MODE_PIPELINE 0
+#define SCALER5_CTL2_ALPHA_MODE_FIXED 1
+#define SCALER5_CTL2_ALPHA_MODE_FIXED_NONZERO 2
+#define SCALER5_CTL2_ALPHA_MODE_FIXED_OVER_0x07 3
+
+#define SCALER5_CTL2_ALPHA_PREMULT BIT(29)
+
+#define SCALER5_CTL2_ALPHA_MIX BIT(28)
+
+#define SCALER5_CTL2_ALPHA_LOC BIT(25)
+
+#define SCALER5_CTL2_MAP_SEL_MASK VC4_MASK(18, 17)
+#define SCALER5_CTL2_MAP_SEL_SHIFT 17
+
+#define SCALER5_CTL2_GAMMA BIT(16)
+
+#define SCALER5_CTL2_ALPHA_MASK VC4_MASK(15, 4)
+#define SCALER5_CTL2_ALPHA_SHIFT 4
+
#define SCALER_POS1_SCL_HEIGHT_MASK VC4_MASK(27, 16)
#define SCALER_POS1_SCL_HEIGHT_SHIFT 16
#define SCALER_POS1_SCL_WIDTH_MASK VC4_MASK(11, 0)
#define SCALER_POS1_SCL_WIDTH_SHIFT 0
+#define SCALER5_POS1_SCL_HEIGHT_MASK VC4_MASK(28, 16)
+#define SCALER5_POS1_SCL_HEIGHT_SHIFT 16
+
+#define SCALER5_POS1_SCL_WIDTH_MASK VC4_MASK(12, 0)
+#define SCALER5_POS1_SCL_WIDTH_SHIFT 0
+
#define SCALER_POS2_ALPHA_MODE_MASK VC4_MASK(31, 30)
#define SCALER_POS2_ALPHA_MODE_SHIFT 30
#define SCALER_POS2_ALPHA_MODE_PIPELINE 0
@@ -931,6 +992,12 @@ enum hvs_pixel_format {
#define SCALER_POS2_WIDTH_MASK VC4_MASK(11, 0)
#define SCALER_POS2_WIDTH_SHIFT 0
+#define SCALER5_POS2_HEIGHT_MASK VC4_MASK(28, 16)
+#define SCALER5_POS2_HEIGHT_SHIFT 16
+
+#define SCALER5_POS2_WIDTH_MASK VC4_MASK(12, 0)
+#define SCALER5_POS2_WIDTH_SHIFT 0
+
/* Color Space Conversion words. Some values are S2.8 signed
* integers, except that the 2 integer bits map as {0x0: 0, 0x1: 1,
* 0x2: 2, 0x3: -1}
--
git-series 0.9.1
The BCM2711 has a reworked display pipeline, and the load tracker needs
some adjustement to operate properly. Let's add a compatible for BCM2711
and disable the load tracker until properly supported.
Signed-off-by: Maxime Ripard <[email protected]>
---
drivers/gpu/drm/vc4/vc4_drv.c | 1 +
drivers/gpu/drm/vc4/vc4_drv.h | 3 +++
drivers/gpu/drm/vc4/vc4_kms.c | 32 +++++++++++++++++++++-----------
drivers/gpu/drm/vc4/vc4_plane.c | 5 +++++
4 files changed, 30 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c
index 76f93b662766..d7f554a6f0ed 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.c
+++ b/drivers/gpu/drm/vc4/vc4_drv.c
@@ -364,6 +364,7 @@ static int vc4_platform_drm_remove(struct platform_device *pdev)
}
static const struct of_device_id vc4_of_match[] = {
+ { .compatible = "brcm,bcm2711-vc5", },
{ .compatible = "brcm,bcm2835-vc4", },
{ .compatible = "brcm,cygnus-vc4", },
{},
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index e7748f8e2967..6024de9ecd35 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -201,6 +201,9 @@ struct vc4_dev {
int power_refcount;
+ /* Set to true when the load tracker is supported. */
+ bool load_tracker_available;
+
/* Set to true when the load tracker is active. */
bool load_tracker_enabled;
diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index 78d4fb0499e3..71e7211a5fb9 100644
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -415,6 +415,9 @@ static int vc4_load_tracker_atomic_check(struct drm_atomic_state *state)
struct drm_plane *plane;
int i;
+ if (!vc4->load_tracker_available)
+ return 0;
+
priv_state = drm_atomic_get_private_obj_state(state,
&vc4->load_tracker);
if (IS_ERR(priv_state))
@@ -514,10 +517,14 @@ int vc4_kms_load(struct drm_device *dev)
struct vc4_load_tracker_state *load_state;
int ret;
- /* Start with the load tracker enabled. Can be disabled through the
- * debugfs load_tracker file.
- */
- vc4->load_tracker_enabled = true;
+ if (!of_device_is_compatible(dev->dev->of_node, "brcm,bcm2711-vc5")) {
+ vc4->load_tracker_available = true;
+
+ /* Start with the load tracker enabled. Can be
+ * disabled through the debugfs load_tracker file.
+ */
+ vc4->load_tracker_enabled = true;
+ }
sema_init(&vc4->async_modeset, 1);
@@ -547,14 +554,17 @@ int vc4_kms_load(struct drm_device *dev)
drm_atomic_private_obj_init(dev, &vc4->ctm_manager, &ctm_state->base,
&vc4_ctm_state_funcs);
- load_state = kzalloc(sizeof(*load_state), GFP_KERNEL);
- if (!load_state) {
- drm_atomic_private_obj_fini(&vc4->ctm_manager);
- return -ENOMEM;
- }
+ if (vc4->load_tracker_available) {
+ load_state = kzalloc(sizeof(*load_state), GFP_KERNEL);
+ if (!load_state) {
+ drm_atomic_private_obj_fini(&vc4->ctm_manager);
+ return -ENOMEM;
+ }
- drm_atomic_private_obj_init(dev, &vc4->load_tracker, &load_state->base,
- &vc4_load_tracker_state_funcs);
+ drm_atomic_private_obj_init(dev, &vc4->load_tracker,
+ &load_state->base,
+ &vc4_load_tracker_state_funcs);
+ }
drm_mode_config_reset(dev);
diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index 91e408f7a56e..57a73a2e2e5c 100644
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -492,6 +492,11 @@ static void vc4_plane_calc_load(struct drm_plane_state *state)
struct vc4_plane_state *vc4_state;
struct drm_crtc_state *crtc_state;
unsigned int vscale_factor;
+ struct vc4_dev *vc4;
+
+ vc4 = to_vc4_dev(state->plane->dev);
+ if (!vc4->load_tracker_available)
+ return;
vc4_state = to_vc4_plane_state(state);
crtc_state = drm_atomic_get_existing_crtc_state(state->state,
--
git-series 0.9.1
We'll need to access the crtc_state from outside of vc4_crtc.c, so let's
move it to vc4_drv.h
Signed-off-by: Maxime Ripard <[email protected]>
---
drivers/gpu/drm/vc4/vc4_crtc.c | 21 ---------------------
drivers/gpu/drm/vc4/vc4_drv.h | 21 +++++++++++++++++++++
2 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 9fdb0ccc4a28..9718df881fab 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -44,27 +44,6 @@
#include "vc4_drv.h"
#include "vc4_regs.h"
-struct vc4_crtc_state {
- struct drm_crtc_state base;
- /* Dlist area for this CRTC configuration. */
- struct drm_mm_node mm;
- bool feed_txp;
- bool txp_armed;
-
- struct {
- unsigned int left;
- unsigned int right;
- unsigned int top;
- unsigned int bottom;
- } margins;
-};
-
-static inline struct vc4_crtc_state *
-to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
-{
- return (struct vc4_crtc_state *)crtc_state;
-}
-
#define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
#define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 25466aa9dceb..487ad72c284d 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -486,6 +486,27 @@ to_vc4_crtc(struct drm_crtc *crtc)
return (struct vc4_crtc *)crtc;
}
+struct vc4_crtc_state {
+ struct drm_crtc_state base;
+ /* Dlist area for this CRTC configuration. */
+ struct drm_mm_node mm;
+ bool feed_txp;
+ bool txp_armed;
+
+ struct {
+ unsigned int left;
+ unsigned int right;
+ unsigned int top;
+ unsigned int bottom;
+ } margins;
+};
+
+static inline struct vc4_crtc_state *
+to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
+{
+ return (struct vc4_crtc_state *)crtc_state;
+}
+
#define V3D_READ(offset) readl(vc4->v3d->regs + offset)
#define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
#define HVS_READ(offset) readl(vc4->hvs->regs + offset)
--
git-series 0.9.1
Now that we have a driver for the DVP, let's add its DT node.
Signed-off-by: Maxime Ripard <[email protected]>
---
arch/arm/boot/dts/bcm2711.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi
index a91cf68e3c4c..00bcaed1be32 100644
--- a/arch/arm/boot/dts/bcm2711.dtsi
+++ b/arch/arm/boot/dts/bcm2711.dtsi
@@ -12,6 +12,13 @@
interrupt-parent = <&gicv2>;
+ clk_108MHz: clk-108M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <108000000>;
+ clock-output-names = "108MHz-clock";
+ };
+
soc {
/*
* Defined ranges:
@@ -244,6 +251,14 @@
hvs@7e400000 {
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ dvp: clock@7ef00000 {
+ compatible = "brcm,brcm2711-dvp";
+ reg = <0x7ef00000 0x10>;
+ clocks = <&clk_108MHz>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
};
/*
--
git-series 0.9.1
While the device tree and the driver expected a clock-names and a
clock-cells properties, it wasn't explicitly documented in the previous
binding. Make sure it is now.
Cc: [email protected]
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
---
Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml | 11 +++++++-
1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml b/Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml
index 3887675f844e..3c643b227a70 100644
--- a/Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml
+++ b/Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml
@@ -10,6 +10,9 @@ maintainers:
- Eric Anholt <[email protected]>
properties:
+ "#clock-cells":
+ const: 1
+
compatible:
enum:
- brcm,bcm2835-dsi0
@@ -24,6 +27,12 @@ properties:
- description: The DSI ESC clock
- description: The DSI pixel clock
+ clock-names:
+ items:
+ - const: phy
+ - const: escape
+ - const: pixel
+
clock-output-names: true
# FIXME: The meta-schemas don't seem to allow it for now
# items:
@@ -35,9 +44,11 @@ properties:
maxItems: 1
required:
+ - "#clock-cells"
- compatible
- reg
- clocks
+ - clock-names
- clock-output-names
- interrupts
--
git-series 0.9.1
The BCM2711 comes with a new VideoCore. Add a compatible for it.
Cc: [email protected]
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
---
Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml b/Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml
index 0dcf0c397375..49a5e041aa49 100644
--- a/Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml
+++ b/Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml
@@ -17,6 +17,7 @@ description: >
properties:
compatible:
enum:
+ - brcm,bcm2711-vc5
- brcm,bcm2835-vc4
- brcm,cygnus-vc4
--
git-series 0.9.1
The HDMI block has a block that controls clocks and reset signals to the
HDMI0 and HDMI1 controllers.
Let's expose that through a clock driver implementing a clock and reset
provider.
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Maxime Ripard <[email protected]>
---
drivers/clk/bcm/Kconfig | 1 +-
drivers/clk/bcm/Makefile | 1 +-
drivers/clk/bcm/clk-bcm2711-dvp.c | 127 +++++++++++++++++++++++++++++++-
3 files changed, 129 insertions(+)
create mode 100644 drivers/clk/bcm/clk-bcm2711-dvp.c
diff --git a/drivers/clk/bcm/Kconfig b/drivers/clk/bcm/Kconfig
index 8c83977a7dc4..03bbd8040451 100644
--- a/drivers/clk/bcm/Kconfig
+++ b/drivers/clk/bcm/Kconfig
@@ -4,6 +4,7 @@ config CLK_BCM2835
depends on ARCH_BCM2835 || ARCH_BRCMSTB || COMPILE_TEST
depends on COMMON_CLK
default ARCH_BCM2835 || ARCH_BRCMSTB
+ select RESET_SIMPLE
help
Enable common clock framework support for Broadcom BCM2835
SoCs.
diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile
index 0070ddf6cdd2..2c1349062147 100644
--- a/drivers/clk/bcm/Makefile
+++ b/drivers/clk/bcm/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o
obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-asiu.o
+obj-$(CONFIG_CLK_BCM2835) += clk-bcm2711-dvp.o
obj-$(CONFIG_CLK_BCM2835) += clk-bcm2835.o
obj-$(CONFIG_CLK_BCM2835) += clk-bcm2835-aux.o
obj-$(CONFIG_CLK_RASPBERRYPI) += clk-raspberrypi.o
diff --git a/drivers/clk/bcm/clk-bcm2711-dvp.c b/drivers/clk/bcm/clk-bcm2711-dvp.c
new file mode 100644
index 000000000000..c1c4b5857d32
--- /dev/null
+++ b/drivers/clk/bcm/clk-bcm2711-dvp.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright 2020 Cerno
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/reset/reset-simple.h>
+
+#define DVP_HT_RPI_SW_INIT 0x04
+#define DVP_HT_RPI_MISC_CONFIG 0x08
+
+#define NR_CLOCKS 2
+#define NR_RESETS 6
+
+struct clk_dvp {
+ struct clk_hw_onecell_data *data;
+ struct reset_simple_data reset;
+};
+
+static const struct clk_parent_data clk_dvp_parent = {
+ .index = 0,
+};
+
+static int clk_dvp_probe(struct platform_device *pdev)
+{
+ struct clk_hw_onecell_data *data;
+ struct resource *res;
+ struct clk_dvp *dvp;
+ void __iomem *base;
+ int ret;
+
+ dvp = devm_kzalloc(&pdev->dev, sizeof(*dvp), GFP_KERNEL);
+ if (!dvp)
+ return -ENOMEM;
+ platform_set_drvdata(pdev, dvp);
+
+ dvp->data = devm_kzalloc(&pdev->dev,
+ struct_size(dvp->data, hws, NR_CLOCKS),
+ GFP_KERNEL);
+ if (!dvp->data)
+ return -ENOMEM;
+ data = dvp->data;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ dvp->reset.rcdev.owner = THIS_MODULE;
+ dvp->reset.rcdev.nr_resets = NR_RESETS;
+ dvp->reset.rcdev.ops = &reset_simple_ops;
+ dvp->reset.rcdev.of_node = pdev->dev.of_node;
+ dvp->reset.membase = base + DVP_HT_RPI_SW_INIT;
+ spin_lock_init(&dvp->reset.lock);
+
+ ret = reset_controller_register(&dvp->reset.rcdev);
+ if (ret)
+ return ret;
+
+ data->hws[0] = clk_hw_register_gate_parent_data(&pdev->dev,
+ "hdmi0-108MHz",
+ &clk_dvp_parent, 0,
+ base + DVP_HT_RPI_MISC_CONFIG, 3,
+ CLK_GATE_SET_TO_DISABLE,
+ &dvp->reset.lock);
+ if (IS_ERR(data->hws[0])) {
+ ret = PTR_ERR(data->hws[0]);
+ goto unregister_reset;
+ }
+
+ data->hws[1] = clk_hw_register_gate_parent_data(&pdev->dev,
+ "hdmi1-108MHz",
+ &clk_dvp_parent, 0,
+ base + DVP_HT_RPI_MISC_CONFIG, 4,
+ CLK_GATE_SET_TO_DISABLE,
+ &dvp->reset.lock);
+ if (IS_ERR(data->hws[1])) {
+ ret = PTR_ERR(data->hws[1]);
+ goto unregister_clk0;
+ }
+
+ data->num = NR_CLOCKS;
+ ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
+ data);
+ if (ret)
+ goto unregister_clk1;
+
+ return 0;
+
+unregister_clk1:
+ clk_hw_unregister_gate(data->hws[1]);
+
+unregister_clk0:
+ clk_hw_unregister_gate(data->hws[0]);
+
+unregister_reset:
+ reset_controller_unregister(&dvp->reset.rcdev);
+ return ret;
+};
+
+static int clk_dvp_remove(struct platform_device *pdev)
+{
+ struct clk_dvp *dvp = platform_get_drvdata(pdev);
+ struct clk_hw_onecell_data *data = dvp->data;
+
+ clk_hw_unregister_gate(data->hws[1]);
+ clk_hw_unregister_gate(data->hws[0]);
+ reset_controller_unregister(&dvp->reset.rcdev);
+
+ return 0;
+}
+
+static const struct of_device_id clk_dvp_dt_ids[] = {
+ { .compatible = "brcm,brcm2711-dvp", },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_dvp_driver = {
+ .probe = clk_dvp_probe,
+ .remove = clk_dvp_remove,
+ .driver = {
+ .name = "brcm2711-dvp",
+ .of_match_table = clk_dvp_dt_ids,
+ },
+};
+module_platform_driver(clk_dvp_driver);
--
git-series 0.9.1
The reset-simple code can be useful for drivers outside of drivers/reset
that have a few reset controls as part of their features. Let's move it to
include/linux/reset.
Cc: Philipp Zabel <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
---
drivers/reset/reset-simple.c | 3 +--
drivers/reset/reset-simple.h | 41 +------------------------------
drivers/reset/reset-socfpga.c | 3 +--
drivers/reset/reset-sunxi.c | 3 +--
drivers/reset/reset-uniphier-glue.c | 3 +--
include/linux/reset/reset-simple.h | 41 ++++++++++++++++++++++++++++++-
6 files changed, 45 insertions(+), 49 deletions(-)
delete mode 100644 drivers/reset/reset-simple.h
create mode 100644 include/linux/reset/reset-simple.h
diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c
index 067e7e7b34f1..c854aa351640 100644
--- a/drivers/reset/reset-simple.c
+++ b/drivers/reset/reset-simple.c
@@ -18,10 +18,9 @@
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
+#include <linux/reset/reset-simple.h>
#include <linux/spinlock.h>
-#include "reset-simple.h"
-
static inline struct reset_simple_data *
to_reset_simple_data(struct reset_controller_dev *rcdev)
{
diff --git a/drivers/reset/reset-simple.h b/drivers/reset/reset-simple.h
deleted file mode 100644
index 08ccb25a55e6..000000000000
--- a/drivers/reset/reset-simple.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Simple Reset Controller ops
- *
- * Based on Allwinner SoCs Reset Controller driver
- *
- * Copyright 2013 Maxime Ripard
- *
- * Maxime Ripard <[email protected]>
- */
-
-#ifndef __RESET_SIMPLE_H__
-#define __RESET_SIMPLE_H__
-
-#include <linux/io.h>
-#include <linux/reset-controller.h>
-#include <linux/spinlock.h>
-
-/**
- * struct reset_simple_data - driver data for simple reset controllers
- * @lock: spinlock to protect registers during read-modify-write cycles
- * @membase: memory mapped I/O register range
- * @rcdev: reset controller device base structure
- * @active_low: if true, bits are cleared to assert the reset. Otherwise, bits
- * are set to assert the reset. Note that this says nothing about
- * the voltage level of the actual reset line.
- * @status_active_low: if true, bits read back as cleared while the reset is
- * asserted. Otherwise, bits read back as set while the
- * reset is asserted.
- */
-struct reset_simple_data {
- spinlock_t lock;
- void __iomem *membase;
- struct reset_controller_dev rcdev;
- bool active_low;
- bool status_active_low;
-};
-
-extern const struct reset_control_ops reset_simple_ops;
-
-#endif /* __RESET_SIMPLE_H__ */
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
index 96953992c2bb..bdd984296196 100644
--- a/drivers/reset/reset-socfpga.c
+++ b/drivers/reset/reset-socfpga.c
@@ -11,13 +11,12 @@
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
+#include <linux/reset/reset-simple.h>
#include <linux/reset/socfpga.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/types.h>
-#include "reset-simple.h"
-
#define SOCFPGA_NR_BANKS 8
static int a10_reset_init(struct device_node *np)
diff --git a/drivers/reset/reset-sunxi.c b/drivers/reset/reset-sunxi.c
index e7f169e57bcf..e752594b6971 100644
--- a/drivers/reset/reset-sunxi.c
+++ b/drivers/reset/reset-sunxi.c
@@ -14,13 +14,12 @@
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
+#include <linux/reset/reset-simple.h>
#include <linux/reset/sunxi.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/types.h>
-#include "reset-simple.h"
-
static int sunxi_reset_init(struct device_node *np)
{
struct reset_simple_data *data;
diff --git a/drivers/reset/reset-uniphier-glue.c b/drivers/reset/reset-uniphier-glue.c
index 2b188b3bb69a..027990b79f61 100644
--- a/drivers/reset/reset-uniphier-glue.c
+++ b/drivers/reset/reset-uniphier-glue.c
@@ -9,8 +9,7 @@
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
-
-#include "reset-simple.h"
+#include <linux/reset/reset-simple.h>
#define MAX_CLKS 2
#define MAX_RSTS 2
diff --git a/include/linux/reset/reset-simple.h b/include/linux/reset/reset-simple.h
new file mode 100644
index 000000000000..08ccb25a55e6
--- /dev/null
+++ b/include/linux/reset/reset-simple.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Simple Reset Controller ops
+ *
+ * Based on Allwinner SoCs Reset Controller driver
+ *
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <[email protected]>
+ */
+
+#ifndef __RESET_SIMPLE_H__
+#define __RESET_SIMPLE_H__
+
+#include <linux/io.h>
+#include <linux/reset-controller.h>
+#include <linux/spinlock.h>
+
+/**
+ * struct reset_simple_data - driver data for simple reset controllers
+ * @lock: spinlock to protect registers during read-modify-write cycles
+ * @membase: memory mapped I/O register range
+ * @rcdev: reset controller device base structure
+ * @active_low: if true, bits are cleared to assert the reset. Otherwise, bits
+ * are set to assert the reset. Note that this says nothing about
+ * the voltage level of the actual reset line.
+ * @status_active_low: if true, bits read back as cleared while the reset is
+ * asserted. Otherwise, bits read back as set while the
+ * reset is asserted.
+ */
+struct reset_simple_data {
+ spinlock_t lock;
+ void __iomem *membase;
+ struct reset_controller_dev rcdev;
+ bool active_low;
+ bool status_active_low;
+};
+
+extern const struct reset_control_ops reset_simple_ops;
+
+#endif /* __RESET_SIMPLE_H__ */
--
git-series 0.9.1
So far the plane creation was done when each CRTC was bound, and those
planes were only tied to the CRTC that was registering them.
This causes two main issues:
- The planes in the vc4 hardware are actually not tied to any CRTC, but
can be used with every combination
- More importantly, so far, we allocate 10 planes per CRTC, with 3 CRTCs.
However, the next generation of hardware will have 5 CRTCs, putting us
well above the maximum of 32 planes currently allowed by DRM.
This patch is the first one in a series of patches that will take down both
of these issues so that we can support the next generation of hardware
while keeping a good amount of planes.
We start by changing the way the planes are registered to first registering
the primary planes for each CRTC in the CRTC bind function as we used to,
but moving the overlay and cursor creation to the main driver bind
function, after all the CRTCs have been bound.
This will slightly change the ID order of the planes, since the primary
planes of all CRTCs will be first, and then a pattern of 8 overlays, 1
cursor plane for each CRTC.
This shouldn't cause any trouble since the ordering between the planes is
preserved though.
Signed-off-by: Maxime Ripard <[email protected]>
---
drivers/gpu/drm/vc4/vc4_crtc.c | 4 ----
drivers/gpu/drm/vc4/vc4_drv.c | 7 +++++++
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 29c72c322c6b..2131164779dd 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -1192,10 +1192,6 @@ static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
*/
drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);
- ret = vc4_plane_create_additional_planes(drm, crtc);
- if (ret)
- goto err_destroy_planes;
-
vc4_crtc_get_cob_allocation(vc4_crtc);
CRTC_WRITE(PV_INTEN, 0);
diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c
index d7f554a6f0ed..daf07a61a7b5 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.c
+++ b/drivers/gpu/drm/vc4/vc4_drv.c
@@ -250,6 +250,7 @@ static int vc4_drm_bind(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct drm_device *drm;
+ struct drm_crtc *crtc;
struct vc4_dev *vc4;
struct device_node *node;
int ret = 0;
@@ -288,6 +289,12 @@ static int vc4_drm_bind(struct device *dev)
if (ret)
goto gem_destroy;
+ drm_for_each_crtc(crtc, drm) {
+ ret = vc4_plane_create_additional_planes(drm, crtc);
+ if (ret)
+ continue;
+ }
+
drm_fb_helper_remove_conflicting_framebuffers(NULL, "vc4drmfb", false);
ret = vc4_kms_load(drm);
--
git-series 0.9.1
The pllb_arm clock is defined as a fixed factor clock with the pllb
clock as a parent. However, all its configuration is entirely static,
and thus we don't really need to call clk_hw_register_fixed_factor() but
can simply call clk_hw_register() with a static clk_fixed_factor
structure.
Cc: Michael Turquette <[email protected]>
Cc: [email protected]
Acked-by: Nicolas Saenz Julienne <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
---
drivers/clk/bcm/clk-raspberrypi.c | 24 ++++++++++++++++++------
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/bcm/clk-raspberrypi.c b/drivers/clk/bcm/clk-raspberrypi.c
index b6d2823c2882..3e9032b9a0a6 100644
--- a/drivers/clk/bcm/clk-raspberrypi.c
+++ b/drivers/clk/bcm/clk-raspberrypi.c
@@ -225,16 +225,28 @@ static int raspberrypi_register_pllb(struct raspberrypi_clk *rpi)
return devm_clk_hw_register(rpi->dev, &rpi->pllb);
}
+static struct clk_fixed_factor raspberrypi_clk_pllb_arm = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data) {
+ .name = "pllb_arm",
+ .parent_names = (const char *[]){ "pllb" },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+ },
+};
+
static int raspberrypi_register_pllb_arm(struct raspberrypi_clk *rpi)
{
- rpi->pllb_arm = clk_hw_register_fixed_factor(rpi->dev,
- "pllb_arm", "pllb",
- CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
- 1, 2);
- if (IS_ERR(rpi->pllb_arm)) {
+ int ret;
+
+ ret = clk_hw_register(rpi->dev, &raspberrypi_clk_pllb_arm.hw);
+ if (ret) {
dev_err(rpi->dev, "Failed to initialize pllb_arm\n");
- return PTR_ERR(rpi->pllb_arm);
+ return ret;
}
+ rpi->pllb_arm = &raspberrypi_clk_pllb_arm.hw;
rpi->pllb_arm_lookup = clkdev_hw_create(rpi->pllb_arm, NULL, "cpu0");
if (!rpi->pllb_arm_lookup) {
--
git-series 0.9.1
The driver has really only supported one clock so far and has hardcoded the
ID used in communications with the firmware in all the functions
implementing the clock framework hooks. Let's store that in the clock data
structure so that we can support more clocks later on.
Cc: Michael Turquette <[email protected]>
Cc: [email protected]
Acked-by: Nicolas Saenz Julienne <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
---
drivers/clk/bcm/clk-raspberrypi.c | 16 +++++++---------
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/bcm/clk-raspberrypi.c b/drivers/clk/bcm/clk-raspberrypi.c
index 75197d8574cf..6aee81f494bb 100644
--- a/drivers/clk/bcm/clk-raspberrypi.c
+++ b/drivers/clk/bcm/clk-raspberrypi.c
@@ -39,6 +39,7 @@ struct raspberrypi_clk {
struct raspberrypi_clk_data {
struct clk_hw hw;
+ unsigned int id;
unsigned long min_rate;
unsigned long max_rate;
@@ -95,7 +96,7 @@ static int raspberrypi_fw_pll_is_on(struct clk_hw *hw)
ret = raspberrypi_clock_property(rpi->firmware,
RPI_FIRMWARE_GET_CLOCK_STATE,
- RPI_FIRMWARE_ARM_CLK_ID, &val);
+ data->id, &val);
if (ret)
return 0;
@@ -114,8 +115,7 @@ static unsigned long raspberrypi_fw_pll_get_rate(struct clk_hw *hw,
ret = raspberrypi_clock_property(rpi->firmware,
RPI_FIRMWARE_GET_CLOCK_RATE,
- RPI_FIRMWARE_ARM_CLK_ID,
- &val);
+ data->id, &val);
if (ret)
return ret;
@@ -133,8 +133,7 @@ static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate,
ret = raspberrypi_clock_property(rpi->firmware,
RPI_FIRMWARE_SET_CLOCK_RATE,
- RPI_FIRMWARE_ARM_CLK_ID,
- &new_rate);
+ data->id, &new_rate);
if (ret)
dev_err_ratelimited(rpi->dev, "Failed to change %s frequency: %d",
clk_hw_get_name(hw), ret);
@@ -189,6 +188,7 @@ static int raspberrypi_register_pllb(struct raspberrypi_clk *rpi)
if (!data)
return -ENOMEM;
data->rpi = rpi;
+ data->id = RPI_FIRMWARE_ARM_CLK_ID;
/* All of the PLLs derive from the external oscillator. */
init.parent_names = (const char *[]){ "osc" };
@@ -200,8 +200,7 @@ static int raspberrypi_register_pllb(struct raspberrypi_clk *rpi)
/* Get min & max rates set by the firmware */
ret = raspberrypi_clock_property(rpi->firmware,
RPI_FIRMWARE_GET_MIN_CLOCK_RATE,
- RPI_FIRMWARE_ARM_CLK_ID,
- &min_rate);
+ data->id, &min_rate);
if (ret) {
dev_err(rpi->dev, "Failed to get %s min freq: %d\n",
init.name, ret);
@@ -210,8 +209,7 @@ static int raspberrypi_register_pllb(struct raspberrypi_clk *rpi)
ret = raspberrypi_clock_property(rpi->firmware,
RPI_FIRMWARE_GET_MAX_CLOCK_RATE,
- RPI_FIRMWARE_ARM_CLK_ID,
- &max_rate);
+ data->id, &max_rate);
if (ret) {
dev_err(rpi->dev, "Failed to get %s max freq: %d\n",
init.name, ret);
--
git-series 0.9.1
The current firmware clock driver for the RaspberryPi can only be probed by
manually registering an associated platform_device.
While this works fine for cpufreq where the device gets attached a clkdev
lookup, it would be tedious to maintain a table of all the devices using
one of the clocks exposed by the firmware.
Since the DT on the other hand is the perfect place to store those
associations, make the firmware clocks driver probe-able through the device
tree so that we can represent it as a node.
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Signed-off-by: Maxime Ripard <[email protected]>
---
drivers/clk/bcm/clk-raspberrypi.c | 20 +++++++++++++++++---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/bcm/clk-raspberrypi.c b/drivers/clk/bcm/clk-raspberrypi.c
index 1654fd0eedc9..aedeaaf2f66b 100644
--- a/drivers/clk/bcm/clk-raspberrypi.c
+++ b/drivers/clk/bcm/clk-raspberrypi.c
@@ -255,15 +255,22 @@ static int raspberrypi_clk_probe(struct platform_device *pdev)
struct raspberrypi_clk *rpi;
int ret;
- firmware_node = of_find_compatible_node(NULL, NULL,
- "raspberrypi,bcm2835-firmware");
+ /*
+ * We can be probed either through the an old-fashioned
+ * platform device registration or through a DT node that is a
+ * child of the firmware node. Handle both cases.
+ */
+ if (dev->of_node)
+ firmware_node = of_get_parent(dev->of_node);
+ else
+ firmware_node = of_find_compatible_node(NULL, NULL,
+ "raspberrypi,bcm2835-firmware");
if (!firmware_node) {
dev_err(dev, "Missing firmware node\n");
return -ENOENT;
}
firmware = rpi_firmware_get(firmware_node);
- of_node_put(firmware_node);
if (!firmware)
return -EPROBE_DEFER;
@@ -300,9 +307,16 @@ static int raspberrypi_clk_remove(struct platform_device *pdev)
return 0;
}
+static const struct of_device_id raspberrypi_clk_match[] = {
+ { .compatible = "raspberrypi,firmware-clocks" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, raspberrypi_clk_match);
+
static struct platform_driver raspberrypi_clk_driver = {
.driver = {
.name = "raspberrypi-clk",
+ .of_match_table = raspberrypi_clk_match,
},
.probe = raspberrypi_clk_probe,
.remove = raspberrypi_clk_remove,
--
git-series 0.9.1
The raspberrypi_register_pllb has been returning an integer so far to
notify whether the functions has exited successfully or not.
However, the OF provider functions in the clock framework require access to
the clk_hw structure so that we can expose those clocks to device tree
consumers.
Since we'll want that for the future clocks, let's return a clk_hw pointer
instead of the return code.
Cc: Michael Turquette <[email protected]>
Cc: [email protected]
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
---
drivers/clk/bcm/clk-raspberrypi.c | 40 +++++++++++++++++---------------
1 file changed, 22 insertions(+), 18 deletions(-)
diff --git a/drivers/clk/bcm/clk-raspberrypi.c b/drivers/clk/bcm/clk-raspberrypi.c
index 8c88d2ea1d67..677d7f3e8d2e 100644
--- a/drivers/clk/bcm/clk-raspberrypi.c
+++ b/drivers/clk/bcm/clk-raspberrypi.c
@@ -190,7 +190,7 @@ static const struct clk_ops raspberrypi_firmware_pll_clk_ops = {
.determine_rate = raspberrypi_pll_determine_rate,
};
-static int raspberrypi_register_pllb(struct raspberrypi_clk *rpi)
+static struct clk_hw *raspberrypi_register_pllb(struct raspberrypi_clk *rpi)
{
struct raspberrypi_clk_data *data;
struct clk_init_data init = {};
@@ -199,7 +199,7 @@ static int raspberrypi_register_pllb(struct raspberrypi_clk *rpi)
data = devm_kzalloc(rpi->dev, sizeof(*data), GFP_KERNEL);
if (!data)
- return -ENOMEM;
+ return ERR_PTR(-ENOMEM);
data->rpi = rpi;
data->id = RPI_FIRMWARE_ARM_CLK_ID;
@@ -217,7 +217,7 @@ static int raspberrypi_register_pllb(struct raspberrypi_clk *rpi)
if (ret) {
dev_err(rpi->dev, "Failed to get %s min freq: %d\n",
init.name, ret);
- return ret;
+ return ERR_PTR(ret);
}
ret = raspberrypi_clock_property(rpi->firmware, data,
@@ -226,13 +226,13 @@ static int raspberrypi_register_pllb(struct raspberrypi_clk *rpi)
if (ret) {
dev_err(rpi->dev, "Failed to get %s max freq: %d\n",
init.name, ret);
- return ret;
+ return ERR_PTR(ret);
}
if (!min_rate || !max_rate) {
dev_err(rpi->dev, "Unexpected frequency range: min %u, max %u\n",
min_rate, max_rate);
- return -EINVAL;
+ return ERR_PTR(-EINVAL);
}
dev_info(rpi->dev, "CPU frequency range: min %u, max %u\n",
@@ -243,7 +243,11 @@ static int raspberrypi_register_pllb(struct raspberrypi_clk *rpi)
data->hw.init = &init;
- return devm_clk_hw_register(rpi->dev, &data->hw);
+ ret = devm_clk_hw_register(rpi->dev, &data->hw);
+ if (ret)
+ return ERR_PTR(ret);
+
+ return &data->hw;
}
static struct clk_fixed_factor raspberrypi_clk_pllb_arm = {
@@ -258,14 +262,14 @@ static struct clk_fixed_factor raspberrypi_clk_pllb_arm = {
},
};
-static int raspberrypi_register_pllb_arm(struct raspberrypi_clk *rpi)
+static struct clk_hw *raspberrypi_register_pllb_arm(struct raspberrypi_clk *rpi)
{
int ret;
ret = devm_clk_hw_register(rpi->dev, &raspberrypi_clk_pllb_arm.hw);
if (ret) {
dev_err(rpi->dev, "Failed to initialize pllb_arm\n");
- return ret;
+ return ERR_PTR(ret);
}
ret = devm_clk_hw_register_clkdev(rpi->dev,
@@ -273,10 +277,10 @@ static int raspberrypi_register_pllb_arm(struct raspberrypi_clk *rpi)
NULL, "cpu0");
if (ret) {
dev_err(rpi->dev, "Failed to initialize clkdev\n");
- return ret;
+ return ERR_PTR(ret);
}
- return 0;
+ return &raspberrypi_clk_pllb_arm.hw;
}
static int raspberrypi_clk_probe(struct platform_device *pdev)
@@ -285,7 +289,7 @@ static int raspberrypi_clk_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct rpi_firmware *firmware;
struct raspberrypi_clk *rpi;
- int ret;
+ struct clk_hw *hw;
/*
* We can be probed either through the an old-fashioned
@@ -314,15 +318,15 @@ static int raspberrypi_clk_probe(struct platform_device *pdev)
rpi->firmware = firmware;
platform_set_drvdata(pdev, rpi);
- ret = raspberrypi_register_pllb(rpi);
- if (ret) {
- dev_err(dev, "Failed to initialize pllb, %d\n", ret);
- return ret;
+ hw = raspberrypi_register_pllb(rpi);
+ if (IS_ERR(hw)) {
+ dev_err(dev, "Failed to initialize pllb, %ld\n", PTR_ERR(hw));
+ return PTR_ERR(hw);
}
- ret = raspberrypi_register_pllb_arm(rpi);
- if (ret)
- return ret;
+ hw = raspberrypi_register_pllb_arm(rpi);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
rpi->cpufreq = platform_device_register_data(dev, "raspberrypi-cpufreq",
-1, NULL, 0);
--
git-series 0.9.1
So far the driver has really only been providing a single clock, and stored
both the data associated to that clock in particular with the data
associated to the "controller".
Since we will change that in the future, let's decouple the clock data from
the provider data.
Cc: Michael Turquette <[email protected]>
Cc: [email protected]
Acked-by: Nicolas Saenz Julienne <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
---
drivers/clk/bcm/clk-raspberrypi.c | 40 ++++++++++++++++++++------------
1 file changed, 26 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/bcm/clk-raspberrypi.c b/drivers/clk/bcm/clk-raspberrypi.c
index eb5c4f5720e8..75197d8574cf 100644
--- a/drivers/clk/bcm/clk-raspberrypi.c
+++ b/drivers/clk/bcm/clk-raspberrypi.c
@@ -35,11 +35,15 @@ struct raspberrypi_clk {
struct device *dev;
struct rpi_firmware *firmware;
struct platform_device *cpufreq;
+};
+
+struct raspberrypi_clk_data {
+ struct clk_hw hw;
unsigned long min_rate;
unsigned long max_rate;
- struct clk_hw pllb;
+ struct raspberrypi_clk *rpi;
};
/*
@@ -83,8 +87,9 @@ static int raspberrypi_clock_property(struct rpi_firmware *firmware, u32 tag,
static int raspberrypi_fw_pll_is_on(struct clk_hw *hw)
{
- struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
- pllb);
+ struct raspberrypi_clk_data *data =
+ container_of(hw, struct raspberrypi_clk_data, hw);
+ struct raspberrypi_clk *rpi = data->rpi;
u32 val = 0;
int ret;
@@ -101,8 +106,9 @@ static int raspberrypi_fw_pll_is_on(struct clk_hw *hw)
static unsigned long raspberrypi_fw_pll_get_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
- struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
- pllb);
+ struct raspberrypi_clk_data *data =
+ container_of(hw, struct raspberrypi_clk_data, hw);
+ struct raspberrypi_clk *rpi = data->rpi;
u32 val = 0;
int ret;
@@ -119,8 +125,9 @@ static unsigned long raspberrypi_fw_pll_get_rate(struct clk_hw *hw,
static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
- struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
- pllb);
+ struct raspberrypi_clk_data *data =
+ container_of(hw, struct raspberrypi_clk_data, hw);
+ struct raspberrypi_clk *rpi = data->rpi;
u32 new_rate = rate / RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
int ret;
@@ -142,13 +149,13 @@ static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate,
static int raspberrypi_pll_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
- struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
- pllb);
+ struct raspberrypi_clk_data *data =
+ container_of(hw, struct raspberrypi_clk_data, hw);
u64 div, final_rate;
u32 ndiv, fdiv;
/* We can't use req->rate directly as it would overflow */
- final_rate = clamp(req->rate, rpi->min_rate, rpi->max_rate);
+ final_rate = clamp(req->rate, data->min_rate, data->max_rate);
div = (u64)final_rate << A2W_PLL_FRAC_BITS;
do_div(div, req->best_parent_rate);
@@ -173,10 +180,15 @@ static const struct clk_ops raspberrypi_firmware_pll_clk_ops = {
static int raspberrypi_register_pllb(struct raspberrypi_clk *rpi)
{
+ struct raspberrypi_clk_data *data;
struct clk_init_data init = {};
u32 min_rate = 0, max_rate = 0;
int ret;
+ data = devm_kzalloc(rpi->dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+ data->rpi = rpi;
/* All of the PLLs derive from the external oscillator. */
init.parent_names = (const char *[]){ "osc" };
@@ -215,12 +227,12 @@ static int raspberrypi_register_pllb(struct raspberrypi_clk *rpi)
dev_info(rpi->dev, "CPU frequency range: min %u, max %u\n",
min_rate, max_rate);
- rpi->min_rate = min_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
- rpi->max_rate = max_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
+ data->min_rate = min_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
+ data->max_rate = max_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
- rpi->pllb.init = &init;
+ data->hw.init = &init;
- return devm_clk_hw_register(rpi->dev, &rpi->pllb);
+ return devm_clk_hw_register(rpi->dev, &data->hw);
}
static struct clk_fixed_factor raspberrypi_clk_pllb_arm = {
--
git-series 0.9.1
On Fri, Apr 24, 2020 at 05:33:42PM +0200, Maxime Ripard wrote:
> The BCM2711, supported by ARCH_BCM2835, also has a controller by the
> brcmstb driver so let's allow it to be compiled on that platform.
>
> Cc: Kamal Dasu <[email protected]>
> Cc: Wolfram Sang <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Acked-by: Florian Fainelli <[email protected]>
> Signed-off-by: Maxime Ripard <[email protected]>
I reconsidered, and took it right away (as simple as it is). Applied to
for-next, thanks!
Hi Maxime,
Thanks for your V2 patch series! I'm testing it.
This patch series is applied upon mainline kernel 5.7-rc2 cleanly and built.
System can boot into console text mode, but no graphic UI.
Get the error in vc5_hdmi_phy_init(), and full dmesg is at [1]:
[ 5.587543] vc4_hdmi fef00700.hdmi: Unknown register ID 46
[ 5.587700] debugfs: Directory 'fef00700.hdmi' with parent 'vc4-hdmi' already present!
[ 5.588070] vc4_hdmi fef00700.hdmi: vc4-hdmi-hifi <-> fef00700.hdmi mapping ok
[ 5.588076] vc4_hdmi fef00700.hdmi: ASoC: no DMI vendor name!
[ 5.588263] vc4-drm gpu: bound fef00700.hdmi (ops vc4_hdmi_ops)
[ 5.588299] vc4_hdmi fef05700.hdmi: Unknown register ID 46
[ 5.588373] debugfs: Directory 'vc4-hdmi' with parent 'asoc' already present!
[ 5.588673] vc4_hdmi fef05700.hdmi: vc4-hdmi-hifi <-> fef05700.hdmi mapping ok
[ 5.588677] vc4_hdmi fef05700.hdmi: ASoC: no DMI vendor name!
[ 5.588809] vc4-drm gpu: bound fef05700.hdmi (ops vc4_hdmi_ops)
[ 5.588854] vc4-drm gpu: bound fe806000.vec (ops vc4_vec_ops)
[ 5.588897] vc4-drm gpu: bound fe004000.txp (ops vc4_txp_ops)
[ 5.588934] vc4-drm gpu: bound fe400000.hvs (ops vc4_hvs_ops)
[ 5.588990] vc4-drm gpu: bound fe206000.pixelvalve (ops vc4_crtc_ops)
[ 5.589030] vc4-drm gpu: bound fe207000.pixelvalve (ops vc4_crtc_ops)
[ 5.589074] vc4-drm gpu: bound fe20a000.pixelvalve (ops vc4_crtc_ops)
[ 5.589106] vc4-drm gpu: bound fe216000.pixelvalve (ops vc4_crtc_ops)
[ 5.589145] vc4-drm gpu: bound fec12000.pixelvalve (ops vc4_crtc_ops)
[ 5.589294] checking generic (3e513000 6d8c00) vs hw (0 ffffffffffffffff)
[ 5.589297] fb0: switching to vc4drmfb from simple
[ 5.589433] Console: switching to colour dummy device 80x25
[ 5.589481] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[ 5.589816] [drm] Initialized vc4 0.0.0 20140616 for gpu on minor 0
[ 5.601079] ------------[ cut here ]------------
[ 5.601095] WARNING: CPU: 2 PID: 127 at drivers/gpu/drm/vc4/vc4_hdmi_phy.c:413 vc5_hdmi_phy_init+0x7ac/0x2078
[ 5.601097] Modules linked in:
[ 5.601103] CPU: 2 PID: 127 Comm: kworker/2:1 Not tainted 5.7.0-rc2-00091-ga181df59a930 #7
[ 5.601105] Hardware name: Raspberry Pi 4 Model B (DT)
[ 5.601112] Workqueue: events deferred_probe_work_func
[ 5.601116] pstate: 20000005 (nzCv daif -PAN -UAO)
[ 5.601119] pc : vc5_hdmi_phy_init+0x7ac/0x2078
[ 5.601123] lr : vc4_hdmi_encoder_enable+0x1b8/0x1ac0
[ 5.601124] sp : ffff80001217b410
[ 5.601126] x29: ffff80001217b410 x28: ffff0000ec6370f0
[ 5.601129] x27: ffff0000f650d400 x26: 000000008a500000
[ 5.601132] x25: ffff8000113b4ac0 x24: 0000000000002060
[ 5.601135] x23: 000000000a500000 x22: 0000000000000300
[ 5.601137] x21: 0000000008d9ee20 x20: ffff0000ec535080
[ 5.601140] x19: 000000010989e7c0 x18: 0000000000000000
[ 5.601142] x17: 0000000000000001 x16: 0000000000005207
[ 5.601145] x15: 00004932ad293c92 x14: 0000000000000137
[ 5.601147] x13: ffff800010015000 x12: 0000000000000001
[ 5.601150] x11: 0000000000000001 x10: 0000000000000000
[ 5.601152] x9 : 0000000000000000 x8 : ffff800010015038
[ 5.601154] x7 : 0000000000000001 x6 : ffff80001217b368
[ 5.601157] x5 : 0000000000000000 x4 : 000000000000004c
[ 5.601159] x3 : 0000000000000000 x2 : ffff8000113b4ac0
[ 5.601162] x1 : ffff8000120c5f44 x0 : 00000000dc8984ff
[ 5.601164] Call trace:
[ 5.601169] vc5_hdmi_phy_init+0x7ac/0x2078
[ 5.601172] vc4_hdmi_encoder_enable+0x1b8/0x1ac0
[ 5.601176] drm_atomic_helper_commit_modeset_enables+0x224/0x248
[ 5.601179] vc4_atomic_complete_commit+0x400/0x558
[ 5.601182] vc4_atomic_commit+0x1e0/0x200
[ 5.601185] drm_atomic_commit+0x4c/0x60
[ 5.601190] drm_client_modeset_commit_atomic.isra.0+0x17c/0x238
[ 5.601192] drm_client_modeset_commit_locked+0x5c/0x198
[ 5.601195] drm_client_modeset_commit+0x30/0x58
[ 5.601201] drm_fb_helper_restore_fbdev_mode_unlocked+0x78/0xe0
[ 5.601204] drm_fb_helper_set_par+0x30/0x68
[ 5.601208] fbcon_init+0x3d4/0x598
[ 5.601212] visual_init+0xb0/0x108
[ 5.601214] do_bind_con_driver+0x1d0/0x3a8
[ 5.601217] do_take_over_console+0x144/0x208
[ 5.601219] do_fbcon_takeover+0x68/0xd8
[ 5.601222] fbcon_fb_registered+0x100/0x118
[ 5.601226] register_framebuffer+0x1f4/0x338
[ 5.601229] __drm_fb_helper_initial_config_and_unlock+0x2f8/0x4a0
[ 5.601232] drm_fbdev_client_hotplug+0xd4/0x1b0
[ 5.601235] drm_fbdev_generic_setup+0xb0/0x130
[ 5.601238] vc4_drm_bind+0x184/0x1a0
[ 5.601241] try_to_bring_up_master+0x168/0x1c8
[ 5.601244] __component_add+0xa4/0x170
[ 5.601246] component_add+0x14/0x20
[ 5.601248] vc4_vec_dev_probe+0x20/0x30
[ 5.601252] platform_drv_probe+0x54/0xa8
[ 5.601254] really_probe+0xd8/0x320
[ 5.601256] driver_probe_device+0x58/0xf0
[ 5.601258] __device_attach_driver+0x84/0xc8
[ 5.601263] bus_for_each_drv+0x78/0xc8
[ 5.601265] __device_attach+0xe4/0x140
[ 5.601267] device_initial_probe+0x14/0x20
[ 5.601269] bus_probe_device+0x9c/0xa8
[ 5.601271] deferred_probe_work_func+0x74/0xb0
[ 5.601276] process_one_work+0x1bc/0x338
[ 5.601279] worker_thread+0x1f8/0x428
[ 5.601282] kthread+0x138/0x158
[ 5.601286] ret_from_fork+0x10/0x1c
[ 5.601288] ---[ end trace cfba0996218c3f3d ]---
[1]: https://gist.github.com/starnight/2236cf350737e3b0e9f05135fc7c910e
Jian-Hong Pan
Hi,
On Mon, Apr 27, 2020 at 03:23:42PM +0800, Jian-Hong Pan wrote:
> Hi Maxime,
>
> Thanks for your V2 patch series! I'm testing it.
>
> This patch series is applied upon mainline kernel 5.7-rc2 cleanly and built.
> System can boot into console text mode, but no graphic UI.
>
> Get the error in vc5_hdmi_phy_init(), and full dmesg is at [1]:
>
> [ 5.587543] vc4_hdmi fef00700.hdmi: Unknown register ID 46
> [ 5.587700] debugfs: Directory 'fef00700.hdmi' with parent 'vc4-hdmi' already present!
> [ 5.588070] vc4_hdmi fef00700.hdmi: vc4-hdmi-hifi <-> fef00700.hdmi mapping ok
> [ 5.588076] vc4_hdmi fef00700.hdmi: ASoC: no DMI vendor name!
> [ 5.588263] vc4-drm gpu: bound fef00700.hdmi (ops vc4_hdmi_ops)
> [ 5.588299] vc4_hdmi fef05700.hdmi: Unknown register ID 46
> [ 5.588373] debugfs: Directory 'vc4-hdmi' with parent 'asoc' already present!
> [ 5.588673] vc4_hdmi fef05700.hdmi: vc4-hdmi-hifi <-> fef05700.hdmi mapping ok
> [ 5.588677] vc4_hdmi fef05700.hdmi: ASoC: no DMI vendor name!
> [ 5.588809] vc4-drm gpu: bound fef05700.hdmi (ops vc4_hdmi_ops)
> [ 5.588854] vc4-drm gpu: bound fe806000.vec (ops vc4_vec_ops)
> [ 5.588897] vc4-drm gpu: bound fe004000.txp (ops vc4_txp_ops)
> [ 5.588934] vc4-drm gpu: bound fe400000.hvs (ops vc4_hvs_ops)
> [ 5.588990] vc4-drm gpu: bound fe206000.pixelvalve (ops vc4_crtc_ops)
> [ 5.589030] vc4-drm gpu: bound fe207000.pixelvalve (ops vc4_crtc_ops)
> [ 5.589074] vc4-drm gpu: bound fe20a000.pixelvalve (ops vc4_crtc_ops)
> [ 5.589106] vc4-drm gpu: bound fe216000.pixelvalve (ops vc4_crtc_ops)
> [ 5.589145] vc4-drm gpu: bound fec12000.pixelvalve (ops vc4_crtc_ops)
> [ 5.589294] checking generic (3e513000 6d8c00) vs hw (0 ffffffffffffffff)
> [ 5.589297] fb0: switching to vc4drmfb from simple
> [ 5.589433] Console: switching to colour dummy device 80x25
> [ 5.589481] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
> [ 5.589816] [drm] Initialized vc4 0.0.0 20140616 for gpu on minor 0
> [ 5.601079] ------------[ cut here ]------------
> [ 5.601095] WARNING: CPU: 2 PID: 127 at drivers/gpu/drm/vc4/vc4_hdmi_phy.c:413 vc5_hdmi_phy_init+0x7ac/0x2078
> [ 5.601097] Modules linked in:
> [ 5.601103] CPU: 2 PID: 127 Comm: kworker/2:1 Not tainted 5.7.0-rc2-00091-ga181df59a930 #7
> [ 5.601105] Hardware name: Raspberry Pi 4 Model B (DT)
> [ 5.601112] Workqueue: events deferred_probe_work_func
> [ 5.601116] pstate: 20000005 (nzCv daif -PAN -UAO)
> [ 5.601119] pc : vc5_hdmi_phy_init+0x7ac/0x2078
> [ 5.601123] lr : vc4_hdmi_encoder_enable+0x1b8/0x1ac0
> [ 5.601124] sp : ffff80001217b410
> [ 5.601126] x29: ffff80001217b410 x28: ffff0000ec6370f0
> [ 5.601129] x27: ffff0000f650d400 x26: 000000008a500000
> [ 5.601132] x25: ffff8000113b4ac0 x24: 0000000000002060
> [ 5.601135] x23: 000000000a500000 x22: 0000000000000300
> [ 5.601137] x21: 0000000008d9ee20 x20: ffff0000ec535080
> [ 5.601140] x19: 000000010989e7c0 x18: 0000000000000000
> [ 5.601142] x17: 0000000000000001 x16: 0000000000005207
> [ 5.601145] x15: 00004932ad293c92 x14: 0000000000000137
> [ 5.601147] x13: ffff800010015000 x12: 0000000000000001
> [ 5.601150] x11: 0000000000000001 x10: 0000000000000000
> [ 5.601152] x9 : 0000000000000000 x8 : ffff800010015038
> [ 5.601154] x7 : 0000000000000001 x6 : ffff80001217b368
> [ 5.601157] x5 : 0000000000000000 x4 : 000000000000004c
> [ 5.601159] x3 : 0000000000000000 x2 : ffff8000113b4ac0
> [ 5.601162] x1 : ffff8000120c5f44 x0 : 00000000dc8984ff
> [ 5.601164] Call trace:
> [ 5.601169] vc5_hdmi_phy_init+0x7ac/0x2078
> [ 5.601172] vc4_hdmi_encoder_enable+0x1b8/0x1ac0
> [ 5.601176] drm_atomic_helper_commit_modeset_enables+0x224/0x248
> [ 5.601179] vc4_atomic_complete_commit+0x400/0x558
> [ 5.601182] vc4_atomic_commit+0x1e0/0x200
> [ 5.601185] drm_atomic_commit+0x4c/0x60
> [ 5.601190] drm_client_modeset_commit_atomic.isra.0+0x17c/0x238
> [ 5.601192] drm_client_modeset_commit_locked+0x5c/0x198
> [ 5.601195] drm_client_modeset_commit+0x30/0x58
> [ 5.601201] drm_fb_helper_restore_fbdev_mode_unlocked+0x78/0xe0
> [ 5.601204] drm_fb_helper_set_par+0x30/0x68
> [ 5.601208] fbcon_init+0x3d4/0x598
> [ 5.601212] visual_init+0xb0/0x108
> [ 5.601214] do_bind_con_driver+0x1d0/0x3a8
> [ 5.601217] do_take_over_console+0x144/0x208
> [ 5.601219] do_fbcon_takeover+0x68/0xd8
> [ 5.601222] fbcon_fb_registered+0x100/0x118
> [ 5.601226] register_framebuffer+0x1f4/0x338
> [ 5.601229] __drm_fb_helper_initial_config_and_unlock+0x2f8/0x4a0
> [ 5.601232] drm_fbdev_client_hotplug+0xd4/0x1b0
> [ 5.601235] drm_fbdev_generic_setup+0xb0/0x130
> [ 5.601238] vc4_drm_bind+0x184/0x1a0
> [ 5.601241] try_to_bring_up_master+0x168/0x1c8
> [ 5.601244] __component_add+0xa4/0x170
> [ 5.601246] component_add+0x14/0x20
> [ 5.601248] vc4_vec_dev_probe+0x20/0x30
> [ 5.601252] platform_drv_probe+0x54/0xa8
> [ 5.601254] really_probe+0xd8/0x320
> [ 5.601256] driver_probe_device+0x58/0xf0
> [ 5.601258] __device_attach_driver+0x84/0xc8
> [ 5.601263] bus_for_each_drv+0x78/0xc8
> [ 5.601265] __device_attach+0xe4/0x140
> [ 5.601267] device_initial_probe+0x14/0x20
> [ 5.601269] bus_probe_device+0x9c/0xa8
> [ 5.601271] deferred_probe_work_func+0x74/0xb0
> [ 5.601276] process_one_work+0x1bc/0x338
> [ 5.601279] worker_thread+0x1f8/0x428
> [ 5.601282] kthread+0x138/0x158
> [ 5.601286] ret_from_fork+0x10/0x1c
> [ 5.601288] ---[ end trace cfba0996218c3f3d ]---
Thanks for testing!
Do you have a bit more details regarding your setup? Was it connected to an
external display? If so, do you know the resolution it was trying to setup?
Thanks!
Maxime
On Fri, 2020-04-24 at 17:33 +0200, Maxime Ripard wrote:
> The current firmware clock driver for the RaspberryPi can only be probed by
> manually registering an associated platform_device.
>
> While this works fine for cpufreq where the device gets attached a clkdev
> lookup, it would be tedious to maintain a table of all the devices using
> one of the clocks exposed by the firmware.
>
> Since the DT on the other hand is the perfect place to store those
> associations, make the firmware clocks driver probe-able through the device
> tree so that we can represent it as a node.
>
> Cc: Michael Turquette <[email protected]>
> Cc: Stephen Boyd <[email protected]>
> Cc: [email protected]
> Signed-off-by: Maxime Ripard <[email protected]>
> ---
> drivers/clk/bcm/clk-raspberrypi.c | 20 +++++++++++++++++---
> 1 file changed, 17 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/bcm/clk-raspberrypi.c b/drivers/clk/bcm/clk-
> raspberrypi.c
> index 1654fd0eedc9..aedeaaf2f66b 100644
> --- a/drivers/clk/bcm/clk-raspberrypi.c
> +++ b/drivers/clk/bcm/clk-raspberrypi.c
> @@ -255,15 +255,22 @@ static int raspberrypi_clk_probe(struct platform_device
> *pdev)
> struct raspberrypi_clk *rpi;
> int ret;
>
> - firmware_node = of_find_compatible_node(NULL, NULL,
> - "raspberrypi,bcm2835-firmware");
> + /*
> + * We can be probed either through the an old-fashioned
> + * platform device registration or through a DT node that is a
> + * child of the firmware node. Handle both cases.
> + */
> + if (dev->of_node)
> + firmware_node = of_get_parent(dev->of_node);
> + else
> + firmware_node = of_find_compatible_node(NULL, NULL,
> + "raspberrypi,bcm2835-
> firmware");
> if (!firmware_node) {
> dev_err(dev, "Missing firmware node\n");
> return -ENOENT;
> }
>
> firmware = rpi_firmware_get(firmware_node);
> - of_node_put(firmware_node);
Why remove this? I think it's still needed after your changes.
Regards,
Nicolas
Maxime Ripard <[email protected]> 於 2020年4月29日 週三 上午12:21寫道：
>
> Hi,
>
> On Mon, Apr 27, 2020 at 03:23:42PM +0800, Jian-Hong Pan wrote:
> > Hi Maxime,
> >
> > Thanks for your V2 patch series! I'm testing it.
> >
> > This patch series is applied upon mainline kernel 5.7-rc2 cleanly and built.
> > System can boot into console text mode, but no graphic UI.
> >
> > Get the error in vc5_hdmi_phy_init(), and full dmesg is at [1]:
> >
> > [ 5.587543] vc4_hdmi fef00700.hdmi: Unknown register ID 46
> > [ 5.587700] debugfs: Directory 'fef00700.hdmi' with parent 'vc4-hdmi' already present!
> > [ 5.588070] vc4_hdmi fef00700.hdmi: vc4-hdmi-hifi <-> fef00700.hdmi mapping ok
> > [ 5.588076] vc4_hdmi fef00700.hdmi: ASoC: no DMI vendor name!
> > [ 5.588263] vc4-drm gpu: bound fef00700.hdmi (ops vc4_hdmi_ops)
> > [ 5.588299] vc4_hdmi fef05700.hdmi: Unknown register ID 46
> > [ 5.588373] debugfs: Directory 'vc4-hdmi' with parent 'asoc' already present!
> > [ 5.588673] vc4_hdmi fef05700.hdmi: vc4-hdmi-hifi <-> fef05700.hdmi mapping ok
> > [ 5.588677] vc4_hdmi fef05700.hdmi: ASoC: no DMI vendor name!
> > [ 5.588809] vc4-drm gpu: bound fef05700.hdmi (ops vc4_hdmi_ops)
> > [ 5.588854] vc4-drm gpu: bound fe806000.vec (ops vc4_vec_ops)
> > [ 5.588897] vc4-drm gpu: bound fe004000.txp (ops vc4_txp_ops)
> > [ 5.588934] vc4-drm gpu: bound fe400000.hvs (ops vc4_hvs_ops)
> > [ 5.588990] vc4-drm gpu: bound fe206000.pixelvalve (ops vc4_crtc_ops)
> > [ 5.589030] vc4-drm gpu: bound fe207000.pixelvalve (ops vc4_crtc_ops)
> > [ 5.589074] vc4-drm gpu: bound fe20a000.pixelvalve (ops vc4_crtc_ops)
> > [ 5.589106] vc4-drm gpu: bound fe216000.pixelvalve (ops vc4_crtc_ops)
> > [ 5.589145] vc4-drm gpu: bound fec12000.pixelvalve (ops vc4_crtc_ops)
> > [ 5.589294] checking generic (3e513000 6d8c00) vs hw (0 ffffffffffffffff)
> > [ 5.589297] fb0: switching to vc4drmfb from simple
> > [ 5.589433] Console: switching to colour dummy device 80x25
> > [ 5.589481] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
> > [ 5.589816] [drm] Initialized vc4 0.0.0 20140616 for gpu on minor 0
> > [ 5.601079] ------------[ cut here ]------------
> > [ 5.601095] WARNING: CPU: 2 PID: 127 at drivers/gpu/drm/vc4/vc4_hdmi_phy.c:413 vc5_hdmi_phy_init+0x7ac/0x2078
> > [ 5.601097] Modules linked in:
> > [ 5.601103] CPU: 2 PID: 127 Comm: kworker/2:1 Not tainted 5.7.0-rc2-00091-ga181df59a930 #7
> > [ 5.601105] Hardware name: Raspberry Pi 4 Model B (DT)
> > [ 5.601112] Workqueue: events deferred_probe_work_func
> > [ 5.601116] pstate: 20000005 (nzCv daif -PAN -UAO)
> > [ 5.601119] pc : vc5_hdmi_phy_init+0x7ac/0x2078
> > [ 5.601123] lr : vc4_hdmi_encoder_enable+0x1b8/0x1ac0
> > [ 5.601124] sp : ffff80001217b410
> > [ 5.601126] x29: ffff80001217b410 x28: ffff0000ec6370f0
> > [ 5.601129] x27: ffff0000f650d400 x26: 000000008a500000
> > [ 5.601132] x25: ffff8000113b4ac0 x24: 0000000000002060
> > [ 5.601135] x23: 000000000a500000 x22: 0000000000000300
> > [ 5.601137] x21: 0000000008d9ee20 x20: ffff0000ec535080
> > [ 5.601140] x19: 000000010989e7c0 x18: 0000000000000000
> > [ 5.601142] x17: 0000000000000001 x16: 0000000000005207
> > [ 5.601145] x15: 00004932ad293c92 x14: 0000000000000137
> > [ 5.601147] x13: ffff800010015000 x12: 0000000000000001
> > [ 5.601150] x11: 0000000000000001 x10: 0000000000000000
> > [ 5.601152] x9 : 0000000000000000 x8 : ffff800010015038
> > [ 5.601154] x7 : 0000000000000001 x6 : ffff80001217b368
> > [ 5.601157] x5 : 0000000000000000 x4 : 000000000000004c
> > [ 5.601159] x3 : 0000000000000000 x2 : ffff8000113b4ac0
> > [ 5.601162] x1 : ffff8000120c5f44 x0 : 00000000dc8984ff
> > [ 5.601164] Call trace:
> > [ 5.601169] vc5_hdmi_phy_init+0x7ac/0x2078
> > [ 5.601172] vc4_hdmi_encoder_enable+0x1b8/0x1ac0
> > [ 5.601176] drm_atomic_helper_commit_modeset_enables+0x224/0x248
> > [ 5.601179] vc4_atomic_complete_commit+0x400/0x558
> > [ 5.601182] vc4_atomic_commit+0x1e0/0x200
> > [ 5.601185] drm_atomic_commit+0x4c/0x60
> > [ 5.601190] drm_client_modeset_commit_atomic.isra.0+0x17c/0x238
> > [ 5.601192] drm_client_modeset_commit_locked+0x5c/0x198
> > [ 5.601195] drm_client_modeset_commit+0x30/0x58
> > [ 5.601201] drm_fb_helper_restore_fbdev_mode_unlocked+0x78/0xe0
> > [ 5.601204] drm_fb_helper_set_par+0x30/0x68
> > [ 5.601208] fbcon_init+0x3d4/0x598
> > [ 5.601212] visual_init+0xb0/0x108
> > [ 5.601214] do_bind_con_driver+0x1d0/0x3a8
> > [ 5.601217] do_take_over_console+0x144/0x208
> > [ 5.601219] do_fbcon_takeover+0x68/0xd8
> > [ 5.601222] fbcon_fb_registered+0x100/0x118
> > [ 5.601226] register_framebuffer+0x1f4/0x338
> > [ 5.601229] __drm_fb_helper_initial_config_and_unlock+0x2f8/0x4a0
> > [ 5.601232] drm_fbdev_client_hotplug+0xd4/0x1b0
> > [ 5.601235] drm_fbdev_generic_setup+0xb0/0x130
> > [ 5.601238] vc4_drm_bind+0x184/0x1a0
> > [ 5.601241] try_to_bring_up_master+0x168/0x1c8
> > [ 5.601244] __component_add+0xa4/0x170
> > [ 5.601246] component_add+0x14/0x20
> > [ 5.601248] vc4_vec_dev_probe+0x20/0x30
> > [ 5.601252] platform_drv_probe+0x54/0xa8
> > [ 5.601254] really_probe+0xd8/0x320
> > [ 5.601256] driver_probe_device+0x58/0xf0
> > [ 5.601258] __device_attach_driver+0x84/0xc8
> > [ 5.601263] bus_for_each_drv+0x78/0xc8
> > [ 5.601265] __device_attach+0xe4/0x140
> > [ 5.601267] device_initial_probe+0x14/0x20
> > [ 5.601269] bus_probe_device+0x9c/0xa8
> > [ 5.601271] deferred_probe_work_func+0x74/0xb0
> > [ 5.601276] process_one_work+0x1bc/0x338
> > [ 5.601279] worker_thread+0x1f8/0x428
> > [ 5.601282] kthread+0x138/0x158
> > [ 5.601286] ret_from_fork+0x10/0x1c
> > [ 5.601288] ---[ end trace cfba0996218c3f3d ]---
>
> Thanks for testing!
>
> Do you have a bit more details regarding your setup? Was it connected to an
> external display?
Yes, the HDMI cable is connected to HDMI0 port on RPi 4.
> If so, do you know the resolution it was trying to setup?
According to the log, I think it is 1920x1080:
Apr 27 15:37:25 endless gdm-Xorg-:0[1960]: (II) modeset(0): Output
HDMI-1 connected
Apr 27 15:37:25 endless gdm-Xorg-:0[1960]: (II) modeset(0): Output
HDMI-2 disconnected
Apr 27 15:37:25 endless gdm-Xorg-:0[1960]: (II) modeset(0): Output
Composite-1 disconnected
Apr 27 15:37:25 endless gdm-Xorg-:0[1960]: (II) modeset(0): Using
exact sizes for initial modes
Apr 27 15:37:25 endless gdm-Xorg-:0[1960]: (II) modeset(0): Output
HDMI-1 using initial mode 1920x1080 +0+0
https://gist.github.com/starnight/45e1468bfa0426a54d2fb4a9269cfb94
Regards,
Jian-Hong Pan
On Fri, 2020-04-24 at 17:34 +0200, Maxime Ripard wrote:
> The reset-simple code can be useful for drivers outside of drivers/reset
> that have a few reset controls as part of their features. Let's move it to
> include/linux/reset.
>
> Cc: Philipp Zabel <[email protected]>
> Signed-off-by: Maxime Ripard <[email protected]>
Reviewed-by: Philipp Zabel <[email protected]>
Do you need the reset patches applied together with this series, or can
I pick them up individually?
regards
Philipp
On Mon, May 04, 2020 at 02:35:08PM +0800, Jian-Hong Pan wrote:
> Maxime Ripard <[email protected]> 於 2020年4月29日 週三 上午12:21寫道：
> >
> > Hi,
> >
> > On Mon, Apr 27, 2020 at 03:23:42PM +0800, Jian-Hong Pan wrote:
> > > Hi Maxime,
> > >
> > > Thanks for your V2 patch series! I'm testing it.
> > >
> > > This patch series is applied upon mainline kernel 5.7-rc2 cleanly and built.
> > > System can boot into console text mode, but no graphic UI.
> > >
> > > Get the error in vc5_hdmi_phy_init(), and full dmesg is at [1]:
> > >
> > > [ 5.587543] vc4_hdmi fef00700.hdmi: Unknown register ID 46
> > > [ 5.587700] debugfs: Directory 'fef00700.hdmi' with parent 'vc4-hdmi' already present!
> > > [ 5.588070] vc4_hdmi fef00700.hdmi: vc4-hdmi-hifi <-> fef00700.hdmi mapping ok
> > > [ 5.588076] vc4_hdmi fef00700.hdmi: ASoC: no DMI vendor name!
> > > [ 5.588263] vc4-drm gpu: bound fef00700.hdmi (ops vc4_hdmi_ops)
> > > [ 5.588299] vc4_hdmi fef05700.hdmi: Unknown register ID 46
> > > [ 5.588373] debugfs: Directory 'vc4-hdmi' with parent 'asoc' already present!
> > > [ 5.588673] vc4_hdmi fef05700.hdmi: vc4-hdmi-hifi <-> fef05700.hdmi mapping ok
> > > [ 5.588677] vc4_hdmi fef05700.hdmi: ASoC: no DMI vendor name!
> > > [ 5.588809] vc4-drm gpu: bound fef05700.hdmi (ops vc4_hdmi_ops)
> > > [ 5.588854] vc4-drm gpu: bound fe806000.vec (ops vc4_vec_ops)
> > > [ 5.588897] vc4-drm gpu: bound fe004000.txp (ops vc4_txp_ops)
> > > [ 5.588934] vc4-drm gpu: bound fe400000.hvs (ops vc4_hvs_ops)
> > > [ 5.588990] vc4-drm gpu: bound fe206000.pixelvalve (ops vc4_crtc_ops)
> > > [ 5.589030] vc4-drm gpu: bound fe207000.pixelvalve (ops vc4_crtc_ops)
> > > [ 5.589074] vc4-drm gpu: bound fe20a000.pixelvalve (ops vc4_crtc_ops)
> > > [ 5.589106] vc4-drm gpu: bound fe216000.pixelvalve (ops vc4_crtc_ops)
> > > [ 5.589145] vc4-drm gpu: bound fec12000.pixelvalve (ops vc4_crtc_ops)
> > > [ 5.589294] checking generic (3e513000 6d8c00) vs hw (0 ffffffffffffffff)
> > > [ 5.589297] fb0: switching to vc4drmfb from simple
> > > [ 5.589433] Console: switching to colour dummy device 80x25
> > > [ 5.589481] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
> > > [ 5.589816] [drm] Initialized vc4 0.0.0 20140616 for gpu on minor 0
> > > [ 5.601079] ------------[ cut here ]------------
> > > [ 5.601095] WARNING: CPU: 2 PID: 127 at drivers/gpu/drm/vc4/vc4_hdmi_phy.c:413 vc5_hdmi_phy_init+0x7ac/0x2078
> > > [ 5.601097] Modules linked in:
> > > [ 5.601103] CPU: 2 PID: 127 Comm: kworker/2:1 Not tainted 5.7.0-rc2-00091-ga181df59a930 #7
> > > [ 5.601105] Hardware name: Raspberry Pi 4 Model B (DT)
> > > [ 5.601112] Workqueue: events deferred_probe_work_func
> > > [ 5.601116] pstate: 20000005 (nzCv daif -PAN -UAO)
> > > [ 5.601119] pc : vc5_hdmi_phy_init+0x7ac/0x2078
> > > [ 5.601123] lr : vc4_hdmi_encoder_enable+0x1b8/0x1ac0
> > > [ 5.601124] sp : ffff80001217b410
> > > [ 5.601126] x29: ffff80001217b410 x28: ffff0000ec6370f0
> > > [ 5.601129] x27: ffff0000f650d400 x26: 000000008a500000
> > > [ 5.601132] x25: ffff8000113b4ac0 x24: 0000000000002060
> > > [ 5.601135] x23: 000000000a500000 x22: 0000000000000300
> > > [ 5.601137] x21: 0000000008d9ee20 x20: ffff0000ec535080
> > > [ 5.601140] x19: 000000010989e7c0 x18: 0000000000000000
> > > [ 5.601142] x17: 0000000000000001 x16: 0000000000005207
> > > [ 5.601145] x15: 00004932ad293c92 x14: 0000000000000137
> > > [ 5.601147] x13: ffff800010015000 x12: 0000000000000001
> > > [ 5.601150] x11: 0000000000000001 x10: 0000000000000000
> > > [ 5.601152] x9 : 0000000000000000 x8 : ffff800010015038
> > > [ 5.601154] x7 : 0000000000000001 x6 : ffff80001217b368
> > > [ 5.601157] x5 : 0000000000000000 x4 : 000000000000004c
> > > [ 5.601159] x3 : 0000000000000000 x2 : ffff8000113b4ac0
> > > [ 5.601162] x1 : ffff8000120c5f44 x0 : 00000000dc8984ff
> > > [ 5.601164] Call trace:
> > > [ 5.601169] vc5_hdmi_phy_init+0x7ac/0x2078
> > > [ 5.601172] vc4_hdmi_encoder_enable+0x1b8/0x1ac0
> > > [ 5.601176] drm_atomic_helper_commit_modeset_enables+0x224/0x248
> > > [ 5.601179] vc4_atomic_complete_commit+0x400/0x558
> > > [ 5.601182] vc4_atomic_commit+0x1e0/0x200
> > > [ 5.601185] drm_atomic_commit+0x4c/0x60
> > > [ 5.601190] drm_client_modeset_commit_atomic.isra.0+0x17c/0x238
> > > [ 5.601192] drm_client_modeset_commit_locked+0x5c/0x198
> > > [ 5.601195] drm_client_modeset_commit+0x30/0x58
> > > [ 5.601201] drm_fb_helper_restore_fbdev_mode_unlocked+0x78/0xe0
> > > [ 5.601204] drm_fb_helper_set_par+0x30/0x68
> > > [ 5.601208] fbcon_init+0x3d4/0x598
> > > [ 5.601212] visual_init+0xb0/0x108
> > > [ 5.601214] do_bind_con_driver+0x1d0/0x3a8
> > > [ 5.601217] do_take_over_console+0x144/0x208
> > > [ 5.601219] do_fbcon_takeover+0x68/0xd8
> > > [ 5.601222] fbcon_fb_registered+0x100/0x118
> > > [ 5.601226] register_framebuffer+0x1f4/0x338
> > > [ 5.601229] __drm_fb_helper_initial_config_and_unlock+0x2f8/0x4a0
> > > [ 5.601232] drm_fbdev_client_hotplug+0xd4/0x1b0
> > > [ 5.601235] drm_fbdev_generic_setup+0xb0/0x130
> > > [ 5.601238] vc4_drm_bind+0x184/0x1a0
> > > [ 5.601241] try_to_bring_up_master+0x168/0x1c8
> > > [ 5.601244] __component_add+0xa4/0x170
> > > [ 5.601246] component_add+0x14/0x20
> > > [ 5.601248] vc4_vec_dev_probe+0x20/0x30
> > > [ 5.601252] platform_drv_probe+0x54/0xa8
> > > [ 5.601254] really_probe+0xd8/0x320
> > > [ 5.601256] driver_probe_device+0x58/0xf0
> > > [ 5.601258] __device_attach_driver+0x84/0xc8
> > > [ 5.601263] bus_for_each_drv+0x78/0xc8
> > > [ 5.601265] __device_attach+0xe4/0x140
> > > [ 5.601267] device_initial_probe+0x14/0x20
> > > [ 5.601269] bus_probe_device+0x9c/0xa8
> > > [ 5.601271] deferred_probe_work_func+0x74/0xb0
> > > [ 5.601276] process_one_work+0x1bc/0x338
> > > [ 5.601279] worker_thread+0x1f8/0x428
> > > [ 5.601282] kthread+0x138/0x158
> > > [ 5.601286] ret_from_fork+0x10/0x1c
> > > [ 5.601288] ---[ end trace cfba0996218c3f3d ]---
> >
> > Thanks for testing!
> >
> > Do you have a bit more details regarding your setup? Was it connected to an
> > external display?
>
> Yes, the HDMI cable is connected to HDMI0 port on RPi 4.
>
> > If so, do you know the resolution it was trying to setup?
>
> According to the log, I think it is 1920x1080:
> Apr 27 15:37:25 endless gdm-Xorg-:0[1960]: (II) modeset(0): Output
> HDMI-1 connected
> Apr 27 15:37:25 endless gdm-Xorg-:0[1960]: (II) modeset(0): Output
> HDMI-2 disconnected
> Apr 27 15:37:25 endless gdm-Xorg-:0[1960]: (II) modeset(0): Output
> Composite-1 disconnected
> Apr 27 15:37:25 endless gdm-Xorg-:0[1960]: (II) modeset(0): Using
> exact sizes for initial modes
> Apr 27 15:37:25 endless gdm-Xorg-:0[1960]: (II) modeset(0): Output
> HDMI-1 using initial mode 1920x1080 +0+0
>
> https://gist.github.com/starnight/45e1468bfa0426a54d2fb4a9269cfb94
It looks to be fairly standard then, and I'm testing on the same resolution so
it should be alright.
Given from your log, it looks like you're running as arm64 though, while I stuck
with arm32, so it could be the explanation.
Can you share your config.txt and .config so that I can try to reproduce it
here?
Thanks!
Maxime
Maxime Ripard <[email protected]> 於 2020年5月8日 週五 上午1:22寫道：
>
> On Mon, May 04, 2020 at 02:35:08PM +0800, Jian-Hong Pan wrote:
> > Maxime Ripard <[email protected]> 於 2020年4月29日 週三 上午12:21寫道：
> > >
> > > Hi,
> > >
> > > On Mon, Apr 27, 2020 at 03:23:42PM +0800, Jian-Hong Pan wrote:
> > > > Hi Maxime,
> > > >
> > > > Thanks for your V2 patch series! I'm testing it.
> > > >
> > > > This patch series is applied upon mainline kernel 5.7-rc2 cleanly and built.
> > > > System can boot into console text mode, but no graphic UI.
> > > >
> > > > Get the error in vc5_hdmi_phy_init(), and full dmesg is at [1]:
> > > >
> > > > [ 5.587543] vc4_hdmi fef00700.hdmi: Unknown register ID 46
> > > > [ 5.587700] debugfs: Directory 'fef00700.hdmi' with parent 'vc4-hdmi' already present!
> > > > [ 5.588070] vc4_hdmi fef00700.hdmi: vc4-hdmi-hifi <-> fef00700.hdmi mapping ok
> > > > [ 5.588076] vc4_hdmi fef00700.hdmi: ASoC: no DMI vendor name!
> > > > [ 5.588263] vc4-drm gpu: bound fef00700.hdmi (ops vc4_hdmi_ops)
> > > > [ 5.588299] vc4_hdmi fef05700.hdmi: Unknown register ID 46
> > > > [ 5.588373] debugfs: Directory 'vc4-hdmi' with parent 'asoc' already present!
> > > > [ 5.588673] vc4_hdmi fef05700.hdmi: vc4-hdmi-hifi <-> fef05700.hdmi mapping ok
> > > > [ 5.588677] vc4_hdmi fef05700.hdmi: ASoC: no DMI vendor name!
> > > > [ 5.588809] vc4-drm gpu: bound fef05700.hdmi (ops vc4_hdmi_ops)
> > > > [ 5.588854] vc4-drm gpu: bound fe806000.vec (ops vc4_vec_ops)
> > > > [ 5.588897] vc4-drm gpu: bound fe004000.txp (ops vc4_txp_ops)
> > > > [ 5.588934] vc4-drm gpu: bound fe400000.hvs (ops vc4_hvs_ops)
> > > > [ 5.588990] vc4-drm gpu: bound fe206000.pixelvalve (ops vc4_crtc_ops)
> > > > [ 5.589030] vc4-drm gpu: bound fe207000.pixelvalve (ops vc4_crtc_ops)
> > > > [ 5.589074] vc4-drm gpu: bound fe20a000.pixelvalve (ops vc4_crtc_ops)
> > > > [ 5.589106] vc4-drm gpu: bound fe216000.pixelvalve (ops vc4_crtc_ops)
> > > > [ 5.589145] vc4-drm gpu: bound fec12000.pixelvalve (ops vc4_crtc_ops)
> > > > [ 5.589294] checking generic (3e513000 6d8c00) vs hw (0 ffffffffffffffff)
> > > > [ 5.589297] fb0: switching to vc4drmfb from simple
> > > > [ 5.589433] Console: switching to colour dummy device 80x25
> > > > [ 5.589481] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
> > > > [ 5.589816] [drm] Initialized vc4 0.0.0 20140616 for gpu on minor 0
> > > > [ 5.601079] ------------[ cut here ]------------
> > > > [ 5.601095] WARNING: CPU: 2 PID: 127 at drivers/gpu/drm/vc4/vc4_hdmi_phy.c:413 vc5_hdmi_phy_init+0x7ac/0x2078
> > > > [ 5.601097] Modules linked in:
> > > > [ 5.601103] CPU: 2 PID: 127 Comm: kworker/2:1 Not tainted 5.7.0-rc2-00091-ga181df59a930 #7
> > > > [ 5.601105] Hardware name: Raspberry Pi 4 Model B (DT)
> > > > [ 5.601112] Workqueue: events deferred_probe_work_func
> > > > [ 5.601116] pstate: 20000005 (nzCv daif -PAN -UAO)
> > > > [ 5.601119] pc : vc5_hdmi_phy_init+0x7ac/0x2078
> > > > [ 5.601123] lr : vc4_hdmi_encoder_enable+0x1b8/0x1ac0
> > > > [ 5.601124] sp : ffff80001217b410
> > > > [ 5.601126] x29: ffff80001217b410 x28: ffff0000ec6370f0
> > > > [ 5.601129] x27: ffff0000f650d400 x26: 000000008a500000
> > > > [ 5.601132] x25: ffff8000113b4ac0 x24: 0000000000002060
> > > > [ 5.601135] x23: 000000000a500000 x22: 0000000000000300
> > > > [ 5.601137] x21: 0000000008d9ee20 x20: ffff0000ec535080
> > > > [ 5.601140] x19: 000000010989e7c0 x18: 0000000000000000
> > > > [ 5.601142] x17: 0000000000000001 x16: 0000000000005207
> > > > [ 5.601145] x15: 00004932ad293c92 x14: 0000000000000137
> > > > [ 5.601147] x13: ffff800010015000 x12: 0000000000000001
> > > > [ 5.601150] x11: 0000000000000001 x10: 0000000000000000
> > > > [ 5.601152] x9 : 0000000000000000 x8 : ffff800010015038
> > > > [ 5.601154] x7 : 0000000000000001 x6 : ffff80001217b368
> > > > [ 5.601157] x5 : 0000000000000000 x4 : 000000000000004c
> > > > [ 5.601159] x3 : 0000000000000000 x2 : ffff8000113b4ac0
> > > > [ 5.601162] x1 : ffff8000120c5f44 x0 : 00000000dc8984ff
> > > > [ 5.601164] Call trace:
> > > > [ 5.601169] vc5_hdmi_phy_init+0x7ac/0x2078
> > > > [ 5.601172] vc4_hdmi_encoder_enable+0x1b8/0x1ac0
> > > > [ 5.601176] drm_atomic_helper_commit_modeset_enables+0x224/0x248
> > > > [ 5.601179] vc4_atomic_complete_commit+0x400/0x558
> > > > [ 5.601182] vc4_atomic_commit+0x1e0/0x200
> > > > [ 5.601185] drm_atomic_commit+0x4c/0x60
> > > > [ 5.601190] drm_client_modeset_commit_atomic.isra.0+0x17c/0x238
> > > > [ 5.601192] drm_client_modeset_commit_locked+0x5c/0x198
> > > > [ 5.601195] drm_client_modeset_commit+0x30/0x58
> > > > [ 5.601201] drm_fb_helper_restore_fbdev_mode_unlocked+0x78/0xe0
> > > > [ 5.601204] drm_fb_helper_set_par+0x30/0x68
> > > > [ 5.601208] fbcon_init+0x3d4/0x598
> > > > [ 5.601212] visual_init+0xb0/0x108
> > > > [ 5.601214] do_bind_con_driver+0x1d0/0x3a8
> > > > [ 5.601217] do_take_over_console+0x144/0x208
> > > > [ 5.601219] do_fbcon_takeover+0x68/0xd8
> > > > [ 5.601222] fbcon_fb_registered+0x100/0x118
> > > > [ 5.601226] register_framebuffer+0x1f4/0x338
> > > > [ 5.601229] __drm_fb_helper_initial_config_and_unlock+0x2f8/0x4a0
> > > > [ 5.601232] drm_fbdev_client_hotplug+0xd4/0x1b0
> > > > [ 5.601235] drm_fbdev_generic_setup+0xb0/0x130
> > > > [ 5.601238] vc4_drm_bind+0x184/0x1a0
> > > > [ 5.601241] try_to_bring_up_master+0x168/0x1c8
> > > > [ 5.601244] __component_add+0xa4/0x170
> > > > [ 5.601246] component_add+0x14/0x20
> > > > [ 5.601248] vc4_vec_dev_probe+0x20/0x30
> > > > [ 5.601252] platform_drv_probe+0x54/0xa8
> > > > [ 5.601254] really_probe+0xd8/0x320
> > > > [ 5.601256] driver_probe_device+0x58/0xf0
> > > > [ 5.601258] __device_attach_driver+0x84/0xc8
> > > > [ 5.601263] bus_for_each_drv+0x78/0xc8
> > > > [ 5.601265] __device_attach+0xe4/0x140
> > > > [ 5.601267] device_initial_probe+0x14/0x20
> > > > [ 5.601269] bus_probe_device+0x9c/0xa8
> > > > [ 5.601271] deferred_probe_work_func+0x74/0xb0
> > > > [ 5.601276] process_one_work+0x1bc/0x338
> > > > [ 5.601279] worker_thread+0x1f8/0x428
> > > > [ 5.601282] kthread+0x138/0x158
> > > > [ 5.601286] ret_from_fork+0x10/0x1c
> > > > [ 5.601288] ---[ end trace cfba0996218c3f3d ]---
> > >
> > > Thanks for testing!
> > >
> > > Do you have a bit more details regarding your setup? Was it connected to an
> > > external display?
> >
> > Yes, the HDMI cable is connected to HDMI0 port on RPi 4.
> >
> > > If so, do you know the resolution it was trying to setup?
> >
> > According to the log, I think it is 1920x1080:
> > Apr 27 15:37:25 endless gdm-Xorg-:0[1960]: (II) modeset(0): Output
> > HDMI-1 connected
> > Apr 27 15:37:25 endless gdm-Xorg-:0[1960]: (II) modeset(0): Output
> > HDMI-2 disconnected
> > Apr 27 15:37:25 endless gdm-Xorg-:0[1960]: (II) modeset(0): Output
> > Composite-1 disconnected
> > Apr 27 15:37:25 endless gdm-Xorg-:0[1960]: (II) modeset(0): Using
> > exact sizes for initial modes
> > Apr 27 15:37:25 endless gdm-Xorg-:0[1960]: (II) modeset(0): Output
> > HDMI-1 using initial mode 1920x1080 +0+0
> >
> > https://gist.github.com/starnight/45e1468bfa0426a54d2fb4a9269cfb94
>
> It looks to be fairly standard then, and I'm testing on the same resolution so
> it should be alright.
>
> Given from your log, it looks like you're running as arm64 though, while I stuck
> with arm32, so it could be the explanation.
Yes, I build it as arm64.
> Can you share your config.txt and .config so that I can try to reproduce it
> here?
Here is the config
https://gist.github.com/starnight/320b757441b6769c36160704b401c98b
Thanks,
Jian-Hong Pan
Jian-Hong Pan <[email protected]> 於 2020年5月8日 週五 下午2:20寫道：
>
> Maxime Ripard <[email protected]> 於 2020年5月8日 週五 上午1:22寫道：
> >
> > On Mon, May 04, 2020 at 02:35:08PM +0800, Jian-Hong Pan wrote:
> > > Maxime Ripard <[email protected]> 於 2020年4月29日 週三 上午12:21寫道：
> > > >
> > > > Hi,
> > > >
> > > > On Mon, Apr 27, 2020 at 03:23:42PM +0800, Jian-Hong Pan wrote:
> > > > > Hi Maxime,
> > > > >
> > > > > Thanks for your V2 patch series! I'm testing it.
> > > > >
> > > > > This patch series is applied upon mainline kernel 5.7-rc2 cleanly and built.
> > > > > System can boot into console text mode, but no graphic UI.
> > > > >
> > > > > Get the error in vc5_hdmi_phy_init(), and full dmesg is at [1]:
> > > > >
> > > > > [ 5.587543] vc4_hdmi fef00700.hdmi: Unknown register ID 46
> > > > > [ 5.587700] debugfs: Directory 'fef00700.hdmi' with parent 'vc4-hdmi' already present!
> > > > > [ 5.588070] vc4_hdmi fef00700.hdmi: vc4-hdmi-hifi <-> fef00700.hdmi mapping ok
> > > > > [ 5.588076] vc4_hdmi fef00700.hdmi: ASoC: no DMI vendor name!
> > > > > [ 5.588263] vc4-drm gpu: bound fef00700.hdmi (ops vc4_hdmi_ops)
> > > > > [ 5.588299] vc4_hdmi fef05700.hdmi: Unknown register ID 46
> > > > > [ 5.588373] debugfs: Directory 'vc4-hdmi' with parent 'asoc' already present!
> > > > > [ 5.588673] vc4_hdmi fef05700.hdmi: vc4-hdmi-hifi <-> fef05700.hdmi mapping ok
> > > > > [ 5.588677] vc4_hdmi fef05700.hdmi: ASoC: no DMI vendor name!
> > > > > [ 5.588809] vc4-drm gpu: bound fef05700.hdmi (ops vc4_hdmi_ops)
> > > > > [ 5.588854] vc4-drm gpu: bound fe806000.vec (ops vc4_vec_ops)
> > > > > [ 5.588897] vc4-drm gpu: bound fe004000.txp (ops vc4_txp_ops)
> > > > > [ 5.588934] vc4-drm gpu: bound fe400000.hvs (ops vc4_hvs_ops)
> > > > > [ 5.588990] vc4-drm gpu: bound fe206000.pixelvalve (ops vc4_crtc_ops)
> > > > > [ 5.589030] vc4-drm gpu: bound fe207000.pixelvalve (ops vc4_crtc_ops)
> > > > > [ 5.589074] vc4-drm gpu: bound fe20a000.pixelvalve (ops vc4_crtc_ops)
> > > > > [ 5.589106] vc4-drm gpu: bound fe216000.pixelvalve (ops vc4_crtc_ops)
> > > > > [ 5.589145] vc4-drm gpu: bound fec12000.pixelvalve (ops vc4_crtc_ops)
> > > > > [ 5.589294] checking generic (3e513000 6d8c00) vs hw (0 ffffffffffffffff)
> > > > > [ 5.589297] fb0: switching to vc4drmfb from simple
> > > > > [ 5.589433] Console: switching to colour dummy device 80x25
> > > > > [ 5.589481] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
> > > > > [ 5.589816] [drm] Initialized vc4 0.0.0 20140616 for gpu on minor 0
> > > > > [ 5.601079] ------------[ cut here ]------------
> > > > > [ 5.601095] WARNING: CPU: 2 PID: 127 at drivers/gpu/drm/vc4/vc4_hdmi_phy.c:413 vc5_hdmi_phy_init+0x7ac/0x2078
> > > > > [ 5.601097] Modules linked in:
> > > > > [ 5.601103] CPU: 2 PID: 127 Comm: kworker/2:1 Not tainted 5.7.0-rc2-00091-ga181df59a930 #7
> > > > > [ 5.601105] Hardware name: Raspberry Pi 4 Model B (DT)
> > > > > [ 5.601112] Workqueue: events deferred_probe_work_func
> > > > > [ 5.601116] pstate: 20000005 (nzCv daif -PAN -UAO)
> > > > > [ 5.601119] pc : vc5_hdmi_phy_init+0x7ac/0x2078
> > > > > [ 5.601123] lr : vc4_hdmi_encoder_enable+0x1b8/0x1ac0
> > > > > [ 5.601124] sp : ffff80001217b410
> > > > > [ 5.601126] x29: ffff80001217b410 x28: ffff0000ec6370f0
> > > > > [ 5.601129] x27: ffff0000f650d400 x26: 000000008a500000
> > > > > [ 5.601132] x25: ffff8000113b4ac0 x24: 0000000000002060
> > > > > [ 5.601135] x23: 000000000a500000 x22: 0000000000000300
> > > > > [ 5.601137] x21: 0000000008d9ee20 x20: ffff0000ec535080
> > > > > [ 5.601140] x19: 000000010989e7c0 x18: 0000000000000000
> > > > > [ 5.601142] x17: 0000000000000001 x16: 0000000000005207
> > > > > [ 5.601145] x15: 00004932ad293c92 x14: 0000000000000137
> > > > > [ 5.601147] x13: ffff800010015000 x12: 0000000000000001
> > > > > [ 5.601150] x11: 0000000000000001 x10: 0000000000000000
> > > > > [ 5.601152] x9 : 0000000000000000 x8 : ffff800010015038
> > > > > [ 5.601154] x7 : 0000000000000001 x6 : ffff80001217b368
> > > > > [ 5.601157] x5 : 0000000000000000 x4 : 000000000000004c
> > > > > [ 5.601159] x3 : 0000000000000000 x2 : ffff8000113b4ac0
> > > > > [ 5.601162] x1 : ffff8000120c5f44 x0 : 00000000dc8984ff
> > > > > [ 5.601164] Call trace:
> > > > > [ 5.601169] vc5_hdmi_phy_init+0x7ac/0x2078
> > > > > [ 5.601172] vc4_hdmi_encoder_enable+0x1b8/0x1ac0
> > > > > [ 5.601176] drm_atomic_helper_commit_modeset_enables+0x224/0x248
> > > > > [ 5.601179] vc4_atomic_complete_commit+0x400/0x558
> > > > > [ 5.601182] vc4_atomic_commit+0x1e0/0x200
> > > > > [ 5.601185] drm_atomic_commit+0x4c/0x60
> > > > > [ 5.601190] drm_client_modeset_commit_atomic.isra.0+0x17c/0x238
> > > > > [ 5.601192] drm_client_modeset_commit_locked+0x5c/0x198
> > > > > [ 5.601195] drm_client_modeset_commit+0x30/0x58
> > > > > [ 5.601201] drm_fb_helper_restore_fbdev_mode_unlocked+0x78/0xe0
> > > > > [ 5.601204] drm_fb_helper_set_par+0x30/0x68
> > > > > [ 5.601208] fbcon_init+0x3d4/0x598
> > > > > [ 5.601212] visual_init+0xb0/0x108
> > > > > [ 5.601214] do_bind_con_driver+0x1d0/0x3a8
> > > > > [ 5.601217] do_take_over_console+0x144/0x208
> > > > > [ 5.601219] do_fbcon_takeover+0x68/0xd8
> > > > > [ 5.601222] fbcon_fb_registered+0x100/0x118
> > > > > [ 5.601226] register_framebuffer+0x1f4/0x338
> > > > > [ 5.601229] __drm_fb_helper_initial_config_and_unlock+0x2f8/0x4a0
> > > > > [ 5.601232] drm_fbdev_client_hotplug+0xd4/0x1b0
> > > > > [ 5.601235] drm_fbdev_generic_setup+0xb0/0x130
> > > > > [ 5.601238] vc4_drm_bind+0x184/0x1a0
> > > > > [ 5.601241] try_to_bring_up_master+0x168/0x1c8
> > > > > [ 5.601244] __component_add+0xa4/0x170
> > > > > [ 5.601246] component_add+0x14/0x20
> > > > > [ 5.601248] vc4_vec_dev_probe+0x20/0x30
> > > > > [ 5.601252] platform_drv_probe+0x54/0xa8
> > > > > [ 5.601254] really_probe+0xd8/0x320
> > > > > [ 5.601256] driver_probe_device+0x58/0xf0
> > > > > [ 5.601258] __device_attach_driver+0x84/0xc8
> > > > > [ 5.601263] bus_for_each_drv+0x78/0xc8
> > > > > [ 5.601265] __device_attach+0xe4/0x140
> > > > > [ 5.601267] device_initial_probe+0x14/0x20
> > > > > [ 5.601269] bus_probe_device+0x9c/0xa8
> > > > > [ 5.601271] deferred_probe_work_func+0x74/0xb0
> > > > > [ 5.601276] process_one_work+0x1bc/0x338
> > > > > [ 5.601279] worker_thread+0x1f8/0x428
> > > > > [ 5.601282] kthread+0x138/0x158
> > > > > [ 5.601286] ret_from_fork+0x10/0x1c
> > > > > [ 5.601288] ---[ end trace cfba0996218c3f3d ]---
> > > >
> > > > Thanks for testing!
> > > >
> > > > Do you have a bit more details regarding your setup? Was it connected to an
> > > > external display?
> > >
> > > Yes, the HDMI cable is connected to HDMI0 port on RPi 4.
> > >
> > > > If so, do you know the resolution it was trying to setup?
> > >
> > > According to the log, I think it is 1920x1080:
> > > Apr 27 15:37:25 endless gdm-Xorg-:0[1960]: (II) modeset(0): Output
> > > HDMI-1 connected
> > > Apr 27 15:37:25 endless gdm-Xorg-:0[1960]: (II) modeset(0): Output
> > > HDMI-2 disconnected
> > > Apr 27 15:37:25 endless gdm-Xorg-:0[1960]: (II) modeset(0): Output
> > > Composite-1 disconnected
> > > Apr 27 15:37:25 endless gdm-Xorg-:0[1960]: (II) modeset(0): Using
> > > exact sizes for initial modes
> > > Apr 27 15:37:25 endless gdm-Xorg-:0[1960]: (II) modeset(0): Output
> > > HDMI-1 using initial mode 1920x1080 +0+0
> > >
> > > https://gist.github.com/starnight/45e1468bfa0426a54d2fb4a9269cfb94
> >
> > It looks to be fairly standard then, and I'm testing on the same resolution so
> > it should be alright.
> >
> > Given from your log, it looks like you're running as arm64 though, while I stuck
> > with arm32, so it could be the explanation.
>
> Yes, I build it as arm64.
>
> > Can you share your config.txt and .config so that I can try to reproduce it
> > here?
>
> Here is the config
> https://gist.github.com/starnight/320b757441b6769c36160704b401c98b
Here is the only one line in config.txt:
enable_uart=1
Actually, we make the Raspberry Pi's firmware bring up U-Boot, then
U-Boot boots kernel.
Jian-Hong Pan
Hi Philipp,
On Wed, May 06, 2020 at 11:26:34AM +0200, Philipp Zabel wrote:
> On Fri, 2020-04-24 at 17:34 +0200, Maxime Ripard wrote:
> > The reset-simple code can be useful for drivers outside of drivers/reset
> > that have a few reset controls as part of their features. Let's move it to
> > include/linux/reset.
> >
> > Cc: Philipp Zabel <[email protected]>
> > Signed-off-by: Maxime Ripard <[email protected]>
>
> Reviewed-by: Philipp Zabel <[email protected]>
>
> Do you need the reset patches applied together with this series, or can
> I pick them up individually?
You can definitely pick them up individually. I'll resend them separately with
your changes addressed.
Thanks!
Maxime
Hi,
On Mon, May 11, 2020 at 11:12:05AM +0800, Jian-Hong Pan wrote:
> Jian-Hong Pan <[email protected]> 於 2020年5月8日 週五 下午2:20寫道：
> >
> > Maxime Ripard <[email protected]> 於 2020年5月8日 週五 上午1:22寫道：
> > >
> > > On Mon, May 04, 2020 at 02:35:08PM +0800, Jian-Hong Pan wrote:
> > > > Maxime Ripard <[email protected]> 於 2020年4月29日 週三 上午12:21寫道：
> > > > >
> > > > > Hi,
> > > > >
> > > > > On Mon, Apr 27, 2020 at 03:23:42PM +0800, Jian-Hong Pan wrote:
> > > > > > Hi Maxime,
> > > > > >
> > > > > > Thanks for your V2 patch series! I'm testing it.
> > > > > >
> > > > > > This patch series is applied upon mainline kernel 5.7-rc2 cleanly and built.
> > > > > > System can boot into console text mode, but no graphic UI.
> > > > > >
> > > > > > Get the error in vc5_hdmi_phy_init(), and full dmesg is at [1]:
> > > > > >
> > > > > > [ 5.587543] vc4_hdmi fef00700.hdmi: Unknown register ID 46
> > > > > > [ 5.587700] debugfs: Directory 'fef00700.hdmi' with parent 'vc4-hdmi' already present!
> > > > > > [ 5.588070] vc4_hdmi fef00700.hdmi: vc4-hdmi-hifi <-> fef00700.hdmi mapping ok
> > > > > > [ 5.588076] vc4_hdmi fef00700.hdmi: ASoC: no DMI vendor name!
> > > > > > [ 5.588263] vc4-drm gpu: bound fef00700.hdmi (ops vc4_hdmi_ops)
> > > > > > [ 5.588299] vc4_hdmi fef05700.hdmi: Unknown register ID 46
> > > > > > [ 5.588373] debugfs: Directory 'vc4-hdmi' with parent 'asoc' already present!
> > > > > > [ 5.588673] vc4_hdmi fef05700.hdmi: vc4-hdmi-hifi <-> fef05700.hdmi mapping ok
> > > > > > [ 5.588677] vc4_hdmi fef05700.hdmi: ASoC: no DMI vendor name!
> > > > > > [ 5.588809] vc4-drm gpu: bound fef05700.hdmi (ops vc4_hdmi_ops)
> > > > > > [ 5.588854] vc4-drm gpu: bound fe806000.vec (ops vc4_vec_ops)
> > > > > > [ 5.588897] vc4-drm gpu: bound fe004000.txp (ops vc4_txp_ops)
> > > > > > [ 5.588934] vc4-drm gpu: bound fe400000.hvs (ops vc4_hvs_ops)
> > > > > > [ 5.588990] vc4-drm gpu: bound fe206000.pixelvalve (ops vc4_crtc_ops)
> > > > > > [ 5.589030] vc4-drm gpu: bound fe207000.pixelvalve (ops vc4_crtc_ops)
> > > > > > [ 5.589074] vc4-drm gpu: bound fe20a000.pixelvalve (ops vc4_crtc_ops)
> > > > > > [ 5.589106] vc4-drm gpu: bound fe216000.pixelvalve (ops vc4_crtc_ops)
> > > > > > [ 5.589145] vc4-drm gpu: bound fec12000.pixelvalve (ops vc4_crtc_ops)
> > > > > > [ 5.589294] checking generic (3e513000 6d8c00) vs hw (0 ffffffffffffffff)
> > > > > > [ 5.589297] fb0: switching to vc4drmfb from simple
> > > > > > [ 5.589433] Console: switching to colour dummy device 80x25
> > > > > > [ 5.589481] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
> > > > > > [ 5.589816] [drm] Initialized vc4 0.0.0 20140616 for gpu on minor 0
> > > > > > [ 5.601079] ------------[ cut here ]------------
> > > > > > [ 5.601095] WARNING: CPU: 2 PID: 127 at drivers/gpu/drm/vc4/vc4_hdmi_phy.c:413 vc5_hdmi_phy_init+0x7ac/0x2078
> > > > > > [ 5.601097] Modules linked in:
> > > > > > [ 5.601103] CPU: 2 PID: 127 Comm: kworker/2:1 Not tainted 5.7.0-rc2-00091-ga181df59a930 #7
> > > > > > [ 5.601105] Hardware name: Raspberry Pi 4 Model B (DT)
> > > > > > [ 5.601112] Workqueue: events deferred_probe_work_func
> > > > > > [ 5.601116] pstate: 20000005 (nzCv daif -PAN -UAO)
> > > > > > [ 5.601119] pc : vc5_hdmi_phy_init+0x7ac/0x2078
> > > > > > [ 5.601123] lr : vc4_hdmi_encoder_enable+0x1b8/0x1ac0
> > > > > > [ 5.601124] sp : ffff80001217b410
> > > > > > [ 5.601126] x29: ffff80001217b410 x28: ffff0000ec6370f0
> > > > > > [ 5.601129] x27: ffff0000f650d400 x26: 000000008a500000
> > > > > > [ 5.601132] x25: ffff8000113b4ac0 x24: 0000000000002060
> > > > > > [ 5.601135] x23: 000000000a500000 x22: 0000000000000300
> > > > > > [ 5.601137] x21: 0000000008d9ee20 x20: ffff0000ec535080
> > > > > > [ 5.601140] x19: 000000010989e7c0 x18: 0000000000000000
> > > > > > [ 5.601142] x17: 0000000000000001 x16: 0000000000005207
> > > > > > [ 5.601145] x15: 00004932ad293c92 x14: 0000000000000137
> > > > > > [ 5.601147] x13: ffff800010015000 x12: 0000000000000001
> > > > > > [ 5.601150] x11: 0000000000000001 x10: 0000000000000000
> > > > > > [ 5.601152] x9 : 0000000000000000 x8 : ffff800010015038
> > > > > > [ 5.601154] x7 : 0000000000000001 x6 : ffff80001217b368
> > > > > > [ 5.601157] x5 : 0000000000000000 x4 : 000000000000004c
> > > > > > [ 5.601159] x3 : 0000000000000000 x2 : ffff8000113b4ac0
> > > > > > [ 5.601162] x1 : ffff8000120c5f44 x0 : 00000000dc8984ff
> > > > > > [ 5.601164] Call trace:
> > > > > > [ 5.601169] vc5_hdmi_phy_init+0x7ac/0x2078
> > > > > > [ 5.601172] vc4_hdmi_encoder_enable+0x1b8/0x1ac0
> > > > > > [ 5.601176] drm_atomic_helper_commit_modeset_enables+0x224/0x248
> > > > > > [ 5.601179] vc4_atomic_complete_commit+0x400/0x558
> > > > > > [ 5.601182] vc4_atomic_commit+0x1e0/0x200
> > > > > > [ 5.601185] drm_atomic_commit+0x4c/0x60
> > > > > > [ 5.601190] drm_client_modeset_commit_atomic.isra.0+0x17c/0x238
> > > > > > [ 5.601192] drm_client_modeset_commit_locked+0x5c/0x198
> > > > > > [ 5.601195] drm_client_modeset_commit+0x30/0x58
> > > > > > [ 5.601201] drm_fb_helper_restore_fbdev_mode_unlocked+0x78/0xe0
> > > > > > [ 5.601204] drm_fb_helper_set_par+0x30/0x68
> > > > > > [ 5.601208] fbcon_init+0x3d4/0x598
> > > > > > [ 5.601212] visual_init+0xb0/0x108
> > > > > > [ 5.601214] do_bind_con_driver+0x1d0/0x3a8
> > > > > > [ 5.601217] do_take_over_console+0x144/0x208
> > > > > > [ 5.601219] do_fbcon_takeover+0x68/0xd8
> > > > > > [ 5.601222] fbcon_fb_registered+0x100/0x118
> > > > > > [ 5.601226] register_framebuffer+0x1f4/0x338
> > > > > > [ 5.601229] __drm_fb_helper_initial_config_and_unlock+0x2f8/0x4a0
> > > > > > [ 5.601232] drm_fbdev_client_hotplug+0xd4/0x1b0
> > > > > > [ 5.601235] drm_fbdev_generic_setup+0xb0/0x130
> > > > > > [ 5.601238] vc4_drm_bind+0x184/0x1a0
> > > > > > [ 5.601241] try_to_bring_up_master+0x168/0x1c8
> > > > > > [ 5.601244] __component_add+0xa4/0x170
> > > > > > [ 5.601246] component_add+0x14/0x20
> > > > > > [ 5.601248] vc4_vec_dev_probe+0x20/0x30
> > > > > > [ 5.601252] platform_drv_probe+0x54/0xa8
> > > > > > [ 5.601254] really_probe+0xd8/0x320
> > > > > > [ 5.601256] driver_probe_device+0x58/0xf0
> > > > > > [ 5.601258] __device_attach_driver+0x84/0xc8
> > > > > > [ 5.601263] bus_for_each_drv+0x78/0xc8
> > > > > > [ 5.601265] __device_attach+0xe4/0x140
> > > > > > [ 5.601267] device_initial_probe+0x14/0x20
> > > > > > [ 5.601269] bus_probe_device+0x9c/0xa8
> > > > > > [ 5.601271] deferred_probe_work_func+0x74/0xb0
> > > > > > [ 5.601276] process_one_work+0x1bc/0x338
> > > > > > [ 5.601279] worker_thread+0x1f8/0x428
> > > > > > [ 5.601282] kthread+0x138/0x158
> > > > > > [ 5.601286] ret_from_fork+0x10/0x1c
> > > > > > [ 5.601288] ---[ end trace cfba0996218c3f3d ]---
> > > > >
> > > > > Thanks for testing!
> > > > >
> > > > > Do you have a bit more details regarding your setup? Was it connected to an
> > > > > external display?
> > > >
> > > > Yes, the HDMI cable is connected to HDMI0 port on RPi 4.
> > > >
> > > > > If so, do you know the resolution it was trying to setup?
> > > >
> > > > According to the log, I think it is 1920x1080:
> > > > Apr 27 15:37:25 endless gdm-Xorg-:0[1960]: (II) modeset(0): Output
> > > > HDMI-1 connected
> > > > Apr 27 15:37:25 endless gdm-Xorg-:0[1960]: (II) modeset(0): Output
> > > > HDMI-2 disconnected
> > > > Apr 27 15:37:25 endless gdm-Xorg-:0[1960]: (II) modeset(0): Output
> > > > Composite-1 disconnected
> > > > Apr 27 15:37:25 endless gdm-Xorg-:0[1960]: (II) modeset(0): Using
> > > > exact sizes for initial modes
> > > > Apr 27 15:37:25 endless gdm-Xorg-:0[1960]: (II) modeset(0): Output
> > > > HDMI-1 using initial mode 1920x1080 +0+0
> > > >
> > > > https://gist.github.com/starnight/45e1468bfa0426a54d2fb4a9269cfb94
> > >
> > > It looks to be fairly standard then, and I'm testing on the same resolution so
> > > it should be alright.
> > >
> > > Given from your log, it looks like you're running as arm64 though, while I stuck
> > > with arm32, so it could be the explanation.
> >
> > Yes, I build it as arm64.
> >
> > > Can you share your config.txt and .config so that I can try to reproduce it
> > > here?
> >
> > Here is the config
> > https://gist.github.com/starnight/320b757441b6769c36160704b401c98b
>
> Here is the only one line in config.txt:
> enable_uart=1
>
> Actually, we make the Raspberry Pi's firmware bring up U-Boot, then
> U-Boot boots kernel.
I gave it a try today, and it seems that you also need arm_64bit=1 in the
config.txt, but then the communication with the firmware doesn't work anymore
and the kernel just falls apart.
I'll give it a try with U-boot
Maxime
Hi,
On Mon, May 11, 2020 at 11:12:05AM +0800, Jian-Hong Pan wrote:
> Jian-Hong Pan <[email protected]> 於 2020年5月8日 週五 下午2:20寫道：
> >
> > Maxime Ripard <[email protected]> 於 2020年5月8日 週五 上午1:22寫道：
> > >
> > > On Mon, May 04, 2020 at 02:35:08PM +0800, Jian-Hong Pan wrote:
> > > > Maxime Ripard <[email protected]> 於 2020年4月29日 週三 上午12:21寫道：
> > > > >
> > > > > Hi,
> > > > >
> > > > > On Mon, Apr 27, 2020 at 03:23:42PM +0800, Jian-Hong Pan wrote:
> > > > > > Hi Maxime,
> > > > > >
> > > > > > Thanks for your V2 patch series! I'm testing it.
> > > > > >
> > > > > > This patch series is applied upon mainline kernel 5.7-rc2 cleanly and built.
> > > > > > System can boot into console text mode, but no graphic UI.
> > > > > >
> > > > > > Get the error in vc5_hdmi_phy_init(), and full dmesg is at [1]:
> > > > > >
> > > > > > [ 5.587543] vc4_hdmi fef00700.hdmi: Unknown register ID 46
> > > > > > [ 5.587700] debugfs: Directory 'fef00700.hdmi' with parent 'vc4-hdmi' already present!
> > > > > > [ 5.588070] vc4_hdmi fef00700.hdmi: vc4-hdmi-hifi <-> fef00700.hdmi mapping ok
> > > > > > [ 5.588076] vc4_hdmi fef00700.hdmi: ASoC: no DMI vendor name!
> > > > > > [ 5.588263] vc4-drm gpu: bound fef00700.hdmi (ops vc4_hdmi_ops)
> > > > > > [ 5.588299] vc4_hdmi fef05700.hdmi: Unknown register ID 46
> > > > > > [ 5.588373] debugfs: Directory 'vc4-hdmi' with parent 'asoc' already present!
> > > > > > [ 5.588673] vc4_hdmi fef05700.hdmi: vc4-hdmi-hifi <-> fef05700.hdmi mapping ok
> > > > > > [ 5.588677] vc4_hdmi fef05700.hdmi: ASoC: no DMI vendor name!
> > > > > > [ 5.588809] vc4-drm gpu: bound fef05700.hdmi (ops vc4_hdmi_ops)
> > > > > > [ 5.588854] vc4-drm gpu: bound fe806000.vec (ops vc4_vec_ops)
> > > > > > [ 5.588897] vc4-drm gpu: bound fe004000.txp (ops vc4_txp_ops)
> > > > > > [ 5.588934] vc4-drm gpu: bound fe400000.hvs (ops vc4_hvs_ops)
> > > > > > [ 5.588990] vc4-drm gpu: bound fe206000.pixelvalve (ops vc4_crtc_ops)
> > > > > > [ 5.589030] vc4-drm gpu: bound fe207000.pixelvalve (ops vc4_crtc_ops)
> > > > > > [ 5.589074] vc4-drm gpu: bound fe20a000.pixelvalve (ops vc4_crtc_ops)
> > > > > > [ 5.589106] vc4-drm gpu: bound fe216000.pixelvalve (ops vc4_crtc_ops)
> > > > > > [ 5.589145] vc4-drm gpu: bound fec12000.pixelvalve (ops vc4_crtc_ops)
> > > > > > [ 5.589294] checking generic (3e513000 6d8c00) vs hw (0 ffffffffffffffff)
> > > > > > [ 5.589297] fb0: switching to vc4drmfb from simple
> > > > > > [ 5.589433] Console: switching to colour dummy device 80x25
> > > > > > [ 5.589481] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
> > > > > > [ 5.589816] [drm] Initialized vc4 0.0.0 20140616 for gpu on minor 0
> > > > > > [ 5.601079] ------------[ cut here ]------------
> > > > > > [ 5.601095] WARNING: CPU: 2 PID: 127 at drivers/gpu/drm/vc4/vc4_hdmi_phy.c:413 vc5_hdmi_phy_init+0x7ac/0x2078
> > > > > > [ 5.601097] Modules linked in:
> > > > > > [ 5.601103] CPU: 2 PID: 127 Comm: kworker/2:1 Not tainted 5.7.0-rc2-00091-ga181df59a930 #7
> > > > > > [ 5.601105] Hardware name: Raspberry Pi 4 Model B (DT)
> > > > > > [ 5.601112] Workqueue: events deferred_probe_work_func
> > > > > > [ 5.601116] pstate: 20000005 (nzCv daif -PAN -UAO)
> > > > > > [ 5.601119] pc : vc5_hdmi_phy_init+0x7ac/0x2078
> > > > > > [ 5.601123] lr : vc4_hdmi_encoder_enable+0x1b8/0x1ac0
> > > > > > [ 5.601124] sp : ffff80001217b410
> > > > > > [ 5.601126] x29: ffff80001217b410 x28: ffff0000ec6370f0
> > > > > > [ 5.601129] x27: ffff0000f650d400 x26: 000000008a500000
> > > > > > [ 5.601132] x25: ffff8000113b4ac0 x24: 0000000000002060
> > > > > > [ 5.601135] x23: 000000000a500000 x22: 0000000000000300
> > > > > > [ 5.601137] x21: 0000000008d9ee20 x20: ffff0000ec535080
> > > > > > [ 5.601140] x19: 000000010989e7c0 x18: 0000000000000000
> > > > > > [ 5.601142] x17: 0000000000000001 x16: 0000000000005207
> > > > > > [ 5.601145] x15: 00004932ad293c92 x14: 0000000000000137
> > > > > > [ 5.601147] x13: ffff800010015000 x12: 0000000000000001
> > > > > > [ 5.601150] x11: 0000000000000001 x10: 0000000000000000
> > > > > > [ 5.601152] x9 : 0000000000000000 x8 : ffff800010015038
> > > > > > [ 5.601154] x7 : 0000000000000001 x6 : ffff80001217b368
> > > > > > [ 5.601157] x5 : 0000000000000000 x4 : 000000000000004c
> > > > > > [ 5.601159] x3 : 0000000000000000 x2 : ffff8000113b4ac0
> > > > > > [ 5.601162] x1 : ffff8000120c5f44 x0 : 00000000dc8984ff
> > > > > > [ 5.601164] Call trace:
> > > > > > [ 5.601169] vc5_hdmi_phy_init+0x7ac/0x2078
> > > > > > [ 5.601172] vc4_hdmi_encoder_enable+0x1b8/0x1ac0
> > > > > > [ 5.601176] drm_atomic_helper_commit_modeset_enables+0x224/0x248
> > > > > > [ 5.601179] vc4_atomic_complete_commit+0x400/0x558
> > > > > > [ 5.601182] vc4_atomic_commit+0x1e0/0x200
> > > > > > [ 5.601185] drm_atomic_commit+0x4c/0x60
> > > > > > [ 5.601190] drm_client_modeset_commit_atomic.isra.0+0x17c/0x238
> > > > > > [ 5.601192] drm_client_modeset_commit_locked+0x5c/0x198
> > > > > > [ 5.601195] drm_client_modeset_commit+0x30/0x58
> > > > > > [ 5.601201] drm_fb_helper_restore_fbdev_mode_unlocked+0x78/0xe0
> > > > > > [ 5.601204] drm_fb_helper_set_par+0x30/0x68
> > > > > > [ 5.601208] fbcon_init+0x3d4/0x598
> > > > > > [ 5.601212] visual_init+0xb0/0x108
> > > > > > [ 5.601214] do_bind_con_driver+0x1d0/0x3a8
> > > > > > [ 5.601217] do_take_over_console+0x144/0x208
> > > > > > [ 5.601219] do_fbcon_takeover+0x68/0xd8
> > > > > > [ 5.601222] fbcon_fb_registered+0x100/0x118
> > > > > > [ 5.601226] register_framebuffer+0x1f4/0x338
> > > > > > [ 5.601229] __drm_fb_helper_initial_config_and_unlock+0x2f8/0x4a0
> > > > > > [ 5.601232] drm_fbdev_client_hotplug+0xd4/0x1b0
> > > > > > [ 5.601235] drm_fbdev_generic_setup+0xb0/0x130
> > > > > > [ 5.601238] vc4_drm_bind+0x184/0x1a0
> > > > > > [ 5.601241] try_to_bring_up_master+0x168/0x1c8
> > > > > > [ 5.601244] __component_add+0xa4/0x170
> > > > > > [ 5.601246] component_add+0x14/0x20
> > > > > > [ 5.601248] vc4_vec_dev_probe+0x20/0x30
> > > > > > [ 5.601252] platform_drv_probe+0x54/0xa8
> > > > > > [ 5.601254] really_probe+0xd8/0x320
> > > > > > [ 5.601256] driver_probe_device+0x58/0xf0
> > > > > > [ 5.601258] __device_attach_driver+0x84/0xc8
> > > > > > [ 5.601263] bus_for_each_drv+0x78/0xc8
> > > > > > [ 5.601265] __device_attach+0xe4/0x140
> > > > > > [ 5.601267] device_initial_probe+0x14/0x20
> > > > > > [ 5.601269] bus_probe_device+0x9c/0xa8
> > > > > > [ 5.601271] deferred_probe_work_func+0x74/0xb0
> > > > > > [ 5.601276] process_one_work+0x1bc/0x338
> > > > > > [ 5.601279] worker_thread+0x1f8/0x428
> > > > > > [ 5.601282] kthread+0x138/0x158
> > > > > > [ 5.601286] ret_from_fork+0x10/0x1c
> > > > > > [ 5.601288] ---[ end trace cfba0996218c3f3d ]---
> > > > >
> > > > > Thanks for testing!
> > > > >
> > > > > Do you have a bit more details regarding your setup? Was it connected to an
> > > > > external display?
> > > >
> > > > Yes, the HDMI cable is connected to HDMI0 port on RPi 4.
> > > >
> > > > > If so, do you know the resolution it was trying to setup?
> > > >
> > > > According to the log, I think it is 1920x1080:
> > > > Apr 27 15:37:25 endless gdm-Xorg-:0[1960]: (II) modeset(0): Output
> > > > HDMI-1 connected
> > > > Apr 27 15:37:25 endless gdm-Xorg-:0[1960]: (II) modeset(0): Output
> > > > HDMI-2 disconnected
> > > > Apr 27 15:37:25 endless gdm-Xorg-:0[1960]: (II) modeset(0): Output
> > > > Composite-1 disconnected
> > > > Apr 27 15:37:25 endless gdm-Xorg-:0[1960]: (II) modeset(0): Using
> > > > exact sizes for initial modes
> > > > Apr 27 15:37:25 endless gdm-Xorg-:0[1960]: (II) modeset(0): Output
> > > > HDMI-1 using initial mode 1920x1080 +0+0
> > > >
> > > > https://gist.github.com/starnight/45e1468bfa0426a54d2fb4a9269cfb94
> > >
> > > It looks to be fairly standard then, and I'm testing on the same resolution so
> > > it should be alright.
> > >
> > > Given from your log, it looks like you're running as arm64 though, while I stuck
> > > with arm32, so it could be the explanation.
> >
> > Yes, I build it as arm64.
> >
> > > Can you share your config.txt and .config so that I can try to reproduce it
> > > here?
> >
> > Here is the config
> > https://gist.github.com/starnight/320b757441b6769c36160704b401c98b
>
> Here is the only one line in config.txt:
> enable_uart=1
>
> Actually, we make the Raspberry Pi's firmware bring up U-Boot, then
> U-Boot boots kernel.
I gave it a try with U-Boot with my latest work and couldn't reproduce it, so it
seems that I fixed it along the way
Maxime
Hi Maxime,
On Tue, May 26, 2020 at 6:20 PM Maxime Ripard <[email protected]> wrote:
> I gave it a try with U-Boot with my latest work and couldn't reproduce it, so it
> seems that I fixed it along the way
Is your latest work available in a git branch anywhere that we could
test directly?
Thanks
Daniel
Quoting Maxime Ripard (2020-04-24 08:33:47)
> Instead of declaring the clk_init_data and then calling memset on it, just
> initialise properly.
>
> Cc: Michael Turquette <[email protected]>
> Cc: Stephen Boyd <[email protected]>
> Cc: [email protected]
> Acked-by: Nicolas Saenz Julienne <[email protected]>
> Signed-off-by: Maxime Ripard <[email protected]>
> ---
Reviewed-by: Stephen Boyd <[email protected]>
Quoting Maxime Ripard (2020-04-24 08:33:50)
> The pllb_arm clock was created at probe time, but was never removed if
> something went wrong later in probe, or if the driver was ever removed from
> the system.
>
> Now that we are using clk_hw_register, we can just use its managed variant
clk_hw_register()
> to take care of that for us.
>
> Cc: Michael Turquette <[email protected]>
> Cc: [email protected]
> Acked-by: Nicolas Saenz Julienne <[email protected]>
> Reviewed-by: Stephen Boyd <[email protected]>
> Signed-off-by: Maxime Ripard <[email protected]>
> ---
Reviewed-by: Stephen Boyd <[email protected]>
Quoting Maxime Ripard (2020-04-24 08:34:06)
> The HDMI block has a block that controls clocks and reset signals to the
> HDMI0 and HDMI1 controllers.
>
> Let's expose that through a clock driver implementing a clock and reset
> provider.
>
> Cc: Michael Turquette <[email protected]>
> Cc: Stephen Boyd <[email protected]>
> Cc: Rob Herring <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Signed-off-by: Maxime Ripard <[email protected]>
> ---
Reviewed-by: Stephen Boyd <[email protected]>
> diff --git a/drivers/clk/bcm/clk-bcm2711-dvp.c b/drivers/clk/bcm/clk-bcm2711-dvp.c
> new file mode 100644
> index 000000000000..c1c4b5857d32
> --- /dev/null
> +++ b/drivers/clk/bcm/clk-bcm2711-dvp.c
> @@ -0,0 +1,127 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +// Copyright 2020 Cerno
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
[...]
> +
> +static int clk_dvp_probe(struct platform_device *pdev)
> +{
> + struct clk_hw_onecell_data *data;
> + struct resource *res;
> + struct clk_dvp *dvp;
> + void __iomem *base;
> + int ret;
> +
> + dvp = devm_kzalloc(&pdev->dev, sizeof(*dvp), GFP_KERNEL);
> + if (!dvp)
> + return -ENOMEM;
> + platform_set_drvdata(pdev, dvp);
> +
> + dvp->data = devm_kzalloc(&pdev->dev,
> + struct_size(dvp->data, hws, NR_CLOCKS),
> + GFP_KERNEL);
> + if (!dvp->data)
> + return -ENOMEM;
> + data = dvp->data;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + base = devm_ioremap_resource(&pdev->dev, res);
devm_platform_ioremap_resource()?
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
Hi Daniel,
On Wed, May 27, 2020 at 11:49:36AM +0800, Daniel Drake wrote:
> Hi Maxime,
>
> On Tue, May 26, 2020 at 6:20 PM Maxime Ripard <[email protected]> wrote:
> > I gave it a try with U-Boot with my latest work and couldn't reproduce it, so it
> > seems that I fixed it along the way
>
> Is your latest work available in a git branch anywhere that we could
> test directly?
I'm about to send a v3 today or tomorrow, I can Cc you (and Jian-Hong) if you
want.
Maxime