Changes since v4: https://lore.kernel.org/lkml/[email protected]/
* Missing SoB added
Changes since v3: https://lore.kernel.org/lkml/[email protected]/
* Examples included
* Included Abel's patches fixing thermal zone, keys and power controller names.
Abel Vesa (14):
arm64: dts: freescale: imx8qxp: Fix thermal zone name for cpu0
dt-bindings: clk: imx: Add fsl,scu-clk yaml file
dt-bindings: pinctrl: imx: Add fsl,scu-iomux yaml file
dt-bindings: input: Add fsl,scu-key yaml file
dt-bindings: nvmem: Add fsl,scu-ocotp yaml file
dt-bindings: power: Add fsl,scu-pd yaml file
dt-bindings: rtc: Add fsl,scu-rtc yaml file
dt-bindings: thermal: Add fsl,scu-thermal yaml file
dt-bindings: watchdog: Add fsl,scu-wdt yaml file
dt-bindings: firmware: Add fsl,scu yaml file
arm64: dts: freescale: imx8: Fix power controller name
arm64: dts: freescale: imx8qxp: Add fallback compatible for clock
controller
arm64: dts: freescale: imx8qxp: Fix the keys node name
dt-bindings: arm: freescale: Remove fsl,scu txt file
.../bindings/arm/freescale/fsl,scu.txt | 271 ------------------
.../bindings/clock/fsl,scu-clk.yaml | 58 ++++
.../devicetree/bindings/firmware/fsl,scu.yaml | 170 +++++++++++
.../bindings/input/fsl,scu-key.yaml | 39 +++
.../bindings/nvmem/fsl,scu-ocotp.yaml | 49 ++++
.../bindings/pinctrl/fsl,scu-pinctrl.yaml | 47 +++
.../devicetree/bindings/power/fsl,scu-pd.yaml | 41 +++
.../devicetree/bindings/rtc/fsl,scu-rtc.yaml | 28 ++
.../bindings/thermal/fsl,scu-thermal.yaml | 38 +++
.../bindings/watchdog/fsl,scu-wdt.yaml | 35 +++
arch/arm64/boot/dts/freescale/imx8qm.dtsi | 2 +-
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 8 +-
12 files changed, 510 insertions(+), 276 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
create mode 100644 Documentation/devicetree/bindings/clock/fsl,scu-clk.yaml
create mode 100644 Documentation/devicetree/bindings/firmware/fsl,scu.yaml
create mode 100644 Documentation/devicetree/bindings/input/fsl,scu-key.yaml
create mode 100644 Documentation/devicetree/bindings/nvmem/fsl,scu-ocotp.yaml
create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml
create mode 100644 Documentation/devicetree/bindings/power/fsl,scu-pd.yaml
create mode 100644 Documentation/devicetree/bindings/rtc/fsl,scu-rtc.yaml
create mode 100644 Documentation/devicetree/bindings/thermal/fsl,scu-thermal.yaml
create mode 100644 Documentation/devicetree/bindings/watchdog/fsl,scu-wdt.yaml
--
2.25.1
From: Abel Vesa <[email protected]>
The proper name is cpu0-thermal, not cpu-thermal0, so change it to that.
Signed-off-by: Abel Vesa <[email protected]>
Signed-off-by: Viorel Suman <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index a79ae33cbad2..483996a1f2d5 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -276,7 +276,7 @@ xtal24m: clock-xtal24m {
};
thermal_zones: thermal-zones {
- cpu-thermal0 {
+ cpu0-thermal {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
--
2.25.1
From: Abel Vesa <[email protected]>
The proper name is power-controller, not imx8qx-pd.
Signed-off-by: Abel Vesa <[email protected]>
Signed-off-by: Viorel Suman <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8qm.dtsi | 2 +-
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index 4f767012f1f5..5ad1c9a5933c 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -190,7 +190,7 @@ scu {
&lsio_mu1 1 0
&lsio_mu1 3 3>;
- pd: imx8qx-pd {
+ pd: power-controller {
compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";
#power-domain-cells = <1>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 483996a1f2d5..542bc47509ca 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -210,7 +210,7 @@ scu {
&lsio_mu1 1 0
&lsio_mu1 3 3>;
- pd: imx8qx-pd {
+ pd: power-controller {
compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
#power-domain-cells = <1>;
};
--
2.25.1
From: Abel Vesa <[email protected]>
In order to replace the fsl,scu txt file from bindings/arm/freescale,
we need to split it between the right subsystems. This patch adds the
fsl,scu.yaml in the firmware bindings folder. This one is only for
the main SCU node. The old txt file will be removed only after all
the child nodes have been properly switch to yaml.
Signed-off-by: Abel Vesa <[email protected]>
Signed-off-by: Viorel Suman <[email protected]>
---
.../devicetree/bindings/firmware/fsl,scu.yaml | 170 ++++++++++++++++++
1 file changed, 170 insertions(+)
create mode 100644 Documentation/devicetree/bindings/firmware/fsl,scu.yaml
diff --git a/Documentation/devicetree/bindings/firmware/fsl,scu.yaml b/Documentation/devicetree/bindings/firmware/fsl,scu.yaml
new file mode 100644
index 000000000000..a28f729bfadb
--- /dev/null
+++ b/Documentation/devicetree/bindings/firmware/fsl,scu.yaml
@@ -0,0 +1,170 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/firmware/fsl,scu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX System Controller Firmware (SCFW)
+
+maintainers:
+ - Dong Aisheng <[email protected]>
+
+description: System Controller Device Node
+ The System Controller Firmware (SCFW) is a low-level system function
+ which runs on a dedicated Cortex-M core to provide power, clock, and
+ resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
+ (QM, QP), and i.MX8QX (QXP, DX).
+ The AP communicates with the SC using a multi-ported MU module found
+ in the LSIO subsystem. The current definition of this MU module provides
+ 5 remote AP connections to the SC to support up to 5 execution environments
+ (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces
+ with the LSIO DSC IP bus. The SC firmware will communicate with this MU
+ using the MSI bus.
+
+properties:
+ $nodename:
+ const: 'scu'
+
+ compatible:
+ const: fsl,imx-scu
+
+ clock-controller:
+ description: |
+ $ref: /schemas/clock/fsl,scu-clk.yaml
+ Clock controller node that provides the clocks controlled by the SCU
+
+ imx8qx-ocotp:
+ description: |
+ $ref: /schemas/nvmem/fsl,scu-ocotp.yaml
+ OCOTP controller node provided by the SCU
+
+ keys:
+ description: |
+ $ref: /schemas/input/fsl,scu-key.yaml
+ Keys provided by the SCU
+
+ mboxes:
+ description: |
+ $ref: /schemas/mailbox/fsl,mu.yaml
+ List of phandle of 4 MU channels for tx, 4 MU channels for
+ rx, and 1 optional MU channel for general interrupt.
+ All MU channels must be in the same MU instance.
+ Cross instances are not allowed. The MU instance can only
+ be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need
+ to make sure use the one which is not conflict with other
+ execution environments. e.g. ATF.
+ minItems: 1
+ maxItems: 10
+
+ mbox-names:
+ description:
+ include "gip3" if want to support general MU interrupt.
+ minItems: 1
+ maxItems: 10
+
+ pinctrl:
+ description: |
+ $ref: /schemas/pinctrl/fsl,scu-pinctrl.yaml
+ Pin controller provided by the SCU
+
+ power-controller:
+ description: |
+ $ref: /schemas/power/fsl,scu-pd.yaml
+ Power domains controller node that provides the power domains
+ controlled by the SCU
+
+ rtc:
+ description: |
+ $ref: /schemas/rtc/fsl,scu-rtc.yaml
+ RTC controller provided by the SCU
+
+ thermal-sensor:
+ description: |
+ $ref: /schemas/thermal/fsl,scu-thermal.yaml
+ Thermal sensor provided by the SCU
+
+ watchdog:
+ description: |
+ $ref: /schemas/watchdog/fsl,scu-wdt.yaml
+ Watchdog controller provided by the SCU
+
+required:
+ - compatible
+ - mbox-names
+ - mboxes
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/firmware/imx/rsrc.h>
+ #include <dt-bindings/input/input.h>
+ #include <dt-bindings/pinctrl/pads-imx8qxp.h>
+
+ firmware {
+ scu {
+ compatible = "fsl,imx-scu";
+ mbox-names = "tx0", "tx1", "tx2", "tx3",
+ "rx0", "rx1", "rx2", "rx3",
+ "gip3";
+ mboxes = <&lsio_mu1 0 0
+ &lsio_mu1 0 1
+ &lsio_mu1 0 2
+ &lsio_mu1 0 3
+ &lsio_mu1 1 0
+ &lsio_mu1 1 1
+ &lsio_mu1 1 2
+ &lsio_mu1 1 3
+ &lsio_mu1 3 3>;
+
+ clock-controller {
+ compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
+ #clock-cells = <2>;
+ };
+
+ pinctrl {
+ compatible = "fsl,imx8qxp-iomuxc";
+
+ pinctrl_lpuart0: lpuart0grp {
+ fsl,pins = <
+ IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020
+ IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020
+ >;
+ };
+ };
+
+ imx8qx-ocotp {
+ compatible = "fsl,imx8qxp-scu-ocotp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ fec_mac0: mac@2c4 {
+ reg = <0x2c4 6>;
+ };
+ };
+
+ power-controller {
+ compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
+ #power-domain-cells = <1>;
+ };
+
+ rtc {
+ compatible = "fsl,imx8qxp-sc-rtc";
+ };
+
+ keys {
+ compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
+ linux,keycodes = <KEY_POWER>;
+ };
+
+ watchdog {
+ compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
+ timeout-sec = <60>;
+ };
+
+ thermal-sensor {
+ compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
+ #thermal-sensor-cells = <1>;
+ };
+ };
+ };
--
2.25.1
From: Abel Vesa <[email protected]>
The proper name is 'keys', not 'scu-keys'.
Signed-off-by: Abel Vesa <[email protected]>
Signed-off-by: Viorel Suman <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index f9c3090c632e..1ef736815969 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -232,7 +232,7 @@ ocotp: imx8qx-ocotp {
#size-cells = <1>;
};
- scu_key: scu-key {
+ scu_key: keys {
compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
linux,keycodes = <KEY_POWER>;
status = "disabled";
--
2.25.1
From: Abel Vesa <[email protected]>
Both i.MX8QM and i.MX8DXL use the fallback fsl,scu-clk compatible.
They rely on the same driver generic part as the i.MX8QXP, so
lets add it to i.MX8QXP too, for consitency.
Signed-off-by: Abel Vesa <[email protected]>
Signed-off-by: Viorel Suman <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 542bc47509ca..f9c3090c632e 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -216,7 +216,7 @@ pd: power-controller {
};
clk: clock-controller {
- compatible = "fsl,imx8qxp-clk";
+ compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
#clock-cells = <2>;
clocks = <&xtal32k &xtal24m>;
clock-names = "xtal_32KHz", "xtal_24Mhz";
--
2.25.1
On 16/06/2022 18:42, Viorel Suman wrote:
> From: Abel Vesa <[email protected]>
>
> In order to replace the fsl,scu txt file from bindings/arm/freescale,
> we need to split it between the right subsystems. This patch adds the
> fsl,scu.yaml in the firmware bindings folder. This one is only for
> the main SCU node. The old txt file will be removed only after all
> the child nodes have been properly switch to yaml.
>
> Signed-off-by: Abel Vesa <[email protected]>
> Signed-off-by: Viorel Suman <[email protected]>
> ---
> .../devicetree/bindings/firmware/fsl,scu.yaml | 170 ++++++++++++++++++
> 1 file changed, 170 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/firmware/fsl,scu.yaml
>
> diff --git a/Documentation/devicetree/bindings/firmware/fsl,scu.yaml b/Documentation/devicetree/bindings/firmware/fsl,scu.yaml
> new file mode 100644
> index 000000000000..a28f729bfadb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/firmware/fsl,scu.yaml
> @@ -0,0 +1,170 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/firmware/fsl,scu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP i.MX System Controller Firmware (SCFW)
> +
> +maintainers:
> + - Dong Aisheng <[email protected]>
> +
> +description: System Controller Device Node
> + The System Controller Firmware (SCFW) is a low-level system function
> + which runs on a dedicated Cortex-M core to provide power, clock, and
> + resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
> + (QM, QP), and i.MX8QX (QXP, DX).
> + The AP communicates with the SC using a multi-ported MU module found
> + in the LSIO subsystem. The current definition of this MU module provides
> + 5 remote AP connections to the SC to support up to 5 execution environments
> + (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces
> + with the LSIO DSC IP bus. The SC firmware will communicate with this MU
> + using the MSI bus.
> +
> +properties:
> + $nodename:
> + const: 'scu'
Why enforcing node name? Second point is that node names should be
generic, so I wonder what "SCU" exactly means and whether it is generic?
> +
> + compatible:
> + const: fsl,imx-scu
> +
> + clock-controller:
> + description: |
> + $ref: /schemas/clock/fsl,scu-clk.yaml
That's not a valid syntax. ref is not part of description
> + Clock controller node that provides the clocks controlled by the SCU
> +
> + imx8qx-ocotp:
> + description: |
> + $ref: /schemas/nvmem/fsl,scu-ocotp.yaml
> + OCOTP controller node provided by the SCU
> +
> + keys:
> + description: |
> + $ref: /schemas/input/fsl,scu-key.yaml
> + Keys provided by the SCU
> +
> + mboxes:
> + description: |
> + $ref: /schemas/mailbox/fsl,mu.yaml
> + List of phandle of 4 MU channels for tx, 4 MU channels for
> + rx, and 1 optional MU channel for general interrupt.
> + All MU channels must be in the same MU instance.
> + Cross instances are not allowed. The MU instance can only
> + be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need
> + to make sure use the one which is not conflict with other
> + execution environments. e.g. ATF.
> + minItems: 1
> + maxItems: 10
> +
> + mbox-names:
> + description:
> + include "gip3" if want to support general MU interrupt.
> + minItems: 1
> + maxItems: 10
> +
> + pinctrl:
> + description: |
> + $ref: /schemas/pinctrl/fsl,scu-pinctrl.yaml
> + Pin controller provided by the SCU
> +
> + power-controller:
> + description: |
> + $ref: /schemas/power/fsl,scu-pd.yaml
> + Power domains controller node that provides the power domains
> + controlled by the SCU
> +
> + rtc:
> + description: |
> + $ref: /schemas/rtc/fsl,scu-rtc.yaml
> + RTC controller provided by the SCU
> +
> + thermal-sensor:
> + description: |
> + $ref: /schemas/thermal/fsl,scu-thermal.yaml
> + Thermal sensor provided by the SCU
> +
> + watchdog:
> + description: |
> + $ref: /schemas/watchdog/fsl,scu-wdt.yaml
> + Watchdog controller provided by the SCU
> +
> +required:
> + - compatible
> + - mbox-names
> + - mboxes
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/firmware/imx/rsrc.h>
> + #include <dt-bindings/input/input.h>
> + #include <dt-bindings/pinctrl/pads-imx8qxp.h>
> +
> + firmware {
> + scu {
> + compatible = "fsl,imx-scu";
> + mbox-names = "tx0", "tx1", "tx2", "tx3",
> + "rx0", "rx1", "rx2", "rx3",
> + "gip3";
> + mboxes = <&lsio_mu1 0 0
> + &lsio_mu1 0 1
> + &lsio_mu1 0 2
> + &lsio_mu1 0 3
> + &lsio_mu1 1 0
> + &lsio_mu1 1 1
> + &lsio_mu1 1 2
> + &lsio_mu1 1 3
> + &lsio_mu1 3 3>;
> +
> + clock-controller {
> + compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
> + #clock-cells = <2>;
> + };
> +
> + pinctrl {
> + compatible = "fsl,imx8qxp-iomuxc";
> +
> + pinctrl_lpuart0: lpuart0grp {
> + fsl,pins = <
> + IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020
> + IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020
> + >;
> + };
> + };
> +
> + imx8qx-ocotp {
> + compatible = "fsl,imx8qxp-scu-ocotp";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + fec_mac0: mac@2c4 {
> + reg = <0x2c4 6>;
> + };
> + };
> +
> + power-controller {
> + compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
> + #power-domain-cells = <1>;
> + };
> +
> + rtc {
> + compatible = "fsl,imx8qxp-sc-rtc";
> + };
> +
> + keys {
> + compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
> + linux,keycodes = <KEY_POWER>;
> + };
> +
> + watchdog {
> + compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
> + timeout-sec = <60>;
> + };
> +
> + thermal-sensor {
> + compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
> + #thermal-sensor-cells = <1>;
> + };
> + };
> + };
Best regards,
Krzysztof
On 22-06-24 12:25:44, Krzysztof Kozlowski wrote:
> On 16/06/2022 18:42, Viorel Suman wrote:
> > From: Abel Vesa <[email protected]>
> >
> > In order to replace the fsl,scu txt file from bindings/arm/freescale,
> > we need to split it between the right subsystems. This patch adds the
> > fsl,scu.yaml in the firmware bindings folder. This one is only for
> > the main SCU node. The old txt file will be removed only after all
> > the child nodes have been properly switch to yaml.
> >
> > Signed-off-by: Abel Vesa <[email protected]>
> > Signed-off-by: Viorel Suman <[email protected]>
> > ---
> > .../devicetree/bindings/firmware/fsl,scu.yaml | 170 ++++++++++++++++++
> > 1 file changed, 170 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/firmware/fsl,scu.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/firmware/fsl,scu.yaml b/Documentation/devicetree/bindings/firmware/fsl,scu.yaml
[...]
> > +properties:
> > + $nodename:
> > + const: 'scu'
>
> Why enforcing node name? Second point is that node names should be
> generic, so I wonder what "SCU" exactly means and whether it is generic?
>
It stands for "System Control Unit" - looks generic to me.
I guess a reason to enforce it - need to check with Abel - might be
the need to group multiple SCU implementations under a common known name.
> > +
> > + compatible:
> > + const: fsl,imx-scu
> > +
> > + clock-controller:
> > + description: |
> > + $ref: /schemas/clock/fsl,scu-clk.yaml
>
> That's not a valid syntax. ref is not part of description
>
Right, will fix that, thank you for review.
Regards,
Viorel
On 27/06/2022 13:49, Viorel Suman wrote:
> On 22-06-24 12:25:44, Krzysztof Kozlowski wrote:
>> On 16/06/2022 18:42, Viorel Suman wrote:
>>> From: Abel Vesa <[email protected]>
>>>
>>> In order to replace the fsl,scu txt file from bindings/arm/freescale,
>>> we need to split it between the right subsystems. This patch adds the
>>> fsl,scu.yaml in the firmware bindings folder. This one is only for
>>> the main SCU node. The old txt file will be removed only after all
>>> the child nodes have been properly switch to yaml.
>>>
>>> Signed-off-by: Abel Vesa <[email protected]>
>>> Signed-off-by: Viorel Suman <[email protected]>
>>> ---
>>> .../devicetree/bindings/firmware/fsl,scu.yaml | 170 ++++++++++++++++++
>>> 1 file changed, 170 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/firmware/fsl,scu.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/firmware/fsl,scu.yaml b/Documentation/devicetree/bindings/firmware/fsl,scu.yaml
>
> [...]
>
>>> +properties:
>>> + $nodename:
>>> + const: 'scu'
>>
>> Why enforcing node name? Second point is that node names should be
>> generic, so I wonder what "SCU" exactly means and whether it is generic?
>>
>
> It stands for "System Control Unit" - looks generic to me.
Nope, it's specific, just like other scu - Snoop Control Unit. What's
more, reusing the same acronym leads to confusions.
If it was generic, then I expect it to be present in several other
places, but it's not (except the other SCU).
Generic name is for example "system-controller".
> I guess a reason to enforce it - need to check with Abel - might be
> the need to group multiple SCU implementations under a common known name.
Device bindings do not enforce the names, unless it's really needed, and
I doubt there is a need here. Just drop it and rename nodes in DTS to
something generic.
Best regards,
Krzysztof