LAN966x SoC flexcoms has two optional I/O lines. Namely, CS0 and CS1
in flexcom SPI mode. CTS and RTS in flexcom USART mode. These pins
can be mapped to lan966x FLEXCOM_SHARED[0-20] pins and usage depends on
functions being configured.
Signed-off-by: Kavyasree Kotagiri <[email protected]>
---
v3 -> v4:
- Added else condition to allOf:if:then.
v2 -> v3:
- Add reg property of lan966x missed in v2.
v1 -> v2:
- Use allOf:if:then for lan966x dt properties
.../bindings/mfd/atmel,flexcom.yaml | 80 ++++++++++++++++++-
1 file changed, 79 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml
index fdb1645d123f..7e0e4d6b1b96 100644
--- a/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml
+++ b/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml
@@ -18,9 +18,11 @@ properties:
compatible:
enum:
- atmel,sama5d2-flexcom
+ - microchip,lan966x-flexcom
reg:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
clocks:
maxItems: 1
@@ -47,6 +49,27 @@ properties:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2, 3]
+ microchip,flx-shrd-pins:
+ description: Specify the Flexcom shared pins to be used for flexcom
+ chip-selects.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 2
+ items:
+ minimum: 0
+ maximum: 20
+
+ microchip,flx-cs:
+ description: Flexcom chip selects. Here, value of '0' represents "cts" line
+ of flexcom USART or "cs0" line of flexcom SPI and value of '1' represents
+ "rts" line of flexcom USART or "cs1" line of flexcom SPI.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 2
+ items:
+ minimum: 0
+ maximum: 1
+
patternProperties:
"^serial@[0-9a-f]+$":
description: See atmel-usart.txt for details of USART bindings.
@@ -73,6 +96,33 @@ required:
- ranges
- atmel,flexcom-mode
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: microchip,lan966x-flexcom
+
+ then:
+ properties:
+ reg:
+ minItems: 2
+ items:
+ - description: Flexcom base regsiters map
+ - description: Flexcom shared registers map
+ required:
+ - microchip,flx-shrd-pins
+ - microchip,flx-cs
+
+ else:
+ properties:
+ reg:
+ maxItems: 1
+ items:
+ - description: Flexcom base regsiters map
+ microchip,flx-shrd-pins: false
+ microchip,flx-cs: false
+
additionalProperties: false
examples:
@@ -101,4 +151,32 @@ examples:
atmel,fifo-size = <32>;
};
};
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ flx3: flexcom@e0064000 {
+ compatible = "microchip,lan966x-flexcom";
+ reg = <0xe0064000 0x100>,
+ <0xe2004180 0x8>;
+ clocks = <&flx0_clk>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xe0040000 0x800>;
+ atmel,flexcom-mode = <2>;
+ microchip,flx-shrd-pins = <9>;
+ microchip,flx-cs = <0>;
+
+ spi3: spi@400 {
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx3_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&nic_clk>;
+ clock-names = "spi_clk";
+ atmel,fifo-size = <32>;
+ };
+ };
...
--
2.17.1
On Fri, 17 Jun 2022 18:37:28 +0530, Kavyasree Kotagiri wrote:
> LAN966x SoC flexcoms has two optional I/O lines. Namely, CS0 and CS1
> in flexcom SPI mode. CTS and RTS in flexcom USART mode. These pins
> can be mapped to lan966x FLEXCOM_SHARED[0-20] pins and usage depends on
> functions being configured.
>
> Signed-off-by: Kavyasree Kotagiri <[email protected]>
> ---
> v3 -> v4:
> - Added else condition to allOf:if:then.
>
> v2 -> v3:
> - Add reg property of lan966x missed in v2.
>
> v1 -> v2:
> - Use allOf:if:then for lan966x dt properties
>
> .../bindings/mfd/atmel,flexcom.yaml | 80 ++++++++++++++++++-
> 1 file changed, 79 insertions(+), 1 deletion(-)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml: allOf:0:else:properties:reg: {'maxItems': 1, 'items': [{'description': 'Flexcom base regsiters map'}]} should not be valid under {'required': ['maxItems']}
hint: "maxItems" is not needed with an "items" list
from schema $id: http://devicetree.org/meta-schemas/items.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml: allOf:0:then:properties:reg: 'oneOf' conditional failed, one must be fixed:
[{'description': 'Flexcom base regsiters map'}, {'description': 'Flexcom shared registers map'}] is too long
[{'description': 'Flexcom base regsiters map'}, {'description': 'Flexcom shared registers map'}] is too short
False schema does not allow 2
1 was expected
hint: "minItems" is only needed if less than the "items" list length
from schema $id: http://devicetree.org/meta-schemas/items.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml: ignoring, error in schema: allOf: 0: else: properties: reg
Documentation/devicetree/bindings/mfd/atmel,flexcom.example.dtb:0:0: /example-0/flexcom@f8034000: failed to match any schema with compatible: ['atmel,sama5d2-flexcom']
Documentation/devicetree/bindings/mfd/atmel,flexcom.example.dtb:0:0: /example-0/flexcom@f8034000/spi@400: failed to match any schema with compatible: ['atmel,at91rm9200-spi']
Documentation/devicetree/bindings/mfd/atmel,flexcom.example.dtb:0:0: /example-1/flexcom@e0064000: failed to match any schema with compatible: ['microchip,lan966x-flexcom']
Documentation/devicetree/bindings/mfd/atmel,flexcom.example.dtb:0:0: /example-1/flexcom@e0064000/spi@400: failed to match any schema with compatible: ['atmel,at91rm9200-spi']
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
On 17/06/2022 06:07, Kavyasree Kotagiri wrote:
> LAN966x SoC flexcoms has two optional I/O lines. Namely, CS0 and CS1
> in flexcom SPI mode. CTS and RTS in flexcom USART mode. These pins
> can be mapped to lan966x FLEXCOM_SHARED[0-20] pins and usage depends on
> functions being configured.
>
> Signed-off-by: Kavyasree Kotagiri <[email protected]>
> ---
> v3 -> v4:
> - Added else condition to allOf:if:then.
>
> v2 -> v3:
> - Add reg property of lan966x missed in v2.
>
> v1 -> v2:
> - Use allOf:if:then for lan966x dt properties
>
> .../bindings/mfd/atmel,flexcom.yaml | 80 ++++++++++++++++++-
> 1 file changed, 79 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml
> index fdb1645d123f..7e0e4d6b1b96 100644
> --- a/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml
> +++ b/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml
> @@ -18,9 +18,11 @@ properties:
> compatible:
> enum:
> - atmel,sama5d2-flexcom
> + - microchip,lan966x-flexcom
This looks good now.
>
> reg:
> - maxItems: 1
> + minItems: 1
> + maxItems: 2
>
> clocks:
> maxItems: 1
> @@ -47,6 +49,27 @@ properties:
> $ref: /schemas/types.yaml#/definitions/uint32
> enum: [1, 2, 3]
>
> + microchip,flx-shrd-pins:
> + description: Specify the Flexcom shared pins to be used for flexcom
> + chip-selects.
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + minItems: 1
> + maxItems: 2
> + items:
> + minimum: 0
> + maximum: 20
> +
> + microchip,flx-cs:
> + description: Flexcom chip selects. Here, value of '0' represents "cts" line
> + of flexcom USART or "cs0" line of flexcom SPI and value of '1' represents
> + "rts" line of flexcom USART or "cs1" line of flexcom SPI.
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + minItems: 1
> + maxItems: 2
> + items:
> + minimum: 0
> + maximum: 1
> +
> patternProperties:
> "^serial@[0-9a-f]+$":
> description: See atmel-usart.txt for details of USART bindings.
> @@ -73,6 +96,33 @@ required:
> - ranges
> - atmel,flexcom-mode
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: microchip,lan966x-flexcom
> +
> + then:
> + properties:
> + reg:
> + minItems: 2
> + items:
> + - description: Flexcom base regsiters map
typo here - registers
> + - description: Flexcom shared registers map
> + required:
> + - microchip,flx-shrd-pins
> + - microchip,flx-cs
> +
> + else:
> + properties:
> + reg:
> + maxItems: 1
I think maxItems are not needed in such case. Rob's bot complains, so be
sure you test your bindings before sending.
> + items:
> + - description: Flexcom base regsiters map
typo
> + microchip,flx-shrd-pins: false
> + microchip,flx-cs: false
> +
> additionalProperties: false
>
> examples:
> @@ -101,4 +151,32 @@ examples:
> atmel,fifo-size = <32>;
> };
> };
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + flx3: flexcom@e0064000 {
> + compatible = "microchip,lan966x-flexcom";
Just like in patch #1 = wrong indentation. 4 spaces for the DTS example.
> + reg = <0xe0064000 0x100>,
> + <0xe2004180 0x8>;
> + clocks = <&flx0_clk>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0xe0040000 0x800>;
> + atmel,flexcom-mode = <2>;
> + microchip,flx-shrd-pins = <9>;
> + microchip,flx-cs = <0>;
> +
> + spi3: spi@400 {
> + compatible = "atmel,at91rm9200-spi";
> + reg = <0x400 0x200>;
> + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flx3_default>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&nic_clk>;
> + clock-names = "spi_clk";
> + atmel,fifo-size = <32>;
> + };
> + };
> ...
Best regards,
Krzysztof