2019-12-23 14:31:49

by Vinod Koul

Subject: [PATCH v3 0/4] phy: qcom-qmp: Fixes and updates for sm8150

For SM8150 we need additional SW reset so clear the no_pcs_sw_reset, and add
SW reset register. Along with that remove duplicate powerdown write.

Changes in v3:
- Drop patch 1 "phy: qcom-qmp: Increase PHY ready timeout" as that is
applied by Kishon
- Drop patch "phy: qcom-qmp: Add optional SW reset" as that is no longer
required
- Add "phy: qcom-qmp: Add SW reset register"

Changes in v2:
- Drop patch 1 and pick the one Bjorn had already sent, makes timeout 10ms
- Fix optional reset write as pointed by Can
- Fix register define as pointed by Can

Vinod Koul (4):
phy: qcom-qmp: Use register defines
phy: qcom-qmp: remove duplicate powerdown write
phy: qcom-qmp: remove no_pcs_sw_reset for sm8150
phy: qcom-qmp: Add SW reset register

drivers/phy/qualcomm/phy-qcom-qmp.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)

--
2.23.0

2019-12-23 14:32:04

by Vinod Koul

Subject: [PATCH v3 2/4] phy: qcom-qmp: remove duplicate powerdown write

We already write to QPHY_POWER_DOWN_CONTROL in qcom_qmp_phy_com_init()
before invoking qcom_qmp_phy_configure() so remove the duplicate write.

Signed-off-by: Vinod Koul <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 1 -
1 file changed, 1 deletion(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 1196c85aa023..4f2e65c7cf45 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -885,7 +885,6 @@ static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
};

static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
- QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
--
2.23.0

2019-12-23 14:32:40

by Vinod Koul

Subject: [PATCH v3 3/4] phy: qcom-qmp: remove no_pcs_sw_reset for sm8150

SM8150 QMPY phy for UFS and onwards the PHY_SW_RESET is present in PHY's
PCS register so we should not mark no_pcs_sw_reset for sm8150 and
onwards

Signed-off-by: Vinod Koul <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 1 -
1 file changed, 1 deletion(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 4f2e65c7cf45..ce5e18f188c3 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -1389,7 +1389,6 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
.pwrdn_ctrl = SW_PWRDN,

.is_dual_lane_phy = true,
- .no_pcs_sw_reset = true,
};

static void qcom_qmp_phy_configure(void __iomem *base,
--
2.23.0

2019-12-23 14:33:04

by Vinod Koul

Subject: [PATCH v3 1/4] phy: qcom-qmp: Use register defines

We already define register offsets so use them in register layout.

Signed-off-by: Vinod Koul <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 66f91726b8b2..1196c85aa023 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -166,8 +166,8 @@ static const unsigned int sdm845_ufsphy_regs_layout[] = {
};

static const unsigned int sm8150_ufsphy_regs_layout[] = {
- [QPHY_START_CTRL] = 0x00,
- [QPHY_PCS_READY_STATUS] = 0x180,
+ [QPHY_START_CTRL] = QPHY_V4_PHY_START,
+ [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_READY_STATUS,
};

static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
--
2.23.0

2019-12-23 14:33:16

by Vinod Koul

Subject: [PATCH v3 4/4] phy: qcom-qmp: Add SW reset register

For V4 QMP UFS Phy, we need to assert reset bits, configure the phy and
then deassert it, so add the QPHY_SW_RESET register which does this.

Signed-off-by: Vinod Koul <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index ce5e18f188c3..7db2a94f7a99 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -168,6 +168,7 @@ static const unsigned int sdm845_ufsphy_regs_layout[] = {
static const unsigned int sm8150_ufsphy_regs_layout[] = {
[QPHY_START_CTRL] = QPHY_V4_PHY_START,
[QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_READY_STATUS,
+ [QPHY_SW_RESET] = QPHY_V4_SW_RESET,
};

static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
--
2.23.0

2019-12-24 03:40:19

by Manu Gautam

Subject: Re: [PATCH v3 3/4] phy: qcom-qmp: remove no_pcs_sw_reset for sm8150

On 12/23/2019 8:00 PM, Vinod Koul wrote:
> SM8150 QMPY phy for UFS and onwards the PHY_SW_RESET is present in PHY's
> PCS register so we should not mark no_pcs_sw_reset for sm8150 and
> onwards
>
> Signed-off-by: Vinod Koul <[email protected]>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
> index 4f2e65c7cf45..ce5e18f188c3 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
> @@ -1389,7 +1389,6 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
> .pwrdn_ctrl = SW_PWRDN,
>
> .is_dual_lane_phy = true,
> - .no_pcs_sw_reset = true,
> };
>

Reviewed-by: Manu Gautam <[email protected]>

--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

2019-12-24 03:41:12

by Manu Gautam

Subject: Re: [PATCH v3 2/4] phy: qcom-qmp: remove duplicate powerdown write

On 12/23/2019 8:00 PM, Vinod Koul wrote:
> We already write to QPHY_POWER_DOWN_CONTROL in qcom_qmp_phy_com_init()
> before invoking qcom_qmp_phy_configure() so remove the duplicate write.
>
> Signed-off-by: Vinod Koul <[email protected]>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
> index 1196c85aa023..4f2e65c7cf45 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
> @@ -885,7 +885,6 @@ static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
> };
>
> static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
> - QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
> QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
> QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
> QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),

Reviewed-by: Manu Gautam <[email protected]>

--

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

2019-12-24 03:41:46

by Manu Gautam

Subject: Re: [PATCH v3 4/4] phy: qcom-qmp: Add SW reset register

On 12/23/2019 8:00 PM, Vinod Koul wrote:
> For V4 QMP UFS Phy, we need to assert reset bits, configure the phy and
> then deassert it, so add the QPHY_SW_RESET register which does this.
>
> Signed-off-by: Vinod Koul <[email protected]>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
> index ce5e18f188c3..7db2a94f7a99 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
> @@ -168,6 +168,7 @@ static const unsigned int sdm845_ufsphy_regs_layout[] = {
> static const unsigned int sm8150_ufsphy_regs_layout[] = {
> [QPHY_START_CTRL] = QPHY_V4_PHY_START,
> [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_READY_STATUS,
> + [QPHY_SW_RESET] = QPHY_V4_SW_RESET,
> };
>
> static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {

Reviewed-by: Manu Gautam <[email protected]>


--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

2019-12-24 03:42:48

by Manu Gautam

Subject: Re: [PATCH v3 1/4] phy: qcom-qmp: Use register defines

On 12/23/2019 8:00 PM, Vinod Koul wrote:
> We already define register offsets so use them in register layout.
>
> Signed-off-by: Vinod Koul <[email protected]>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
> index 66f91726b8b2..1196c85aa023 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
> @@ -166,8 +166,8 @@ static const unsigned int sdm845_ufsphy_regs_layout[] = {
> };
>
> static const unsigned int sm8150_ufsphy_regs_layout[] = {
> - [QPHY_START_CTRL] = 0x00,
> - [QPHY_PCS_READY_STATUS] = 0x180,
> + [QPHY_START_CTRL] = QPHY_V4_PHY_START,
> + [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_READY_STATUS,
> };
>
> static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {

Reviewed-by: Manu Gautam <[email protected]>


--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

2019-12-24 05:51:48

by Can Guo

Subject: Re: [PATCH v3 1/4] phy: qcom-qmp: Use register defines

On 2019-12-23 22:30, Vinod Koul wrote:
> We already define register offsets so use them in register layout.
>
> Signed-off-by: Vinod Koul <[email protected]>

Reviewed-by: Can Guo <[email protected]>

> ---
> drivers/phy/qualcomm/phy-qcom-qmp.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
> b/drivers/phy/qualcomm/phy-qcom-qmp.c
> index 66f91726b8b2..1196c85aa023 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
> @@ -166,8 +166,8 @@ static const unsigned int
> sdm845_ufsphy_regs_layout[] = {
> };
>
> static const unsigned int sm8150_ufsphy_regs_layout[] = {
> - [QPHY_START_CTRL] = 0x00,
> - [QPHY_PCS_READY_STATUS] = 0x180,
> + [QPHY_START_CTRL] = QPHY_V4_PHY_START,
> + [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_READY_STATUS,
> };
>
> static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {

2019-12-24 05:56:23

by Can Guo

Subject: Re: [PATCH v3 3/4] phy: qcom-qmp: remove no_pcs_sw_reset for sm8150

On 2019-12-23 22:30, Vinod Koul wrote:
> SM8150 QMPY phy for UFS and onwards the PHY_SW_RESET is present in
> PHY's
> PCS register so we should not mark no_pcs_sw_reset for sm8150 and
> onwards
>
> Signed-off-by: Vinod Koul <[email protected]>

Reviewed-by: Can Guo <[email protected]>

> ---
> drivers/phy/qualcomm/phy-qcom-qmp.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
> b/drivers/phy/qualcomm/phy-qcom-qmp.c
> index 4f2e65c7cf45..ce5e18f188c3 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
> @@ -1389,7 +1389,6 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg
> = {
> .pwrdn_ctrl = SW_PWRDN,
>
> .is_dual_lane_phy = true,
> - .no_pcs_sw_reset = true,
> };
>
> static void qcom_qmp_phy_configure(void __iomem *base,

2019-12-24 05:57:23

by Can Guo

Subject: Re: [PATCH v3 2/4] phy: qcom-qmp: remove duplicate powerdown write

On 2019-12-23 22:30, Vinod Koul wrote:
> We already write to QPHY_POWER_DOWN_CONTROL in qcom_qmp_phy_com_init()
> before invoking qcom_qmp_phy_configure() so remove the duplicate write.
>
> Signed-off-by: Vinod Koul <[email protected]>

Reviewed-by: Can Guo <[email protected]>

> ---
> drivers/phy/qualcomm/phy-qcom-qmp.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
> b/drivers/phy/qualcomm/phy-qcom-qmp.c
> index 1196c85aa023..4f2e65c7cf45 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
> @@ -885,7 +885,6 @@ static const struct qmp_phy_init_tbl
> msm8998_usb3_pcs_tbl[] = {
> };
>
> static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
> - QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
> QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
> QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
> QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),

2019-12-24 05:57:42

by Can Guo

Subject: Re: [PATCH v3 4/4] phy: qcom-qmp: Add SW reset register

On 2019-12-23 22:30, Vinod Koul wrote:
> For V4 QMP UFS Phy, we need to assert reset bits, configure the phy and
> then deassert it, so add the QPHY_SW_RESET register which does this.
>
> Signed-off-by: Vinod Koul <[email protected]>

Reviewed-by: Can Guo <[email protected]>

> ---
> drivers/phy/qualcomm/phy-qcom-qmp.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
> b/drivers/phy/qualcomm/phy-qcom-qmp.c
> index ce5e18f188c3..7db2a94f7a99 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
> @@ -168,6 +168,7 @@ static const unsigned int
> sdm845_ufsphy_regs_layout[] = {
> static const unsigned int sm8150_ufsphy_regs_layout[] = {
> [QPHY_START_CTRL] = QPHY_V4_PHY_START,
> [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_READY_STATUS,
> + [QPHY_SW_RESET] = QPHY_V4_SW_RESET,
> };
>
> static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {

2020-01-03 06:22:58

by Vinod Koul

Subject: Re: [PATCH v3 0/4] phy: qcom-qmp: Fixes and updates for sm8150

Hi Kishon,

On 23-12-19, 20:00, Vinod Koul wrote:
> For SM8150 we need additional SW reset so clear the no_pcs_sw_reset, and add
> SW reset register. Along with that remove duplicate powerdown write.

Any update on this series?

Thanks
>
> Changes in v3:
> - Drop patch 1 "phy: qcom-qmp: Increase PHY ready timeout" as that is
> applied by Kishon
> - Drop patch "phy: qcom-qmp: Add optional SW reset" as that is no longer
> required
> - Add "phy: qcom-qmp: Add SW reset register"
>
> Changes in v2:
> - Drop patch 1 and pick the one Bjorn had already sent, makes timeout 10ms
> - Fix optional reset write as pointed by Can
> - Fix register define as pointed by Can
>
> Vinod Koul (4):
> phy: qcom-qmp: Use register defines
> phy: qcom-qmp: remove duplicate powerdown write
> phy: qcom-qmp: remove no_pcs_sw_reset for sm8150
> phy: qcom-qmp: Add SW reset register
>
> drivers/phy/qualcomm/phy-qcom-qmp.c | 7 +++----
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> --
> 2.23.0

--
~Vinod