This patch series is based on 5.16-rc6.
change since v1:
- remove vppsys in clock document
- unregister clock when fail to add clock provider
Chun-Jie Chen (3):
clk: mediatek: Add error handle when fail to register clock provider
dt-bindings: ARM: Mediatek: Remove vppsys in MT8195 clock document
clk: mediatek: Integrate vppsys with mtk-mmsys in MT8195
.../arm/mediatek/mediatek,mt8195-clock.yaml | 16 -------
drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 5 ++-
drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 5 ++-
drivers/clk/mediatek/clk-mt8195-topckgen.c | 5 ++-
drivers/clk/mediatek/clk-mt8195-vdo0.c | 5 ++-
drivers/clk/mediatek/clk-mt8195-vdo1.c | 5 ++-
drivers/clk/mediatek/clk-mt8195-vpp0.c | 42 ++++++++++++-------
drivers/clk/mediatek/clk-mt8195-vpp1.c | 42 ++++++++++++-------
drivers/clk/mediatek/clk-mtk.c | 14 ++++++-
drivers/clk/mediatek/clk-mtk.h | 1 +
10 files changed, 89 insertions(+), 51 deletions(-)
--
2.18.0
Need to deference registered clocks when fail to
regisiter clock provider.
Signed-off-by: Chun-Jie Chen <[email protected]>
---
drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 5 ++++-
drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 5 +++--
drivers/clk/mediatek/clk-mt8195-topckgen.c | 5 ++++-
drivers/clk/mediatek/clk-mt8195-vdo0.c | 5 ++++-
drivers/clk/mediatek/clk-mt8195-vdo1.c | 5 ++++-
drivers/clk/mediatek/clk-mtk.c | 14 +++++++++++++-
drivers/clk/mediatek/clk-mtk.h | 1 +
7 files changed, 33 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
index 6156ceeed71e..be0a716e24d2 100644
--- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
@@ -126,10 +126,13 @@ static int clk_mt8195_apmixed_probe(struct platform_device *pdev)
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
if (r)
- goto free_apmixed_data;
+ goto unregister_clk;
return r;
+unregister_clk:
+ mtk_clk_unregister(clk_data);
+
free_apmixed_data:
mtk_free_clk_data(clk_data);
return r;
diff --git a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c b/drivers/clk/mediatek/clk-mt8195-apusys_pll.c
index f1c84186346e..bc5fc84e48dd 100644
--- a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c
+++ b/drivers/clk/mediatek/clk-mt8195-apusys_pll.c
@@ -68,11 +68,12 @@ static int clk_mt8195_apusys_pll_probe(struct platform_device *pdev)
mtk_clk_register_plls(node, apusys_plls, ARRAY_SIZE(apusys_plls), clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
if (r)
- goto free_apusys_pll_data;
+ goto unregister_clk;
return r;
-free_apusys_pll_data:
+unregister_clk:
+ mtk_clk_unregister(clk_data);
mtk_free_clk_data(clk_data);
return r;
}
diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/mediatek/clk-mt8195-topckgen.c
index 3e2aba9c40bb..02a1801dfe86 100644
--- a/drivers/clk/mediatek/clk-mt8195-topckgen.c
+++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c
@@ -1254,10 +1254,13 @@ static int clk_mt8195_topck_probe(struct platform_device *pdev)
r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
if (r)
- goto free_top_data;
+ goto unregister_clk;
return r;
+unregister_clk:
+ mtk_clk_unregister(top_clk_data);
+
free_top_data:
mtk_free_clk_data(top_clk_data);
return r;
diff --git a/drivers/clk/mediatek/clk-mt8195-vdo0.c b/drivers/clk/mediatek/clk-mt8195-vdo0.c
index f7ff7618c714..b7ceb6c7a33f 100644
--- a/drivers/clk/mediatek/clk-mt8195-vdo0.c
+++ b/drivers/clk/mediatek/clk-mt8195-vdo0.c
@@ -105,10 +105,13 @@ static int clk_mt8195_vdo0_probe(struct platform_device *pdev)
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
if (r)
- goto free_vdo0_data;
+ goto unregister_clk;
return r;
+unregister_clk:
+ mtk_clk_unregister(clk_data);
+
free_vdo0_data:
mtk_free_clk_data(clk_data);
return r;
diff --git a/drivers/clk/mediatek/clk-mt8195-vdo1.c b/drivers/clk/mediatek/clk-mt8195-vdo1.c
index 03df8eae8838..cca90c2632a1 100644
--- a/drivers/clk/mediatek/clk-mt8195-vdo1.c
+++ b/drivers/clk/mediatek/clk-mt8195-vdo1.c
@@ -122,10 +122,13 @@ static int clk_mt8195_vdo1_probe(struct platform_device *pdev)
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
if (r)
- goto free_vdo1_data;
+ goto unregister_clk;
return r;
+unregister_clk:
+ mtk_clk_unregister(clk_data);
+
free_vdo1_data:
mtk_free_clk_data(clk_data);
return r;
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 8d5791b3f460..ee4de1094458 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -303,6 +303,15 @@ void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds,
}
}
+void mtk_clk_unregister(struct clk_onecell_data *clk_data)
+{
+ int i;
+
+ for (i = 0; i < clk_data->clk_num; i++)
+ clk_unregister(clk_data->clks[i]);
+}
+EXPORT_SYMBOL_GPL(mtk_clk_unregister);
+
int mtk_clk_simple_probe(struct platform_device *pdev)
{
const struct mtk_clk_desc *mcd;
@@ -324,10 +333,13 @@ int mtk_clk_simple_probe(struct platform_device *pdev)
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
if (r)
- goto free_data;
+ goto unregister_clk;
return r;
+unregister_clk:
+ mtk_clk_unregister(clk_data);
+
free_data:
mtk_free_clk_data(clk_data);
return r;
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 0ff289d93452..4c0958f66f51 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -200,6 +200,7 @@ struct mtk_clk_divider {
void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds,
int num, void __iomem *base, spinlock_t *lock,
struct clk_onecell_data *clk_data);
+void mtk_clk_unregister(struct clk_onecell_data *clk_data);
struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
void mtk_free_clk_data(struct clk_onecell_data *clk_data);
--
2.18.0
vppsys0 and vppsys1 sub-system are both integrated with mmsys driver,
should be describe in mediatek,mmsys.yaml
Signed-off-by: Chun-Jie Chen <[email protected]>
---
.../arm/mediatek/mediatek,mt8195-clock.yaml | 16 ----------------
1 file changed, 16 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
index 17fcbb45d121..d62d60181147 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
@@ -28,11 +28,9 @@ properties:
- mediatek,mt8195-imp_iic_wrap_s
- mediatek,mt8195-imp_iic_wrap_w
- mediatek,mt8195-mfgcfg
- - mediatek,mt8195-vppsys0
- mediatek,mt8195-wpesys
- mediatek,mt8195-wpesys_vpp0
- mediatek,mt8195-wpesys_vpp1
- - mediatek,mt8195-vppsys1
- mediatek,mt8195-imgsys
- mediatek,mt8195-imgsys1_dip_top
- mediatek,mt8195-imgsys1_dip_nr
@@ -92,13 +90,6 @@ examples:
#clock-cells = <1>;
};
- - |
- vppsys0: clock-controller@14000000 {
- compatible = "mediatek,mt8195-vppsys0";
- reg = <0x14000000 0x1000>;
- #clock-cells = <1>;
- };
-
- |
wpesys: clock-controller@14e00000 {
compatible = "mediatek,mt8195-wpesys";
@@ -120,13 +111,6 @@ examples:
#clock-cells = <1>;
};
- - |
- vppsys1: clock-controller@14f00000 {
- compatible = "mediatek,mt8195-vppsys1";
- reg = <0x14f00000 0x1000>;
- #clock-cells = <1>;
- };
-
- |
imgsys: clock-controller@15000000 {
compatible = "mediatek,mt8195-imgsys";
--
2.18.0
Integrate vpp0 and vpp1 with mtk-mmsys driver which
will populate device by platform_device_register_data
to start vppsys clock driver.
Signed-off-by: Chun-Jie Chen <[email protected]>
---
drivers/clk/mediatek/clk-mt8195-vpp0.c | 42 +++++++++++++++++---------
drivers/clk/mediatek/clk-mt8195-vpp1.c | 42 +++++++++++++++++---------
2 files changed, 56 insertions(+), 28 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt8195-vpp0.c b/drivers/clk/mediatek/clk-mt8195-vpp0.c
index c3241466a8d0..68c375bfce8b 100644
--- a/drivers/clk/mediatek/clk-mt8195-vpp0.c
+++ b/drivers/clk/mediatek/clk-mt8195-vpp0.c
@@ -86,25 +86,39 @@ static const struct mtk_gate vpp0_clks[] = {
GATE_VPP0_2(CLK_VPP0_WARP1_MDP_DL_ASYNC, "vpp0_warp1_mdp_dl_async", "top_wpe_vpp", 3),
};
-static const struct mtk_clk_desc vpp0_desc = {
- .clks = vpp0_clks,
- .num_clks = ARRAY_SIZE(vpp0_clks),
-};
+static int clk_mt8195_vpp0_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *node = dev->parent->of_node;
+ struct clk_onecell_data *clk_data;
+ int r;
-static const struct of_device_id of_match_clk_mt8195_vpp0[] = {
- {
- .compatible = "mediatek,mt8195-vppsys0",
- .data = &vpp0_desc,
- }, {
- /* sentinel */
- }
-};
+ clk_data = mtk_alloc_clk_data(CLK_VPP0_NR_CLK);
+ if (!clk_data)
+ return -ENOMEM;
+
+ r = mtk_clk_register_gates(node, vpp0_clks, ARRAY_SIZE(vpp0_clks), clk_data);
+ if (r)
+ goto free_vpp0_data;
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ goto unregister_clk;
+
+ return r;
+
+unregister_clk:
+ mtk_clk_unregister(clk_data);
+
+free_vpp0_data:
+ mtk_free_clk_data(clk_data);
+ return r;
+}
static struct platform_driver clk_mt8195_vpp0_drv = {
- .probe = mtk_clk_simple_probe,
+ .probe = clk_mt8195_vpp0_probe,
.driver = {
.name = "clk-mt8195-vpp0",
- .of_match_table = of_match_clk_mt8195_vpp0,
},
};
builtin_platform_driver(clk_mt8195_vpp0_drv);
diff --git a/drivers/clk/mediatek/clk-mt8195-vpp1.c b/drivers/clk/mediatek/clk-mt8195-vpp1.c
index ce0b9a40a179..237077c60f54 100644
--- a/drivers/clk/mediatek/clk-mt8195-vpp1.c
+++ b/drivers/clk/mediatek/clk-mt8195-vpp1.c
@@ -84,25 +84,39 @@ static const struct mtk_gate vpp1_clks[] = {
GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_26M, "vpp1_vpp_split_26m", "clk26m", 26),
};
-static const struct mtk_clk_desc vpp1_desc = {
- .clks = vpp1_clks,
- .num_clks = ARRAY_SIZE(vpp1_clks),
-};
+static int clk_mt8195_vpp1_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *node = dev->parent->of_node;
+ struct clk_onecell_data *clk_data;
+ int r;
-static const struct of_device_id of_match_clk_mt8195_vpp1[] = {
- {
- .compatible = "mediatek,mt8195-vppsys1",
- .data = &vpp1_desc,
- }, {
- /* sentinel */
- }
-};
+ clk_data = mtk_alloc_clk_data(CLK_VPP1_NR_CLK);
+ if (!clk_data)
+ return -ENOMEM;
+
+ r = mtk_clk_register_gates(node, vpp1_clks, ARRAY_SIZE(vpp1_clks), clk_data);
+ if (r)
+ goto free_vpp1_data;
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ goto unregister_clk;
+
+ return r;
+
+unregister_clk:
+ mtk_clk_unregister(clk_data);
+
+free_vpp1_data:
+ mtk_free_clk_data(clk_data);
+ return r;
+}
static struct platform_driver clk_mt8195_vpp1_drv = {
- .probe = mtk_clk_simple_probe,
+ .probe = clk_mt8195_vpp1_probe,
.driver = {
.name = "clk-mt8195-vpp1",
- .of_match_table = of_match_clk_mt8195_vpp1,
},
};
builtin_platform_driver(clk_mt8195_vpp1_drv);
--
2.18.0
Il 10/01/22 01:59, Chun-Jie Chen ha scritto:
> Need to deference registered clocks when fail to
> regisiter clock provider.
>
> Signed-off-by: Chun-Jie Chen <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Il 10/01/22 01:59, Chun-Jie Chen ha scritto:
> Integrate vpp0 and vpp1 with mtk-mmsys driver which
> will populate device by platform_device_register_data
> to start vppsys clock driver.
>
> Signed-off-by: Chun-Jie Chen <[email protected]>
Hello Chun-Jie,
I agree with this series and I would be happy to give you my R-b, but
this patch will make these clocks to *never* probe in in the targeted
kernel version.
You forgot to mention that this patch will break vpp0/vpp1 clocks entirely
unless applied on top of patch series [1].
Please, either mention that said series is *required* for this one to work
as expected, or move series [1], patches 6 and 7 to this series instead;
since the MDP3 driver will need quite a while to get merged, I would suggest
to move the patches here, as to get something "complete" to merge.
[1]: https://patchwork.kernel.org/project/linux-mediatek/list/?series=568283
> ---
> drivers/clk/mediatek/clk-mt8195-vpp0.c | 42 +++++++++++++++++---------
> drivers/clk/mediatek/clk-mt8195-vpp1.c | 42 +++++++++++++++++---------
> 2 files changed, 56 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/clk/mediatek/clk-mt8195-vpp0.c b/drivers/clk/mediatek/clk-mt8195-vpp0.c
> index c3241466a8d0..68c375bfce8b 100644
> --- a/drivers/clk/mediatek/clk-mt8195-vpp0.c
> +++ b/drivers/clk/mediatek/clk-mt8195-vpp0.c
> @@ -86,25 +86,39 @@ static const struct mtk_gate vpp0_clks[] = {
> GATE_VPP0_2(CLK_VPP0_WARP1_MDP_DL_ASYNC, "vpp0_warp1_mdp_dl_async", "top_wpe_vpp", 3),
> };
>
> -static const struct mtk_clk_desc vpp0_desc = {
> - .clks = vpp0_clks,
> - .num_clks = ARRAY_SIZE(vpp0_clks),
> -};
> +static int clk_mt8195_vpp0_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *node = dev->parent->of_node;
> + struct clk_onecell_data *clk_data;
> + int r;
>
> -static const struct of_device_id of_match_clk_mt8195_vpp0[] = {
> - {
> - .compatible = "mediatek,mt8195-vppsys0",
> - .data = &vpp0_desc,
> - }, {
> - /* sentinel */
> - }
> -};
> + clk_data = mtk_alloc_clk_data(CLK_VPP0_NR_CLK);
> + if (!clk_data)
> + return -ENOMEM;
> +
> + r = mtk_clk_register_gates(node, vpp0_clks, ARRAY_SIZE(vpp0_clks), clk_data);
> + if (r)
> + goto free_vpp0_data;
> +
> + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> + if (r)
> + goto unregister_clk;
> +
> + return r;
> +
> +unregister_clk:
> + mtk_clk_unregister(clk_data);
> +
> +free_vpp0_data:
> + mtk_free_clk_data(clk_data);
> + return r;
> +}
>
> static struct platform_driver clk_mt8195_vpp0_drv = {
> - .probe = mtk_clk_simple_probe,
> + .probe = clk_mt8195_vpp0_probe,
> .driver = {
> .name = "clk-mt8195-vpp0",
> - .of_match_table = of_match_clk_mt8195_vpp0,
> },
> };
> builtin_platform_driver(clk_mt8195_vpp0_drv);
> diff --git a/drivers/clk/mediatek/clk-mt8195-vpp1.c b/drivers/clk/mediatek/clk-mt8195-vpp1.c
> index ce0b9a40a179..237077c60f54 100644
> --- a/drivers/clk/mediatek/clk-mt8195-vpp1.c
> +++ b/drivers/clk/mediatek/clk-mt8195-vpp1.c
> @@ -84,25 +84,39 @@ static const struct mtk_gate vpp1_clks[] = {
> GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_26M, "vpp1_vpp_split_26m", "clk26m", 26),
> };
>
> -static const struct mtk_clk_desc vpp1_desc = {
> - .clks = vpp1_clks,
> - .num_clks = ARRAY_SIZE(vpp1_clks),
> -};
> +static int clk_mt8195_vpp1_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *node = dev->parent->of_node;
> + struct clk_onecell_data *clk_data;
> + int r;
>
> -static const struct of_device_id of_match_clk_mt8195_vpp1[] = {
> - {
> - .compatible = "mediatek,mt8195-vppsys1",
> - .data = &vpp1_desc,
> - }, {
> - /* sentinel */
> - }
> -};
> + clk_data = mtk_alloc_clk_data(CLK_VPP1_NR_CLK);
> + if (!clk_data)
> + return -ENOMEM;
> +
> + r = mtk_clk_register_gates(node, vpp1_clks, ARRAY_SIZE(vpp1_clks), clk_data);
> + if (r)
> + goto free_vpp1_data;
> +
> + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> + if (r)
> + goto unregister_clk;
> +
> + return r;
> +
> +unregister_clk:
> + mtk_clk_unregister(clk_data);
> +
> +free_vpp1_data:
> + mtk_free_clk_data(clk_data);
> + return r;
> +}
>
> static struct platform_driver clk_mt8195_vpp1_drv = {
> - .probe = mtk_clk_simple_probe,
> + .probe = clk_mt8195_vpp1_probe,
> .driver = {
> .name = "clk-mt8195-vpp1",
> - .of_match_table = of_match_clk_mt8195_vpp1,
> },
> };
> builtin_platform_driver(clk_mt8195_vpp1_drv);
>
--
AngeloGioacchino Del Regno
Software Engineer
Collabora Ltd.
Platinum Building, St John's Innovation Park, Cambridge CB4 0DS, UK
Registered in England & Wales, no. 5513718
On Mon, Jan 10, 2022 at 08:59:01AM +0800, Chun-Jie Chen wrote:
> vppsys0 and vppsys1 sub-system are both integrated with mmsys driver,
> should be describe in mediatek,mmsys.yaml
Driver partitioning is not a reason to change the DT. This needs a
better description answering why you are doing this and what are the
implications (is this breaking the ABI?).
>
> Signed-off-by: Chun-Jie Chen <[email protected]>
> ---
> .../arm/mediatek/mediatek,mt8195-clock.yaml | 16 ----------------
> 1 file changed, 16 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
> index 17fcbb45d121..d62d60181147 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
> @@ -28,11 +28,9 @@ properties:
> - mediatek,mt8195-imp_iic_wrap_s
> - mediatek,mt8195-imp_iic_wrap_w
> - mediatek,mt8195-mfgcfg
> - - mediatek,mt8195-vppsys0
> - mediatek,mt8195-wpesys
> - mediatek,mt8195-wpesys_vpp0
> - mediatek,mt8195-wpesys_vpp1
> - - mediatek,mt8195-vppsys1
> - mediatek,mt8195-imgsys
> - mediatek,mt8195-imgsys1_dip_top
> - mediatek,mt8195-imgsys1_dip_nr
> @@ -92,13 +90,6 @@ examples:
> #clock-cells = <1>;
> };
>
> - - |
> - vppsys0: clock-controller@14000000 {
> - compatible = "mediatek,mt8195-vppsys0";
> - reg = <0x14000000 0x1000>;
> - #clock-cells = <1>;
> - };
> -
> - |
> wpesys: clock-controller@14e00000 {
> compatible = "mediatek,mt8195-wpesys";
> @@ -120,13 +111,6 @@ examples:
> #clock-cells = <1>;
> };
>
> - - |
> - vppsys1: clock-controller@14f00000 {
> - compatible = "mediatek,mt8195-vppsys1";
> - reg = <0x14f00000 0x1000>;
> - #clock-cells = <1>;
> - };
> -
> - |
> imgsys: clock-controller@15000000 {
> compatible = "mediatek,mt8195-imgsys";
> --
> 2.18.0
>
>