2022-02-14 18:52:23

by liuqi (BA)

Subject: [PATCH 2/2] perf jevents: Add support for HiSilicon CPA PMU aliasing

Add support for HiSilicon CPA PMU aliasing.

The kernel driver is in drivers/perf/hisilicon/hisi_uncore_cpa_pmu.c

Signed-off-by: Qi Liu <[email protected]>
---
.../arm64/hisilicon/hip09/sys/uncore-cpa.json | 81 +++++++++++++++++++
tools/perf/pmu-events/jevents.c | 1 +
2 files changed, 82 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-cpa.json

diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-cpa.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-cpa.json
new file mode 100644
index 000000000000..35c90da7f54b
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-cpa.json
@@ -0,0 +1,81 @@
+[
+ {
+ "ConfigCode": "0x00",
+ "EventName": "cpa_cycles",
+ "BriefDescription": "count of CPA cycles",
+ "Compat": "0x00000030",
+ "Unit": "hisi_sicl,cpa"
+ },
+ {
+ "ConfigCode": "0x61",
+ "EventName": "p1_wr_dat",
+ "BriefDescription": "Number of write ops transmitted by the P1 port",
+ "Compat": "0x00000030",
+ "Unit": "hisi_sicl,cpa"
+ },
+ {
+ "ConfigCode": "0x62",
+ "EventName": "p1_rd_dat",
+ "BriefDescription": "Number of read ops transmitted by the P1 port",
+ "Compat": "0x00000030",
+ "Unit": "hisi_sicl,cpa"
+ },
+ {
+ "ConfigCode": "0x3",
+ "EventName": "p1_rd_dat_64b",
+ "BriefDescription": "Number of read ops transmitted by the P1 port which size is 64 bytes",
+ "Compat": "0x00000030",
+ "Unit": "hisi_sicl,cpa"
+ },
+ {
+ "ConfigCode": "0x4",
+ "EventName": "p1_rd_dat_32b",
+ "BriefDescription": "Number of read ops transmitted by the P1 port which size is 32 bytes",
+ "Compat": "0x00000030",
+ "Unit": "hisi_sicl,cpa"
+ },
+ {
+ "ConfigCode": "0xE1",
+ "EventName": "p0_wr_dat",
+ "BriefDescription": "Number of write ops transmitted by the P0 port",
+ "Compat": "0x00000030",
+ "Unit": "hisi_sicl,cpa"
+ },
+ {
+ "ConfigCode": "0xE2",
+ "EventName": "p0_rd_dat",
+ "BriefDescription": "Number of read ops transmitted by the P0 port",
+ "Compat": "0x00000030",
+ "Unit": "hisi_sicl,cpa"
+ },
+ {
+ "ConfigCode": "0x83",
+ "EventName": "p0_rd_dat_64b",
+ "BriefDescription": "Number of read ops transmitted by the P0 port which size is 64 bytes",
+ "Compat": "0x00000030",
+ "Unit": "hisi_sicl,cpa"
+ },
+ {
+ "ConfigCode": "0x84",
+ "EventName": "p0_rd_dat_32b",
+ "BriefDescription": "Number of read ops transmitted by the P0 port which size is 32 bytes",
+ "Compat": "0x00000030",
+ "Unit": "hisi_sicl,cpa"
+ },
+ {
+ "MetricExpr": "(p1_wr_dat * 64 + p1_rd_dat_64b * 64 + p1_rd_dat_32b * 32) / cpa_cycles",
+ "BriefDescription": "Average bandwidth of CPA Port 1",
+ "MetricGroup": "CPA",
+ "MetricName": "p1_avg_bw",
+ "Compat": "0x00000030",
+ "Unit": "hisi_sicl,cpa"
+ },
+ {
+ "MetricExpr": "(p0_wr_dat * 64 + p0_rd_dat_64b * 64 + p0_rd_dat_32b * 32) / cpa_cycles",
+ "BriefDescription": "Average bandwidth of CPA Port 0",
+ "MetricGroup": "CPA",
+ "MetricName": "p0_avg_bw",
+ "Compat": "0x00000030",
+ "Unit": "hisi_sicl,cpa"
+ }
+]
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index 1a57c3f81dd4..159d9eab6e79 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -277,6 +277,7 @@ static struct map {
{ "CPU-M-CF", "cpum_cf" },
{ "CPU-M-SF", "cpum_sf" },
{ "UPI LL", "uncore_upi" },
+ { "hisi_sicl,cpa", "hisi_sicl,cpa"},
{ "hisi_sccl,ddrc", "hisi_sccl,ddrc" },
{ "hisi_sccl,hha", "hisi_sccl,hha" },
{ "hisi_sccl,l3c", "hisi_sccl,l3c" },
--
2.24.0

2022-02-14 19:51:09

by John Garry

Subject: Re: [PATCH 2/2] perf jevents: Add support for HiSilicon CPA PMU aliasing

On 14/02/2022 11:42, Qi Liu wrote:
> Add support for HiSilicon CPA PMU aliasing.
>
> The kernel driver is in drivers/perf/hisilicon/hisi_uncore_cpa_pmu.c
>
> Signed-off-by: Qi Liu<[email protected]>

You realy should cc the perf tool list and maintainers there also.

Reviewed-by: John Garry <[email protected]>

> + },
> + {
> + "MetricExpr": "(p0_wr_dat * 64 + p0_rd_dat_64b * 64 + p0_rd_dat_32b * 32) / cpa_cycles",
> + "BriefDescription": "Average bandwidth of CPA Port 0",
> + "MetricGroup": "CPA",

nit: maybe this should have a more distrinct name

> + "MetricName": "p0_avg_bw",
> + "Compat": "0x00000030",

JFYI, I have a rewrite of the perf tool system pmu metric support that
will not require us to add the compat here.

> + "Unit": "hisi_sicl,cpa"

Thanks,
John

2022-02-15 02:03:46

by liuqi (BA)

Subject: Re: [PATCH 2/2] perf jevents: Add support for HiSilicon CPA PMU aliasing

On 2022/2/14 20:04, John Garry wrote:
> On 14/02/2022 11:42, Qi Liu wrote:
>> Add support for HiSilicon CPA PMU aliasing.
>>
>> The kernel driver is in drivers/perf/hisilicon/hisi_uncore_cpa_pmu.c
>>
>> Signed-off-by: Qi Liu<[email protected]>
>
> You realy should cc the perf tool list and maintainers there also.
>
> Reviewed-by: John Garry <[email protected]>
>
>> +    },
>> +    {
>> +        "MetricExpr": "(p0_wr_dat * 64 + p0_rd_dat_64b * 64 +
>> p0_rd_dat_32b * 32) / cpa_cycles",
>> +        "BriefDescription": "Average bandwidth of CPA Port 0",
>> +        "MetricGroup": "CPA",
>
Hi john,

> nit: maybe this should have a more distrinct name

got it, will change metric's name next version.

>
>> +        "MetricName": "p0_avg_bw",
>> +        "Compat": "0x00000030",
>
> JFYI, I have a rewrite of the perf tool system pmu metric support that
> will not require us to add the compat here.
>
great! I'm very glad to test it using CPA PMU.

Thanks,
Qi
>> +        "Unit": "hisi_sicl,cpa"
>
> Thanks,
> John
> .

2022-02-15 03:21:41

by liuqi (BA)

Subject: Re: [PATCH 2/2] perf jevents: Add support for HiSilicon CPA PMU aliasing

+CC perf tool list and maintainers.

Qi

On 2022/2/14 19:42, Qi Liu wrote:
> Add support for HiSilicon CPA PMU aliasing.
>
> The kernel driver is in drivers/perf/hisilicon/hisi_uncore_cpa_pmu.c
>
> Signed-off-by: Qi Liu <[email protected]>
> ---
> .../arm64/hisilicon/hip09/sys/uncore-cpa.json | 81 +++++++++++++++++++
> tools/perf/pmu-events/jevents.c | 1 +
> 2 files changed, 82 insertions(+)
> create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-cpa.json
>
> diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-cpa.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-cpa.json
> new file mode 100644
> index 000000000000..35c90da7f54b
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-cpa.json
> @@ -0,0 +1,81 @@
> +[
> + {
> + "ConfigCode": "0x00",
> + "EventName": "cpa_cycles",
> + "BriefDescription": "count of CPA cycles",
> + "Compat": "0x00000030",
> + "Unit": "hisi_sicl,cpa"
> + },
> + {
> + "ConfigCode": "0x61",
> + "EventName": "p1_wr_dat",
> + "BriefDescription": "Number of write ops transmitted by the P1 port",
> + "Compat": "0x00000030",
> + "Unit": "hisi_sicl,cpa"
> + },
> + {
> + "ConfigCode": "0x62",
> + "EventName": "p1_rd_dat",
> + "BriefDescription": "Number of read ops transmitted by the P1 port",
> + "Compat": "0x00000030",
> + "Unit": "hisi_sicl,cpa"
> + },
> + {
> + "ConfigCode": "0x3",
> + "EventName": "p1_rd_dat_64b",
> + "BriefDescription": "Number of read ops transmitted by the P1 port which size is 64 bytes",
> + "Compat": "0x00000030",
> + "Unit": "hisi_sicl,cpa"
> + },
> + {
> + "ConfigCode": "0x4",
> + "EventName": "p1_rd_dat_32b",
> + "BriefDescription": "Number of read ops transmitted by the P1 port which size is 32 bytes",
> + "Compat": "0x00000030",
> + "Unit": "hisi_sicl,cpa"
> + },
> + {
> + "ConfigCode": "0xE1",
> + "EventName": "p0_wr_dat",
> + "BriefDescription": "Number of write ops transmitted by the P0 port",
> + "Compat": "0x00000030",
> + "Unit": "hisi_sicl,cpa"
> + },
> + {
> + "ConfigCode": "0xE2",
> + "EventName": "p0_rd_dat",
> + "BriefDescription": "Number of read ops transmitted by the P0 port",
> + "Compat": "0x00000030",
> + "Unit": "hisi_sicl,cpa"
> + },
> + {
> + "ConfigCode": "0x83",
> + "EventName": "p0_rd_dat_64b",
> + "BriefDescription": "Number of read ops transmitted by the P0 port which size is 64 bytes",
> + "Compat": "0x00000030",
> + "Unit": "hisi_sicl,cpa"
> + },
> + {
> + "ConfigCode": "0x84",
> + "EventName": "p0_rd_dat_32b",
> + "BriefDescription": "Number of read ops transmitted by the P0 port which size is 32 bytes",
> + "Compat": "0x00000030",
> + "Unit": "hisi_sicl,cpa"
> + },
> + {
> + "MetricExpr": "(p1_wr_dat * 64 + p1_rd_dat_64b * 64 + p1_rd_dat_32b * 32) / cpa_cycles",
> + "BriefDescription": "Average bandwidth of CPA Port 1",
> + "MetricGroup": "CPA",
> + "MetricName": "p1_avg_bw",
> + "Compat": "0x00000030",
> + "Unit": "hisi_sicl,cpa"
> + },
> + {
> + "MetricExpr": "(p0_wr_dat * 64 + p0_rd_dat_64b * 64 + p0_rd_dat_32b * 32) / cpa_cycles",
> + "BriefDescription": "Average bandwidth of CPA Port 0",
> + "MetricGroup": "CPA",
> + "MetricName": "p0_avg_bw",
> + "Compat": "0x00000030",
> + "Unit": "hisi_sicl,cpa"
> + }
> +]
> diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
> index 1a57c3f81dd4..159d9eab6e79 100644
> --- a/tools/perf/pmu-events/jevents.c
> +++ b/tools/perf/pmu-events/jevents.c
> @@ -277,6 +277,7 @@ static struct map {
> { "CPU-M-CF", "cpum_cf" },
> { "CPU-M-SF", "cpum_sf" },
> { "UPI LL", "uncore_upi" },
> + { "hisi_sicl,cpa", "hisi_sicl,cpa"},
> { "hisi_sccl,ddrc", "hisi_sccl,ddrc" },
> { "hisi_sccl,hha", "hisi_sccl,hha" },
> { "hisi_sccl,l3c", "hisi_sccl,l3c" },
>