Changes in v7:
- Fix up the sclk_sfc parent error in rk3036
- Unify to "rockchip,sfc" compatible id because all the feature update
will have a new IP version, so the driver is used for the SFC IP in
all SoCs
- Change to use node "sfc" to name the SFC pinctrl group
- Add subnode reg property check
- Add rockchip_sfc_adjust_op_size to workaround in CMD + DUMMY case
- Limit max_iosize to 32KB
Changes in v6:
- Add support in device trees for rv1126(Declared in series 5 but not
submitted)
- Change to use "clk_sfc" "hclk_sfc" as clock lable, since it does not
affect interpretation and has been widely used
- Support sfc tx_dual, tx_quad(Declared in series 5 but not submitted)
- Simplify the code, such as remove "rockchip_sfc_register_all"(Declared
in series 5 but not submitted)
- Support SFC ver4 ver5(Declared in series 5 but not submitted)
- Add author Chris Morgan and Jon Lin to spi-rockchip-sfc.c
- Change to use devm_spi_alloc_master and spi_unregister_master
Changes in v5:
- Add support in device trees for rv1126
- Support sfc tx_dual, tx_quad
- Simplify the code, such as remove "rockchip_sfc_register_all"
- Support SFC ver4 ver5
Changes in v4:
- Changing patch back to an "RFC". An engineer from Rockchip
reached out to me to let me know they are working on this patch for
upstream, I am submitting this v4 for the community to see however
I expect Jon Lin ([email protected]) will submit new patches
soon and these are the ones we should pursue for mainlining. Jon's
patch series should include support for more hardware than this
series.
- Clean up documentation more and ensure it is correct per
make dt_binding_check.
- Add support in device trees for rk3036, rk3308, and rv1108.
- Add ahb clock (hclk_sfc) support for rk3036.
- Change rockchip_sfc_wait_fifo_ready() to use a switch statement.
- Change IRQ code to only mark IRQ as handled if it handles the
specific IRQ (DMA transfer finish) it is supposed to handle.
Changes in v3:
- Changed the name of the clocks to sfc/ahb (from clk-sfc/clk-hsfc).
- Changed the compatible string from rockchip,sfc to
rockchip,rk3036-sfc. A quick glance at the datasheets suggests this
driver should work for the PX30, RK180x, RK3036, RK312x, RK3308 and
RV1108 SoCs, and possibly more. However, I am currently only able
to test this on a PX30 (an RK3326). The technical reference manuals
appear to list the same registers for each device.
- Corrected devicetree documentation for formatting and to note these
changes.
- Replaced the maintainer with Heiko Stuebner and myself, as we will
take ownership of this going forward.
- Noted that the device (per the reference manual) supports 4 CS, but
I am only able to test a single CS (CS 0).
- Reordered patches to comply with upstream rules.
Changes in v2:
- Reimplemented driver using spi-mem subsystem.
- Removed power management code as I couldn't get it working properly.
- Added device tree bindings for Odroid Go Advance.
Changes in v1:
hanges made in this new series versus the v8 of the old series:
- Added function to read spi-rx-bus-width from device tree, in the
event that the SPI chip supports 4x mode but only has 2 pins
wired (such as the Odroid Go Advance).
- Changed device tree documentation from txt to yaml format.
- Made "reset" message a dev_dbg from a dev_info.
- Changed read and write fifo functions to remove redundant checks.
- Changed the write and read from relaxed to non-relaxed when
starting the DMA transfer or reading the DMA IRQ.
- Changed from dma_coerce_mask_and_coherent to just
dma_set_mask_and_coherent.
- Changed name of get_if_type to rockchip_sfc_get_if_type.
Chris Morgan (8):
dt-bindings: rockchip-sfc: Bindings for Rockchip serial flash
controller
spi: rockchip-sfc: add rockchip serial flash controller
arm64: dts: rockchip: Add SFC to PX30
clk: rockchip: Add support for hclk_sfc on rk3036
arm: dts: rockchip: Add SFC to RK3036
arm: dts: rockchip: Add SFC to RV1108
arm64: dts: rockchip: Add SFC to RK3308
arm64: dts: rockchip: Enable SFC for Odroid Go Advance
Jon Lin (1):
clk: rockchip: rk3036: fix up the sclk_sfc parent error
.../devicetree/bindings/spi/rockchip-sfc.yaml | 88 +++
arch/arm/boot/dts/rk3036.dtsi | 42 ++
arch/arm/boot/dts/rv1108.dtsi | 37 +
arch/arm64/boot/dts/rockchip/px30.dtsi | 38 +
arch/arm64/boot/dts/rockchip/rk3308.dtsi | 37 +
.../boot/dts/rockchip/rk3326-odroid-go2.dts | 16 +
drivers/clk/rockchip/clk-rk3036.c | 5 +-
drivers/spi/Kconfig | 9 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-rockchip-sfc.c | 676 ++++++++++++++++++
include/dt-bindings/clock/rk3036-cru.h | 1 +
11 files changed, 948 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/rockchip-sfc.yaml
create mode 100644 drivers/spi/spi-rockchip-sfc.c
--
2.17.1
From: Chris Morgan <[email protected]>
Add bindings for the Rockchip serial flash controller. New device
specific parameter of rockchip,sfc-no-dma included in documentation.
Signed-off-by: Chris Morgan <[email protected]>
Signed-off-by: Jon Lin <[email protected]>
---
Changes in v7:
- Fix up the sclk_sfc parent error in rk3036
- Unify to "rockchip,sfc" compatible id because all the feature update
will have a new IP version, so the driver is used for the SFC IP in
all SoCs
- Change to use node "sfc" to name the SFC pinctrl group
- Add subnode reg property check
- Add rockchip_sfc_adjust_op_size to workaround in CMD + DUMMY case
- Limit max_iosize to 32KB
Changes in v6:
- Add support in device trees for rv1126(Declared in series 5 but not
submitted)
- Change to use "clk_sfc" "hclk_sfc" as clock lable, since it does not
affect interpretation and has been widely used
- Support sfc tx_dual, tx_quad(Declared in series 5 but not submitted)
- Simplify the code, such as remove "rockchip_sfc_register_all"(Declared
in series 5 but not submitted)
- Support SFC ver4 ver5(Declared in series 5 but not submitted)
- Add author Chris Morgan and Jon Lin to spi-rockchip-sfc.c
- Change to use devm_spi_alloc_master and spi_unregister_master
Changes in v5:
- Add support in device trees for rv1126
- Support sfc tx_dual, tx_quad
- Simplify the code, such as remove "rockchip_sfc_register_all"
- Support SFC ver4 ver5
Changes in v4:
- Changing patch back to an "RFC". An engineer from Rockchip
reached out to me to let me know they are working on this patch for
upstream, I am submitting this v4 for the community to see however
I expect Jon Lin ([email protected]) will submit new patches
soon and these are the ones we should pursue for mainlining. Jon's
patch series should include support for more hardware than this
series.
- Clean up documentation more and ensure it is correct per
make dt_binding_check.
- Add support in device trees for rk3036, rk3308, and rv1108.
- Add ahb clock (hclk_sfc) support for rk3036.
- Change rockchip_sfc_wait_fifo_ready() to use a switch statement.
- Change IRQ code to only mark IRQ as handled if it handles the
specific IRQ (DMA transfer finish) it is supposed to handle.
Changes in v3:
- Changed the name of the clocks to sfc/ahb (from clk-sfc/clk-hsfc).
- Changed the compatible string from rockchip,sfc to
rockchip,rk3036-sfc. A quick glance at the datasheets suggests this
driver should work for the PX30, RK180x, RK3036, RK312x, RK3308 and
RV1108 SoCs, and possibly more. However, I am currently only able
to test this on a PX30 (an RK3326). The technical reference manuals
appear to list the same registers for each device.
- Corrected devicetree documentation for formatting and to note these
changes.
- Replaced the maintainer with Heiko Stuebner and myself, as we will
take ownership of this going forward.
- Noted that the device (per the reference manual) supports 4 CS, but
I am only able to test a single CS (CS 0).
- Reordered patches to comply with upstream rules.
Changes in v2:
- Reimplemented driver using spi-mem subsystem.
- Removed power management code as I couldn't get it working properly.
- Added device tree bindings for Odroid Go Advance.
Changes in v1:
hanges made in this new series versus the v8 of the old series:
- Added function to read spi-rx-bus-width from device tree, in the
event that the SPI chip supports 4x mode but only has 2 pins
wired (such as the Odroid Go Advance).
- Changed device tree documentation from txt to yaml format.
- Made "reset" message a dev_dbg from a dev_info.
- Changed read and write fifo functions to remove redundant checks.
- Changed the write and read from relaxed to non-relaxed when
starting the DMA transfer or reading the DMA IRQ.
- Changed from dma_coerce_mask_and_coherent to just
dma_set_mask_and_coherent.
- Changed name of get_if_type to rockchip_sfc_get_if_type.
.../devicetree/bindings/spi/rockchip-sfc.yaml | 88 +++++++++++++++++++
1 file changed, 88 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/rockchip-sfc.yaml
diff --git a/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml b/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml
new file mode 100644
index 000000000000..42e4198e92af
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/rockchip-sfc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip Serial Flash Controller (SFC)
+
+maintainers:
+ - Heiko Stuebner <[email protected]>
+ - Chris Morgan <[email protected]>
+
+allOf:
+ - $ref: spi-controller.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - const: rockchip,sfc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Bus Clock
+ - description: Module Clock
+
+ clock-names:
+ items:
+ - const: clk_sfc
+ - const: hclk_sfc
+
+ power-domains:
+ maxItems: 1
+
+ rockchip,sfc-no-dma:
+ description: Disable DMA and utilize FIFO mode only
+ type: boolean
+
+patternProperties:
+ "^flash@[0-3]$":
+ type: object
+ properties:
+ reg:
+ minimum: 0
+ maximum: 3
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/px30-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/px30-power.h>
+
+ sfc: spi@ff3a0000 {
+ compatible = "rockchip,sfc";
+ reg = <0xff3a0000 0x4000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>;
+ pinctrl-names = "default";
+ power-domains = <&power PX30_PD_MMC_NAND>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <108000000>;
+ spi-rx-bus-width = <2>;
+ spi-tx-bus-width = <2>;
+ };
+ };
+
+...
--
2.17.1
From: Chris Morgan <[email protected]>
Add a devicetree entry for the Rockchip SFC for the PX30 SOC.
Signed-off-by: Chris Morgan <[email protected]>
Signed-off-by: Jon Lin <[email protected]>
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
Changes in v1: None
arch/arm64/boot/dts/rockchip/px30.dtsi | 38 ++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index 09baa8a167ce..d854f2577067 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -966,6 +966,18 @@
status = "disabled";
};
+ sfc: spi@ff3a0000 {
+ compatible = "rockchip,sfc";
+ reg = <0x0 0xff3a0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
+ pinctrl-names = "default";
+ power-domains = <&power PX30_PD_MMC_NAND>;
+ status = "disabled";
+ };
+
nfc: nand-controller@ff3b0000 {
compatible = "rockchip,px30-nfc";
reg = <0x0 0xff3b0000 0x0 0x4000>;
@@ -1967,6 +1979,32 @@
};
};
+ sfc {
+ sfc_bus4: sfc-bus4 {
+ rockchip,pins =
+ <1 RK_PA0 3 &pcfg_pull_none>,
+ <1 RK_PA1 3 &pcfg_pull_none>,
+ <1 RK_PA2 3 &pcfg_pull_none>,
+ <1 RK_PA3 3 &pcfg_pull_none>;
+ };
+
+ sfc_bus2: sfc-bus2 {
+ rockchip,pins =
+ <1 RK_PA0 3 &pcfg_pull_none>,
+ <1 RK_PA1 3 &pcfg_pull_none>;
+ };
+
+ sfc_cs0: sfc-cs0 {
+ rockchip,pins =
+ <1 RK_PA4 3 &pcfg_pull_none>;
+ };
+
+ sfc_clk: sfc-clk {
+ rockchip,pins =
+ <1 RK_PB1 3 &pcfg_pull_none>;
+ };
+ };
+
lcdc {
lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
rockchip,pins =
--
2.17.1
From: Chris Morgan <[email protected]>
Add support for the bus clock for the serial flash controller on the
rk3036. Taken from the Rockchip BSP kernel but not tested on real
hardware (as I lack a 3036 based SoC to test).
Signed-off-by: Chris Morgan <[email protected]>
Signed-off-by: Jon Lin <[email protected]>
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
Changes in v1: None
drivers/clk/rockchip/clk-rk3036.c | 2 +-
include/dt-bindings/clock/rk3036-cru.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index 1986856d94b2..828af715d92e 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -404,7 +404,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS),
GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 3, GFLAGS),
GATE(HCLK_I2S, "hclk_i2s", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
- GATE(0, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS),
+ GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS),
GATE(HCLK_MAC, "hclk_mac", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS),
/* pclk_peri gates */
diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h
index 35a5a01f9697..a96a9870ad59 100644
--- a/include/dt-bindings/clock/rk3036-cru.h
+++ b/include/dt-bindings/clock/rk3036-cru.h
@@ -81,6 +81,7 @@
#define HCLK_OTG0 449
#define HCLK_OTG1 450
#define HCLK_NANDC 453
+#define HCLK_SFC 454
#define HCLK_SDMMC 456
#define HCLK_SDIO 457
#define HCLK_EMMC 459
--
2.17.1
Choose the correct pll
Signed-off-by: Elaine Zhang <[email protected]>
Signed-off-by: Jon Lin <[email protected]>
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
Changes in v1: None
drivers/clk/rockchip/clk-rk3036.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index 91d56ad45817..1986856d94b2 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -121,6 +121,7 @@ PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" };
PNAME(mux_timer_p) = { "xin24m", "pclk_peri_src" };
PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll", "usb480m" };
+PNAME(mux_pll_src_dmyapll_dpll_gpll_xin24_p) = { "dummy_apll", "dpll", "gpll", "xin24m" };
PNAME(mux_mmc_src_p) = { "apll", "dpll", "gpll", "xin24m" };
PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
@@ -340,7 +341,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
RK2928_CLKSEL_CON(16), 8, 2, MFLAGS, 10, 5, DFLAGS,
RK2928_CLKGATE_CON(10), 4, GFLAGS),
- COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_apll_dpll_gpll_usb480m_p, 0,
+ COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_dmyapll_dpll_gpll_xin24_p, 0,
RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS,
RK2928_CLKGATE_CON(10), 5, GFLAGS),
--
2.17.1
From: Chris Morgan <[email protected]>
Add a devicetree entry for the Rockchip SFC for the RK3036 SOC.
Signed-off-by: Chris Morgan <[email protected]>
Signed-off-by: Jon Lin <[email protected]>
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
Changes in v1: None
arch/arm/boot/dts/rk3036.dtsi | 42 +++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index e24230d50a78..06e37be81393 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -206,6 +206,17 @@
status = "disabled";
};
+ sfc: spi@10208000 {
+ compatible = "rockchip,sfc";
+ reg = <0x10208000 0x4000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
sdmmc: mmc@10214000 {
compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x10214000 0x4000>;
@@ -684,6 +695,37 @@
};
};
+ sfc {
+ sfc_bus4: sfc-bus4 {
+ rockchip,pins =
+ <1 RK_PD0 3 &pcfg_pull_none>,
+ <1 RK_PD1 3 &pcfg_pull_none>,
+ <1 RK_PD2 3 &pcfg_pull_none>,
+ <1 RK_PD3 3 &pcfg_pull_none>;
+ };
+
+ sfc_bus2: sfc-bus2 {
+ rockchip,pins =
+ <1 RK_PD0 3 &pcfg_pull_none>,
+ <1 RK_PD1 3 &pcfg_pull_none>;
+ };
+
+ sfc_cs0: sfc-cs0 {
+ rockchip,pins =
+ <2 RK_PA2 3 &pcfg_pull_none>;
+ };
+
+ sfc_cs1: sfc-cs1 {
+ rockchip,pins =
+ <2 RK_PA3 3 &pcfg_pull_none>;
+ };
+
+ sfc_clk: sfc-clk {
+ rockchip,pins =
+ <2 RK_PA4 3 &pcfg_pull_none>;
+ };
+ };
+
emac {
emac_xfer: emac-xfer {
rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */
--
2.17.1
From: Chris Morgan <[email protected]>
This enables the Rockchip Serial Flash Controller for the Odroid Go
Advance. Note that while the attached SPI NOR flash and the controller
both support quad read mode, only 2 of the required 4 pins are present.
The rx and tx bus width is set to 2 for this reason.
Signed-off-by: Chris Morgan <[email protected]>
Signed-off-by: Jon Lin <[email protected]>
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
Changes in v1: None
.../boot/dts/rockchip/rk3326-odroid-go2.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
index 49c97f76df77..f78e11dd8447 100644
--- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
@@ -484,6 +484,22 @@
status = "okay";
};
+&sfc {
+ pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <108000000>;
+ spi-rx-bus-width = <2>;
+ spi-tx-bus-width = <2>;
+ };
+};
+
&tsadc {
status = "okay";
};
--
2.17.1
On Wed, 09 Jun 2021 22:04:04 +0800, Jon Lin wrote:
> From: Chris Morgan <[email protected]>
>
> Add bindings for the Rockchip serial flash controller. New device
> specific parameter of rockchip,sfc-no-dma included in documentation.
>
> Signed-off-by: Chris Morgan <[email protected]>
> Signed-off-by: Jon Lin <[email protected]>
> ---
>
> Changes in v7:
> - Fix up the sclk_sfc parent error in rk3036
> - Unify to "rockchip,sfc" compatible id because all the feature update
> will have a new IP version, so the driver is used for the SFC IP in
> all SoCs
> - Change to use node "sfc" to name the SFC pinctrl group
> - Add subnode reg property check
> - Add rockchip_sfc_adjust_op_size to workaround in CMD + DUMMY case
> - Limit max_iosize to 32KB
>
> Changes in v6:
> - Add support in device trees for rv1126(Declared in series 5 but not
> submitted)
> - Change to use "clk_sfc" "hclk_sfc" as clock lable, since it does not
> affect interpretation and has been widely used
> - Support sfc tx_dual, tx_quad(Declared in series 5 but not submitted)
> - Simplify the code, such as remove "rockchip_sfc_register_all"(Declared
> in series 5 but not submitted)
> - Support SFC ver4 ver5(Declared in series 5 but not submitted)
> - Add author Chris Morgan and Jon Lin to spi-rockchip-sfc.c
> - Change to use devm_spi_alloc_master and spi_unregister_master
>
> Changes in v5:
> - Add support in device trees for rv1126
> - Support sfc tx_dual, tx_quad
> - Simplify the code, such as remove "rockchip_sfc_register_all"
> - Support SFC ver4 ver5
>
> Changes in v4:
> - Changing patch back to an "RFC". An engineer from Rockchip
> reached out to me to let me know they are working on this patch for
> upstream, I am submitting this v4 for the community to see however
> I expect Jon Lin ([email protected]) will submit new patches
> soon and these are the ones we should pursue for mainlining. Jon's
> patch series should include support for more hardware than this
> series.
> - Clean up documentation more and ensure it is correct per
> make dt_binding_check.
> - Add support in device trees for rk3036, rk3308, and rv1108.
> - Add ahb clock (hclk_sfc) support for rk3036.
> - Change rockchip_sfc_wait_fifo_ready() to use a switch statement.
> - Change IRQ code to only mark IRQ as handled if it handles the
> specific IRQ (DMA transfer finish) it is supposed to handle.
>
> Changes in v3:
> - Changed the name of the clocks to sfc/ahb (from clk-sfc/clk-hsfc).
> - Changed the compatible string from rockchip,sfc to
> rockchip,rk3036-sfc. A quick glance at the datasheets suggests this
> driver should work for the PX30, RK180x, RK3036, RK312x, RK3308 and
> RV1108 SoCs, and possibly more. However, I am currently only able
> to test this on a PX30 (an RK3326). The technical reference manuals
> appear to list the same registers for each device.
> - Corrected devicetree documentation for formatting and to note these
> changes.
> - Replaced the maintainer with Heiko Stuebner and myself, as we will
> take ownership of this going forward.
> - Noted that the device (per the reference manual) supports 4 CS, but
> I am only able to test a single CS (CS 0).
> - Reordered patches to comply with upstream rules.
>
> Changes in v2:
> - Reimplemented driver using spi-mem subsystem.
> - Removed power management code as I couldn't get it working properly.
> - Added device tree bindings for Odroid Go Advance.
>
> Changes in v1:
> hanges made in this new series versus the v8 of the old series:
> - Added function to read spi-rx-bus-width from device tree, in the
> event that the SPI chip supports 4x mode but only has 2 pins
> wired (such as the Odroid Go Advance).
> - Changed device tree documentation from txt to yaml format.
> - Made "reset" message a dev_dbg from a dev_info.
> - Changed read and write fifo functions to remove redundant checks.
> - Changed the write and read from relaxed to non-relaxed when
> starting the DMA transfer or reading the DMA IRQ.
> - Changed from dma_coerce_mask_and_coherent to just
> dma_set_mask_and_coherent.
> - Changed name of get_if_type to rockchip_sfc_get_if_type.
>
> .../devicetree/bindings/spi/rockchip-sfc.yaml | 88 +++++++++++++++++++
> 1 file changed, 88 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/spi/rockchip-sfc.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
./Documentation/devicetree/bindings/spi/rockchip-sfc.yaml:45:5: [warning] wrong indentation: expected 2 but found 4 (indentation)
dtschema/dtc warnings/errors:
\ndoc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1489897
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
On Wed, Jun 09, 2021 at 10:04:04PM +0800, Jon Lin wrote:
> From: Chris Morgan <[email protected]>
>
> Add bindings for the Rockchip serial flash controller. New device
> specific parameter of rockchip,sfc-no-dma included in documentation.
>
> Signed-off-by: Chris Morgan <[email protected]>
> Signed-off-by: Jon Lin <[email protected]>
> ---
>
> Changes in v7:
> - Fix up the sclk_sfc parent error in rk3036
> - Unify to "rockchip,sfc" compatible id because all the feature update
> will have a new IP version, so the driver is used for the SFC IP in
> all SoCs
> - Change to use node "sfc" to name the SFC pinctrl group
> - Add subnode reg property check
> - Add rockchip_sfc_adjust_op_size to workaround in CMD + DUMMY case
> - Limit max_iosize to 32KB
>
> Changes in v6:
> - Add support in device trees for rv1126(Declared in series 5 but not
> submitted)
> - Change to use "clk_sfc" "hclk_sfc" as clock lable, since it does not
> affect interpretation and has been widely used
> - Support sfc tx_dual, tx_quad(Declared in series 5 but not submitted)
> - Simplify the code, such as remove "rockchip_sfc_register_all"(Declared
> in series 5 but not submitted)
> - Support SFC ver4 ver5(Declared in series 5 but not submitted)
> - Add author Chris Morgan and Jon Lin to spi-rockchip-sfc.c
> - Change to use devm_spi_alloc_master and spi_unregister_master
>
> Changes in v5:
> - Add support in device trees for rv1126
> - Support sfc tx_dual, tx_quad
> - Simplify the code, such as remove "rockchip_sfc_register_all"
> - Support SFC ver4 ver5
>
> Changes in v4:
> - Changing patch back to an "RFC". An engineer from Rockchip
> reached out to me to let me know they are working on this patch for
> upstream, I am submitting this v4 for the community to see however
> I expect Jon Lin ([email protected]) will submit new patches
> soon and these are the ones we should pursue for mainlining. Jon's
> patch series should include support for more hardware than this
> series.
> - Clean up documentation more and ensure it is correct per
> make dt_binding_check.
> - Add support in device trees for rk3036, rk3308, and rv1108.
> - Add ahb clock (hclk_sfc) support for rk3036.
> - Change rockchip_sfc_wait_fifo_ready() to use a switch statement.
> - Change IRQ code to only mark IRQ as handled if it handles the
> specific IRQ (DMA transfer finish) it is supposed to handle.
>
> Changes in v3:
> - Changed the name of the clocks to sfc/ahb (from clk-sfc/clk-hsfc).
> - Changed the compatible string from rockchip,sfc to
> rockchip,rk3036-sfc. A quick glance at the datasheets suggests this
> driver should work for the PX30, RK180x, RK3036, RK312x, RK3308 and
> RV1108 SoCs, and possibly more. However, I am currently only able
> to test this on a PX30 (an RK3326). The technical reference manuals
> appear to list the same registers for each device.
> - Corrected devicetree documentation for formatting and to note these
> changes.
> - Replaced the maintainer with Heiko Stuebner and myself, as we will
> take ownership of this going forward.
> - Noted that the device (per the reference manual) supports 4 CS, but
> I am only able to test a single CS (CS 0).
> - Reordered patches to comply with upstream rules.
>
> Changes in v2:
> - Reimplemented driver using spi-mem subsystem.
> - Removed power management code as I couldn't get it working properly.
> - Added device tree bindings for Odroid Go Advance.
>
> Changes in v1:
> hanges made in this new series versus the v8 of the old series:
> - Added function to read spi-rx-bus-width from device tree, in the
> event that the SPI chip supports 4x mode but only has 2 pins
> wired (such as the Odroid Go Advance).
> - Changed device tree documentation from txt to yaml format.
> - Made "reset" message a dev_dbg from a dev_info.
> - Changed read and write fifo functions to remove redundant checks.
> - Changed the write and read from relaxed to non-relaxed when
> starting the DMA transfer or reading the DMA IRQ.
> - Changed from dma_coerce_mask_and_coherent to just
> dma_set_mask_and_coherent.
> - Changed name of get_if_type to rockchip_sfc_get_if_type.
>
> .../devicetree/bindings/spi/rockchip-sfc.yaml | 88 +++++++++++++++++++
> 1 file changed, 88 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/spi/rockchip-sfc.yaml
>
> diff --git a/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml b/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml
> new file mode 100644
> index 000000000000..42e4198e92af
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml
> @@ -0,0 +1,88 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spi/rockchip-sfc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip Serial Flash Controller (SFC)
> +
> +maintainers:
> + - Heiko Stuebner <[email protected]>
> + - Chris Morgan <[email protected]>
> +
> +allOf:
> + - $ref: spi-controller.yaml#
> +
> +properties:
> + compatible:
> + oneOf:
> + - const: rockchip,sfc
Use 'enum' instead of oneOf+const.
You need an SoC specific compatible.
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: Bus Clock
> + - description: Module Clock
> +
> + clock-names:
> + items:
> + - const: clk_sfc
> + - const: hclk_sfc
Do you have these backwards? 'hclk' is usually an AHB bus clock.
Also, '_sfc' is redundant.
> +
> + power-domains:
> + maxItems: 1
> +
> + rockchip,sfc-no-dma:
> + description: Disable DMA and utilize FIFO mode only
> + type: boolean
> +
> +patternProperties:
> + "^flash@[0-3]$":
> + type: object
> + properties:
> + reg:
> + minimum: 0
> + maximum: 3
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/px30-cru.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/power/px30-power.h>
> +
> + sfc: spi@ff3a0000 {
> + compatible = "rockchip,sfc";
> + reg = <0xff3a0000 0x4000>;
> + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
> + clock-names = "clk_sfc", "hclk_sfc";
> + pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>;
> + pinctrl-names = "default";
> + power-domains = <&power PX30_PD_MMC_NAND>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + flash@0 {
> + compatible = "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <108000000>;
> + spi-rx-bus-width = <2>;
> + spi-tx-bus-width = <2>;
> + };
> + };
> +
> +...
> --
> 2.17.1
Hi Rob,
On 2021/6/10 上午10:43, Rob Herring wrote:
> On Wed, Jun 09, 2021 at 10:04:04PM +0800, Jon Lin wrote:
>> From: Chris Morgan <[email protected]>
>>
>> Add bindings for the Rockchip serial flash controller. New device
>> specific parameter of rockchip,sfc-no-dma included in documentation.
>>
>> Signed-off-by: Chris Morgan <[email protected]>
>> Signed-off-by: Jon Lin <[email protected]>
>> ---
>>
>> Changes in v7:
>> - Fix up the sclk_sfc parent error in rk3036
>> - Unify to "rockchip,sfc" compatible id because all the feature update
>> will have a new IP version, so the driver is used for the SFC IP in
>> all SoCs
>> - Change to use node "sfc" to name the SFC pinctrl group
>> - Add subnode reg property check
>> - Add rockchip_sfc_adjust_op_size to workaround in CMD + DUMMY case
>> - Limit max_iosize to 32KB
>>
>> Changes in v6:
>> - Add support in device trees for rv1126(Declared in series 5 but not
>> submitted)
>> - Change to use "clk_sfc" "hclk_sfc" as clock lable, since it does not
>> affect interpretation and has been widely used
>> - Support sfc tx_dual, tx_quad(Declared in series 5 but not submitted)
>> - Simplify the code, such as remove "rockchip_sfc_register_all"(Declared
>> in series 5 but not submitted)
>> - Support SFC ver4 ver5(Declared in series 5 but not submitted)
>> - Add author Chris Morgan and Jon Lin to spi-rockchip-sfc.c
>> - Change to use devm_spi_alloc_master and spi_unregister_master
>>
>> Changes in v5:
>> - Add support in device trees for rv1126
>> - Support sfc tx_dual, tx_quad
>> - Simplify the code, such as remove "rockchip_sfc_register_all"
>> - Support SFC ver4 ver5
>>
>> Changes in v4:
>> - Changing patch back to an "RFC". An engineer from Rockchip
>> reached out to me to let me know they are working on this patch for
>> upstream, I am submitting this v4 for the community to see however
>> I expect Jon Lin ([email protected]) will submit new patches
>> soon and these are the ones we should pursue for mainlining. Jon's
>> patch series should include support for more hardware than this
>> series.
>> - Clean up documentation more and ensure it is correct per
>> make dt_binding_check.
>> - Add support in device trees for rk3036, rk3308, and rv1108.
>> - Add ahb clock (hclk_sfc) support for rk3036.
>> - Change rockchip_sfc_wait_fifo_ready() to use a switch statement.
>> - Change IRQ code to only mark IRQ as handled if it handles the
>> specific IRQ (DMA transfer finish) it is supposed to handle.
>>
>> Changes in v3:
>> - Changed the name of the clocks to sfc/ahb (from clk-sfc/clk-hsfc).
>> - Changed the compatible string from rockchip,sfc to
>> rockchip,rk3036-sfc. A quick glance at the datasheets suggests this
>> driver should work for the PX30, RK180x, RK3036, RK312x, RK3308 and
>> RV1108 SoCs, and possibly more. However, I am currently only able
>> to test this on a PX30 (an RK3326). The technical reference manuals
>> appear to list the same registers for each device.
>> - Corrected devicetree documentation for formatting and to note these
>> changes.
>> - Replaced the maintainer with Heiko Stuebner and myself, as we will
>> take ownership of this going forward.
>> - Noted that the device (per the reference manual) supports 4 CS, but
>> I am only able to test a single CS (CS 0).
>> - Reordered patches to comply with upstream rules.
>>
>> Changes in v2:
>> - Reimplemented driver using spi-mem subsystem.
>> - Removed power management code as I couldn't get it working properly.
>> - Added device tree bindings for Odroid Go Advance.
>>
>> Changes in v1:
>> hanges made in this new series versus the v8 of the old series:
>> - Added function to read spi-rx-bus-width from device tree, in the
>> event that the SPI chip supports 4x mode but only has 2 pins
>> wired (such as the Odroid Go Advance).
>> - Changed device tree documentation from txt to yaml format.
>> - Made "reset" message a dev_dbg from a dev_info.
>> - Changed read and write fifo functions to remove redundant checks.
>> - Changed the write and read from relaxed to non-relaxed when
>> starting the DMA transfer or reading the DMA IRQ.
>> - Changed from dma_coerce_mask_and_coherent to just
>> dma_set_mask_and_coherent.
>> - Changed name of get_if_type to rockchip_sfc_get_if_type.
>>
>> .../devicetree/bindings/spi/rockchip-sfc.yaml | 88 +++++++++++++++++++
>> 1 file changed, 88 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/spi/rockchip-sfc.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml b/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml
>> new file mode 100644
>> index 000000000000..42e4198e92af
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml
>> @@ -0,0 +1,88 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/spi/rockchip-sfc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Rockchip Serial Flash Controller (SFC)
>> +
>> +maintainers:
>> + - Heiko Stuebner <[email protected]>
>> + - Chris Morgan <[email protected]>
>> +
>> +allOf:
>> + - $ref: spi-controller.yaml#
>> +
>> +properties:
>> + compatible:
>> + oneOf:
>> + - const: rockchip,sfc
> Use 'enum' instead of oneOf+const.
>
> You need an SoC specific compatible.
The rockchip sfc controller is a standalone IP with version register,
and the driver can
handle all the feature difference inside the IP, so we would like to use
a more generic
compatible name instead of bind to any of SoC name. So can we use
"rockchip,sfc"
like "snps,designware-spi", which is a generic one, instead of an SoC
specific compatible?
Thanks,
- Kever
On Wed, Jun 09, 2021 at 10:13:48PM +0800, Jon Lin wrote:
> From: Chris Morgan <[email protected]>
>
> This enables the Rockchip Serial Flash Controller for the Odroid Go
> Advance. Note that while the attached SPI NOR flash and the controller
> both support quad read mode, only 2 of the required 4 pins are present.
> The rx and tx bus width is set to 2 for this reason.
>
> Signed-off-by: Chris Morgan <[email protected]>
> Signed-off-by: Jon Lin <[email protected]>
> ---
>
> Changes in v7: None
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
> Changes in v1: None
>
> .../boot/dts/rockchip/rk3326-odroid-go2.dts | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
> index 49c97f76df77..f78e11dd8447 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
> @@ -484,6 +484,22 @@
> status = "okay";
> };
>
> +&sfc {
> + pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
> + pinctrl-names = "default";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "okay";
> +
> + flash@0 {
> + compatible = "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <108000000>;
> + spi-rx-bus-width = <2>;
> + spi-tx-bus-width = <2>;
Note that I am still working with Jon Lin to research this, but it was
found in testing that if I set the tx bus width to 1 the problems I
encountered in earlier are resolved. At this time I do not know if it
is an issue with the driver for the flash controller, or if the NOR, or
board itself has some sort of errata which prevent dual tx from working
correctly. Note that as of right now the flash chip I am using (an
XTX XT25F128B) is not currently supported in mainline, so it's very
possible this is some sort of errata with the chip. It's also possible
that there is something with the board that is interferring with dual
mode TX. When Jon comes back that he has tested dual mode on the SFC
with a different board/chip I will recommend that we change the tx
bus width here to a 1, and then once the XT25F128B gets mainlined we
can see if someone else has issues with dual tx mode so we can note
that as a problem with the chip. Or maybe there is something weird
with dual tx mode yet on the SFC driver/controller, I don't know yet.
I'm all too happy to work with a Rockchip engineer so things like
this can be determined before we hit mainline. :-)
The XTX25F128B driver is currently awaiting a decision on how to handle
continuation codes, as this chip ID should be using continuation codes,
but doesn't appear to return them when you query for manufacturer ID.
So I should also note in the commit here that the SFC will still be
unusable on the Odroid Go Advance until the XTX25F128B is also
mainlined.
Thank you.
> + };
> +};
> +
> &tsadc {
> status = "okay";
> };
> --
> 2.17.1
>
>
>
Hi Chris
May you attach the XT25F128B device code to me, and I'll try to work it out.
On 6/11/21 1:36 AM, Chris Morgan wrote:
> On Wed, Jun 09, 2021 at 10:13:48PM +0800, Jon Lin wrote:
>> From: Chris Morgan <[email protected]>
>>
>> This enables the Rockchip Serial Flash Controller for the Odroid Go
>> Advance. Note that while the attached SPI NOR flash and the controller
>> both support quad read mode, only 2 of the required 4 pins are present.
>> The rx and tx bus width is set to 2 for this reason.
>>
>> Signed-off-by: Chris Morgan <[email protected]>
>> Signed-off-by: Jon Lin <[email protected]>
>> ---
>>
>> Changes in v7: None
>> Changes in v6: None
>> Changes in v5: None
>> Changes in v4: None
>> Changes in v3: None
>> Changes in v2: None
>> Changes in v1: None
>>
>> .../boot/dts/rockchip/rk3326-odroid-go2.dts | 16 ++++++++++++++++
>> 1 file changed, 16 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
>> index 49c97f76df77..f78e11dd8447 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
>> +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
>> @@ -484,6 +484,22 @@
>> status = "okay";
>> };
>>
>> +&sfc {
>> + pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
>> + pinctrl-names = "default";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + status = "okay";
>> +
>> + flash@0 {
>> + compatible = "jedec,spi-nor";
>> + reg = <0>;
>> + spi-max-frequency = <108000000>;
>> + spi-rx-bus-width = <2>;
>> + spi-tx-bus-width = <2>;
> Note that I am still working with Jon Lin to research this, but it was
> found in testing that if I set the tx bus width to 1 the problems I
> encountered in earlier are resolved. At this time I do not know if it
> is an issue with the driver for the flash controller, or if the NOR, or
> board itself has some sort of errata which prevent dual tx from working
> correctly. Note that as of right now the flash chip I am using (an
> XTX XT25F128B) is not currently supported in mainline, so it's very
> possible this is some sort of errata with the chip. It's also possible
> that there is something with the board that is interferring with dual
> mode TX. When Jon comes back that he has tested dual mode on the SFC
> with a different board/chip I will recommend that we change the tx
> bus width here to a 1, and then once the XT25F128B gets mainlined we
> can see if someone else has issues with dual tx mode so we can note
> that as a problem with the chip. Or maybe there is something weird
> with dual tx mode yet on the SFC driver/controller, I don't know yet.
> I'm all too happy to work with a Rockchip engineer so things like
> this can be determined before we hit mainline. :-)
>
> The XTX25F128B driver is currently awaiting a decision on how to handle
> continuation codes, as this chip ID should be using continuation codes,
> but doesn't appear to return them when you query for manufacturer ID.
> So I should also note in the commit here that the SFC will still be
> unusable on the Odroid Go Advance until the XTX25F128B is also
> mainlined.
>
> Thank you.
>
>> + };
>> +};
>> +
>> &tsadc {
>> status = "okay";
>> };
>> --
>> 2.17.1
>>
>>
>>
>
>
On 6/11/21 11:38 AM, Chris Morgan wrote:
> On Fri, Jun 11, 2021 at 10:26:35AM +0800, Jon Lin wrote:
>> Hi Chris
>>
>> May you attach the XT25F128B device code to me, and I'll try to work it out.
> Sure, here is the patch I am using:
>
> https://patchwork.ozlabs.org/project/linux-mtd/patch/SN6PR06MB5342C82F372F37FB8E21B327A57A9@SN6PR06MB5342.namprd06.prod.outlook.com/
this patch works well in my rk3308 tx-2 rx-2 XT25F128BSSIGU case.
# dd if=/tmp/rand.img of=/dev/mtdblock0 bs=4096 seek=1024
1024+0 records in
1024+0 records out
#
# dd if=/dev/mtd0 of=/tmp/rand1.img bs=4096 skip=1024 count=1024
1024+0 records in
1024+0 records out
#
#
# md5sum /tmp/*.img
83e45a56766168b47e6db1d41b1b403d /tmp/rand.img
83e45a56766168b47e6db1d41b1b403d /tmp/rand1.img
#
# dmesg | grep XT25F128BSSIGU
[ 0.200738] spi-nor spi3.0: XT25F128BSSIGU (16384 Kbytes)
#
>
>> On 6/11/21 1:36 AM, Chris Morgan wrote:
>>> On Wed, Jun 09, 2021 at 10:13:48PM +0800, Jon Lin wrote:
>>>> From: Chris Morgan <[email protected]>
>>>>
>>>> This enables the Rockchip Serial Flash Controller for the Odroid Go
>>>> Advance. Note that while the attached SPI NOR flash and the controller
>>>> both support quad read mode, only 2 of the required 4 pins are present.
>>>> The rx and tx bus width is set to 2 for this reason.
>>>>
>>>> Signed-off-by: Chris Morgan <[email protected]>
>>>> Signed-off-by: Jon Lin <[email protected]>
>>>> ---
>>>>
>>>> Changes in v7: None
>>>> Changes in v6: None
>>>> Changes in v5: None
>>>> Changes in v4: None
>>>> Changes in v3: None
>>>> Changes in v2: None
>>>> Changes in v1: None
>>>>
>>>> .../boot/dts/rockchip/rk3326-odroid-go2.dts | 16 ++++++++++++++++
>>>> 1 file changed, 16 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
>>>> index 49c97f76df77..f78e11dd8447 100644
>>>> --- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
>>>> +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
>>>> @@ -484,6 +484,22 @@
>>>> status = "okay";
>>>> };
>>>> +&sfc {
>>>> + pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
>>>> + pinctrl-names = "default";
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> + status = "okay";
>>>> +
>>>> + flash@0 {
>>>> + compatible = "jedec,spi-nor";
>>>> + reg = <0>;
>>>> + spi-max-frequency = <108000000>;
>>>> + spi-rx-bus-width = <2>;
>>>> + spi-tx-bus-width = <2>;
>>> Note that I am still working with Jon Lin to research this, but it was
>>> found in testing that if I set the tx bus width to 1 the problems I
>>> encountered in earlier are resolved. At this time I do not know if it
>>> is an issue with the driver for the flash controller, or if the NOR, or
>>> board itself has some sort of errata which prevent dual tx from working
>>> correctly. Note that as of right now the flash chip I am using (an
>>> XTX XT25F128B) is not currently supported in mainline, so it's very
>>> possible this is some sort of errata with the chip. It's also possible
>>> that there is something with the board that is interferring with dual
>>> mode TX. When Jon comes back that he has tested dual mode on the SFC
>>> with a different board/chip I will recommend that we change the tx
>>> bus width here to a 1, and then once the XT25F128B gets mainlined we
>>> can see if someone else has issues with dual tx mode so we can note
>>> that as a problem with the chip. Or maybe there is something weird
>>> with dual tx mode yet on the SFC driver/controller, I don't know yet.
>>> I'm all too happy to work with a Rockchip engineer so things like
>>> this can be determined before we hit mainline. :-)
>>>
>>> The XTX25F128B driver is currently awaiting a decision on how to handle
>>> continuation codes, as this chip ID should be using continuation codes,
>>> but doesn't appear to return them when you query for manufacturer ID.
>>> So I should also note in the commit here that the SFC will still be
>>> unusable on the Odroid Go Advance until the XTX25F128B is also
>>> mainlined.
>>>
>>> Thank you.
>>>
>>>> + };
>>>> +};
>>>> +
>>>> &tsadc {
>>>> status = "okay";
>>>> };
>>>> --
>>>> 2.17.1
>>>>
>>>>
>>>>
>>>
>>
>
>
Hi all,
On Thu, 10 Jun 2021 at 00:04, Kever Yang <[email protected]> wrote:
>
> Hi Rob,
>
> On 2021/6/10 上午10:43, Rob Herring wrote:
> > On Wed, Jun 09, 2021 at 10:04:04PM +0800, Jon Lin wrote:
> >> From: Chris Morgan <[email protected]>
> >>
> >> Add bindings for the Rockchip serial flash controller. New device
> >> specific parameter of rockchip,sfc-no-dma included in documentation.
> >>
> >> Signed-off-by: Chris Morgan <[email protected]>
> >> Signed-off-by: Jon Lin <[email protected]>
> >> ---
> >>
> >> Changes in v7:
> >> - Fix up the sclk_sfc parent error in rk3036
> >> - Unify to "rockchip,sfc" compatible id because all the feature update
> >> will have a new IP version, so the driver is used for the SFC IP in
> >> all SoCs
> >> - Change to use node "sfc" to name the SFC pinctrl group
> >> - Add subnode reg property check
> >> - Add rockchip_sfc_adjust_op_size to workaround in CMD + DUMMY case
> >> - Limit max_iosize to 32KB
> >>
> >> Changes in v6:
> >> - Add support in device trees for rv1126(Declared in series 5 but not
> >> submitted)
> >> - Change to use "clk_sfc" "hclk_sfc" as clock lable, since it does not
> >> affect interpretation and has been widely used
> >> - Support sfc tx_dual, tx_quad(Declared in series 5 but not submitted)
> >> - Simplify the code, such as remove "rockchip_sfc_register_all"(Declared
> >> in series 5 but not submitted)
> >> - Support SFC ver4 ver5(Declared in series 5 but not submitted)
> >> - Add author Chris Morgan and Jon Lin to spi-rockchip-sfc.c
> >> - Change to use devm_spi_alloc_master and spi_unregister_master
> >>
> >> Changes in v5:
> >> - Add support in device trees for rv1126
> >> - Support sfc tx_dual, tx_quad
> >> - Simplify the code, such as remove "rockchip_sfc_register_all"
> >> - Support SFC ver4 ver5
> >>
> >> Changes in v4:
> >> - Changing patch back to an "RFC". An engineer from Rockchip
> >> reached out to me to let me know they are working on this patch for
> >> upstream, I am submitting this v4 for the community to see however
> >> I expect Jon Lin ([email protected]) will submit new patches
> >> soon and these are the ones we should pursue for mainlining. Jon's
> >> patch series should include support for more hardware than this
> >> series.
> >> - Clean up documentation more and ensure it is correct per
> >> make dt_binding_check.
> >> - Add support in device trees for rk3036, rk3308, and rv1108.
> >> - Add ahb clock (hclk_sfc) support for rk3036.
> >> - Change rockchip_sfc_wait_fifo_ready() to use a switch statement.
> >> - Change IRQ code to only mark IRQ as handled if it handles the
> >> specific IRQ (DMA transfer finish) it is supposed to handle.
> >>
> >> Changes in v3:
> >> - Changed the name of the clocks to sfc/ahb (from clk-sfc/clk-hsfc).
> >> - Changed the compatible string from rockchip,sfc to
> >> rockchip,rk3036-sfc. A quick glance at the datasheets suggests this
> >> driver should work for the PX30, RK180x, RK3036, RK312x, RK3308 and
> >> RV1108 SoCs, and possibly more. However, I am currently only able
> >> to test this on a PX30 (an RK3326). The technical reference manuals
> >> appear to list the same registers for each device.
> >> - Corrected devicetree documentation for formatting and to note these
> >> changes.
> >> - Replaced the maintainer with Heiko Stuebner and myself, as we will
> >> take ownership of this going forward.
> >> - Noted that the device (per the reference manual) supports 4 CS, but
> >> I am only able to test a single CS (CS 0).
> >> - Reordered patches to comply with upstream rules.
> >>
> >> Changes in v2:
> >> - Reimplemented driver using spi-mem subsystem.
> >> - Removed power management code as I couldn't get it working properly.
> >> - Added device tree bindings for Odroid Go Advance.
> >>
> >> Changes in v1:
> >> hanges made in this new series versus the v8 of the old series:
> >> - Added function to read spi-rx-bus-width from device tree, in the
> >> event that the SPI chip supports 4x mode but only has 2 pins
> >> wired (such as the Odroid Go Advance).
> >> - Changed device tree documentation from txt to yaml format.
> >> - Made "reset" message a dev_dbg from a dev_info.
> >> - Changed read and write fifo functions to remove redundant checks.
> >> - Changed the write and read from relaxed to non-relaxed when
> >> starting the DMA transfer or reading the DMA IRQ.
> >> - Changed from dma_coerce_mask_and_coherent to just
> >> dma_set_mask_and_coherent.
> >> - Changed name of get_if_type to rockchip_sfc_get_if_type.
> >>
> >> .../devicetree/bindings/spi/rockchip-sfc.yaml | 88 +++++++++++++++++++
> >> 1 file changed, 88 insertions(+)
> >> create mode 100644 Documentation/devicetree/bindings/spi/rockchip-sfc.yaml
> >>
> >> diff --git a/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml b/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml
> >> new file mode 100644
> >> index 000000000000..42e4198e92af
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml
> >> @@ -0,0 +1,88 @@
> >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >> +%YAML 1.2
> >> +---
> >> +$id: http://devicetree.org/schemas/spi/rockchip-sfc.yaml#
> >> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >> +
> >> +title: Rockchip Serial Flash Controller (SFC)
> >> +
> >> +maintainers:
> >> + - Heiko Stuebner <[email protected]>
> >> + - Chris Morgan <[email protected]>
> >> +
> >> +allOf:
> >> + - $ref: spi-controller.yaml#
> >> +
> >> +properties:
> >> + compatible:
> >> + oneOf:
> >> + - const: rockchip,sfc
> > Use 'enum' instead of oneOf+const.
> >
> > You need an SoC specific compatible.
>
>
> The rockchip sfc controller is a standalone IP with version register,
> and the driver can
>
> handle all the feature difference inside the IP, so we would like to use
> a more generic
>
> compatible name instead of bind to any of SoC name. So can we use
> "rockchip,sfc"
>
> like "snps,designware-spi", which is a generic one, instead of an SoC
> specific compatible?
>
IIUC, the way this works is along these lines:
* The SFC driver can only care for the rockchip,sfc compatible string
and, if suitable, use the IP version register mentioned by Kever [1].
* The bindings doc specifies both the SoC-specific and the generic one
with:
- items:
- enum:
- rockchip,px30-sfc
- const: rockchip,sfc
* The device tree lists both as well:
compatible = "rockchip,px30-sfc", "rockchip,sfc";
This can apply to all IP cores really; and will allow some
compatibility between the downstream/vendor device tree
and upstream.
This scheme is indeed more convoluted than just
picking any SoC name for the compatible string, and
use that compatible string for all the SoCs (given they
are all compatible, again as per [1]).
IOW, you only have "rockchip,px30-sfc" in the bindings,
in the devicetree files and in the driver.
[1] https://lkml.org/lkml/2021/6/8/2030
Thanks!
Ezequiel
On Fri, Jun 11, 2021 at 10:33 AM Ezequiel Garcia
<[email protected]> wrote:
>
> Hi all,
>
> On Thu, 10 Jun 2021 at 00:04, Kever Yang <[email protected]> wrote:
> >
> > Hi Rob,
> >
> > On 2021/6/10 上午10:43, Rob Herring wrote:
> > > On Wed, Jun 09, 2021 at 10:04:04PM +0800, Jon Lin wrote:
> > >> From: Chris Morgan <[email protected]>
> > >>
> > >> Add bindings for the Rockchip serial flash controller. New device
> > >> specific parameter of rockchip,sfc-no-dma included in documentation.
> > >>
> > >> Signed-off-by: Chris Morgan <[email protected]>
> > >> Signed-off-by: Jon Lin <[email protected]>
> > >> ---
> > >>
> > >> Changes in v7:
> > >> - Fix up the sclk_sfc parent error in rk3036
> > >> - Unify to "rockchip,sfc" compatible id because all the feature update
> > >> will have a new IP version, so the driver is used for the SFC IP in
> > >> all SoCs
> > >> - Change to use node "sfc" to name the SFC pinctrl group
> > >> - Add subnode reg property check
> > >> - Add rockchip_sfc_adjust_op_size to workaround in CMD + DUMMY case
> > >> - Limit max_iosize to 32KB
> > >>
> > >> Changes in v6:
> > >> - Add support in device trees for rv1126(Declared in series 5 but not
> > >> submitted)
> > >> - Change to use "clk_sfc" "hclk_sfc" as clock lable, since it does not
> > >> affect interpretation and has been widely used
> > >> - Support sfc tx_dual, tx_quad(Declared in series 5 but not submitted)
> > >> - Simplify the code, such as remove "rockchip_sfc_register_all"(Declared
> > >> in series 5 but not submitted)
> > >> - Support SFC ver4 ver5(Declared in series 5 but not submitted)
> > >> - Add author Chris Morgan and Jon Lin to spi-rockchip-sfc.c
> > >> - Change to use devm_spi_alloc_master and spi_unregister_master
> > >>
> > >> Changes in v5:
> > >> - Add support in device trees for rv1126
> > >> - Support sfc tx_dual, tx_quad
> > >> - Simplify the code, such as remove "rockchip_sfc_register_all"
> > >> - Support SFC ver4 ver5
> > >>
> > >> Changes in v4:
> > >> - Changing patch back to an "RFC". An engineer from Rockchip
> > >> reached out to me to let me know they are working on this patch for
> > >> upstream, I am submitting this v4 for the community to see however
> > >> I expect Jon Lin ([email protected]) will submit new patches
> > >> soon and these are the ones we should pursue for mainlining. Jon's
> > >> patch series should include support for more hardware than this
> > >> series.
> > >> - Clean up documentation more and ensure it is correct per
> > >> make dt_binding_check.
> > >> - Add support in device trees for rk3036, rk3308, and rv1108.
> > >> - Add ahb clock (hclk_sfc) support for rk3036.
> > >> - Change rockchip_sfc_wait_fifo_ready() to use a switch statement.
> > >> - Change IRQ code to only mark IRQ as handled if it handles the
> > >> specific IRQ (DMA transfer finish) it is supposed to handle.
> > >>
> > >> Changes in v3:
> > >> - Changed the name of the clocks to sfc/ahb (from clk-sfc/clk-hsfc).
> > >> - Changed the compatible string from rockchip,sfc to
> > >> rockchip,rk3036-sfc. A quick glance at the datasheets suggests this
> > >> driver should work for the PX30, RK180x, RK3036, RK312x, RK3308 and
> > >> RV1108 SoCs, and possibly more. However, I am currently only able
> > >> to test this on a PX30 (an RK3326). The technical reference manuals
> > >> appear to list the same registers for each device.
> > >> - Corrected devicetree documentation for formatting and to note these
> > >> changes.
> > >> - Replaced the maintainer with Heiko Stuebner and myself, as we will
> > >> take ownership of this going forward.
> > >> - Noted that the device (per the reference manual) supports 4 CS, but
> > >> I am only able to test a single CS (CS 0).
> > >> - Reordered patches to comply with upstream rules.
> > >>
> > >> Changes in v2:
> > >> - Reimplemented driver using spi-mem subsystem.
> > >> - Removed power management code as I couldn't get it working properly.
> > >> - Added device tree bindings for Odroid Go Advance.
> > >>
> > >> Changes in v1:
> > >> hanges made in this new series versus the v8 of the old series:
> > >> - Added function to read spi-rx-bus-width from device tree, in the
> > >> event that the SPI chip supports 4x mode but only has 2 pins
> > >> wired (such as the Odroid Go Advance).
> > >> - Changed device tree documentation from txt to yaml format.
> > >> - Made "reset" message a dev_dbg from a dev_info.
> > >> - Changed read and write fifo functions to remove redundant checks.
> > >> - Changed the write and read from relaxed to non-relaxed when
> > >> starting the DMA transfer or reading the DMA IRQ.
> > >> - Changed from dma_coerce_mask_and_coherent to just
> > >> dma_set_mask_and_coherent.
> > >> - Changed name of get_if_type to rockchip_sfc_get_if_type.
> > >>
> > >> .../devicetree/bindings/spi/rockchip-sfc.yaml | 88 +++++++++++++++++++
> > >> 1 file changed, 88 insertions(+)
> > >> create mode 100644 Documentation/devicetree/bindings/spi/rockchip-sfc.yaml
> > >>
> > >> diff --git a/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml b/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml
> > >> new file mode 100644
> > >> index 000000000000..42e4198e92af
> > >> --- /dev/null
> > >> +++ b/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml
> > >> @@ -0,0 +1,88 @@
> > >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > >> +%YAML 1.2
> > >> +---
> > >> +$id: http://devicetree.org/schemas/spi/rockchip-sfc.yaml#
> > >> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > >> +
> > >> +title: Rockchip Serial Flash Controller (SFC)
> > >> +
> > >> +maintainers:
> > >> + - Heiko Stuebner <[email protected]>
> > >> + - Chris Morgan <[email protected]>
> > >> +
> > >> +allOf:
> > >> + - $ref: spi-controller.yaml#
> > >> +
> > >> +properties:
> > >> + compatible:
> > >> + oneOf:
> > >> + - const: rockchip,sfc
> > > Use 'enum' instead of oneOf+const.
> > >
> > > You need an SoC specific compatible.
> >
> >
> > The rockchip sfc controller is a standalone IP with version register,
> > and the driver can
> >
> > handle all the feature difference inside the IP, so we would like to use
> > a more generic
Okay, if the version register can be relied on, then this is fine.
Just add a comment that further differentiation is done using a
version register.
> >
> > compatible name instead of bind to any of SoC name. So can we use
> > "rockchip,sfc"
> >
> > like "snps,designware-spi", which is a generic one, instead of an SoC
> > specific compatible?
That's a licensed IP which is a bit different. Though generic names on
those are useless too. There's different versions and different
integration quirks.
> >
>
> IIUC, the way this works is along these lines:
>
> * The SFC driver can only care for the rockchip,sfc compatible string
> and, if suitable, use the IP version register mentioned by Kever [1].
>
> * The bindings doc specifies both the SoC-specific and the generic one
> with:
>
> - items:
> - enum:
> - rockchip,px30-sfc
> - const: rockchip,sfc
>
> * The device tree lists both as well:
>
> compatible = "rockchip,px30-sfc", "rockchip,sfc";
>
> This can apply to all IP cores really; and will allow some
> compatibility between the downstream/vendor device tree
> and upstream.
>
> This scheme is indeed more convoluted than just
> picking any SoC name for the compatible string, and
> use that compatible string for all the SoCs (given they
> are all compatible, again as per [1]).
>
> IOW, you only have "rockchip,px30-sfc" in the bindings,
> in the devicetree files and in the driver.
This is fine too, but again if a version or capability register is
sufficient, no need to put this into DT. Maybe someday h/w designers
will clue in and always have version and/or capability registers.
Rob
Hi Rob,
On 2021/6/16 下午11:38, Rob Herring wrote:
> On Fri, Jun 11, 2021 at 10:33 AM Ezequiel Garcia
> <[email protected]> wrote:
>> Hi all,
>>
>> On Thu, 10 Jun 2021 at 00:04, Kever Yang <[email protected]> wrote:
>>> Hi Rob,
>>>
>>> On 2021/6/10 上午10:43, Rob Herring wrote:
>>>> On Wed, Jun 09, 2021 at 10:04:04PM +0800, Jon Lin wrote:
>>>>> From: Chris Morgan <[email protected]>
>>>>>
>>>>> Add bindings for the Rockchip serial flash controller. New device
>>>>> specific parameter of rockchip,sfc-no-dma included in documentation.
>>>>>
>>>>> Signed-off-by: Chris Morgan <[email protected]>
>>>>> Signed-off-by: Jon Lin <[email protected]>
>>>>> ---
>>>>>
>>>>> Changes in v7:
>>>>> - Fix up the sclk_sfc parent error in rk3036
>>>>> - Unify to "rockchip,sfc" compatible id because all the feature update
>>>>> will have a new IP version, so the driver is used for the SFC IP in
>>>>> all SoCs
>>>>> - Change to use node "sfc" to name the SFC pinctrl group
>>>>> - Add subnode reg property check
>>>>> - Add rockchip_sfc_adjust_op_size to workaround in CMD + DUMMY case
>>>>> - Limit max_iosize to 32KB
>>>>>
>>>>> Changes in v6:
>>>>> - Add support in device trees for rv1126(Declared in series 5 but not
>>>>> submitted)
>>>>> - Change to use "clk_sfc" "hclk_sfc" as clock lable, since it does not
>>>>> affect interpretation and has been widely used
>>>>> - Support sfc tx_dual, tx_quad(Declared in series 5 but not submitted)
>>>>> - Simplify the code, such as remove "rockchip_sfc_register_all"(Declared
>>>>> in series 5 but not submitted)
>>>>> - Support SFC ver4 ver5(Declared in series 5 but not submitted)
>>>>> - Add author Chris Morgan and Jon Lin to spi-rockchip-sfc.c
>>>>> - Change to use devm_spi_alloc_master and spi_unregister_master
>>>>>
>>>>> Changes in v5:
>>>>> - Add support in device trees for rv1126
>>>>> - Support sfc tx_dual, tx_quad
>>>>> - Simplify the code, such as remove "rockchip_sfc_register_all"
>>>>> - Support SFC ver4 ver5
>>>>>
>>>>> Changes in v4:
>>>>> - Changing patch back to an "RFC". An engineer from Rockchip
>>>>> reached out to me to let me know they are working on this patch for
>>>>> upstream, I am submitting this v4 for the community to see however
>>>>> I expect Jon Lin ([email protected]) will submit new patches
>>>>> soon and these are the ones we should pursue for mainlining. Jon's
>>>>> patch series should include support for more hardware than this
>>>>> series.
>>>>> - Clean up documentation more and ensure it is correct per
>>>>> make dt_binding_check.
>>>>> - Add support in device trees for rk3036, rk3308, and rv1108.
>>>>> - Add ahb clock (hclk_sfc) support for rk3036.
>>>>> - Change rockchip_sfc_wait_fifo_ready() to use a switch statement.
>>>>> - Change IRQ code to only mark IRQ as handled if it handles the
>>>>> specific IRQ (DMA transfer finish) it is supposed to handle.
>>>>>
>>>>> Changes in v3:
>>>>> - Changed the name of the clocks to sfc/ahb (from clk-sfc/clk-hsfc).
>>>>> - Changed the compatible string from rockchip,sfc to
>>>>> rockchip,rk3036-sfc. A quick glance at the datasheets suggests this
>>>>> driver should work for the PX30, RK180x, RK3036, RK312x, RK3308 and
>>>>> RV1108 SoCs, and possibly more. However, I am currently only able
>>>>> to test this on a PX30 (an RK3326). The technical reference manuals
>>>>> appear to list the same registers for each device.
>>>>> - Corrected devicetree documentation for formatting and to note these
>>>>> changes.
>>>>> - Replaced the maintainer with Heiko Stuebner and myself, as we will
>>>>> take ownership of this going forward.
>>>>> - Noted that the device (per the reference manual) supports 4 CS, but
>>>>> I am only able to test a single CS (CS 0).
>>>>> - Reordered patches to comply with upstream rules.
>>>>>
>>>>> Changes in v2:
>>>>> - Reimplemented driver using spi-mem subsystem.
>>>>> - Removed power management code as I couldn't get it working properly.
>>>>> - Added device tree bindings for Odroid Go Advance.
>>>>>
>>>>> Changes in v1:
>>>>> hanges made in this new series versus the v8 of the old series:
>>>>> - Added function to read spi-rx-bus-width from device tree, in the
>>>>> event that the SPI chip supports 4x mode but only has 2 pins
>>>>> wired (such as the Odroid Go Advance).
>>>>> - Changed device tree documentation from txt to yaml format.
>>>>> - Made "reset" message a dev_dbg from a dev_info.
>>>>> - Changed read and write fifo functions to remove redundant checks.
>>>>> - Changed the write and read from relaxed to non-relaxed when
>>>>> starting the DMA transfer or reading the DMA IRQ.
>>>>> - Changed from dma_coerce_mask_and_coherent to just
>>>>> dma_set_mask_and_coherent.
>>>>> - Changed name of get_if_type to rockchip_sfc_get_if_type.
>>>>>
>>>>> .../devicetree/bindings/spi/rockchip-sfc.yaml | 88 +++++++++++++++++++
>>>>> 1 file changed, 88 insertions(+)
>>>>> create mode 100644 Documentation/devicetree/bindings/spi/rockchip-sfc.yaml
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml b/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml
>>>>> new file mode 100644
>>>>> index 000000000000..42e4198e92af
>>>>> --- /dev/null
>>>>> +++ b/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml
>>>>> @@ -0,0 +1,88 @@
>>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>>> +%YAML 1.2
>>>>> +---
>>>>> +$id: http://devicetree.org/schemas/spi/rockchip-sfc.yaml#
>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>>> +
>>>>> +title: Rockchip Serial Flash Controller (SFC)
>>>>> +
>>>>> +maintainers:
>>>>> + - Heiko Stuebner <[email protected]>
>>>>> + - Chris Morgan <[email protected]>
>>>>> +
>>>>> +allOf:
>>>>> + - $ref: spi-controller.yaml#
>>>>> +
>>>>> +properties:
>>>>> + compatible:
>>>>> + oneOf:
>>>>> + - const: rockchip,sfc
>>>> Use 'enum' instead of oneOf+const.
>>>>
>>>> You need an SoC specific compatible.
>>>
>>> The rockchip sfc controller is a standalone IP with version register,
>>> and the driver can
>>>
>>> handle all the feature difference inside the IP, so we would like to use
>>> a more generic
> Okay, if the version register can be relied on, then this is fine.
> Just add a comment that further differentiation is done using a
> version register.
Thanks for your confirm, this will make things much simple for driver
maintain.
@Jon, please update your patch per Rob's requirement.
Thanks,
- Kever