Add support for detection of Intel Sapphire Rapids processor based on
CPU family & model.
Sapphire Rapids Xeon processors with the family set to 6 and the
model set to INTEL_FAM6_SAPPHIRERAPIDS_X. The data field for this entry
is "spr".
Signed-off-by: Patrick Rudolph <[email protected]>
Signed-off-by: Naresh Solanki <[email protected]>
---
Changes in V2:
- Refactored from previous patchset as seperate patch based on subsystem.
---
drivers/peci/cpu.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/peci/cpu.c b/drivers/peci/cpu.c
index de4a7b3e5966..3668a908d259 100644
--- a/drivers/peci/cpu.c
+++ b/drivers/peci/cpu.c
@@ -318,6 +318,11 @@ static const struct peci_device_id peci_cpu_device_ids[] = {
.model = INTEL_FAM6_ICELAKE_X,
.data = "icx",
},
+ { /* Sapphire Rapids Xeon */
+ .family = 6,
+ .model = INTEL_FAM6_SAPPHIRERAPIDS_X,
+ .data = "spr",
+ },
{ /* Icelake Xeon D */
.family = 6,
.model = INTEL_FAM6_ICELAKE_D,
base-commit: 4dbbaf8fbdbd13adc80731b2452257857e4c2d8b
--
2.41.0
From: Patrick Rudolph <[email protected]>
Add support to read DTS for reading Intel Sapphire Rapids platform.
Signed-off-by: Patrick Rudolph <[email protected]>
Signed-off-by: Naresh Solanki <[email protected]>
---
Changes in V2:
- Refactored from previous patchset as seperate patch based on subsystem.
---
drivers/hwmon/peci/cputemp.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/hwmon/peci/cputemp.c b/drivers/hwmon/peci/cputemp.c
index e5b65a382772..a812c15948d9 100644
--- a/drivers/hwmon/peci/cputemp.c
+++ b/drivers/hwmon/peci/cputemp.c
@@ -363,6 +363,7 @@ static int init_core_mask(struct peci_cputemp *priv)
switch (peci_dev->info.model) {
case INTEL_FAM6_ICELAKE_X:
case INTEL_FAM6_ICELAKE_D:
+ case INTEL_FAM6_SAPPHIRERAPIDS_X:
ret = peci_ep_pci_local_read(peci_dev, 0, reg->bus, reg->dev,
reg->func, reg->offset + 4, &data);
if (ret)
@@ -531,6 +532,13 @@ static struct resolved_cores_reg resolved_cores_reg_icx = {
.offset = 0xd0,
};
+static struct resolved_cores_reg resolved_cores_reg_spr = {
+ .bus = 31,
+ .dev = 30,
+ .func = 6,
+ .offset = 0x80,
+};
+
static const struct cpu_info cpu_hsx = {
.reg = &resolved_cores_reg_hsx,
.min_peci_revision = 0x33,
@@ -549,6 +557,12 @@ static const struct cpu_info cpu_icx = {
.thermal_margin_to_millidegree = &dts_ten_dot_six_to_millidegree,
};
+static const struct cpu_info cpu_spr = {
+ .reg = &resolved_cores_reg_spr,
+ .min_peci_revision = 0x40,
+ .thermal_margin_to_millidegree = &dts_ten_dot_six_to_millidegree,
+};
+
static const struct auxiliary_device_id peci_cputemp_ids[] = {
{
.name = "peci_cpu.cputemp.hsx",
@@ -574,6 +588,10 @@ static const struct auxiliary_device_id peci_cputemp_ids[] = {
.name = "peci_cpu.cputemp.icxd",
.driver_data = (kernel_ulong_t)&cpu_icx,
},
+ {
+ .name = "peci_cpu.cputemp.spr",
+ .driver_data = (kernel_ulong_t)&cpu_spr,
+ },
{ }
};
MODULE_DEVICE_TABLE(auxiliary, peci_cputemp_ids);
--
2.41.0
From: Patrick Rudolph <[email protected]>
This patch extends the functionality of the hwmon (peci/dimmtemp) to
include support for Sapphire Rapids platform.
Sapphire Rapids can accommodate up to 8 CPUs, each with 16 DIMMs. To
accommodate this configuration, the maximum supported DIMM count is
increased, and the corresponding Sapphire Rapids ID and threshold code
are added.
The patch has been tested on a 4S system with 64 DIMMs installed.
Default thresholds are utilized for Sapphire Rapids, as accessing the
threshold requires accessing the UBOX device on Uncore bus 0, which can
only be achieved using MSR access. The non-PCI-compliant MMIO BARs are
not available for this purpose.
Signed-off-by: Patrick Rudolph <[email protected]>
Signed-off-by: Naresh Solanki <[email protected]>
---
Changes in V2:
- Update subject.
---
drivers/hwmon/peci/dimmtemp.c | 24 +++++++++++++++++++++++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/hwmon/peci/dimmtemp.c b/drivers/hwmon/peci/dimmtemp.c
index ed968401f93c..edafbfd66fef 100644
--- a/drivers/hwmon/peci/dimmtemp.c
+++ b/drivers/hwmon/peci/dimmtemp.c
@@ -30,8 +30,10 @@
#define DIMM_IDX_MAX_ON_ICX 2
#define CHAN_RANK_MAX_ON_ICXD 4
#define DIMM_IDX_MAX_ON_ICXD 2
+#define CHAN_RANK_MAX_ON_SPR 128
+#define DIMM_IDX_MAX_ON_SPR 2
-#define CHAN_RANK_MAX CHAN_RANK_MAX_ON_HSX
+#define CHAN_RANK_MAX CHAN_RANK_MAX_ON_SPR
#define DIMM_IDX_MAX DIMM_IDX_MAX_ON_HSX
#define DIMM_NUMS_MAX (CHAN_RANK_MAX * DIMM_IDX_MAX)
@@ -530,6 +532,15 @@ read_thresholds_icx(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u
return 0;
}
+static int
+read_thresholds_spr(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data)
+{
+ /* Use defaults */
+ *data = (95 << 16) | (90 << 8);
+
+ return 0;
+}
+
static const struct dimm_info dimm_hsx = {
.chan_rank_max = CHAN_RANK_MAX_ON_HSX,
.dimm_idx_max = DIMM_IDX_MAX_ON_HSX,
@@ -572,6 +583,13 @@ static const struct dimm_info dimm_icxd = {
.read_thresholds = &read_thresholds_icx,
};
+static const struct dimm_info dimm_spr = {
+ .chan_rank_max = CHAN_RANK_MAX_ON_SPR,
+ .dimm_idx_max = DIMM_IDX_MAX_ON_SPR,
+ .min_peci_revision = 0x40,
+ .read_thresholds = &read_thresholds_spr,
+};
+
static const struct auxiliary_device_id peci_dimmtemp_ids[] = {
{
.name = "peci_cpu.dimmtemp.hsx",
@@ -597,6 +615,10 @@ static const struct auxiliary_device_id peci_dimmtemp_ids[] = {
.name = "peci_cpu.dimmtemp.icxd",
.driver_data = (kernel_ulong_t)&dimm_icxd,
},
+ {
+ .name = "peci_cpu.dimmtemp.spr",
+ .driver_data = (kernel_ulong_t)&dimm_spr,
+ },
{ }
};
MODULE_DEVICE_TABLE(auxiliary, peci_dimmtemp_ids);
--
2.41.0
Dear Naresh,
Thank you for the patch.
Am 12.07.23 um 11:12 schrieb Naresh Solanki:
> Add support for detection of Intel Sapphire Rapids processor based on
> CPU family & model.
>
> Sapphire Rapids Xeon processors with the family set to 6 and the
> model set to INTEL_FAM6_SAPPHIRERAPIDS_X. The data field for this entry
> is "spr".
Please add, how you tested this.
> Signed-off-by: Patrick Rudolph <[email protected]>
> Signed-off-by: Naresh Solanki <[email protected]>
> ---
> Changes in V2:
> - Refactored from previous patchset as seperate patch based on subsystem.
> ---
> drivers/peci/cpu.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/peci/cpu.c b/drivers/peci/cpu.c
> index de4a7b3e5966..3668a908d259 100644
> --- a/drivers/peci/cpu.c
> +++ b/drivers/peci/cpu.c
> @@ -318,6 +318,11 @@ static const struct peci_device_id peci_cpu_device_ids[] = {
> .model = INTEL_FAM6_ICELAKE_X,
> .data = "icx",
> },
> + { /* Sapphire Rapids Xeon */
> + .family = 6,
> + .model = INTEL_FAM6_SAPPHIRERAPIDS_X,
> + .data = "spr",
> + },
> { /* Icelake Xeon D */
> .family = 6,
> .model = INTEL_FAM6_ICELAKE_D,
It looks like it’s incorrectly sorted, probably due to merge conflict
resolution?
Kind regards,
Paul
Hi Paul,
On Wed, 19 Jul 2023 at 16:50, Paul Menzel <[email protected]> wrote:
>
> Dear Naresh,
>
>
> Thank you for the patch.
>
> Am 12.07.23 um 11:12 schrieb Naresh Solanki:
> > Add support for detection of Intel Sapphire Rapids processor based on
> > CPU family & model.
> >
> > Sapphire Rapids Xeon processors with the family set to 6 and the
> > model set to INTEL_FAM6_SAPPHIRERAPIDS_X. The data field for this entry
> > is "spr".
>
> Please add, how you tested this.
Yeah, sure. Missed adding that. Will update the same in next revision.
>
> > Signed-off-by: Patrick Rudolph <[email protected]>
> > Signed-off-by: Naresh Solanki <[email protected]>
> > ---
> > Changes in V2:
> > - Refactored from previous patchset as seperate patch based on subsystem.
> > ---
> > drivers/peci/cpu.c | 5 +++++
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/drivers/peci/cpu.c b/drivers/peci/cpu.c
> > index de4a7b3e5966..3668a908d259 100644
> > --- a/drivers/peci/cpu.c
> > +++ b/drivers/peci/cpu.c
> > @@ -318,6 +318,11 @@ static const struct peci_device_id peci_cpu_device_ids[] = {
> > .model = INTEL_FAM6_ICELAKE_X,
> > .data = "icx",
> > },
> > + { /* Sapphire Rapids Xeon */
> > + .family = 6,
> > + .model = INTEL_FAM6_SAPPHIRERAPIDS_X,
> > + .data = "spr",
> > + },
> > { /* Icelake Xeon D */
> > .family = 6,
> > .model = INTEL_FAM6_ICELAKE_D,
>
> It looks like it’s incorrectly sorted, probably due to merge conflict
> resolution?
Will move it to after Xeon D in next revision.
Thanks,
Naresh
>
>
> Kind regards,
>
> Paul
On 7/12/23 02:12, Naresh Solanki wrote:
> From: Patrick Rudolph <[email protected]>
>
> Add support to read DTS for reading Intel Sapphire Rapids platform.
>
> Signed-off-by: Patrick Rudolph <[email protected]>
> Signed-off-by: Naresh Solanki <[email protected]>
I don't know what the plan is to apply this and the next patch, since
(I assume) it depends on the first patch of the series. Assuming it will
be applied through the peci tree:
Acked-by: Guenter Roeck <[email protected]>
Guenter
> ---
> Changes in V2:
> - Refactored from previous patchset as seperate patch based on subsystem.
> ---
> drivers/hwmon/peci/cputemp.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/hwmon/peci/cputemp.c b/drivers/hwmon/peci/cputemp.c
> index e5b65a382772..a812c15948d9 100644
> --- a/drivers/hwmon/peci/cputemp.c
> +++ b/drivers/hwmon/peci/cputemp.c
> @@ -363,6 +363,7 @@ static int init_core_mask(struct peci_cputemp *priv)
> switch (peci_dev->info.model) {
> case INTEL_FAM6_ICELAKE_X:
> case INTEL_FAM6_ICELAKE_D:
> + case INTEL_FAM6_SAPPHIRERAPIDS_X:
> ret = peci_ep_pci_local_read(peci_dev, 0, reg->bus, reg->dev,
> reg->func, reg->offset + 4, &data);
> if (ret)
> @@ -531,6 +532,13 @@ static struct resolved_cores_reg resolved_cores_reg_icx = {
> .offset = 0xd0,
> };
>
> +static struct resolved_cores_reg resolved_cores_reg_spr = {
> + .bus = 31,
> + .dev = 30,
> + .func = 6,
> + .offset = 0x80,
> +};
> +
> static const struct cpu_info cpu_hsx = {
> .reg = &resolved_cores_reg_hsx,
> .min_peci_revision = 0x33,
> @@ -549,6 +557,12 @@ static const struct cpu_info cpu_icx = {
> .thermal_margin_to_millidegree = &dts_ten_dot_six_to_millidegree,
> };
>
> +static const struct cpu_info cpu_spr = {
> + .reg = &resolved_cores_reg_spr,
> + .min_peci_revision = 0x40,
> + .thermal_margin_to_millidegree = &dts_ten_dot_six_to_millidegree,
> +};
> +
> static const struct auxiliary_device_id peci_cputemp_ids[] = {
> {
> .name = "peci_cpu.cputemp.hsx",
> @@ -574,6 +588,10 @@ static const struct auxiliary_device_id peci_cputemp_ids[] = {
> .name = "peci_cpu.cputemp.icxd",
> .driver_data = (kernel_ulong_t)&cpu_icx,
> },
> + {
> + .name = "peci_cpu.cputemp.spr",
> + .driver_data = (kernel_ulong_t)&cpu_spr,
> + },
> { }
> };
> MODULE_DEVICE_TABLE(auxiliary, peci_cputemp_ids);
On 7/12/23 02:12, Naresh Solanki wrote:
> From: Patrick Rudolph <[email protected]>
>
> This patch extends the functionality of the hwmon (peci/dimmtemp) to
> include support for Sapphire Rapids platform.
>
> Sapphire Rapids can accommodate up to 8 CPUs, each with 16 DIMMs. To
> accommodate this configuration, the maximum supported DIMM count is
> increased, and the corresponding Sapphire Rapids ID and threshold code
> are added.
>
> The patch has been tested on a 4S system with 64 DIMMs installed.
> Default thresholds are utilized for Sapphire Rapids, as accessing the
> threshold requires accessing the UBOX device on Uncore bus 0, which can
> only be achieved using MSR access. The non-PCI-compliant MMIO BARs are
> not available for this purpose.
>
> Signed-off-by: Patrick Rudolph <[email protected]>
> Signed-off-by: Naresh Solanki <[email protected]>
Assuming this will be applied through the peci tree:
Acked-by: Guenter Roeck <[email protected]>
> ---
> Changes in V2:
> - Update subject.
> ---
> drivers/hwmon/peci/dimmtemp.c | 24 +++++++++++++++++++++++-
> 1 file changed, 23 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/hwmon/peci/dimmtemp.c b/drivers/hwmon/peci/dimmtemp.c
> index ed968401f93c..edafbfd66fef 100644
> --- a/drivers/hwmon/peci/dimmtemp.c
> +++ b/drivers/hwmon/peci/dimmtemp.c
> @@ -30,8 +30,10 @@
> #define DIMM_IDX_MAX_ON_ICX 2
> #define CHAN_RANK_MAX_ON_ICXD 4
> #define DIMM_IDX_MAX_ON_ICXD 2
> +#define CHAN_RANK_MAX_ON_SPR 128
> +#define DIMM_IDX_MAX_ON_SPR 2
>
> -#define CHAN_RANK_MAX CHAN_RANK_MAX_ON_HSX
> +#define CHAN_RANK_MAX CHAN_RANK_MAX_ON_SPR
> #define DIMM_IDX_MAX DIMM_IDX_MAX_ON_HSX
> #define DIMM_NUMS_MAX (CHAN_RANK_MAX * DIMM_IDX_MAX)
>
> @@ -530,6 +532,15 @@ read_thresholds_icx(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u
> return 0;
> }
>
> +static int
> +read_thresholds_spr(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data)
> +{
> + /* Use defaults */
> + *data = (95 << 16) | (90 << 8);
> +
> + return 0;
> +}
> +
> static const struct dimm_info dimm_hsx = {
> .chan_rank_max = CHAN_RANK_MAX_ON_HSX,
> .dimm_idx_max = DIMM_IDX_MAX_ON_HSX,
> @@ -572,6 +583,13 @@ static const struct dimm_info dimm_icxd = {
> .read_thresholds = &read_thresholds_icx,
> };
>
> +static const struct dimm_info dimm_spr = {
> + .chan_rank_max = CHAN_RANK_MAX_ON_SPR,
> + .dimm_idx_max = DIMM_IDX_MAX_ON_SPR,
> + .min_peci_revision = 0x40,
> + .read_thresholds = &read_thresholds_spr,
> +};
> +
> static const struct auxiliary_device_id peci_dimmtemp_ids[] = {
> {
> .name = "peci_cpu.dimmtemp.hsx",
> @@ -597,6 +615,10 @@ static const struct auxiliary_device_id peci_dimmtemp_ids[] = {
> .name = "peci_cpu.dimmtemp.icxd",
> .driver_data = (kernel_ulong_t)&dimm_icxd,
> },
> + {
> + .name = "peci_cpu.dimmtemp.spr",
> + .driver_data = (kernel_ulong_t)&dimm_spr,
> + },
> { }
> };
> MODULE_DEVICE_TABLE(auxiliary, peci_dimmtemp_ids);
On Wed, 2023-07-19 at 06:34 -0700, Guenter Roeck wrote:
> On 7/12/23 02:12, Naresh Solanki wrote:
> > From: Patrick Rudolph <[email protected]>
> >
> > Add support to read DTS for reading Intel Sapphire Rapids platform.
> >
> > Signed-off-by: Patrick Rudolph <[email protected]>
> > Signed-off-by: Naresh Solanki <[email protected]>
>
> I don't know what the plan is to apply this and the next patch, since
> (I assume) it depends on the first patch of the series. Assuming it will
> be applied through the peci tree:
>
> Acked-by: Guenter Roeck <[email protected]>
Sure - it can go through the PECI tree once my review comments are addressed.
Thanks
-Iwona
>
> Guenter
>
> > ---
> > Changes in V2:
> > - Refactored from previous patchset as seperate patch based on subsystem.
> > ---
> > drivers/hwmon/peci/cputemp.c | 18 ++++++++++++++++++
> > 1 file changed, 18 insertions(+)
> >
> > diff --git a/drivers/hwmon/peci/cputemp.c b/drivers/hwmon/peci/cputemp.c
> > index e5b65a382772..a812c15948d9 100644
> > --- a/drivers/hwmon/peci/cputemp.c
> > +++ b/drivers/hwmon/peci/cputemp.c
> > @@ -363,6 +363,7 @@ static int init_core_mask(struct peci_cputemp *priv)
> > switch (peci_dev->info.model) {
> > case INTEL_FAM6_ICELAKE_X:
> > case INTEL_FAM6_ICELAKE_D:
> > + case INTEL_FAM6_SAPPHIRERAPIDS_X:
> > ret = peci_ep_pci_local_read(peci_dev, 0, reg->bus, reg-
> > >dev,
> > reg->func, reg->offset + 4,
> > &data);
> > if (ret)
> > @@ -531,6 +532,13 @@ static struct resolved_cores_reg resolved_cores_reg_icx
> > = {
> > .offset = 0xd0,
> > };
> >
> > +static struct resolved_cores_reg resolved_cores_reg_spr = {
> > + .bus = 31,
> > + .dev = 30,
> > + .func = 6,
> > + .offset = 0x80,
> > +};
> > +
> > static const struct cpu_info cpu_hsx = {
> > .reg = &resolved_cores_reg_hsx,
> > .min_peci_revision = 0x33,
> > @@ -549,6 +557,12 @@ static const struct cpu_info cpu_icx = {
> > .thermal_margin_to_millidegree = &dts_ten_dot_six_to_millidegree,
> > };
> >
> > +static const struct cpu_info cpu_spr = {
> > + .reg = &resolved_cores_reg_spr,
> > + .min_peci_revision = 0x40,
> > + .thermal_margin_to_millidegree = &dts_ten_dot_six_to_millidegree,
> > +};
> > +
> > static const struct auxiliary_device_id peci_cputemp_ids[] = {
> > {
> > .name = "peci_cpu.cputemp.hsx",
> > @@ -574,6 +588,10 @@ static const struct auxiliary_device_id
> > peci_cputemp_ids[] = {
> > .name = "peci_cpu.cputemp.icxd",
> > .driver_data = (kernel_ulong_t)&cpu_icx,
> > },
> > + {
> > + .name = "peci_cpu.cputemp.spr",
> > + .driver_data = (kernel_ulong_t)&cpu_spr,
> > + },
> > { }
> > };
> > MODULE_DEVICE_TABLE(auxiliary, peci_cputemp_ids);
>