Add bootph-pre-ram property for all the nodes used in SPL stage,
for syncing it later to u-boot j784s4 dts.
Signed-off-by: Apurva Nandan <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
index 740ee794d7b9..57bf0261c343 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
@@ -6,7 +6,9 @@
*/
&cbass_mcu_wakeup {
+ bootph-pre-ram;
sms: system-controller@44083000 {
+ bootph-pre-ram;
compatible = "ti,k2g-sci";
ti,host-id = <12>;
@@ -19,22 +21,26 @@ sms: system-controller@44083000 {
reg = <0x00 0x44083000 0x00 0x1000>;
k3_pds: power-controller {
+ bootph-pre-ram;
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
};
k3_clks: clock-controller {
+ bootph-pre-ram;
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
k3_reset: reset-controller {
+ bootph-pre-ram;
compatible = "ti,sci-reset";
#reset-cells = <2>;
};
};
chipid@43000014 {
+ bootph-pre-ram;
compatible = "ti,am654-chipid";
reg = <0x00 0x43000014 0x00 0x4>;
};
@@ -442,6 +448,7 @@ mcu_spi2: spi@40320000 {
};
mcu_navss: bus@28380000 {
+ bootph-pre-ram;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@@ -451,6 +458,7 @@ mcu_navss: bus@28380000 {
dma-ranges;
mcu_ringacc: ringacc@2b800000 {
+ bootph-pre-ram;
compatible = "ti,am654-navss-ringacc";
reg = <0x00 0x2b800000 0x00 0x400000>,
<0x00 0x2b000000 0x00 0x400000>,
@@ -465,6 +473,7 @@ mcu_ringacc: ringacc@2b800000 {
};
mcu_udmap: dma-controller@285c0000 {
+ bootph-pre-ram;
compatible = "ti,j721e-navss-mcu-udmap";
reg = <0x00 0x285c0000 0x00 0x100>,
<0x00 0x2a800000 0x00 0x40000>,
--
2.34.1
Hi Apurva
On 8/6/2023 10:18 PM, Apurva Nandan wrote:
> Add bootph-pre-ram property for all the nodes used in SPL stage,
> for syncing it later to u-boot j784s4 dts.
>
> Signed-off-by: Apurva Nandan <[email protected]>
> ---
> arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
> index 740ee794d7b9..57bf0261c343 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
> @@ -6,7 +6,9 @@
> */
>
> &cbass_mcu_wakeup {
> + bootph-pre-ram;
> sms: system-controller@44083000 {
> + bootph-pre-ram;
> compatible = "ti,k2g-sci";
> ti,host-id = <12>;
>
> @@ -19,22 +21,26 @@ sms: system-controller@44083000 {
> reg = <0x00 0x44083000 0x00 0x1000>;
>
> k3_pds: power-controller {
> + bootph-pre-ram;
> compatible = "ti,sci-pm-domain";
> #power-domain-cells = <2>;
> };
>
> k3_clks: clock-controller {
> + bootph-pre-ram;
> compatible = "ti,k2g-sci-clk";
> #clock-cells = <2>;
> };
>
> k3_reset: reset-controller {
> + bootph-pre-ram;
> compatible = "ti,sci-reset";
> #reset-cells = <2>;
> };
> };
>
> chipid@43000014 {
> + bootph-pre-ram;
> compatible = "ti,am654-chipid";
> reg = <0x00 0x43000014 0x00 0x4>;
> };
> @@ -442,6 +448,7 @@ mcu_spi2: spi@40320000 {
> };
mcu_timer0: timer@40400000 should be part of your list.
>
> mcu_navss: bus@28380000 {
> + bootph-pre-ram;
> compatible = "simple-bus";
> #address-cells = <2>;
> #size-cells = <2>;
> @@ -451,6 +458,7 @@ mcu_navss: bus@28380000 {
> dma-ranges;
>
> mcu_ringacc: ringacc@2b800000 {
> + bootph-pre-ram;
> compatible = "ti,am654-navss-ringacc";
> reg = <0x00 0x2b800000 0x00 0x400000>,
> <0x00 0x2b000000 0x00 0x400000>,
> @@ -465,6 +473,7 @@ mcu_ringacc: ringacc@2b800000 {
> };
>
> mcu_udmap: dma-controller@285c0000 {
> + bootph-pre-ram;
> compatible = "ti,j721e-navss-mcu-udmap";
> reg = <0x00 0x285c0000 0x00 0x100>,
> <0x00 0x2a800000 0x00 0x40000>,
On 07/08/23 22:51, Nishanth Menon wrote:
> On 22:43-20230807, Apurva Nandan wrote:
> [..]
>
>>> mcu_timer0: timer@40400000 should be part of your list.
>> Maybe you are referring to mcu_timer1. mcu_timer1 will be a part of
>> u-boot.dtsi as we need to edit
>> the node for removing k3_clks and power-domains properties from it. So we
>> should add bootph-pre-ram
>> there itself in uboot.dtsi as the node will be already there.
> a) you need the timer even before talking to anything - u-boot needs it
> for basic delay - so add the pre-ram property.
> b) what you are doing in u-boot currently a hack - am625 in u-boot got
> it fixed the right way - follow the model then you dont need the hackery
> with deleting clock and power-domains properties.
>
Okay, thanks!
On 22:43-20230807, Apurva Nandan wrote:
[..]
> > mcu_timer0: timer@40400000 should be part of your list.
> Maybe you are referring to mcu_timer1. mcu_timer1 will be a part of
> u-boot.dtsi as we need to edit
> the node for removing k3_clks and power-domains properties from it. So we
> should add bootph-pre-ram
> there itself in uboot.dtsi as the node will be already there.
a) you need the timer even before talking to anything - u-boot needs it
for basic delay - so add the pre-ram property.
b) what you are doing in u-boot currently a hack - am625 in u-boot got
it fixed the right way - follow the model then you dont need the hackery
with deleting clock and power-domains properties.
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
On 07/08/23 10:01, Kumar, Udit wrote:
> Hi Apurva
>
> On 8/6/2023 10:18 PM, Apurva Nandan wrote:
>> Add bootph-pre-ram property for all the nodes used in SPL stage,
>> for syncing it later to u-boot j784s4 dts.
>>
>> Signed-off-by: Apurva Nandan <[email protected]>
>> ---
>> arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 9 +++++++++
>> 1 file changed, 9 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
>> b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
>> index 740ee794d7b9..57bf0261c343 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
>> @@ -6,7 +6,9 @@
>> */
>> &cbass_mcu_wakeup {
>> + bootph-pre-ram;
>> sms: system-controller@44083000 {
>> + bootph-pre-ram;
>> compatible = "ti,k2g-sci";
>> ti,host-id = <12>;
>> @@ -19,22 +21,26 @@ sms: system-controller@44083000 {
>> reg = <0x00 0x44083000 0x00 0x1000>;
>> k3_pds: power-controller {
>> + bootph-pre-ram;
>> compatible = "ti,sci-pm-domain";
>> #power-domain-cells = <2>;
>> };
>> k3_clks: clock-controller {
>> + bootph-pre-ram;
>> compatible = "ti,k2g-sci-clk";
>> #clock-cells = <2>;
>> };
>> k3_reset: reset-controller {
>> + bootph-pre-ram;
>> compatible = "ti,sci-reset";
>> #reset-cells = <2>;
>> };
>> };
>> chipid@43000014 {
>> + bootph-pre-ram;
>> compatible = "ti,am654-chipid";
>> reg = <0x00 0x43000014 0x00 0x4>;
>> };
>> @@ -442,6 +448,7 @@ mcu_spi2: spi@40320000 {
>> };
>
>
> mcu_timer0: timer@40400000 should be part of your list.
Maybe you are referring to mcu_timer1. mcu_timer1 will be a part of
u-boot.dtsi as we need to edit
the node for removing k3_clks and power-domains properties from it. So
we should add bootph-pre-ram
there itself in uboot.dtsi as the node will be already there.
>
>> mcu_navss: bus@28380000 {
>> + bootph-pre-ram;
>> compatible = "simple-bus";
>> #address-cells = <2>;
>> #size-cells = <2>;
>> @@ -451,6 +458,7 @@ mcu_navss: bus@28380000 {
>> dma-ranges;
>> mcu_ringacc: ringacc@2b800000 {
>> + bootph-pre-ram;
>> compatible = "ti,am654-navss-ringacc";
>> reg = <0x00 0x2b800000 0x00 0x400000>,
>> <0x00 0x2b000000 0x00 0x400000>,
>> @@ -465,6 +473,7 @@ mcu_ringacc: ringacc@2b800000 {
>> };
>> mcu_udmap: dma-controller@285c0000 {
>> + bootph-pre-ram;
>> compatible = "ti,j721e-navss-mcu-udmap";
>> reg = <0x00 0x285c0000 0x00 0x100>,
>> <0x00 0x2a800000 0x00 0x40000>,