2023-12-27 03:35:25

by Qiang Yu

Subject: [PATCH v2] arm64: dts: qcom: sm8550: Increase supported MSI interrupts.

On sm8550, synopsys MSI controller supports 256 MSI interrupts. Hence,
enable all GIC interrupts required by MSI controller for PCIe0 and PCIe1.

Signed-off-by: Qiang Yu <[email protected]>
---
v1->v2: make interrupt-names one per line

arch/arm64/boot/dts/qcom/sm8550.dtsi | 36 ++++++++++++++++++++++++++++++++----
1 file changed, 32 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index ee1ba5a..3f413cb 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1713,8 +1713,22 @@
linux,pci-domain = <0>;
num-lanes = <2>;

- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";

#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
@@ -1804,8 +1818,22 @@
linux,pci-domain = <1>;
num-lanes = <2>;

- interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";

#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
--
2.7.4

2024-01-03 13:49:04

by Konrad Dybcio

Subject: Re: [PATCH v2] arm64: dts: qcom: sm8550: Increase supported MSI interrupts.

On 27.12.2023 04:34, Qiang Yu wrote:
> On sm8550, synopsys MSI controller supports 256 MSI interrupts. Hence,
> enable all GIC interrupts required by MSI controller for PCIe0 and PCIe1.
>
> Signed-off-by: Qiang Yu <[email protected]>
> ---

Reviewed-by: Konrad Dybcio <[email protected]>

Konrad