2023-03-15 10:44:24

by Minda Chen

Subject: [PATCH v3 1/5] dt-bindings: phy: Add StarFive JH7110 USB/PCIe document

Add StarFive JH7110 SoC USB 2.0/3.0 and PCIe 2.0 PHY dt-binding.
PCIe 2.0 phy can use as USB 3.0 PHY.

Signed-off-by: Minda Chen <[email protected]>
---
.../phy/starfive,jh7110-usb-pcie-phy.yaml | 62 +++++++++++++++++++
1 file changed, 62 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-pcie-phy.yaml

diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-pcie-phy.yaml
new file mode 100644
index 000000000000..aa1c3fe93100
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-pcie-phy.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/starfive,jh7110-usb-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive USB 2.0 and PCIe 2.0 PHY
+
+maintainers:
+ - Minda Chen <[email protected]>
+
+properties:
+ compatible:
+ enum:
+ - starfive,jh7110-usb-phy
+ - starfive,jh7110-pcie-phy
+
+ reg:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+ clocks:
+ items:
+ - description: usb 125m clock
+ - description: app 125m clock
+
+ clock-names:
+ items:
+ - const: 125m
+ - const: app_125
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ phy@10200000 {
+ compatible = "starfive,jh7110-usb-phy";
+ reg = <0x10200000 0x10000>;
+ clocks = <&syscrg 95>,
+ <&stgcrg 6>;
+ clock-names = "125m", "app_125";
+ #phy-cells = <0>;
+ };
+
+ phy@10210000 {
+ compatible = "starfive,jh7110-pcie-phy";
+ reg = <0x10210000 0x10000>;
+ #phy-cells = <0>;
+ };
+
+ phy@10220000 {
+ compatible = "starfive,jh7110-pcie-phy";
+ reg = <0x10220000 0x10000>;
+ #phy-cells = <0>;
+ };
--
2.17.1

2023-03-17 08:41:24

by Krzysztof Kozlowski

Subject: Re: [PATCH v3 1/5] dt-bindings: phy: Add StarFive JH7110 USB/PCIe document

On 15/03/2023 11:44, Minda Chen wrote:
> Add StarFive JH7110 SoC USB 2.0/3.0 and PCIe 2.0 PHY dt-binding.
> PCIe 2.0 phy can use as USB 3.0 PHY.
>
> Signed-off-by: Minda Chen <[email protected]>
> ---
> .../phy/starfive,jh7110-usb-pcie-phy.yaml | 62 +++++++++++++++++++
> 1 file changed, 62 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-pcie-phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-pcie-phy.yaml
> new file mode 100644
> index 000000000000..aa1c3fe93100
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-pcie-phy.yaml
> @@ -0,0 +1,62 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/starfive,jh7110-usb-pcie-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive USB 2.0 and PCIe 2.0 PHY
> +
> +maintainers:
> + - Minda Chen <[email protected]>
> +
> +properties:
> + compatible:
> + enum:
> + - starfive,jh7110-usb-phy
> + - starfive,jh7110-pcie-phy
> +
> + reg:
> + maxItems: 1
> +
> + "#phy-cells":
> + const: 0
> +
> + clocks:
> + items:
> + - description: usb 125m clock
> + - description: app 125m clock
> +
> + clock-names:
> + items:
> + - const: 125m
> + - const: app_125
> +
> +required:
> + - compatible
> + - reg
> + - "#phy-cells"
> +

It seems pci phy does not take these clocks, thus you should have
allOf:if:then which will customize it per variant. Otherwise binding is
incorrect for the pci.

> +additionalProperties: false
> +
> +examples:
> + - |
> + phy@10200000 {
> + compatible = "starfive,jh7110-usb-phy";
> + reg = <0x10200000 0x10000>;
> + clocks = <&syscrg 95>,
> + <&stgcrg 6>;
> + clock-names = "125m", "app_125";
> + #phy-cells = <0>;
> + };
> +
> + phy@10210000 {
> + compatible = "starfive,jh7110-pcie-phy";
> + reg = <0x10210000 0x10000>;
> + #phy-cells = <0>;
> + };
> +
> + phy@10220000 {
> + compatible = "starfive,jh7110-pcie-phy";
> + reg = <0x10220000 0x10000>;
> + #phy-cells = <0>;
> + };

Drop duplicated examples. Keep usb and maybe one phy.

Best regards,
Krzysztof

2023-03-17 10:29:17

by Minda Chen

Subject: Re: [PATCH v3 1/5] dt-bindings: phy: Add StarFive JH7110 USB/PCIe document

On 2023/3/17 16:39, Krzysztof Kozlowski wrote:
> On 15/03/2023 11:44, Minda Chen wrote:
>> Add StarFive JH7110 SoC USB 2.0/3.0 and PCIe 2.0 PHY dt-binding.
>> PCIe 2.0 phy can use as USB 3.0 PHY.
>>
>> Signed-off-by: Minda Chen <[email protected]>
>> ---
>> .../phy/starfive,jh7110-usb-pcie-phy.yaml | 62 +++++++++++++++++++
>> 1 file changed, 62 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-pcie-phy.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-pcie-phy.yaml
>> new file mode 100644
>> index 000000000000..aa1c3fe93100
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-pcie-phy.yaml
>> @@ -0,0 +1,62 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/phy/starfive,jh7110-usb-pcie-phy.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive USB 2.0 and PCIe 2.0 PHY
>> +
>> +maintainers:
>> + - Minda Chen <[email protected]>
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - starfive,jh7110-usb-phy
>> + - starfive,jh7110-pcie-phy
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + "#phy-cells":
>> + const: 0
>> +
>> + clocks:
>> + items:
>> + - description: usb 125m clock
>> + - description: app 125m clock
>> +
>> + clock-names:
>> + items:
>> + - const: 125m
>> + - const: app_125
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - "#phy-cells"
>> +
>
> It seems pci phy does not take these clocks, thus you should have
> allOf:if:then which will customize it per variant. Otherwise binding is
> incorrect for the pci.
>
ok
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + phy@10200000 {
>> + compatible = "starfive,jh7110-usb-phy";
>> + reg = <0x10200000 0x10000>;
>> + clocks = <&syscrg 95>,
>> + <&stgcrg 6>;
>> + clock-names = "125m", "app_125";
>> + #phy-cells = <0>;
>> + };
>> +
>> + phy@10210000 {
>> + compatible = "starfive,jh7110-pcie-phy";
>> + reg = <0x10210000 0x10000>;
>> + #phy-cells = <0>;
>> + };
>> +
>> + phy@10220000 {
>> + compatible = "starfive,jh7110-pcie-phy";
>> + reg = <0x10220000 0x10000>;
>> + #phy-cells = <0>;
>> + };
>
> Drop duplicated examples. Keep usb and maybe one phy.
>
ok, thanks
> Best regards,
> Krzysztof
>