From: Fenghua Yu <[email protected]>
The documentation mentions that non-contiguous bit masks are not
supported in Intel Cache Allocation Technology (CAT).
Update the documentation on how to determine if sparse bit masks are
allowed in L2 and L3 CAT.
Mention the file with feature support information is located in
the /sys/fs/resctrl/info/{resource}/ directories and enumerate what
are the possible outputs on file read operation.
Signed-off-by: Fenghua Yu <[email protected]>
Signed-off-by: Maciej Wieczor-Retman <[email protected]>
Tested-by: Peter Newman <[email protected]>
Reviewed-by: Ilpo Järvinen <[email protected]>
Reviewed-by: Peter Newman <[email protected]>
Reviewed-by: Reinette Chatre <[email protected]>
---
Changelog v4:
- Add Ilpo's reviewed-by tag.
- Add Reinette's reviewed-by tag.
Changelog v3:
- Add Peter's tested-by and reviewed-by tags.
Changelog v2:
- Change bitmap naming convention to bit mask. (Reinette)
Documentation/arch/x86/resctrl.rst | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/resctrl.rst
index cb05d90111b4..4c6421e2aa31 100644
--- a/Documentation/arch/x86/resctrl.rst
+++ b/Documentation/arch/x86/resctrl.rst
@@ -124,6 +124,13 @@ related to allocation:
"P":
Corresponding region is pseudo-locked. No
sharing allowed.
+"sparse_masks":
+ Indicates if non-contiguous 1s value in CBM is supported.
+
+ "0":
+ Only contiguous 1s value in CBM is supported.
+ "1":
+ Non-contiguous 1s value in CBM is supported.
Memory bandwidth(MB) subdirectory contains the following files
with respect to allocation:
@@ -445,12 +452,13 @@ For cache resources we describe the portion of the cache that is available
for allocation using a bitmask. The maximum value of the mask is defined
by each cpu model (and may be different for different cache levels). It
is found using CPUID, but is also provided in the "info" directory of
-the resctrl file system in "info/{resource}/cbm_mask". Intel hardware
+the resctrl file system in "info/{resource}/cbm_mask". Some Intel hardware
requires that these masks have all the '1' bits in a contiguous block. So
0x3, 0x6 and 0xC are legal 4-bit masks with two bits set, but 0x5, 0x9
-and 0xA are not. On a system with a 20-bit mask each bit represents 5%
-of the capacity of the cache. You could partition the cache into four
-equal parts with masks: 0x1f, 0x3e0, 0x7c00, 0xf8000.
+and 0xA are not. Check /sys/fs/resctrl/info/{resource}/sparse_masks
+if non-contiguous 1s value is supported. On a system with a 20-bit mask
+each bit represents 5% of the capacity of the cache. You could partition
+the cache into four equal parts with masks: 0x1f, 0x3e0, 0x7c00, 0xf8000.
Memory bandwidth Allocation and monitoring
==========================================
--
2.42.0
Hi Maciej,
My last comment didn't make it to lkml. Could be my mail server
problem. Commenting again.
On 10/5/2023 3:15 AM, Maciej Wieczor-Retman wrote:
> From: Fenghua Yu <[email protected]>
>
> The documentation mentions that non-contiguous bit masks are not
> supported in Intel Cache Allocation Technology (CAT).
>
> Update the documentation on how to determine if sparse bit masks are
> allowed in L2 and L3 CAT.
>
> Mention the file with feature support information is located in
> the /sys/fs/resctrl/info/{resource}/ directories and enumerate what
> are the possible outputs on file read operation.
This last paragraph is not clear. All the information is already in the
documentation.
You can drop this paragraph. First two paragraphs are fine.
>
> Signed-off-by: Fenghua Yu <[email protected]>
> Signed-off-by: Maciej Wieczor-Retman <[email protected]>
> Tested-by: Peter Newman <[email protected]>
> Reviewed-by: Ilpo Järvinen <[email protected]>
> Reviewed-by: Peter Newman <[email protected]>
> Reviewed-by: Reinette Chatre <[email protected]>
Otherwise patch looks fine.
Reviewed-by: Babu Moger <[email protected]>
Thanks
Babu
> ---
> Changelog v4:
> - Add Ilpo's reviewed-by tag.
> - Add Reinette's reviewed-by tag.
>
> Changelog v3:
> - Add Peter's tested-by and reviewed-by tags.
>
> Changelog v2:
> - Change bitmap naming convention to bit mask. (Reinette)
>
> Documentation/arch/x86/resctrl.rst | 16 ++++++++++++----
> 1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/resctrl.rst
> index cb05d90111b4..4c6421e2aa31 100644
> --- a/Documentation/arch/x86/resctrl.rst
> +++ b/Documentation/arch/x86/resctrl.rst
> @@ -124,6 +124,13 @@ related to allocation:
> "P":
> Corresponding region is pseudo-locked. No
> sharing allowed.
> +"sparse_masks":
> + Indicates if non-contiguous 1s value in CBM is supported.
> +
> + "0":
> + Only contiguous 1s value in CBM is supported.
> + "1":
> + Non-contiguous 1s value in CBM is supported.
>
> Memory bandwidth(MB) subdirectory contains the following files
> with respect to allocation:
> @@ -445,12 +452,13 @@ For cache resources we describe the portion of the cache that is available
> for allocation using a bitmask. The maximum value of the mask is defined
> by each cpu model (and may be different for different cache levels). It
> is found using CPUID, but is also provided in the "info" directory of
> -the resctrl file system in "info/{resource}/cbm_mask". Intel hardware
> +the resctrl file system in "info/{resource}/cbm_mask". Some Intel hardware
> requires that these masks have all the '1' bits in a contiguous block. So
> 0x3, 0x6 and 0xC are legal 4-bit masks with two bits set, but 0x5, 0x9
> -and 0xA are not. On a system with a 20-bit mask each bit represents 5%
> -of the capacity of the cache. You could partition the cache into four
> -equal parts with masks: 0x1f, 0x3e0, 0x7c00, 0xf8000.
> +and 0xA are not. Check /sys/fs/resctrl/info/{resource}/sparse_masks
> +if non-contiguous 1s value is supported. On a system with a 20-bit mask
> +each bit represents 5% of the capacity of the cache. You could partition
> +the cache into four equal parts with masks: 0x1f, 0x3e0, 0x7c00, 0xf8000.
>
> Memory bandwidth Allocation and monitoring
> ==========================================
Hi, thanks for reviewing the series!
On 2023-10-06 at 15:42:15 -0500, Moger, Babu wrote:
>Hi Maciej,
>
>My last comment didn't make it to lkml.? Could be my mail server problem.
>Commenting again.
>
>On 10/5/2023 3:15 AM, Maciej Wieczor-Retman wrote:
>> From: Fenghua Yu <[email protected]>
>>
>> The documentation mentions that non-contiguous bit masks are not
>> supported in Intel Cache Allocation Technology (CAT).
>>
>> Update the documentation on how to determine if sparse bit masks are
>> allowed in L2 and L3 CAT.
>>
>> Mention the file with feature support information is located in
>> the /sys/fs/resctrl/info/{resource}/ directories and enumerate what
>> are the possible outputs on file read operation.
>
>This last paragraph is not clear.? All the information is already in the
>documentation.
Right, I guess that paragraph does mirror patch contents a bit too much.
I'll remove it and repost it.
>You can drop this paragraph. First two paragraphs are fine.
>
>>
>> Signed-off-by: Fenghua Yu <[email protected]>
>> Signed-off-by: Maciej Wieczor-Retman <[email protected]>
>> Tested-by: Peter Newman <[email protected]>
>> Reviewed-by: Ilpo J?rvinen <[email protected]>
>> Reviewed-by: Peter Newman <[email protected]>
>> Reviewed-by: Reinette Chatre <[email protected]>
>
>Otherwise patch looks fine.
>
>Reviewed-by: Babu Moger <[email protected]>
>
>Thanks
>
>Babu
>
--
Kind regards
Maciej Wiecz?r-Retman