2024-03-28 02:23:15

by Maximilian Luz

Subject: [PATCH] arm64: dts: qcom: sc8180x: Fix ss_phy_irq for secondary USB controller

The ACPI DSDT of the Surface Pro X (SQ2) specifies the interrupts for
the secondary UBS controller as

Name (_CRS, ResourceTemplate ()
{
Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
{
0x000000AA,
}
Interrupt (ResourceConsumer, Level, ActiveHigh, SharedAndWake, ,, )
{
0x000000A7, // hs_phy_irq: &intc GIC_SPI 136
}
Interrupt (ResourceConsumer, Level, ActiveHigh, SharedAndWake, ,, )
{
0x00000228, // ss_phy_irq: &pdc 40
}
Interrupt (ResourceConsumer, Edge, ActiveHigh, SharedAndWake, ,, )
{
0x0000020A, // dm_hs_phy_irq: &pdc 10
}
Interrupt (ResourceConsumer, Edge, ActiveHigh, SharedAndWake, ,, )
{
0x0000020B, // dp_hs_phy_irq: &pdc 11
}
})

Generally, the interrupts above 0x200 map to the PDC interrupts (as used
in the devicetree) as ACPI_NUMBER - 0x200. Note that this lines up with
dm_hs_phy_irq and dp_hs_phy_irq (as well as the interrupts for the
primary USB controller).

Based on the snippet above, ss_phy_irq should therefore be PDC 40 (=
0x28) and not PDC 7. The latter is according to ACPI instead used as
ss_phy_irq for port 0 of the multiport USB controller). Fix this by
setting ss_phy_irq to '&pdc 40'.

Fixes: b080f53a8f44 ("arm64: dts: qcom: sc8180x: Add remoteprocs, wifi and usb nodes")
Signed-off-by: Maximilian Luz <[email protected]>
---
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index 32afc78d5b769..053f7861c3cec 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
@@ -2701,7 +2701,7 @@ usb_sec: usb@a8f8800 {
resets = <&gcc GCC_USB30_SEC_BCR>;
power-domains = <&gcc USB30_SEC_GDSC>;
interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 7 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 40 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 10 IRQ_TYPE_EDGE_BOTH>,
<&pdc 11 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
--
2.44.0

2024-03-28 02:29:56

by Bjorn Andersson

Subject: Re: [PATCH] arm64: dts: qcom: sc8180x: Fix ss_phy_irq for secondary USB controller

On Thu, Mar 28, 2024 at 03:21:57AM +0100, Maximilian Luz wrote:
> The ACPI DSDT of the Surface Pro X (SQ2) specifies the interrupts for
> the secondary UBS controller as
>
> Name (_CRS, ResourceTemplate ()
> {
> Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
> {
> 0x000000AA,
> }
> Interrupt (ResourceConsumer, Level, ActiveHigh, SharedAndWake, ,, )
> {
> 0x000000A7, // hs_phy_irq: &intc GIC_SPI 136
> }
> Interrupt (ResourceConsumer, Level, ActiveHigh, SharedAndWake, ,, )
> {
> 0x00000228, // ss_phy_irq: &pdc 40
> }
> Interrupt (ResourceConsumer, Edge, ActiveHigh, SharedAndWake, ,, )
> {
> 0x0000020A, // dm_hs_phy_irq: &pdc 10
> }
> Interrupt (ResourceConsumer, Edge, ActiveHigh, SharedAndWake, ,, )
> {
> 0x0000020B, // dp_hs_phy_irq: &pdc 11
> }
> })
>
> Generally, the interrupts above 0x200 map to the PDC interrupts (as used
> in the devicetree) as ACPI_NUMBER - 0x200. Note that this lines up with
> dm_hs_phy_irq and dp_hs_phy_irq (as well as the interrupts for the
> primary USB controller).
>
> Based on the snippet above, ss_phy_irq should therefore be PDC 40 (=
> 0x28) and not PDC 7. The latter is according to ACPI instead used as
> ss_phy_irq for port 0 of the multiport USB controller). Fix this by
> setting ss_phy_irq to '&pdc 40'.
>
> Fixes: b080f53a8f44 ("arm64: dts: qcom: sc8180x: Add remoteprocs, wifi and usb nodes")
> Signed-off-by: Maximilian Luz <[email protected]>

Reviewed-by: Bjorn Andersson <[email protected]>

Regards,
Bjorn

> ---
> arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
> index 32afc78d5b769..053f7861c3cec 100644
> --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
> @@ -2701,7 +2701,7 @@ usb_sec: usb@a8f8800 {
> resets = <&gcc GCC_USB30_SEC_BCR>;
> power-domains = <&gcc USB30_SEC_GDSC>;
> interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
> - <&pdc 7 IRQ_TYPE_LEVEL_HIGH>,
> + <&pdc 40 IRQ_TYPE_LEVEL_HIGH>,
> <&pdc 10 IRQ_TYPE_EDGE_BOTH>,
> <&pdc 11 IRQ_TYPE_EDGE_BOTH>;
> interrupt-names = "hs_phy_irq", "ss_phy_irq",
> --
> 2.44.0
>