This series introduces support for A690 in the DRM/MSM driver and
enables it for the two SC8280XP laptops.
Bjorn Andersson (3):
drm/msm/adreno: Add Adreno A690 support
arm64: dts: qcom: sc8280xp: Add GPU related nodes
arm64: dts: qcom: sc8280xp: Enable GPU related nodes
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 26 +++
.../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 26 +++
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 169 ++++++++++++++++++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 113 +++++++++++-
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 33 ++++
drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 11 +-
7 files changed, 387 insertions(+), 5 deletions(-)
--
2.39.2
From: Bjorn Andersson <[email protected]>
Add memory reservation for the zap-shader and enable the Adreno SMMU,
GPU clock controller, GMU and the GPU nodes for the SC8280XP CRD and the
Lenovo ThinkPad X13s.
Signed-off-by: Bjorn Andersson <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
---
Changes since v1:
- None
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 26 +++++++++++++++++++
.../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 26 +++++++++++++++++++
2 files changed, 52 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
index 5b25d54b9591..547277924ea3 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
@@ -210,6 +210,11 @@ vreg_wwan: regulator-wwan {
};
reserved-memory {
+ gpu_mem: gpu-mem@8bf00000 {
+ reg = <0 0x8bf00000 0 0x2000>;
+ no-map;
+ };
+
linux,cma {
compatible = "shared-dma-pool";
size = <0x0 0x8000000>;
@@ -259,6 +264,10 @@ usb1_sbu_mux: endpoint {
};
};
+&adreno_smmu {
+ status = "okay";
+};
+
&apps_rsc {
regulators-0 {
compatible = "qcom,pm8350-rpmh-regulators";
@@ -376,6 +385,23 @@ &dispcc0 {
status = "okay";
};
+&gmu {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+
+ zap-shader {
+ memory-region = <&gpu_mem>;
+ firmware-name = "qcom/sc8280xp/qcdxkmsuc8280.mbn";
+ };
+};
+
+&gpucc {
+ status = "okay";
+};
+
&mdss0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
index bdcba719fc38..5ef3f4c07d75 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
@@ -264,6 +264,11 @@ vreg_wwan: regulator-wwan {
};
reserved-memory {
+ gpu_mem: gpu-mem@8bf00000 {
+ reg = <0 0x8bf00000 0 0x2000>;
+ no-map;
+ };
+
linux,cma {
compatible = "shared-dma-pool";
size = <0x0 0x8000000>;
@@ -359,6 +364,10 @@ usb1_sbu_mux: endpoint {
};
};
+&adreno_smmu {
+ status = "okay";
+};
+
&apps_rsc {
regulators-0 {
compatible = "qcom,pm8350-rpmh-regulators";
@@ -518,6 +527,23 @@ &dispcc0 {
status = "okay";
};
+&gmu {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+
+ zap-shader {
+ memory-region = <&gpu_mem>;
+ firmware-name = "qcom/sc8280xp/LENOVO/21BX/qcdxkmsuc8280.mbn";
+ };
+};
+
+&gpucc {
+ status = "okay";
+};
+
&mdss0 {
status = "okay";
};
--
2.39.2
From: Bjorn Andersson <[email protected]>
Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the
SC8280XP.
Signed-off-by: Bjorn Andersson <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
---
Changes since v1:
- Dropped gmu_pdc_seq region from &gmu, as it shouldn't have been used.
- Added missing compatible to &adreno_smmu.
- Dropped aoss_qmp clock in &gmu and &adreno_smmu.
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 169 +++++++++++++++++++++++++
1 file changed, 169 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index d2a2224d138a..329ec2119ecf 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
+#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc8280xp.h>
@@ -2331,6 +2332,174 @@ tcsr: syscon@1fc0000 {
reg = <0x0 0x01fc0000 0x0 0x30000>;
};
+ gpu: gpu@3d00000 {
+ compatible = "qcom,adreno-690.0", "qcom,adreno";
+
+ reg = <0 0x03d00000 0 0x40000>,
+ <0 0x03d9e000 0 0x1000>,
+ <0 0x03d61000 0 0x800>;
+ reg-names = "kgsl_3d0_reg_memory",
+ "cx_mem",
+ "cx_dbgc";
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&adreno_smmu 0 0xc00>, <&adreno_smmu 1 0xc00>;
+ operating-points-v2 = <&gpu_opp_table>;
+
+ qcom,gmu = <&gmu>;
+ interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "gfx-mem";
+ #cooling-cells = <2>;
+
+ status = "disabled";
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ opp-peak-kBps = <451000>;
+ };
+
+ opp-410000000 {
+ opp-hz = /bits/ 64 <410000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ opp-peak-kBps = <1555000>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ opp-peak-kBps = <1555000>;
+ };
+
+ opp-547000000 {
+ opp-hz = /bits/ 64 <547000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+ opp-peak-kBps = <1555000>;
+ };
+
+ opp-606000000 {
+ opp-hz = /bits/ 64 <606000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ opp-peak-kBps = <2736000>;
+ };
+
+ opp-640000000 {
+ opp-hz = /bits/ 64 <640000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ opp-peak-kBps = <2736000>;
+ };
+
+ opp-690000000 {
+ opp-hz = /bits/ 64 <690000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ opp-peak-kBps = <2736000>;
+ };
+ };
+ };
+
+ gmu: gmu@3d6a000 {
+ compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
+ reg = <0 0x03d6a000 0 0x34000>,
+ <0 0x03de0000 0 0x10000>,
+ <0 0x0b290000 0 0x10000>;
+ reg-names = "gmu", "rscc", "gmu_pdc";
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hfi", "gmu";
+ clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
+ clock-names = "gmu",
+ "cxo",
+ "axi",
+ "memnoc",
+ "ahb",
+ "hub",
+ "smmu_vote";
+ power-domains = <&gpucc GPU_CC_CX_GDSC>,
+ <&gpucc GPU_CC_GX_GDSC>;
+ power-domain-names = "cx",
+ "gx";
+ iommus = <&adreno_smmu 5 0xc00>;
+ operating-points-v2 = <&gmu_opp_table>;
+
+ status = "disabled";
+
+ gmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+ };
+ };
+
+ gpucc: clock-controller@3d90000 {
+ compatible = "qcom,sc8280xp-gpucc";
+ reg = <0 0x03d90000 0 0x9000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+ clock-names = "bi_tcxo",
+ "gcc_gpu_gpll0_clk_src",
+ "gcc_gpu_gpll0_div_clk_src";
+
+ power-domains = <&rpmhpd SC8280XP_GFX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+
+ status = "disabled";
+ };
+
+ adreno_smmu: iommu@3da0000 {
+ compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu",
+ "qcom,smmu-500", "arm,mmu-500";
+ reg = <0 0x03da0000 0 0x20000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+ <&gpucc GPU_CC_HUB_AON_CLK>;
+ clock-names = "gcc_gpu_memnoc_gfx_clk",
+ "gcc_gpu_snoc_dvm_gfx_clk",
+ "gpu_cc_ahb_clk",
+ "gpu_cc_hlos1_vote_gpu_smmu_clk",
+ "gpu_cc_cx_gmu_clk",
+ "gpu_cc_hub_cx_int_clk",
+ "gpu_cc_hub_aon_clk";
+
+ power-domains = <&gpucc GPU_CC_CX_GDSC>;
+
+ status = "disabled";
+ };
+
usb_0_hsphy: phy@88e5000 {
compatible = "qcom,sc8280xp-usb-hs-phy",
"qcom,usb-snps-hs-5nm-phy";
--
2.39.2
From: Bjorn Andersson <[email protected]>
Introduce support for the Adreno A690, found in Qualcomm SC8280XP.
Signed-off-by: Bjorn Andersson <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
---
Changes since v1:
- Moved a690 to adreno_is_a660_family(), which simplifies hw_init() and
ensured that pdc_in_aop got set.
- Dropped dynamic lookup in cmd-db. Will look into posting this
separately.
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 113 ++++++++++++++++++++-
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 33 ++++++
drivers/gpu/drm/msm/adreno/adreno_device.c | 14 +++
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 11 +-
4 files changed, 166 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 9fb214f150dd..cabc8f9a12d7 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -588,6 +588,63 @@ const struct adreno_reglist a660_hwcg[] = {
{},
};
+const struct adreno_reglist a690_hwcg[] = {
+ {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
+ {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
+ {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
+ {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
+ {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
+ {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
+ {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
+ {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
+ {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
+ {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
+ {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
+ {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
+ {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
+ {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
+ {REG_A6XX_RBBM_CLOCK_CNTL, 0x8AA8AA82},
+ {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
+ {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
+ {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
+ {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
+ {REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 0x20200},
+ {REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111},
+ {REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555},
+ {}
+};
+
static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
@@ -747,6 +804,45 @@ static const u32 a660_protect[] = {
A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
};
+/* These are for a690 */
+static const u32 a690_protect[] = {
+ A6XX_PROTECT_RDONLY(0x00000, 0x004ff),
+ A6XX_PROTECT_RDONLY(0x00501, 0x00001),
+ A6XX_PROTECT_RDONLY(0x0050b, 0x002f4),
+ A6XX_PROTECT_NORDWR(0x0050e, 0x00000),
+ A6XX_PROTECT_NORDWR(0x00510, 0x00000),
+ A6XX_PROTECT_NORDWR(0x00534, 0x00000),
+ A6XX_PROTECT_NORDWR(0x00800, 0x00082),
+ A6XX_PROTECT_NORDWR(0x008a0, 0x00008),
+ A6XX_PROTECT_NORDWR(0x008ab, 0x00024),
+ A6XX_PROTECT_RDONLY(0x008d0, 0x000bc),
+ A6XX_PROTECT_NORDWR(0x00900, 0x0004d),
+ A6XX_PROTECT_NORDWR(0x0098d, 0x00272),
+ A6XX_PROTECT_NORDWR(0x00e00, 0x00001),
+ A6XX_PROTECT_NORDWR(0x00e03, 0x0000c),
+ A6XX_PROTECT_NORDWR(0x03c00, 0x000c3),
+ A6XX_PROTECT_RDONLY(0x03cc4, 0x01fff),
+ A6XX_PROTECT_NORDWR(0x08630, 0x001cf),
+ A6XX_PROTECT_NORDWR(0x08e00, 0x00000),
+ A6XX_PROTECT_NORDWR(0x08e08, 0x00008),
+ A6XX_PROTECT_NORDWR(0x08e50, 0x0001f),
+ A6XX_PROTECT_NORDWR(0x08e80, 0x0027f),
+ A6XX_PROTECT_NORDWR(0x09624, 0x001db),
+ A6XX_PROTECT_NORDWR(0x09e60, 0x00011),
+ A6XX_PROTECT_NORDWR(0x09e78, 0x00187),
+ A6XX_PROTECT_NORDWR(0x0a630, 0x001cf),
+ A6XX_PROTECT_NORDWR(0x0ae02, 0x00000),
+ A6XX_PROTECT_NORDWR(0x0ae50, 0x0012f),
+ A6XX_PROTECT_NORDWR(0x0b604, 0x00000),
+ A6XX_PROTECT_NORDWR(0x0b608, 0x00006),
+ A6XX_PROTECT_NORDWR(0x0be02, 0x00001),
+ A6XX_PROTECT_NORDWR(0x0be20, 0x0015f),
+ A6XX_PROTECT_NORDWR(0x0d000, 0x005ff),
+ A6XX_PROTECT_NORDWR(0x0f000, 0x00bff),
+ A6XX_PROTECT_RDONLY(0x0fc00, 0x01fff),
+ A6XX_PROTECT_NORDWR(0x11c00, 0x00000), /*note: infiite range */
+};
+
static void a6xx_set_cp_protect(struct msm_gpu *gpu)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
@@ -758,6 +854,11 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)
count = ARRAY_SIZE(a650_protect);
count_max = 48;
BUILD_BUG_ON(ARRAY_SIZE(a650_protect) > 48);
+ } else if (adreno_is_a690(adreno_gpu)) {
+ regs = a690_protect;
+ count = ARRAY_SIZE(a690_protect);
+ count_max = 48;
+ BUILD_BUG_ON(ARRAY_SIZE(a690_protect) > 48);
} else if (adreno_is_a660_family(adreno_gpu)) {
regs = a660_protect;
count = ARRAY_SIZE(a660_protect);
@@ -806,6 +907,13 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
uavflagprd_inv = 2;
}
+ if (adreno_is_a690(adreno_gpu)) {
+ lower_bit = 2;
+ amsbc = 1;
+ rgb565_predicator = 1;
+ uavflagprd_inv = 2;
+ }
+
if (adreno_is_7c3(adreno_gpu)) {
lower_bit = 1;
amsbc = 1;
@@ -1084,7 +1192,7 @@ static int hw_init(struct msm_gpu *gpu)
/* Setting the primFifo thresholds default values,
* and vccCacheSkipDis=1 bit (0x200) for A640 and newer
*/
- if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
+ if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu) || adreno_is_a690(adreno_gpu))
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);
else if (adreno_is_a640_family(adreno_gpu) || adreno_is_7c3(adreno_gpu))
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200);
@@ -1991,7 +2099,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
info = adreno_info(config->rev);
if (info && (info->revn == 650 || info->revn == 660 ||
- adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), info->rev)))
+ info->revn == 690 ||
+ adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), info->rev)))
adreno_gpu->base.hw_apriv = true;
a6xx_llc_slices_init(pdev, a6xx_gpu);
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
index 2cc83e049613..25b235b49ebc 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
@@ -414,6 +414,37 @@ static void a650_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
msg->cnoc_cmds_data[1][0] = 0x60000001;
}
+static void a690_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
+{
+ /*
+ * Send a single "off" entry just to get things running
+ * TODO: bus scaling
+ */
+ msg->bw_level_num = 1;
+
+ msg->ddr_cmds_num = 3;
+ msg->ddr_wait_bitmask = 0x01;
+
+ msg->ddr_cmds_addrs[0] = 0x50004;
+ msg->ddr_cmds_addrs[1] = 0x50000;
+ msg->ddr_cmds_addrs[2] = 0x500ac;
+
+ msg->ddr_cmds_data[0][0] = 0x40000000;
+ msg->ddr_cmds_data[0][1] = 0x40000000;
+ msg->ddr_cmds_data[0][2] = 0x40000000;
+
+ /*
+ * These are the CX (CNOC) votes - these are used by the GMU but the
+ * votes are known and fixed for the target
+ */
+ msg->cnoc_cmds_num = 1;
+ msg->cnoc_wait_bitmask = 0x01;
+
+ msg->cnoc_cmds_addrs[0] = 0x5003c;
+ msg->cnoc_cmds_data[0][0] = 0x40000000;
+ msg->cnoc_cmds_data[1][0] = 0x60000001;
+}
+
static void a660_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
{
/*
@@ -531,6 +562,8 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu)
adreno_7c3_build_bw_table(&msg);
else if (adreno_is_a660(adreno_gpu))
a660_build_bw_table(&msg);
+ else if (adreno_is_a690(adreno_gpu))
+ a690_build_bw_table(&msg);
else
a6xx_build_bw_table(&msg);
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 8cff86e9d35c..e5a865024e94 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -355,6 +355,20 @@ static const struct adreno_info gpulist[] = {
.init = a6xx_gpu_init,
.zapfw = "a640_zap.mdt",
.hwcg = a640_hwcg,
+ }, {
+ .rev = ADRENO_REV(6, 9, 0, ANY_ID),
+ .revn = 690,
+ .name = "A690",
+ .fw = {
+ [ADRENO_FW_SQE] = "a660_sqe.fw",
+ [ADRENO_FW_GMU] = "a690_gmu.bin",
+ },
+ .gmem = SZ_4M,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .init = a6xx_gpu_init,
+ .zapfw = "a690_zap.mdt",
+ .hwcg = a690_hwcg,
+ .address_space_size = SZ_16G,
},
};
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index f62612a5c70f..ac9c429ca07b 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -55,7 +55,7 @@ struct adreno_reglist {
u32 value;
};
-extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[];
+extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[], a690_hwcg[];
struct adreno_info {
struct adreno_rev rev;
@@ -272,6 +272,11 @@ static inline int adreno_is_a660(struct adreno_gpu *gpu)
return gpu->revn == 660;
}
+static inline int adreno_is_a690(struct adreno_gpu *gpu)
+{
+ return gpu->revn == 690;
+};
+
/* check for a615, a616, a618, a619 or any derivatives */
static inline int adreno_is_a615_family(struct adreno_gpu *gpu)
{
@@ -280,13 +285,13 @@ static inline int adreno_is_a615_family(struct adreno_gpu *gpu)
static inline int adreno_is_a660_family(struct adreno_gpu *gpu)
{
- return adreno_is_a660(gpu) || adreno_is_7c3(gpu);
+ return adreno_is_a660(gpu) || adreno_is_a690(gpu) || adreno_is_7c3(gpu);
}
/* check for a650, a660, or any derivatives */
static inline int adreno_is_a650_family(struct adreno_gpu *gpu)
{
- return gpu->revn == 650 || gpu->revn == 620 || adreno_is_a660_family(gpu);
+ return gpu->revn == 650 || gpu->revn == 620 || adreno_is_a660_family(gpu);
}
u64 adreno_private_address_space_size(struct msm_gpu *gpu);
--
2.39.2
On Mon, May 22, 2023 at 8:15 PM Bjorn Andersson
<[email protected]> wrote:
>
> This series introduces support for A690 in the DRM/MSM driver and
> enables it for the two SC8280XP laptops.
>
> Bjorn Andersson (3):
> drm/msm/adreno: Add Adreno A690 support
> arm64: dts: qcom: sc8280xp: Add GPU related nodes
> arm64: dts: qcom: sc8280xp: Enable GPU related nodes
>
> arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 26 +++
> .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 26 +++
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 169 ++++++++++++++++++
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 113 +++++++++++-
> drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 33 ++++
> drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 11 +-
> 7 files changed, 387 insertions(+), 5 deletions(-)
>
> --
> 2.39.2
>
Tested here on my X13s with GNOME 44.1 and using Wayland.
Tested-by: Steev Klimaszewski <[email protected]>
On 23.05.2023 03:15, Bjorn Andersson wrote:
> From: Bjorn Andersson <[email protected]>
>
> Introduce support for the Adreno A690, found in Qualcomm SC8280XP.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
>
> Changes since v1:
> - Moved a690 to adreno_is_a660_family(), which simplifies hw_init() and
> ensured that pdc_in_aop got set.
> - Dropped dynamic lookup in cmd-db. Will look into posting this
> separately.
>
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 113 ++++++++++++++++++++-
> drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 33 ++++++
> drivers/gpu/drm/msm/adreno/adreno_device.c | 14 +++
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 11 +-
> 4 files changed, 166 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index 9fb214f150dd..cabc8f9a12d7 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -588,6 +588,63 @@ const struct adreno_reglist a660_hwcg[] = {
> {},
> };
>
> +const struct adreno_reglist a690_hwcg[] = {
> + {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
> + {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
> + {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
> + {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
> + {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
> + {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
> + {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
> + {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
> + {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
> + {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
> + {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
> + {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
> + {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
> + {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
> + {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
> + {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
> + {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
> + {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
> + {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
> + {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
> + {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
> + {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
> + {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
> + {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
> + {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
> + {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
> + {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
> + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
> + {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
> + {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
> + {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
> + {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
> + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
> + {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
> + {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
> + {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
> + {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
> + {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
> + {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
> + {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
> + {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
> + {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
> + {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
> + {REG_A6XX_RBBM_CLOCK_CNTL, 0x8AA8AA82},
> + {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
> + {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
> + {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
> + {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
> + {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
> + {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
> + {REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 0x20200},
> + {REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111},
> + {REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555},
> + {}
> +};
> +
> static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
> {
> struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> @@ -747,6 +804,45 @@ static const u32 a660_protect[] = {
> A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
> };
>
> +/* These are for a690 */
> +static const u32 a690_protect[] = {
> + A6XX_PROTECT_RDONLY(0x00000, 0x004ff),
> + A6XX_PROTECT_RDONLY(0x00501, 0x00001),
> + A6XX_PROTECT_RDONLY(0x0050b, 0x002f4),
> + A6XX_PROTECT_NORDWR(0x0050e, 0x00000),
> + A6XX_PROTECT_NORDWR(0x00510, 0x00000),
> + A6XX_PROTECT_NORDWR(0x00534, 0x00000),
> + A6XX_PROTECT_NORDWR(0x00800, 0x00082),
> + A6XX_PROTECT_NORDWR(0x008a0, 0x00008),
> + A6XX_PROTECT_NORDWR(0x008ab, 0x00024),
> + A6XX_PROTECT_RDONLY(0x008d0, 0x000bc),
> + A6XX_PROTECT_NORDWR(0x00900, 0x0004d),
> + A6XX_PROTECT_NORDWR(0x0098d, 0x00272),
> + A6XX_PROTECT_NORDWR(0x00e00, 0x00001),
> + A6XX_PROTECT_NORDWR(0x00e03, 0x0000c),
> + A6XX_PROTECT_NORDWR(0x03c00, 0x000c3),
> + A6XX_PROTECT_RDONLY(0x03cc4, 0x01fff),
> + A6XX_PROTECT_NORDWR(0x08630, 0x001cf),
> + A6XX_PROTECT_NORDWR(0x08e00, 0x00000),
> + A6XX_PROTECT_NORDWR(0x08e08, 0x00008),
> + A6XX_PROTECT_NORDWR(0x08e50, 0x0001f),
> + A6XX_PROTECT_NORDWR(0x08e80, 0x0027f),
> + A6XX_PROTECT_NORDWR(0x09624, 0x001db),
> + A6XX_PROTECT_NORDWR(0x09e60, 0x00011),
> + A6XX_PROTECT_NORDWR(0x09e78, 0x00187),
> + A6XX_PROTECT_NORDWR(0x0a630, 0x001cf),
> + A6XX_PROTECT_NORDWR(0x0ae02, 0x00000),
> + A6XX_PROTECT_NORDWR(0x0ae50, 0x0012f),
> + A6XX_PROTECT_NORDWR(0x0b604, 0x00000),
> + A6XX_PROTECT_NORDWR(0x0b608, 0x00006),
> + A6XX_PROTECT_NORDWR(0x0be02, 0x00001),
> + A6XX_PROTECT_NORDWR(0x0be20, 0x0015f),
> + A6XX_PROTECT_NORDWR(0x0d000, 0x005ff),
> + A6XX_PROTECT_NORDWR(0x0f000, 0x00bff),
> + A6XX_PROTECT_RDONLY(0x0fc00, 0x01fff),
> + A6XX_PROTECT_NORDWR(0x11c00, 0x00000), /*note: infiite range */
> +};
> +
> static void a6xx_set_cp_protect(struct msm_gpu *gpu)
> {
> struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> @@ -758,6 +854,11 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)
> count = ARRAY_SIZE(a650_protect);
> count_max = 48;
> BUILD_BUG_ON(ARRAY_SIZE(a650_protect) > 48);
> + } else if (adreno_is_a690(adreno_gpu)) {
> + regs = a690_protect;
> + count = ARRAY_SIZE(a690_protect);
> + count_max = 48;
> + BUILD_BUG_ON(ARRAY_SIZE(a690_protect) > 48);
> } else if (adreno_is_a660_family(adreno_gpu)) {
> regs = a660_protect;
> count = ARRAY_SIZE(a660_protect);
> @@ -806,6 +907,13 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
> uavflagprd_inv = 2;
> }
>
> + if (adreno_is_a690(adreno_gpu)) {
> + lower_bit = 2;
> + amsbc = 1;
> + rgb565_predicator = 1;
> + uavflagprd_inv = 2;
> + }
> +
> if (adreno_is_7c3(adreno_gpu)) {
> lower_bit = 1;
> amsbc = 1;
> @@ -1084,7 +1192,7 @@ static int hw_init(struct msm_gpu *gpu)
> /* Setting the primFifo thresholds default values,
> * and vccCacheSkipDis=1 bit (0x200) for A640 and newer
> */
> - if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
> + if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu) || adreno_is_a690(adreno_gpu))
> gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);
> else if (adreno_is_a640_family(adreno_gpu) || adreno_is_7c3(adreno_gpu))
> gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200);
> @@ -1991,7 +2099,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
> info = adreno_info(config->rev);
>
> if (info && (info->revn == 650 || info->revn == 660 ||
> - adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), info->rev)))
> + info->revn == 690 ||
> + adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), info->rev)))
> adreno_gpu->base.hw_apriv = true;
>
> a6xx_llc_slices_init(pdev, a6xx_gpu);
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
> index 2cc83e049613..25b235b49ebc 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
> @@ -414,6 +414,37 @@ static void a650_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
> msg->cnoc_cmds_data[1][0] = 0x60000001;
> }
>
> +static void a690_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
> +{
> + /*
> + * Send a single "off" entry just to get things running
> + * TODO: bus scaling
> + */
> + msg->bw_level_num = 1;
> +
> + msg->ddr_cmds_num = 3;
> + msg->ddr_wait_bitmask = 0x01;
> +
> + msg->ddr_cmds_addrs[0] = 0x50004;
> + msg->ddr_cmds_addrs[1] = 0x50000;
> + msg->ddr_cmds_addrs[2] = 0x500ac;
> +
> + msg->ddr_cmds_data[0][0] = 0x40000000;
> + msg->ddr_cmds_data[0][1] = 0x40000000;
> + msg->ddr_cmds_data[0][2] = 0x40000000;
> +
> + /*
> + * These are the CX (CNOC) votes - these are used by the GMU but the
> + * votes are known and fixed for the target
> + */
> + msg->cnoc_cmds_num = 1;
> + msg->cnoc_wait_bitmask = 0x01;
> +
> + msg->cnoc_cmds_addrs[0] = 0x5003c;
> + msg->cnoc_cmds_data[0][0] = 0x40000000;
> + msg->cnoc_cmds_data[1][0] = 0x60000001;
> +}
> +
> static void a660_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
> {
> /*
> @@ -531,6 +562,8 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu)
> adreno_7c3_build_bw_table(&msg);
> else if (adreno_is_a660(adreno_gpu))
> a660_build_bw_table(&msg);
> + else if (adreno_is_a690(adreno_gpu))
> + a690_build_bw_table(&msg);
> else
> a6xx_build_bw_table(&msg);
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> index 8cff86e9d35c..e5a865024e94 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> @@ -355,6 +355,20 @@ static const struct adreno_info gpulist[] = {
> .init = a6xx_gpu_init,
> .zapfw = "a640_zap.mdt",
> .hwcg = a640_hwcg,
> + }, {
> + .rev = ADRENO_REV(6, 9, 0, ANY_ID),
> + .revn = 690,
> + .name = "A690",
> + .fw = {
> + [ADRENO_FW_SQE] = "a660_sqe.fw",
> + [ADRENO_FW_GMU] = "a690_gmu.bin",
> + },
> + .gmem = SZ_4M,
> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .init = a6xx_gpu_init,
> + .zapfw = "a690_zap.mdt",
> + .hwcg = a690_hwcg,
> + .address_space_size = SZ_16G,
> },
> };
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index f62612a5c70f..ac9c429ca07b 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -55,7 +55,7 @@ struct adreno_reglist {
> u32 value;
> };
>
> -extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[];
> +extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[], a690_hwcg[];
>
> struct adreno_info {
> struct adreno_rev rev;
> @@ -272,6 +272,11 @@ static inline int adreno_is_a660(struct adreno_gpu *gpu)
> return gpu->revn == 660;
> }
>
> +static inline int adreno_is_a690(struct adreno_gpu *gpu)
> +{
> + return gpu->revn == 690;
> +};
> +
> /* check for a615, a616, a618, a619 or any derivatives */
> static inline int adreno_is_a615_family(struct adreno_gpu *gpu)
> {
> @@ -280,13 +285,13 @@ static inline int adreno_is_a615_family(struct adreno_gpu *gpu)
>
> static inline int adreno_is_a660_family(struct adreno_gpu *gpu)
> {
> - return adreno_is_a660(gpu) || adreno_is_7c3(gpu);
> + return adreno_is_a660(gpu) || adreno_is_a690(gpu) || adreno_is_7c3(gpu);
> }
>
> /* check for a650, a660, or any derivatives */
> static inline int adreno_is_a650_family(struct adreno_gpu *gpu)
> {
> - return gpu->revn == 650 || gpu->revn == 620 || adreno_is_a660_family(gpu);
> + return gpu->revn == 650 || gpu->revn == 620 || adreno_is_a660_family(gpu);
> }
>
> u64 adreno_private_address_space_size(struct msm_gpu *gpu);
On 23.05.2023 03:15, Bjorn Andersson wrote:
> From: Bjorn Andersson <[email protected]>
>
> Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the
> SC8280XP.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
It does not look like you tested the DTS against bindings. Please run
`make dtbs_check` (see
Documentation/devicetree/bindings/writing-schema.rst for instructions).
>
> Changes since v1:
> - Dropped gmu_pdc_seq region from &gmu, as it shouldn't have been used.
> - Added missing compatible to &adreno_smmu.
> - Dropped aoss_qmp clock in &gmu and &adreno_smmu.
>
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 169 +++++++++++++++++++++++++
> 1 file changed, 169 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index d2a2224d138a..329ec2119ecf 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -6,6 +6,7 @@
>
> #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
> #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
> +#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
> #include <dt-bindings/clock/qcom,rpmh.h>
> #include <dt-bindings/interconnect/qcom,osm-l3.h>
> #include <dt-bindings/interconnect/qcom,sc8280xp.h>
> @@ -2331,6 +2332,174 @@ tcsr: syscon@1fc0000 {
> reg = <0x0 0x01fc0000 0x0 0x30000>;
> };
>
> + gpu: gpu@3d00000 {
> + compatible = "qcom,adreno-690.0", "qcom,adreno";
> +
> + reg = <0 0x03d00000 0 0x40000>,
> + <0 0x03d9e000 0 0x1000>,
> + <0 0x03d61000 0 0x800>;
> + reg-names = "kgsl_3d0_reg_memory",
> + "cx_mem",
> + "cx_dbgc";
> + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
> + iommus = <&adreno_smmu 0 0xc00>, <&adreno_smmu 1 0xc00>;
> + operating-points-v2 = <&gpu_opp_table>;
> +
> + qcom,gmu = <&gmu>;
> + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "gfx-mem";
> + #cooling-cells = <2>;
> +
> + status = "disabled";
> +
> + gpu_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-270000000 {
> + opp-hz = /bits/ 64 <270000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> + opp-peak-kBps = <451000>;
> + };
> +
> + opp-410000000 {
> + opp-hz = /bits/ 64 <410000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> + opp-peak-kBps = <1555000>;
> + };
> +
> + opp-500000000 {
> + opp-hz = /bits/ 64 <500000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> + opp-peak-kBps = <1555000>;
> + };
> +
> + opp-547000000 {
> + opp-hz = /bits/ 64 <547000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
> + opp-peak-kBps = <1555000>;
> + };
> +
> + opp-606000000 {
> + opp-hz = /bits/ 64 <606000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> + opp-peak-kBps = <2736000>;
> + };
> +
> + opp-640000000 {
> + opp-hz = /bits/ 64 <640000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> + opp-peak-kBps = <2736000>;
> + };
> +
> + opp-690000000 {
> + opp-hz = /bits/ 64 <690000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> + opp-peak-kBps = <2736000>;
> + };
> + };
> + };
> +
> + gmu: gmu@3d6a000 {
> + compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
> + reg = <0 0x03d6a000 0 0x34000>,
> + <0 0x03de0000 0 0x10000>,
> + <0 0x0b290000 0 0x10000>;
> + reg-names = "gmu", "rscc", "gmu_pdc";
> + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hfi", "gmu";
> + clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
> + <&gpucc GPU_CC_CXO_CLK>,
> + <&gcc GCC_DDRSS_GPU_AXI_CLK>,
> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> + <&gpucc GPU_CC_AHB_CLK>,
> + <&gpucc GPU_CC_HUB_CX_INT_CLK>,
> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
> + clock-names = "gmu",
> + "cxo",
> + "axi",
> + "memnoc",
> + "ahb",
> + "hub",
> + "smmu_vote";
> + power-domains = <&gpucc GPU_CC_CX_GDSC>,
> + <&gpucc GPU_CC_GX_GDSC>;
> + power-domain-names = "cx",
> + "gx";
> + iommus = <&adreno_smmu 5 0xc00>;
> + operating-points-v2 = <&gmu_opp_table>;
> +
> + status = "disabled";
I've recently discovered that - and I am not 100% sure - all GMUs are
cache-coherent. Could you please ask somebody at qc about this?
> +
> + gmu_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-200000000 {
> + opp-hz = /bits/ 64 <200000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> + };
Missing 500MHz + RPMH_REGULATOR_LEVEL_SVS
(that may be used in the future for hw scheduling)
> + };
> + };
> +
> + gpucc: clock-controller@3d90000 {
> + compatible = "qcom,sc8280xp-gpucc";
> + reg = <0 0x03d90000 0 0x9000>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_GPU_GPLL0_CLK_SRC>,
> + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
> + clock-names = "bi_tcxo",
> + "gcc_gpu_gpll0_clk_src",
> + "gcc_gpu_gpll0_div_clk_src";
FWIW the driver doesn't use clock-names, but the binding defines it,
so I suppose it's fine
> +
> + power-domains = <&rpmhpd SC8280XP_GFX>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> +
> + status = "disabled";
> + };
> +
> + adreno_smmu: iommu@3da0000 {
> + compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu",
> + "qcom,smmu-500", "arm,mmu-500";
> + reg = <0 0x03da0000 0 0x20000>;
> + #iommu-cells = <2>;
> + #global-interrupts = <2>;
> + interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
> + <&gpucc GPU_CC_AHB_CLK>,
> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
> + <&gpucc GPU_CC_CX_GMU_CLK>,
> + <&gpucc GPU_CC_HUB_CX_INT_CLK>,
> + <&gpucc GPU_CC_HUB_AON_CLK>;
> + clock-names = "gcc_gpu_memnoc_gfx_clk",
> + "gcc_gpu_snoc_dvm_gfx_clk",
> + "gpu_cc_ahb_clk",
> + "gpu_cc_hlos1_vote_gpu_smmu_clk",
> + "gpu_cc_cx_gmu_clk",
> + "gpu_cc_hub_cx_int_clk",
> + "gpu_cc_hub_aon_clk";
> +
> + power-domains = <&gpucc GPU_CC_CX_GDSC>;
> +
> + status = "disabled";
This one should be dma-coherent (per downstream, plus 8350's mmu is for sure)
Konrad
> + };
> +
> usb_0_hsphy: phy@88e5000 {
> compatible = "qcom,sc8280xp-usb-hs-phy",
> "qcom,usb-snps-hs-5nm-phy";
On 23.05.2023 09:59, Konrad Dybcio wrote:
>
>
> On 23.05.2023 03:15, Bjorn Andersson wrote:
>> From: Bjorn Andersson <[email protected]>
>>
>> Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the
>> SC8280XP.
>>
>> Signed-off-by: Bjorn Andersson <[email protected]>
>> Signed-off-by: Bjorn Andersson <[email protected]>
>> ---
> It does not look like you tested the DTS against bindings. Please run
> `make dtbs_check` (see
> Documentation/devicetree/bindings/writing-schema.rst for instructions).
>
>>
>> Changes since v1:
>> - Dropped gmu_pdc_seq region from &gmu, as it shouldn't have been used.
>> - Added missing compatible to &adreno_smmu.
>> - Dropped aoss_qmp clock in &gmu and &adreno_smmu.
>>
>> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 169 +++++++++++++++++++++++++
>> 1 file changed, 169 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>> index d2a2224d138a..329ec2119ecf 100644
>> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>> @@ -6,6 +6,7 @@
>>
>> #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
>> #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
>> +#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
>> #include <dt-bindings/clock/qcom,rpmh.h>
>> #include <dt-bindings/interconnect/qcom,osm-l3.h>
>> #include <dt-bindings/interconnect/qcom,sc8280xp.h>
>> @@ -2331,6 +2332,174 @@ tcsr: syscon@1fc0000 {
>> reg = <0x0 0x01fc0000 0x0 0x30000>;
>> };
>>
>> + gpu: gpu@3d00000 {
>> + compatible = "qcom,adreno-690.0", "qcom,adreno";
>> +
>> + reg = <0 0x03d00000 0 0x40000>,
>> + <0 0x03d9e000 0 0x1000>,
>> + <0 0x03d61000 0 0x800>;
>> + reg-names = "kgsl_3d0_reg_memory",
>> + "cx_mem",
>> + "cx_dbgc";
>> + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
>> + iommus = <&adreno_smmu 0 0xc00>, <&adreno_smmu 1 0xc00>;
>> + operating-points-v2 = <&gpu_opp_table>;
>> +
>> + qcom,gmu = <&gmu>;
>> + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
>> + interconnect-names = "gfx-mem";
I also noticed downstream adds additional votes for L3 (*not* LLCC), should
we explore that?
Konrad
>> + #cooling-cells = <2>;
>> +
>> + status = "disabled";
>> +
>> + gpu_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + opp-270000000 {
>> + opp-hz = /bits/ 64 <270000000>;
>> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
>> + opp-peak-kBps = <451000>;
>> + };
>> +
>> + opp-410000000 {
>> + opp-hz = /bits/ 64 <410000000>;
>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
>> + opp-peak-kBps = <1555000>;
>> + };
>> +
>> + opp-500000000 {
>> + opp-hz = /bits/ 64 <500000000>;
>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
>> + opp-peak-kBps = <1555000>;
>> + };
>> +
>> + opp-547000000 {
>> + opp-hz = /bits/ 64 <547000000>;
>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
>> + opp-peak-kBps = <1555000>;
>> + };
>> +
>> + opp-606000000 {
>> + opp-hz = /bits/ 64 <606000000>;
>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
>> + opp-peak-kBps = <2736000>;
>> + };
>> +
>> + opp-640000000 {
>> + opp-hz = /bits/ 64 <640000000>;
>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
>> + opp-peak-kBps = <2736000>;
>> + };
>> +
>> + opp-690000000 {
>> + opp-hz = /bits/ 64 <690000000>;
>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
>> + opp-peak-kBps = <2736000>;
>> + };
>> + };
>> + };
>> +
>> + gmu: gmu@3d6a000 {
>> + compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
>> + reg = <0 0x03d6a000 0 0x34000>,
>> + <0 0x03de0000 0 0x10000>,
>> + <0 0x0b290000 0 0x10000>;
>> + reg-names = "gmu", "rscc", "gmu_pdc";
>> + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "hfi", "gmu";
>> + clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
>> + <&gpucc GPU_CC_CXO_CLK>,
>> + <&gcc GCC_DDRSS_GPU_AXI_CLK>,
>> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
>> + <&gpucc GPU_CC_AHB_CLK>,
>> + <&gpucc GPU_CC_HUB_CX_INT_CLK>,
>> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
>> + clock-names = "gmu",
>> + "cxo",
>> + "axi",
>> + "memnoc",
>> + "ahb",
>> + "hub",
>> + "smmu_vote";
>> + power-domains = <&gpucc GPU_CC_CX_GDSC>,
>> + <&gpucc GPU_CC_GX_GDSC>;
>> + power-domain-names = "cx",
>> + "gx";
>> + iommus = <&adreno_smmu 5 0xc00>;
>> + operating-points-v2 = <&gmu_opp_table>;
>> +
>> + status = "disabled";
> I've recently discovered that - and I am not 100% sure - all GMUs are
> cache-coherent. Could you please ask somebody at qc about this?
>
>> +
>> + gmu_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + opp-200000000 {
>> + opp-hz = /bits/ 64 <200000000>;
>> + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
>> + };
> Missing 500MHz + RPMH_REGULATOR_LEVEL_SVS
>
> (that may be used in the future for hw scheduling)
>> + };
>> + };
>> +
>> + gpucc: clock-controller@3d90000 {
>> + compatible = "qcom,sc8280xp-gpucc";
>> + reg = <0 0x03d90000 0 0x9000>;
>> + clocks = <&rpmhcc RPMH_CXO_CLK>,
>> + <&gcc GCC_GPU_GPLL0_CLK_SRC>,
>> + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
>> + clock-names = "bi_tcxo",
>> + "gcc_gpu_gpll0_clk_src",
>> + "gcc_gpu_gpll0_div_clk_src";
> FWIW the driver doesn't use clock-names, but the binding defines it,
> so I suppose it's fine
>
>> +
>> + power-domains = <&rpmhpd SC8280XP_GFX>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>> +
>> + status = "disabled";
>> + };
>> +
>> + adreno_smmu: iommu@3da0000 {
>> + compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu",
>> + "qcom,smmu-500", "arm,mmu-500";
>> + reg = <0 0x03da0000 0 0x20000>;
>> + #iommu-cells = <2>;
>> + #global-interrupts = <2>;
>> + interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
>> + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
>> + <&gpucc GPU_CC_AHB_CLK>,
>> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
>> + <&gpucc GPU_CC_CX_GMU_CLK>,
>> + <&gpucc GPU_CC_HUB_CX_INT_CLK>,
>> + <&gpucc GPU_CC_HUB_AON_CLK>;
>> + clock-names = "gcc_gpu_memnoc_gfx_clk",
>> + "gcc_gpu_snoc_dvm_gfx_clk",
>> + "gpu_cc_ahb_clk",
>> + "gpu_cc_hlos1_vote_gpu_smmu_clk",
>> + "gpu_cc_cx_gmu_clk",
>> + "gpu_cc_hub_cx_int_clk",
>> + "gpu_cc_hub_aon_clk";
>> +
>> + power-domains = <&gpucc GPU_CC_CX_GDSC>;
>> +
>> + status = "disabled";
> This one should be dma-coherent (per downstream, plus 8350's mmu is for sure)
>
> Konrad
>> + };
>> +
>> usb_0_hsphy: phy@88e5000 {
>> compatible = "qcom,sc8280xp-usb-hs-phy",
>> "qcom,usb-snps-hs-5nm-phy";
On 23.05.2023 03:15, Bjorn Andersson wrote:
> From: Bjorn Andersson <[email protected]>
>
> Add memory reservation for the zap-shader and enable the Adreno SMMU,
> GPU clock controller, GMU and the GPU nodes for the SC8280XP CRD and the
> Lenovo ThinkPad X13s.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
>
> Changes since v1:
> - None
>
> arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 26 +++++++++++++++++++
> .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 26 +++++++++++++++++++
> 2 files changed, 52 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> index 5b25d54b9591..547277924ea3 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> @@ -210,6 +210,11 @@ vreg_wwan: regulator-wwan {
> };
>
> reserved-memory {
> + gpu_mem: gpu-mem@8bf00000 {
The ZAP region is very seldom moved around, and I wouldn't expect it
to be uncommon among the very usecase-specific 8280 machines.
> + reg = <0 0x8bf00000 0 0x2000>;
> + no-map;
> + };
> +
> linux,cma {
> compatible = "shared-dma-pool";
> size = <0x0 0x8000000>;
> @@ -259,6 +264,10 @@ usb1_sbu_mux: endpoint {
> };
> };
>
> +&adreno_smmu {
> + status = "okay";
> +};
Ugh. Should definitely be enabled by default.
> +
> &apps_rsc {
> regulators-0 {
> compatible = "qcom,pm8350-rpmh-regulators";
> @@ -376,6 +385,23 @@ &dispcc0 {
> status = "okay";
> };
>
> +&gmu {
> + status = "okay";
> +};
You can keep the GMU enabled by default as well, it won't "probe" on
its own (the GPU's hw_init calls its registration)
> +
> +&gpu {
> + status = "okay";
> +
> + zap-shader {
> + memory-region = <&gpu_mem>;
> + firmware-name = "qcom/sc8280xp/qcdxkmsuc8280.mbn";
> + };
> +};
> +
> +&gpucc {
> + status = "okay";
> +};
Clock controllers have no reason to be off by default.
Konrad
> +
> &mdss0 {
> status = "okay";
> };
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> index bdcba719fc38..5ef3f4c07d75 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> @@ -264,6 +264,11 @@ vreg_wwan: regulator-wwan {
> };
>
> reserved-memory {
> + gpu_mem: gpu-mem@8bf00000 {
> + reg = <0 0x8bf00000 0 0x2000>;
> + no-map;
> + };
> +
> linux,cma {
> compatible = "shared-dma-pool";
> size = <0x0 0x8000000>;
> @@ -359,6 +364,10 @@ usb1_sbu_mux: endpoint {
> };
> };
>
> +&adreno_smmu {
> + status = "okay";
> +};
> +
> &apps_rsc {
> regulators-0 {
> compatible = "qcom,pm8350-rpmh-regulators";
> @@ -518,6 +527,23 @@ &dispcc0 {
> status = "okay";
> };
>
> +&gmu {
> + status = "okay";
> +};
> +
> +&gpu {
> + status = "okay";
> +
> + zap-shader {
> + memory-region = <&gpu_mem>;
> + firmware-name = "qcom/sc8280xp/LENOVO/21BX/qcdxkmsuc8280.mbn";
> + };
> +};
> +
> +&gpucc {
> + status = "okay";
> +};
> +
> &mdss0 {
> status = "okay";
> };
On Tue, May 23, 2023 at 10:04:40AM +0200, Konrad Dybcio wrote:
>
>
> On 23.05.2023 03:15, Bjorn Andersson wrote:
> > From: Bjorn Andersson <[email protected]>
> >
> > Add memory reservation for the zap-shader and enable the Adreno SMMU,
> > GPU clock controller, GMU and the GPU nodes for the SC8280XP CRD and the
> > Lenovo ThinkPad X13s.
> >
> > Signed-off-by: Bjorn Andersson <[email protected]>
> > Signed-off-by: Bjorn Andersson <[email protected]>
> > ---
> >
> > Changes since v1:
> > - None
> >
> > arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 26 +++++++++++++++++++
> > .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 26 +++++++++++++++++++
> > 2 files changed, 52 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> > index 5b25d54b9591..547277924ea3 100644
> > --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> > +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> > @@ -210,6 +210,11 @@ vreg_wwan: regulator-wwan {
> > };
> >
> > reserved-memory {
> > + gpu_mem: gpu-mem@8bf00000 {
> The ZAP region is very seldom moved around, and I wouldn't expect it
> to be uncommon among the very usecase-specific 8280 machines.
>
> > + reg = <0 0x8bf00000 0 0x2000>;
> > + no-map;
> > + };
> > +
> > linux,cma {
> > compatible = "shared-dma-pool";
> > size = <0x0 0x8000000>;
> > @@ -259,6 +264,10 @@ usb1_sbu_mux: endpoint {
> > };
> > };
> >
> > +&adreno_smmu {
> > + status = "okay";
> > +};
> Ugh. Should definitely be enabled by default.
>
> > +
> > &apps_rsc {
> > regulators-0 {
> > compatible = "qcom,pm8350-rpmh-regulators";
> > @@ -376,6 +385,23 @@ &dispcc0 {
> > status = "okay";
> > };
> >
> > +&gmu {
> > + status = "okay";
> > +};
> You can keep the GMU enabled by default as well, it won't "probe" on
> its own (the GPU's hw_init calls its registration)
>
> > +
> > +&gpu {
> > + status = "okay";
> > +
> > + zap-shader {
> > + memory-region = <&gpu_mem>;
> > + firmware-name = "qcom/sc8280xp/qcdxkmsuc8280.mbn";
> > + };
> > +};
> > +
> > +&gpucc {
> > + status = "okay";
> > +};
> Clock controllers have no reason to be off by default.
>
On sa8295p/sa8540p the GPU is powered differently, so if I leave it
enabled by default I need to disable it (or configure it) for those, or
they won't boot.
Regards,
Bjorn
> Konrad
> > +
> > &mdss0 {
> > status = "okay";
> > };
> > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> > index bdcba719fc38..5ef3f4c07d75 100644
> > --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> > +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> > @@ -264,6 +264,11 @@ vreg_wwan: regulator-wwan {
> > };
> >
> > reserved-memory {
> > + gpu_mem: gpu-mem@8bf00000 {
> > + reg = <0 0x8bf00000 0 0x2000>;
> > + no-map;
> > + };
> > +
> > linux,cma {
> > compatible = "shared-dma-pool";
> > size = <0x0 0x8000000>;
> > @@ -359,6 +364,10 @@ usb1_sbu_mux: endpoint {
> > };
> > };
> >
> > +&adreno_smmu {
> > + status = "okay";
> > +};
> > +
> > &apps_rsc {
> > regulators-0 {
> > compatible = "qcom,pm8350-rpmh-regulators";
> > @@ -518,6 +527,23 @@ &dispcc0 {
> > status = "okay";
> > };
> >
> > +&gmu {
> > + status = "okay";
> > +};
> > +
> > +&gpu {
> > + status = "okay";
> > +
> > + zap-shader {
> > + memory-region = <&gpu_mem>;
> > + firmware-name = "qcom/sc8280xp/LENOVO/21BX/qcdxkmsuc8280.mbn";
> > + };
> > +};
> > +
> > +&gpucc {
> > + status = "okay";
> > +};
> > +
> > &mdss0 {
> > status = "okay";
> > };
On 23.05.2023 14:28, Bjorn Andersson wrote:
> On Tue, May 23, 2023 at 10:04:40AM +0200, Konrad Dybcio wrote:
>>
>>
>> On 23.05.2023 03:15, Bjorn Andersson wrote:
>>> From: Bjorn Andersson <[email protected]>
>>>
>>> Add memory reservation for the zap-shader and enable the Adreno SMMU,
>>> GPU clock controller, GMU and the GPU nodes for the SC8280XP CRD and the
>>> Lenovo ThinkPad X13s.
>>>
>>> Signed-off-by: Bjorn Andersson <[email protected]>
>>> Signed-off-by: Bjorn Andersson <[email protected]>
>>> ---
>>>
>>> Changes since v1:
>>> - None
>>>
>>> arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 26 +++++++++++++++++++
>>> .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 26 +++++++++++++++++++
>>> 2 files changed, 52 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
>>> index 5b25d54b9591..547277924ea3 100644
>>> --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
>>> +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
>>> @@ -210,6 +210,11 @@ vreg_wwan: regulator-wwan {
>>> };
>>>
>>> reserved-memory {
>>> + gpu_mem: gpu-mem@8bf00000 {
>> The ZAP region is very seldom moved around, and I wouldn't expect it
>> to be uncommon among the very usecase-specific 8280 machines.
>>
>>> + reg = <0 0x8bf00000 0 0x2000>;
>>> + no-map;
>>> + };
>>> +
>>> linux,cma {
>>> compatible = "shared-dma-pool";
>>> size = <0x0 0x8000000>;
>>> @@ -259,6 +264,10 @@ usb1_sbu_mux: endpoint {
>>> };
>>> };
>>>
>>> +&adreno_smmu {
>>> + status = "okay";
>>> +};
>> Ugh. Should definitely be enabled by default.
>>
>>> +
>>> &apps_rsc {
>>> regulators-0 {
>>> compatible = "qcom,pm8350-rpmh-regulators";
>>> @@ -376,6 +385,23 @@ &dispcc0 {
>>> status = "okay";
>>> };
>>>
>>> +&gmu {
>>> + status = "okay";
>>> +};
>> You can keep the GMU enabled by default as well, it won't "probe" on
>> its own (the GPU's hw_init calls its registration)
>>
>>> +
>>> +&gpu {
>>> + status = "okay";
>>> +
>>> + zap-shader {
>>> + memory-region = <&gpu_mem>;
>>> + firmware-name = "qcom/sc8280xp/qcdxkmsuc8280.mbn";
>>> + };
>>> +};
>>> +
>>> +&gpucc {
>>> + status = "okay";
>>> +};
>> Clock controllers have no reason to be off by default.
>>
>
> On sa8295p/sa8540p the GPU is powered differently, so if I leave it
> enabled by default I need to disable it (or configure it) for those, or
> they won't boot.
Another "messed up automotive forks" situation, eh..
Would it take a lot of new code to configure these platforms correctly?
Konrad
>
> Regards,
> Bjorn
>
>> Konrad
>>> +
>>> &mdss0 {
>>> status = "okay";
>>> };
>>> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
>>> index bdcba719fc38..5ef3f4c07d75 100644
>>> --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
>>> +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
>>> @@ -264,6 +264,11 @@ vreg_wwan: regulator-wwan {
>>> };
>>>
>>> reserved-memory {
>>> + gpu_mem: gpu-mem@8bf00000 {
>>> + reg = <0 0x8bf00000 0 0x2000>;
>>> + no-map;
>>> + };
>>> +
>>> linux,cma {
>>> compatible = "shared-dma-pool";
>>> size = <0x0 0x8000000>;
>>> @@ -359,6 +364,10 @@ usb1_sbu_mux: endpoint {
>>> };
>>> };
>>>
>>> +&adreno_smmu {
>>> + status = "okay";
>>> +};
>>> +
>>> &apps_rsc {
>>> regulators-0 {
>>> compatible = "qcom,pm8350-rpmh-regulators";
>>> @@ -518,6 +527,23 @@ &dispcc0 {
>>> status = "okay";
>>> };
>>>
>>> +&gmu {
>>> + status = "okay";
>>> +};
>>> +
>>> +&gpu {
>>> + status = "okay";
>>> +
>>> + zap-shader {
>>> + memory-region = <&gpu_mem>;
>>> + firmware-name = "qcom/sc8280xp/LENOVO/21BX/qcdxkmsuc8280.mbn";
>>> + };
>>> +};
>>> +
>>> +&gpucc {
>>> + status = "okay";
>>> +};
>>> +
>>> &mdss0 {
>>> status = "okay";
>>> };
On Tue, May 23, 2023 at 09:59:53AM +0200, Konrad Dybcio wrote:
>
>
> On 23.05.2023 03:15, Bjorn Andersson wrote:
> > From: Bjorn Andersson <[email protected]>
> >
> > Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the
> > SC8280XP.
> >
> > Signed-off-by: Bjorn Andersson <[email protected]>
> > Signed-off-by: Bjorn Andersson <[email protected]>
> > ---
> It does not look like you tested the DTS against bindings. Please run
> `make dtbs_check` (see
> Documentation/devicetree/bindings/writing-schema.rst for instructions).
>
> >
> > Changes since v1:
> > - Dropped gmu_pdc_seq region from &gmu, as it shouldn't have been used.
> > - Added missing compatible to &adreno_smmu.
> > - Dropped aoss_qmp clock in &gmu and &adreno_smmu.
> >
> > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 169 +++++++++++++++++++++++++
> > 1 file changed, 169 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > index d2a2224d138a..329ec2119ecf 100644
> > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > @@ -6,6 +6,7 @@
> >
> > #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
> > #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
> > +#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
> > #include <dt-bindings/clock/qcom,rpmh.h>
> > #include <dt-bindings/interconnect/qcom,osm-l3.h>
> > #include <dt-bindings/interconnect/qcom,sc8280xp.h>
> > @@ -2331,6 +2332,174 @@ tcsr: syscon@1fc0000 {
> > reg = <0x0 0x01fc0000 0x0 0x30000>;
> > };
> >
> > + gpu: gpu@3d00000 {
> > + compatible = "qcom,adreno-690.0", "qcom,adreno";
> > +
> > + reg = <0 0x03d00000 0 0x40000>,
> > + <0 0x03d9e000 0 0x1000>,
> > + <0 0x03d61000 0 0x800>;
> > + reg-names = "kgsl_3d0_reg_memory",
> > + "cx_mem",
> > + "cx_dbgc";
> > + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
> > + iommus = <&adreno_smmu 0 0xc00>, <&adreno_smmu 1 0xc00>;
> > + operating-points-v2 = <&gpu_opp_table>;
> > +
> > + qcom,gmu = <&gmu>;
> > + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
> > + interconnect-names = "gfx-mem";
> > + #cooling-cells = <2>;
> > +
> > + status = "disabled";
> > +
> > + gpu_opp_table: opp-table {
> > + compatible = "operating-points-v2";
> > +
> > + opp-270000000 {
> > + opp-hz = /bits/ 64 <270000000>;
> > + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> > + opp-peak-kBps = <451000>;
> > + };
> > +
> > + opp-410000000 {
> > + opp-hz = /bits/ 64 <410000000>;
> > + opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> > + opp-peak-kBps = <1555000>;
> > + };
> > +
> > + opp-500000000 {
> > + opp-hz = /bits/ 64 <500000000>;
> > + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> > + opp-peak-kBps = <1555000>;
> > + };
> > +
> > + opp-547000000 {
> > + opp-hz = /bits/ 64 <547000000>;
> > + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
> > + opp-peak-kBps = <1555000>;
> > + };
> > +
> > + opp-606000000 {
> > + opp-hz = /bits/ 64 <606000000>;
> > + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> > + opp-peak-kBps = <2736000>;
> > + };
> > +
> > + opp-640000000 {
> > + opp-hz = /bits/ 64 <640000000>;
> > + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> > + opp-peak-kBps = <2736000>;
> > + };
> > +
> > + opp-690000000 {
> > + opp-hz = /bits/ 64 <690000000>;
> > + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> > + opp-peak-kBps = <2736000>;
> > + };
> > + };
> > + };
> > +
> > + gmu: gmu@3d6a000 {
> > + compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
> > + reg = <0 0x03d6a000 0 0x34000>,
> > + <0 0x03de0000 0 0x10000>,
> > + <0 0x0b290000 0 0x10000>;
> > + reg-names = "gmu", "rscc", "gmu_pdc";
> > + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "hfi", "gmu";
> > + clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
> > + <&gpucc GPU_CC_CXO_CLK>,
> > + <&gcc GCC_DDRSS_GPU_AXI_CLK>,
> > + <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> > + <&gpucc GPU_CC_AHB_CLK>,
> > + <&gpucc GPU_CC_HUB_CX_INT_CLK>,
> > + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
> > + clock-names = "gmu",
> > + "cxo",
> > + "axi",
> > + "memnoc",
> > + "ahb",
> > + "hub",
> > + "smmu_vote";
> > + power-domains = <&gpucc GPU_CC_CX_GDSC>,
> > + <&gpucc GPU_CC_GX_GDSC>;
> > + power-domain-names = "cx",
> > + "gx";
> > + iommus = <&adreno_smmu 5 0xc00>;
> > + operating-points-v2 = <&gmu_opp_table>;
> > +
> > + status = "disabled";
> I've recently discovered that - and I am not 100% sure - all GMUs are
> cache-coherent. Could you please ask somebody at qc about this?
>
AFAIU, GMU's job is controlling the voltage and clock to the GPU. It doesn't do
any data transactions on its own. So cache-coherent doesn't make sense to me.
- Mani
> > +
> > + gmu_opp_table: opp-table {
> > + compatible = "operating-points-v2";
> > +
> > + opp-200000000 {
> > + opp-hz = /bits/ 64 <200000000>;
> > + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> > + };
> Missing 500MHz + RPMH_REGULATOR_LEVEL_SVS
>
> (that may be used in the future for hw scheduling)
> > + };
> > + };
> > +
> > + gpucc: clock-controller@3d90000 {
> > + compatible = "qcom,sc8280xp-gpucc";
> > + reg = <0 0x03d90000 0 0x9000>;
> > + clocks = <&rpmhcc RPMH_CXO_CLK>,
> > + <&gcc GCC_GPU_GPLL0_CLK_SRC>,
> > + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
> > + clock-names = "bi_tcxo",
> > + "gcc_gpu_gpll0_clk_src",
> > + "gcc_gpu_gpll0_div_clk_src";
> FWIW the driver doesn't use clock-names, but the binding defines it,
> so I suppose it's fine
>
> > +
> > + power-domains = <&rpmhpd SC8280XP_GFX>;
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + #power-domain-cells = <1>;
> > +
> > + status = "disabled";
> > + };
> > +
> > + adreno_smmu: iommu@3da0000 {
> > + compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu",
> > + "qcom,smmu-500", "arm,mmu-500";
> > + reg = <0 0x03da0000 0 0x20000>;
> > + #iommu-cells = <2>;
> > + #global-interrupts = <2>;
> > + interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>;
> > +
> > + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> > + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
> > + <&gpucc GPU_CC_AHB_CLK>,
> > + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
> > + <&gpucc GPU_CC_CX_GMU_CLK>,
> > + <&gpucc GPU_CC_HUB_CX_INT_CLK>,
> > + <&gpucc GPU_CC_HUB_AON_CLK>;
> > + clock-names = "gcc_gpu_memnoc_gfx_clk",
> > + "gcc_gpu_snoc_dvm_gfx_clk",
> > + "gpu_cc_ahb_clk",
> > + "gpu_cc_hlos1_vote_gpu_smmu_clk",
> > + "gpu_cc_cx_gmu_clk",
> > + "gpu_cc_hub_cx_int_clk",
> > + "gpu_cc_hub_aon_clk";
> > +
> > + power-domains = <&gpucc GPU_CC_CX_GDSC>;
> > +
> > + status = "disabled";
> This one should be dma-coherent (per downstream, plus 8350's mmu is for sure)
>
> Konrad
> > + };
> > +
> > usb_0_hsphy: phy@88e5000 {
> > compatible = "qcom,sc8280xp-usb-hs-phy",
> > "qcom,usb-snps-hs-5nm-phy";
--
மணிவண்ணன் சதாசிவம்
On 28.05.2023 19:07, Manivannan Sadhasivam wrote:
> On Tue, May 23, 2023 at 09:59:53AM +0200, Konrad Dybcio wrote:
>>
>>
>> On 23.05.2023 03:15, Bjorn Andersson wrote:
>>> From: Bjorn Andersson <[email protected]>
>>>
>>> Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the
>>> SC8280XP.
>>>
>>> Signed-off-by: Bjorn Andersson <[email protected]>
>>> Signed-off-by: Bjorn Andersson <[email protected]>
>>> ---
>> It does not look like you tested the DTS against bindings. Please run
>> `make dtbs_check` (see
>> Documentation/devicetree/bindings/writing-schema.rst for instructions).
>>
>>>
>>> Changes since v1:
>>> - Dropped gmu_pdc_seq region from &gmu, as it shouldn't have been used.
>>> - Added missing compatible to &adreno_smmu.
>>> - Dropped aoss_qmp clock in &gmu and &adreno_smmu.
>>>
>>> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 169 +++++++++++++++++++++++++
>>> 1 file changed, 169 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>>> index d2a2224d138a..329ec2119ecf 100644
>>> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>>> @@ -6,6 +6,7 @@
>>>
>>> #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
>>> #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
>>> +#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
>>> #include <dt-bindings/clock/qcom,rpmh.h>
>>> #include <dt-bindings/interconnect/qcom,osm-l3.h>
>>> #include <dt-bindings/interconnect/qcom,sc8280xp.h>
>>> @@ -2331,6 +2332,174 @@ tcsr: syscon@1fc0000 {
>>> reg = <0x0 0x01fc0000 0x0 0x30000>;
>>> };
>>>
>>> + gpu: gpu@3d00000 {
>>> + compatible = "qcom,adreno-690.0", "qcom,adreno";
>>> +
>>> + reg = <0 0x03d00000 0 0x40000>,
>>> + <0 0x03d9e000 0 0x1000>,
>>> + <0 0x03d61000 0 0x800>;
>>> + reg-names = "kgsl_3d0_reg_memory",
>>> + "cx_mem",
>>> + "cx_dbgc";
>>> + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
>>> + iommus = <&adreno_smmu 0 0xc00>, <&adreno_smmu 1 0xc00>;
>>> + operating-points-v2 = <&gpu_opp_table>;
>>> +
>>> + qcom,gmu = <&gmu>;
>>> + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
>>> + interconnect-names = "gfx-mem";
>>> + #cooling-cells = <2>;
>>> +
>>> + status = "disabled";
>>> +
>>> + gpu_opp_table: opp-table {
>>> + compatible = "operating-points-v2";
>>> +
>>> + opp-270000000 {
>>> + opp-hz = /bits/ 64 <270000000>;
>>> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
>>> + opp-peak-kBps = <451000>;
>>> + };
>>> +
>>> + opp-410000000 {
>>> + opp-hz = /bits/ 64 <410000000>;
>>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
>>> + opp-peak-kBps = <1555000>;
>>> + };
>>> +
>>> + opp-500000000 {
>>> + opp-hz = /bits/ 64 <500000000>;
>>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
>>> + opp-peak-kBps = <1555000>;
>>> + };
>>> +
>>> + opp-547000000 {
>>> + opp-hz = /bits/ 64 <547000000>;
>>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
>>> + opp-peak-kBps = <1555000>;
>>> + };
>>> +
>>> + opp-606000000 {
>>> + opp-hz = /bits/ 64 <606000000>;
>>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
>>> + opp-peak-kBps = <2736000>;
>>> + };
>>> +
>>> + opp-640000000 {
>>> + opp-hz = /bits/ 64 <640000000>;
>>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
>>> + opp-peak-kBps = <2736000>;
>>> + };
>>> +
>>> + opp-690000000 {
>>> + opp-hz = /bits/ 64 <690000000>;
>>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
>>> + opp-peak-kBps = <2736000>;
>>> + };
>>> + };
>>> + };
>>> +
>>> + gmu: gmu@3d6a000 {
>>> + compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
>>> + reg = <0 0x03d6a000 0 0x34000>,
>>> + <0 0x03de0000 0 0x10000>,
>>> + <0 0x0b290000 0 0x10000>;
>>> + reg-names = "gmu", "rscc", "gmu_pdc";
>>> + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
>>> + interrupt-names = "hfi", "gmu";
>>> + clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
>>> + <&gpucc GPU_CC_CXO_CLK>,
>>> + <&gcc GCC_DDRSS_GPU_AXI_CLK>,
>>> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
>>> + <&gpucc GPU_CC_AHB_CLK>,
>>> + <&gpucc GPU_CC_HUB_CX_INT_CLK>,
>>> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
>>> + clock-names = "gmu",
>>> + "cxo",
>>> + "axi",
>>> + "memnoc",
>>> + "ahb",
>>> + "hub",
>>> + "smmu_vote";
>>> + power-domains = <&gpucc GPU_CC_CX_GDSC>,
>>> + <&gpucc GPU_CC_GX_GDSC>;
>>> + power-domain-names = "cx",
>>> + "gx";
>>> + iommus = <&adreno_smmu 5 0xc00>;
>>> + operating-points-v2 = <&gmu_opp_table>;
>>> +
>>> + status = "disabled";
>> I've recently discovered that - and I am not 100% sure - all GMUs are
>> cache-coherent. Could you please ask somebody at qc about this?
>>
>
> AFAIU, GMU's job is controlling the voltage and clock to the GPU.
Not just that, it's only the limited functionality we've implemented
upstream so far.
It doesn't do
> any data transactions on its own.
Of course it does. AP communication is done through MMIO writes and
the GMU talks to RPMh via the GPU RSC directly. Apart from that, some
of the GPU registers (that nota bene don't have anything to do with
the GMU M3 core itself) lay within the GMU address space.
Bjorn noticed that this coherent mask setting downstream may be
a bluff, but I guess we could poke Qualcomm about whether it's
cache-coherent (Akhil, could you say anything about that?).
Konrad
So cache-coherent doesn't make sense to me.
>
> - Mani
>
>>> +
>>> + gmu_opp_table: opp-table {
>>> + compatible = "operating-points-v2";
>>> +
>>> + opp-200000000 {
>>> + opp-hz = /bits/ 64 <200000000>;
>>> + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
>>> + };
>> Missing 500MHz + RPMH_REGULATOR_LEVEL_SVS
>>
>> (that may be used in the future for hw scheduling)
>>> + };
>>> + };
>>> +
>>> + gpucc: clock-controller@3d90000 {
>>> + compatible = "qcom,sc8280xp-gpucc";
>>> + reg = <0 0x03d90000 0 0x9000>;
>>> + clocks = <&rpmhcc RPMH_CXO_CLK>,
>>> + <&gcc GCC_GPU_GPLL0_CLK_SRC>,
>>> + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
>>> + clock-names = "bi_tcxo",
>>> + "gcc_gpu_gpll0_clk_src",
>>> + "gcc_gpu_gpll0_div_clk_src";
>> FWIW the driver doesn't use clock-names, but the binding defines it,
>> so I suppose it's fine
>>
>>> +
>>> + power-domains = <&rpmhpd SC8280XP_GFX>;
>>> + #clock-cells = <1>;
>>> + #reset-cells = <1>;
>>> + #power-domain-cells = <1>;
>>> +
>>> + status = "disabled";
>>> + };
>>> +
>>> + adreno_smmu: iommu@3da0000 {
>>> + compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu",
>>> + "qcom,smmu-500", "arm,mmu-500";
>>> + reg = <0 0x03da0000 0 0x20000>;
>>> + #iommu-cells = <2>;
>>> + #global-interrupts = <2>;
>>> + interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>;
>>> +
>>> + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
>>> + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
>>> + <&gpucc GPU_CC_AHB_CLK>,
>>> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
>>> + <&gpucc GPU_CC_CX_GMU_CLK>,
>>> + <&gpucc GPU_CC_HUB_CX_INT_CLK>,
>>> + <&gpucc GPU_CC_HUB_AON_CLK>;
>>> + clock-names = "gcc_gpu_memnoc_gfx_clk",
>>> + "gcc_gpu_snoc_dvm_gfx_clk",
>>> + "gpu_cc_ahb_clk",
>>> + "gpu_cc_hlos1_vote_gpu_smmu_clk",
>>> + "gpu_cc_cx_gmu_clk",
>>> + "gpu_cc_hub_cx_int_clk",
>>> + "gpu_cc_hub_aon_clk";
>>> +
>>> + power-domains = <&gpucc GPU_CC_CX_GDSC>;
>>> +
>>> + status = "disabled";
>> This one should be dma-coherent (per downstream, plus 8350's mmu is for sure)
>>
>> Konrad
>>> + };
>>> +
>>> usb_0_hsphy: phy@88e5000 {
>>> compatible = "qcom,sc8280xp-usb-hs-phy",
>>> "qcom,usb-snps-hs-5nm-phy";
>
On Mon, May 29, 2023 at 09:38:59AM +0200, Konrad Dybcio wrote:
>
>
> On 28.05.2023 19:07, Manivannan Sadhasivam wrote:
> > On Tue, May 23, 2023 at 09:59:53AM +0200, Konrad Dybcio wrote:
> >>
> >>
> >> On 23.05.2023 03:15, Bjorn Andersson wrote:
> >>> From: Bjorn Andersson <[email protected]>
> >>>
> >>> Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the
> >>> SC8280XP.
> >>>
> >>> Signed-off-by: Bjorn Andersson <[email protected]>
> >>> Signed-off-by: Bjorn Andersson <[email protected]>
> >>> ---
> >> It does not look like you tested the DTS against bindings. Please run
> >> `make dtbs_check` (see
> >> Documentation/devicetree/bindings/writing-schema.rst for instructions).
> >>
> >>>
> >>> Changes since v1:
> >>> - Dropped gmu_pdc_seq region from &gmu, as it shouldn't have been used.
> >>> - Added missing compatible to &adreno_smmu.
> >>> - Dropped aoss_qmp clock in &gmu and &adreno_smmu.
> >>>
> >>> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 169 +++++++++++++++++++++++++
> >>> 1 file changed, 169 insertions(+)
> >>>
> >>> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> >>> index d2a2224d138a..329ec2119ecf 100644
> >>> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> >>> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> >>> @@ -6,6 +6,7 @@
> >>>
> >>> #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
> >>> #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
> >>> +#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
> >>> #include <dt-bindings/clock/qcom,rpmh.h>
> >>> #include <dt-bindings/interconnect/qcom,osm-l3.h>
> >>> #include <dt-bindings/interconnect/qcom,sc8280xp.h>
> >>> @@ -2331,6 +2332,174 @@ tcsr: syscon@1fc0000 {
> >>> reg = <0x0 0x01fc0000 0x0 0x30000>;
> >>> };
> >>>
> >>> + gpu: gpu@3d00000 {
> >>> + compatible = "qcom,adreno-690.0", "qcom,adreno";
> >>> +
> >>> + reg = <0 0x03d00000 0 0x40000>,
> >>> + <0 0x03d9e000 0 0x1000>,
> >>> + <0 0x03d61000 0 0x800>;
> >>> + reg-names = "kgsl_3d0_reg_memory",
> >>> + "cx_mem",
> >>> + "cx_dbgc";
> >>> + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
> >>> + iommus = <&adreno_smmu 0 0xc00>, <&adreno_smmu 1 0xc00>;
> >>> + operating-points-v2 = <&gpu_opp_table>;
> >>> +
> >>> + qcom,gmu = <&gmu>;
> >>> + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
> >>> + interconnect-names = "gfx-mem";
> >>> + #cooling-cells = <2>;
> >>> +
> >>> + status = "disabled";
> >>> +
> >>> + gpu_opp_table: opp-table {
> >>> + compatible = "operating-points-v2";
> >>> +
> >>> + opp-270000000 {
> >>> + opp-hz = /bits/ 64 <270000000>;
> >>> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> >>> + opp-peak-kBps = <451000>;
> >>> + };
> >>> +
> >>> + opp-410000000 {
> >>> + opp-hz = /bits/ 64 <410000000>;
> >>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> >>> + opp-peak-kBps = <1555000>;
> >>> + };
> >>> +
> >>> + opp-500000000 {
> >>> + opp-hz = /bits/ 64 <500000000>;
> >>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> >>> + opp-peak-kBps = <1555000>;
> >>> + };
> >>> +
> >>> + opp-547000000 {
> >>> + opp-hz = /bits/ 64 <547000000>;
> >>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
> >>> + opp-peak-kBps = <1555000>;
> >>> + };
> >>> +
> >>> + opp-606000000 {
> >>> + opp-hz = /bits/ 64 <606000000>;
> >>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> >>> + opp-peak-kBps = <2736000>;
> >>> + };
> >>> +
> >>> + opp-640000000 {
> >>> + opp-hz = /bits/ 64 <640000000>;
> >>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> >>> + opp-peak-kBps = <2736000>;
> >>> + };
> >>> +
> >>> + opp-690000000 {
> >>> + opp-hz = /bits/ 64 <690000000>;
> >>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> >>> + opp-peak-kBps = <2736000>;
> >>> + };
> >>> + };
> >>> + };
> >>> +
> >>> + gmu: gmu@3d6a000 {
> >>> + compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
> >>> + reg = <0 0x03d6a000 0 0x34000>,
> >>> + <0 0x03de0000 0 0x10000>,
> >>> + <0 0x0b290000 0 0x10000>;
> >>> + reg-names = "gmu", "rscc", "gmu_pdc";
> >>> + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> >>> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
> >>> + interrupt-names = "hfi", "gmu";
> >>> + clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
> >>> + <&gpucc GPU_CC_CXO_CLK>,
> >>> + <&gcc GCC_DDRSS_GPU_AXI_CLK>,
> >>> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> >>> + <&gpucc GPU_CC_AHB_CLK>,
> >>> + <&gpucc GPU_CC_HUB_CX_INT_CLK>,
> >>> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
> >>> + clock-names = "gmu",
> >>> + "cxo",
> >>> + "axi",
> >>> + "memnoc",
> >>> + "ahb",
> >>> + "hub",
> >>> + "smmu_vote";
> >>> + power-domains = <&gpucc GPU_CC_CX_GDSC>,
> >>> + <&gpucc GPU_CC_GX_GDSC>;
> >>> + power-domain-names = "cx",
> >>> + "gx";
> >>> + iommus = <&adreno_smmu 5 0xc00>;
> >>> + operating-points-v2 = <&gmu_opp_table>;
> >>> +
> >>> + status = "disabled";
> >> I've recently discovered that - and I am not 100% sure - all GMUs are
> >> cache-coherent. Could you please ask somebody at qc about this?
> >>
> >
> > AFAIU, GMU's job is controlling the voltage and clock to the GPU.
> Not just that, it's only the limited functionality we've implemented
> upstream so far.
>
Okay, good to know!
> It doesn't do
> > any data transactions on its own.
> Of course it does. AP communication is done through MMIO writes and
> the GMU talks to RPMh via the GPU RSC directly. Apart from that, some
> of the GPU registers (that nota bene don't have anything to do with
> the GMU M3 core itself) lay within the GMU address space.
>
That doesn't justify the fact that cache coherency is needed, especially
MMIO writes, unless GMU could snoop the MMIO writes to AP caches.
- Mani
>
> Bjorn noticed that this coherent mask setting downstream may be
> a bluff, but I guess we could poke Qualcomm about whether it's
> cache-coherent (Akhil, could you say anything about that?).
>
> Konrad
>
> So cache-coherent doesn't make sense to me.
> >
> > - Mani
> >
> >>> +
> >>> + gmu_opp_table: opp-table {
> >>> + compatible = "operating-points-v2";
> >>> +
> >>> + opp-200000000 {
> >>> + opp-hz = /bits/ 64 <200000000>;
> >>> + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> >>> + };
> >> Missing 500MHz + RPMH_REGULATOR_LEVEL_SVS
> >>
> >> (that may be used in the future for hw scheduling)
> >>> + };
> >>> + };
> >>> +
> >>> + gpucc: clock-controller@3d90000 {
> >>> + compatible = "qcom,sc8280xp-gpucc";
> >>> + reg = <0 0x03d90000 0 0x9000>;
> >>> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> >>> + <&gcc GCC_GPU_GPLL0_CLK_SRC>,
> >>> + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
> >>> + clock-names = "bi_tcxo",
> >>> + "gcc_gpu_gpll0_clk_src",
> >>> + "gcc_gpu_gpll0_div_clk_src";
> >> FWIW the driver doesn't use clock-names, but the binding defines it,
> >> so I suppose it's fine
> >>
> >>> +
> >>> + power-domains = <&rpmhpd SC8280XP_GFX>;
> >>> + #clock-cells = <1>;
> >>> + #reset-cells = <1>;
> >>> + #power-domain-cells = <1>;
> >>> +
> >>> + status = "disabled";
> >>> + };
> >>> +
> >>> + adreno_smmu: iommu@3da0000 {
> >>> + compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu",
> >>> + "qcom,smmu-500", "arm,mmu-500";
> >>> + reg = <0 0x03da0000 0 0x20000>;
> >>> + #iommu-cells = <2>;
> >>> + #global-interrupts = <2>;
> >>> + interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
> >>> + <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
> >>> + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
> >>> + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
> >>> + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
> >>> + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
> >>> + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
> >>> + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
> >>> + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
> >>> + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
> >>> + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
> >>> + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
> >>> + <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
> >>> + <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>;
> >>> +
> >>> + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> >>> + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
> >>> + <&gpucc GPU_CC_AHB_CLK>,
> >>> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
> >>> + <&gpucc GPU_CC_CX_GMU_CLK>,
> >>> + <&gpucc GPU_CC_HUB_CX_INT_CLK>,
> >>> + <&gpucc GPU_CC_HUB_AON_CLK>;
> >>> + clock-names = "gcc_gpu_memnoc_gfx_clk",
> >>> + "gcc_gpu_snoc_dvm_gfx_clk",
> >>> + "gpu_cc_ahb_clk",
> >>> + "gpu_cc_hlos1_vote_gpu_smmu_clk",
> >>> + "gpu_cc_cx_gmu_clk",
> >>> + "gpu_cc_hub_cx_int_clk",
> >>> + "gpu_cc_hub_aon_clk";
> >>> +
> >>> + power-domains = <&gpucc GPU_CC_CX_GDSC>;
> >>> +
> >>> + status = "disabled";
> >> This one should be dma-coherent (per downstream, plus 8350's mmu is for sure)
> >>
> >> Konrad
> >>> + };
> >>> +
> >>> usb_0_hsphy: phy@88e5000 {
> >>> compatible = "qcom,sc8280xp-usb-hs-phy",
> >>> "qcom,usb-snps-hs-5nm-phy";
> >
--
மணிவண்ணன் சதாசிவம்
On Mon, May 29, 2023 at 02:16:14PM +0530, Manivannan Sadhasivam wrote:
> On Mon, May 29, 2023 at 09:38:59AM +0200, Konrad Dybcio wrote:
> > On 28.05.2023 19:07, Manivannan Sadhasivam wrote:
> > > On Tue, May 23, 2023 at 09:59:53AM +0200, Konrad Dybcio wrote:
> > >> On 23.05.2023 03:15, Bjorn Andersson wrote:
> > >>> From: Bjorn Andersson <[email protected]>
[..]
> > >>> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
[..]
> > >>> + gmu: gmu@3d6a000 {
[..]
> > >>> + status = "disabled";
> > >> I've recently discovered that - and I am not 100% sure - all GMUs are
> > >> cache-coherent. Could you please ask somebody at qc about this?
> > >>
> > >
> > > AFAIU, GMU's job is controlling the voltage and clock to the GPU.
> > Not just that, it's only the limited functionality we've implemented
> > upstream so far.
> >
>
> Okay, good to know!
>
> > It doesn't do
> > > any data transactions on its own.
> > Of course it does. AP communication is done through MMIO writes and
> > the GMU talks to RPMh via the GPU RSC directly. Apart from that, some
> > of the GPU registers (that nota bene don't have anything to do with
> > the GMU M3 core itself) lay within the GMU address space.
> >
But those aren't shared memory accesses.
>
> That doesn't justify the fact that cache coherency is needed, especially
> MMIO writes, unless GMU could snoop the MMIO writes to AP caches.
>
In reviewing the downstream state again I noticed that the GPU smmu is
marked dma-coherent, so I will adjust that in v3.
Regards,
Bjorn
On Mon, May 29, 2023 at 09:38:59AM +0200, Konrad Dybcio wrote:
>
>
>
> On 28.05.2023 19:07, Manivannan Sadhasivam wrote:
> > On Tue, May 23, 2023 at 09:59:53AM +0200, Konrad Dybcio wrote:
> >>
> >>
> >> On 23.05.2023 03:15, Bjorn Andersson wrote:
> >>> From: Bjorn Andersson <[email protected]>
> >>>
> >>> Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the
> >>> SC8280XP.
> >>>
> >>> Signed-off-by: Bjorn Andersson <[email protected]>
> >>> Signed-off-by: Bjorn Andersson <[email protected]>
> >>> ---
> >> It does not look like you tested the DTS against bindings. Please run
> >> `make dtbs_check` (see
> >> Documentation/devicetree/bindings/writing-schema.rst for instructions).
> >>
> >>>
> >>> Changes since v1:
> >>> - Dropped gmu_pdc_seq region from &gmu, as it shouldn't have been used.
> >>> - Added missing compatible to &adreno_smmu.
> >>> - Dropped aoss_qmp clock in &gmu and &adreno_smmu.
> >>>
> >>> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 169 +++++++++++++++++++++++++
> >>> 1 file changed, 169 insertions(+)
> >>>
> >>> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> >>> index d2a2224d138a..329ec2119ecf 100644
> >>> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> >>> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> >>> @@ -6,6 +6,7 @@
> >>>
> >>> #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
> >>> #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
> >>> +#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
> >>> #include <dt-bindings/clock/qcom,rpmh.h>
> >>> #include <dt-bindings/interconnect/qcom,osm-l3.h>
> >>> #include <dt-bindings/interconnect/qcom,sc8280xp.h>
> >>> @@ -2331,6 +2332,174 @@ tcsr: syscon@1fc0000 {
> >>> reg = <0x0 0x01fc0000 0x0 0x30000>;
> >>> };
> >>>
> >>> + gpu: gpu@3d00000 {
> >>> + compatible = "qcom,adreno-690.0", "qcom,adreno";
> >>> +
> >>> + reg = <0 0x03d00000 0 0x40000>,
> >>> + <0 0x03d9e000 0 0x1000>,
> >>> + <0 0x03d61000 0 0x800>;
> >>> + reg-names = "kgsl_3d0_reg_memory",
> >>> + "cx_mem",
> >>> + "cx_dbgc";
> >>> + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
> >>> + iommus = <&adreno_smmu 0 0xc00>, <&adreno_smmu 1 0xc00>;
> >>> + operating-points-v2 = <&gpu_opp_table>;
> >>> +
> >>> + qcom,gmu = <&gmu>;
> >>> + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
> >>> + interconnect-names = "gfx-mem";
> >>> + #cooling-cells = <2>;
> >>> +
> >>> + status = "disabled";
> >>> +
> >>> + gpu_opp_table: opp-table {
> >>> + compatible = "operating-points-v2";
> >>> +
> >>> + opp-270000000 {
> >>> + opp-hz = /bits/ 64 <270000000>;
> >>> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> >>> + opp-peak-kBps = <451000>;
> >>> + };
> >>> +
> >>> + opp-410000000 {
> >>> + opp-hz = /bits/ 64 <410000000>;
> >>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> >>> + opp-peak-kBps = <1555000>;
> >>> + };
> >>> +
> >>> + opp-500000000 {
> >>> + opp-hz = /bits/ 64 <500000000>;
> >>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> >>> + opp-peak-kBps = <1555000>;
> >>> + };
> >>> +
> >>> + opp-547000000 {
> >>> + opp-hz = /bits/ 64 <547000000>;
> >>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
> >>> + opp-peak-kBps = <1555000>;
> >>> + };
> >>> +
> >>> + opp-606000000 {
> >>> + opp-hz = /bits/ 64 <606000000>;
> >>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> >>> + opp-peak-kBps = <2736000>;
> >>> + };
> >>> +
> >>> + opp-640000000 {
> >>> + opp-hz = /bits/ 64 <640000000>;
> >>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> >>> + opp-peak-kBps = <2736000>;
> >>> + };
> >>> +
> >>> + opp-690000000 {
> >>> + opp-hz = /bits/ 64 <690000000>;
> >>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> >>> + opp-peak-kBps = <2736000>;
> >>> + };
> >>> + };
> >>> + };
> >>> +
> >>> + gmu: gmu@3d6a000 {
> >>> + compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
> >>> + reg = <0 0x03d6a000 0 0x34000>,
> >>> + <0 0x03de0000 0 0x10000>,
> >>> + <0 0x0b290000 0 0x10000>;
> >>> + reg-names = "gmu", "rscc", "gmu_pdc";
> >>> + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> >>> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
> >>> + interrupt-names = "hfi", "gmu";
> >>> + clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
> >>> + <&gpucc GPU_CC_CXO_CLK>,
> >>> + <&gcc GCC_DDRSS_GPU_AXI_CLK>,
> >>> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> >>> + <&gpucc GPU_CC_AHB_CLK>,
> >>> + <&gpucc GPU_CC_HUB_CX_INT_CLK>,
> >>> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
> >>> + clock-names = "gmu",
> >>> + "cxo",
> >>> + "axi",
> >>> + "memnoc",
> >>> + "ahb",
> >>> + "hub",
> >>> + "smmu_vote";
> >>> + power-domains = <&gpucc GPU_CC_CX_GDSC>,
> >>> + <&gpucc GPU_CC_GX_GDSC>;
> >>> + power-domain-names = "cx",
> >>> + "gx";
> >>> + iommus = <&adreno_smmu 5 0xc00>;
> >>> + operating-points-v2 = <&gmu_opp_table>;
> >>> +
> >>> + status = "disabled";
> >> I've recently discovered that - and I am not 100% sure - all GMUs are
> >> cache-coherent. Could you please ask somebody at qc about this?
If supported at hw and necessary pte attributes are present, all GPU transactions are
cache-coherent. Since gmu is part of GPU, it is a fairly good assumption that it would
be too.
But current set of GMUs doesn't do enough frequent chatter with CPU to
get any meaningful benefit with coherency. So I feel it is better to
leave it similar to downstream.
-Akhil
> >>
> >
> > AFAIU, GMU's job is controlling the voltage and clock to the GPU.
> Not just that, it's only the limited functionality we've implemented
> upstream so far.
>
> It doesn't do
> > any data transactions on its own.
> Of course it does. AP communication is done through MMIO writes and
> the GMU talks to RPMh via the GPU RSC directly. Apart from that, some
> of the GPU registers (that nota bene don't have anything to do with
> the GMU M3 core itself) lay within the GMU address space.
>
>
> Bjorn noticed that this coherent mask setting downstream may be
> a bluff, but I guess we could poke Qualcomm about whether it's
> cache-coherent (Akhil, could you say anything about that?).
>
> Konrad
>
> So cache-coherent doesn't make sense to me.
> >
> > - Mani
> >
> >>> +
> >>> + gmu_opp_table: opp-table {
> >>> + compatible = "operating-points-v2";
> >>> +
> >>> + opp-200000000 {
> >>> + opp-hz = /bits/ 64 <200000000>;
> >>> + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> >>> + };
> >> Missing 500MHz + RPMH_REGULATOR_LEVEL_SVS
> >>
> >> (that may be used in the future for hw scheduling)
> >>> + };
> >>> + };
> >>> +
> >>> + gpucc: clock-controller@3d90000 {
> >>> + compatible = "qcom,sc8280xp-gpucc";
> >>> + reg = <0 0x03d90000 0 0x9000>;
> >>> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> >>> + <&gcc GCC_GPU_GPLL0_CLK_SRC>,
> >>> + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
> >>> + clock-names = "bi_tcxo",
> >>> + "gcc_gpu_gpll0_clk_src",
> >>> + "gcc_gpu_gpll0_div_clk_src";
> >> FWIW the driver doesn't use clock-names, but the binding defines it,
> >> so I suppose it's fine
> >>
> >>> +
> >>> + power-domains = <&rpmhpd SC8280XP_GFX>;
> >>> + #clock-cells = <1>;
> >>> + #reset-cells = <1>;
> >>> + #power-domain-cells = <1>;
> >>> +
> >>> + status = "disabled";
> >>> + };
> >>> +
> >>> + adreno_smmu: iommu@3da0000 {
> >>> + compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu",
> >>> + "qcom,smmu-500", "arm,mmu-500";
> >>> + reg = <0 0x03da0000 0 0x20000>;
> >>> + #iommu-cells = <2>;
> >>> + #global-interrupts = <2>;
> >>> + interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
> >>> + <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
> >>> + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
> >>> + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
> >>> + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
> >>> + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
> >>> + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
> >>> + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
> >>> + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
> >>> + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
> >>> + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
> >>> + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
> >>> + <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
> >>> + <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>;
> >>> +
> >>> + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> >>> + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
> >>> + <&gpucc GPU_CC_AHB_CLK>,
> >>> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
> >>> + <&gpucc GPU_CC_CX_GMU_CLK>,
> >>> + <&gpucc GPU_CC_HUB_CX_INT_CLK>,
> >>> + <&gpucc GPU_CC_HUB_AON_CLK>;
> >>> + clock-names = "gcc_gpu_memnoc_gfx_clk",
> >>> + "gcc_gpu_snoc_dvm_gfx_clk",
> >>> + "gpu_cc_ahb_clk",
> >>> + "gpu_cc_hlos1_vote_gpu_smmu_clk",
> >>> + "gpu_cc_cx_gmu_clk",
> >>> + "gpu_cc_hub_cx_int_clk",
> >>> + "gpu_cc_hub_aon_clk";
> >>> +
> >>> + power-domains = <&gpucc GPU_CC_CX_GDSC>;
> >>> +
> >>> + status = "disabled";
> >> This one should be dma-coherent (per downstream, plus 8350's mmu is for sure)
> >>
> >> Konrad
> >>> + };
> >>> +
> >>> usb_0_hsphy: phy@88e5000 {
> >>> compatible = "qcom,sc8280xp-usb-hs-phy",
> >>> "qcom,usb-snps-hs-5nm-phy";
> >
On Tue, May 30, 2023 at 08:35:14AM -0700, Bjorn Andersson wrote:
>
> On Mon, May 29, 2023 at 02:16:14PM +0530, Manivannan Sadhasivam wrote:
> > On Mon, May 29, 2023 at 09:38:59AM +0200, Konrad Dybcio wrote:
> > > On 28.05.2023 19:07, Manivannan Sadhasivam wrote:
> > > > On Tue, May 23, 2023 at 09:59:53AM +0200, Konrad Dybcio wrote:
> > > >> On 23.05.2023 03:15, Bjorn Andersson wrote:
> > > >>> From: Bjorn Andersson <[email protected]>
> [..]
> > > >>> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> [..]
> > > >>> + gmu: gmu@3d6a000 {
> [..]
> > > >>> + status = "disabled";
> > > >> I've recently discovered that - and I am not 100% sure - all GMUs are
> > > >> cache-coherent. Could you please ask somebody at qc about this?
> > > >>
> > > >
> > > > AFAIU, GMU's job is controlling the voltage and clock to the GPU.
> > > Not just that, it's only the limited functionality we've implemented
> > > upstream so far.
> > >
> >
> > Okay, good to know!
> >
> > > It doesn't do
> > > > any data transactions on its own.
> > > Of course it does. AP communication is done through MMIO writes and
> > > the GMU talks to RPMh via the GPU RSC directly. Apart from that, some
> > > of the GPU registers (that nota bene don't have anything to do with
> > > the GMU M3 core itself) lay within the GMU address space.
> > >
>
> But those aren't shared memory accesses.
>
> >
> > That doesn't justify the fact that cache coherency is needed, especially
> > MMIO writes, unless GMU could snoop the MMIO writes to AP caches.
> >
>
> In reviewing the downstream state again I noticed that the GPU smmu is
> marked dma-coherent, so I will adjust that in v3.
Bjorn,
Would you mind sharing a perf delta (preferrably manhattan offscreen)
you see with and without this dma-coherent property?
-Akhil.
>
> Regards,
> Bjorn
On Mon, 22 May 2023 18:15:19 -0700, Bjorn Andersson wrote:
> This series introduces support for A690 in the DRM/MSM driver and
> enables it for the two SC8280XP laptops.
>
> Bjorn Andersson (3):
> drm/msm/adreno: Add Adreno A690 support
> arm64: dts: qcom: sc8280xp: Add GPU related nodes
> arm64: dts: qcom: sc8280xp: Enable GPU related nodes
>
> [...]
Applied, thanks!
[1/3] drm/msm/adreno: Add Adreno A690 support
(no commit info)
[2/3] arm64: dts: qcom: sc8280xp: Add GPU related nodes
commit: eec51ab2fd6f447a993c502364704d0cb5bc8cae
[3/3] arm64: dts: qcom: sc8280xp: Enable GPU related nodes
commit: 598a06afca5a2ab4850ce9ff8146ec728cca570c
Best regards,
--
Bjorn Andersson <[email protected]>
On Wed, Jun 14, 2023 at 09:03:34AM -0700, Bjorn Andersson wrote:
> On Mon, 22 May 2023 18:15:19 -0700, Bjorn Andersson wrote:
> > This series introduces support for A690 in the DRM/MSM driver and
> > enables it for the two SC8280XP laptops.
> >
> > Bjorn Andersson (3):
> > drm/msm/adreno: Add Adreno A690 support
> > arm64: dts: qcom: sc8280xp: Add GPU related nodes
> > arm64: dts: qcom: sc8280xp: Enable GPU related nodes
> >
> > [...]
>
> Applied, thanks!
>
> [1/3] drm/msm/adreno: Add Adreno A690 support
> (no commit info)
> [2/3] arm64: dts: qcom: sc8280xp: Add GPU related nodes
> commit: eec51ab2fd6f447a993c502364704d0cb5bc8cae
> [3/3] arm64: dts: qcom: sc8280xp: Enable GPU related nodes
> commit: 598a06afca5a2ab4850ce9ff8146ec728cca570c
>
Seems like I managed to confuse b4, only v4 of the DTS patches were
merged, while Rob merged the driver change.
Regards,
Bjorn