The following changes since commit 924cbb8cbe3460ea192e6243017ceb0ceb255b1b:
riscv: Improve description for RISCV_ISA_SVPBMT Kconfig symbol (2022-06-16 15:47:39 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-5.20-mw0
for you to fetch changes up to ba6cfef057e1c594c456627aad81c2343fdb5d13:
riscv: enable Docker requirements in defconfig (2022-07-22 13:43:28 -0700)
----------------------------------------------------------------
RISC-V Patches for the 5.20 Merge Window, Part 1
* Enabling the FPU is now a static_key.
* Improvements to the Svpbmt support.
* CPU topology bindings for a handful of systems.
* Support for systems with 64-bit hart IDs.
* Many settings have been enabled in the defconfig, including both
support for the StarFive systems and many of the Docker requirements.
There are also a handful of cleanups and improvements, like usual.
----------------------------------------------------------------
This all passes my standard tests, with the old caveat that I'm still seeing
some weirdness with QEMU-7.0 and a new issue where GCC-11 is tripping up on
some fortify string checks in lm90.c on rv32 (GCC-12 works). I don't really
like to send stuff when there's some outstanding issues like this, but after
poking around for a bit it doesn't look like either is related to this pull
request so it seems worse to hold off any longer.
I'm also not 100% sure why it's calling out a patch in the middle as the base,
I see v5.19-rc1 in the history. Sorry if something went off the rails there.
I have one merge conflict, these defines were set to non-zero in arch/riscv at
the same time the refactoring to make them generic went in. I'd considered
merging that PR locally and making the fix in my tree, but that looked uglier
than just passing the merge conflict on. Let me know if I should have done
this the other way around, though.
diff --cc arch/riscv/include/asm/pci.h
index 830ac621dbbc,6ef4a1426194..cc2a184cfc2e
--- a/arch/riscv/include/asm/pci.h
+++ b/arch/riscv/include/asm/pci.h
@@@ -12,31 -12,7 +12,10 @@@
#include <asm/io.h>
+#define PCIBIOS_MIN_IO 4
+#define PCIBIOS_MIN_MEM 16
+
- /* RISC-V shim does not initialize PCI bus */
- #define pcibios_assign_all_busses() 1
-
- #define ARCH_GENERIC_PCI_MMAP_RESOURCE 1
-
- extern int isa_dma_bridge_buggy;
-
- #ifdef CONFIG_PCI
- static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
- {
- /* no legacy IRQ on risc-v */
- return -ENODEV;
- }
-
- static inline int pci_proc_domain(struct pci_bus *bus)
- {
- /* always show the domain in /proc */
- return 1;
- }
-
- #ifdef CONFIG_NUMA
-
+ #if defined(CONFIG_PCI) && defined(CONFIG_NUMA)
static inline int pcibus_to_node(struct pci_bus *bus)
{
return dev_to_node(&bus->dev);
----------------------------------------------------------------
Celeste Liu (1):
riscv: mmap with PROT_WRITE but no PROT_READ is invalid
Conor Dooley (7):
riscv: dts: microchip: remove spi-max-frequency property
riscv: dts: microchip: Add mpfs' topology information
riscv: config: enable SOC_STARFIVE in defconfig
riscv: dts: sifive: Add fu540 topology information
riscv: dts: sifive: Add fu740 topology information
riscv: dts: canaan: Add k210 topology information
riscv: dts: sifive: "fix" pmic watchdog node name
Heiko Stuebner (4):
riscv: make patch-function pointer more generic in cpu_manufacturer_info struct
riscv: remove usage of function-pointers from cpufeatures and t-head errata
riscv: introduce nops and __nops macros for NOP sequences
riscv: convert the t-head pbmt errata to use the __nops macro
Heinrich Schuchardt (1):
riscv: enable Docker requirements in defconfig
Jisheng Zhang (2):
riscv: introduce unified static key mechanism for ISA extensions
riscv: switch has_fpu() to the unified static key mechanism
Jonas Hahnfeld (1):
riscv: dts: starfive: Add JH7100 CPU topology
Juerg Haefliger (3):
riscv: Kconfig: Fix indentation and add comments
riscv: Kconfig.erratas: Add comments
riscv: Kconfig.socs: Add comments
Maciej W. Rozycki (1):
RISC-V: PCI: Avoid handing out address 0 to devices
Nagasuresh Relli (1):
riscv: dts: microchip: remove spi-max-frequency property
Palmer Dabbelt (8):
RISC-V: Use the extension probing code to enable the FPU
RISC-V: Some Svpbmt fixes and cleanups
riscv: Kconfig: Style cleanups
RISC-V: Add CONFIG_{NON,}PORTABLE
Merge tag 'dt-for-palmer-v5.20-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git into for-next
Merge branch 'riscv-cpu_map_topo' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git into for-next
RISC-V: Support for 64bit hartid on RV64 platforms
riscv: Add macro for multiple nop instructions
Sunil V L (5):
riscv: cpu_ops_sbi: Add 64bit hartid support on RV64
riscv: spinwait: Fix hartid variable type
riscv: smp: Add 64bit hartid support on RV64
riscv: cpu: Add 64bit hartid support on RV64
riscv/efi_stub: Add 64bit boot-hartid support on RV64
Xianting Tian (1):
RISC-V: Add fast call path of crash_kexec()
arch/riscv/Kconfig | 47 ++++++++++++----
arch/riscv/Kconfig.erratas | 2 +-
arch/riscv/Kconfig.socs | 4 +-
arch/riscv/boot/dts/canaan/k210.dtsi | 12 ++++
arch/riscv/boot/dts/microchip/mpfs.dtsi | 27 ++++++++-
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 24 ++++++++
arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 24 ++++++++
.../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 2 +-
arch/riscv/boot/dts/starfive/jh7100.dtsi | 16 +++++-
arch/riscv/configs/32-bit.config | 2 +
arch/riscv/configs/defconfig | 65 +++++++++++++++++++++-
arch/riscv/configs/nommu_k210_defconfig | 1 +
arch/riscv/configs/nommu_k210_sdcard_defconfig | 1 +
arch/riscv/configs/nommu_virt_defconfig | 1 +
arch/riscv/configs/rv32_defconfig | 1 +
arch/riscv/errata/thead/errata.c | 38 ++++---------
arch/riscv/include/asm/asm.h | 15 +++++
arch/riscv/include/asm/barrier.h | 2 +
arch/riscv/include/asm/errata_list.h | 8 +--
arch/riscv/include/asm/hwcap.h | 25 +++++++++
arch/riscv/include/asm/pci.h | 4 +-
arch/riscv/include/asm/processor.h | 4 +-
arch/riscv/include/asm/smp.h | 4 +-
arch/riscv/include/asm/switch_to.h | 4 +-
arch/riscv/kernel/alternative.c | 18 +++---
arch/riscv/kernel/cpu.c | 26 +++++----
arch/riscv/kernel/cpu_ops_sbi.c | 4 +-
arch/riscv/kernel/cpu_ops_spinwait.c | 4 +-
arch/riscv/kernel/cpufeature.c | 52 +++++++----------
arch/riscv/kernel/smp.c | 4 +-
arch/riscv/kernel/smpboot.c | 9 +--
arch/riscv/kernel/sys_riscv.c | 5 +-
arch/riscv/kernel/traps.c | 4 ++
drivers/clocksource/timer-riscv.c | 15 ++---
drivers/firmware/efi/libstub/riscv-stub.c | 13 ++++-
drivers/irqchip/irq-riscv-intc.c | 7 ++-
drivers/irqchip/irq-sifive-plic.c | 7 ++-
37 files changed, 358 insertions(+), 143 deletions(-)
The pull request you sent on Fri, 05 Aug 2022 16:36:38 -0700 (PDT):
> git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-5.20-mw0
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/4d1044fcb996e8de9b9ab392f4a767890e45202d
Thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/prtracker.html
On 06/08/2022 00:36, Palmer Dabbelt wrote:
> The following changes since commit 924cbb8cbe3460ea192e6243017ceb0ceb255b1b:
>
> riscv: Improve description for RISCV_ISA_SVPBMT Kconfig symbol (2022-06-16 15:47:39 -0700)
>
> are available in the Git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-5.20-mw0
>
> for you to fetch changes up to ba6cfef057e1c594c456627aad81c2343fdb5d13:
>
> riscv: enable Docker requirements in defconfig (2022-07-22 13:43:28 -0700)
>
> ----------------------------------------------------------------
> RISC-V Patches for the 5.20 Merge Window, Part 1
>
> * Enabling the FPU is now a static_key.
> * Improvements to the Svpbmt support.
> * CPU topology bindings for a handful of systems.
> * Support for systems with 64-bit hart IDs.
> * Many settings have been enabled in the defconfig, including both
> support for the StarFive systems and many of the Docker requirements.
>
> There are also a handful of cleanups and improvements, like usual.
>
Hi, are some of mine and Connor's fixes planned for part2?
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
https://www.codethink.co.uk/privacy.html
Hi Palmer,
On Fri, Aug 05, 2022 at 04:36:38PM -0700, Palmer Dabbelt wrote:
> The following changes since commit 924cbb8cbe3460ea192e6243017ceb0ceb255b1b:
>
> riscv: Improve description for RISCV_ISA_SVPBMT Kconfig symbol (2022-06-16 15:47:39 -0700)
>
> are available in the Git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-5.20-mw0
Just FYI, the WireGuard test suite over on build.wireguard.com no longer
boots for riscv32 after this merge. Investigating...
Jason
Hi Palmer,
On Mon, Aug 08, 2022 at 04:31:30PM +0200, Jason A. Donenfeld wrote:
> Hi Palmer,
>
> On Fri, Aug 05, 2022 at 04:36:38PM -0700, Palmer Dabbelt wrote:
> > The following changes since commit 924cbb8cbe3460ea192e6243017ceb0ceb255b1b:
> >
> > riscv: Improve description for RISCV_ISA_SVPBMT Kconfig symbol (2022-06-16 15:47:39 -0700)
> >
> > are available in the Git repository at:
> >
> > git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-5.20-mw0
>
> Just FYI, the WireGuard test suite over on build.wireguard.com no longer
> boots for riscv32 after this merge. Investigating...
Ahh, looks like it's caused by 44c1e84a38a0 ("RISC-V: Add
CONFIG_{NON,}PORTABLE"). I pushed a patch for it to
https://git.zx2c4.com/wireguard-linux/commit/?id=99a1a96f1f80b68b0fb5156ff6bd3f0973cd1f4d
to kick the CI, which should be green again shortly.
If you want, feel free to take that into your risc-v pull part 2,
whenever you make that. Otherwise I'll eventually send it the long way
through net.git.
Jason
On Mon, 08 Aug 2022 00:35:24 PDT (-0700), [email protected] wrote:
> On 06/08/2022 00:36, Palmer Dabbelt wrote:
>> The following changes since commit 924cbb8cbe3460ea192e6243017ceb0ceb255b1b:
>>
>> riscv: Improve description for RISCV_ISA_SVPBMT Kconfig symbol (2022-06-16 15:47:39 -0700)
>>
>> are available in the Git repository at:
>>
>> git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-5.20-mw0
>>
>> for you to fetch changes up to ba6cfef057e1c594c456627aad81c2343fdb5d13:
>>
>> riscv: enable Docker requirements in defconfig (2022-07-22 13:43:28 -0700)
>>
>> ----------------------------------------------------------------
>> RISC-V Patches for the 5.20 Merge Window, Part 1
>>
>> * Enabling the FPU is now a static_key.
>> * Improvements to the Svpbmt support.
>> * CPU topology bindings for a handful of systems.
>> * Support for systems with 64-bit hart IDs.
>> * Many settings have been enabled in the defconfig, including both
>> support for the StarFive systems and many of the Docker requirements.
>>
>> There are also a handful of cleanups and improvements, like usual.
>>
>
> Hi, are some of mine and Connor's fixes planned for part2?
Yes, though maybe that's obvious given that a bunch of them are on
for-next now...
I was hoping to send that this morning but I ran into a few snags. If
there's anything else missing just let me know, IRC is usually the best
way to jump the queue for small stuff -- it kind of just gets buried
otherwise.