From: Conor Dooley <[email protected]>
Do the various bits needed to drop the additionalProperties: true that
we currently have in riscv/cpu.yaml, to permit actually enforcing what
people put in cpus nodes.
Changes in v2:
- drop patches 2 -> 5, they're now standard in dt-schema
CC: Rob Herring <[email protected]>
CC: Krzysztof Kozlowski <[email protected]>
CC: Paul Walmsley <[email protected]>
CC: Palmer Dabbelt <[email protected]>
CC: [email protected]
CC: [email protected]
CC: [email protected]
Conor Dooley (2):
dt-bindings: riscv: cpus: add a ref the common cpu schema
dt-bindings: riscv: cpus: switch to unevaluatedProperties: false
Documentation/devicetree/bindings/riscv/cpus.yaml | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
--
2.39.2
From: Conor Dooley <[email protected]>
To permit validation of RISC-V cpu nodes, "additionalProperties: true"
needs to be swapped for "unevaluatedProperties: false". To facilitate
this in a way that passes dt_binding_check, a reference to the cpu
schema is required.
Disallow the generic cache-op-block-size property that that drags in,
since the RISC-V CBO extensions do not require a common size, and have
individual properties.
Signed-off-by: Conor Dooley <[email protected]>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 3d2934b15e80..e89a10d9c06b 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -23,6 +23,9 @@ description: |
two cores, each of which has two hyperthreads, could be described as
having four harts.
+allOf:
+ - $ref: /schemas/cpu.yaml#
+
properties:
compatible:
oneOf:
@@ -98,6 +101,9 @@ properties:
$ref: "/schemas/types.yaml#/definitions/string"
pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
+ # RISC-V has multiple properties for cache op block sizes as the sizes
+ # differ between individual CBO extensions
+ cache-op-block-size: false
# RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
timebase-frequency: false
--
2.39.2
On Thu, 15 Jun 2023 15:50:13 PDT (-0700), Conor Dooley wrote:
> From: Conor Dooley <[email protected]>
>
> Do the various bits needed to drop the additionalProperties: true that
> we currently have in riscv/cpu.yaml, to permit actually enforcing what
> people put in cpus nodes.
>
> Changes in v2:
> - drop patches 2 -> 5, they're now standard in dt-schema
>
> CC: Rob Herring <[email protected]>
> CC: Krzysztof Kozlowski <[email protected]>
> CC: Paul Walmsley <[email protected]>
> CC: Palmer Dabbelt <[email protected]>
> CC: [email protected]
> CC: [email protected]
> CC: [email protected]
>
> Conor Dooley (2):
> dt-bindings: riscv: cpus: add a ref the common cpu schema
> dt-bindings: riscv: cpus: switch to unevaluatedProperties: false
>
> Documentation/devicetree/bindings/riscv/cpus.yaml | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
Acked-by: Palmer Dabbelt <[email protected]>
LMK if you wanted me to pick these up?
On Thu, 15 Jun 2023 23:50:14 +0100, Conor Dooley wrote:
> From: Conor Dooley <[email protected]>
>
> To permit validation of RISC-V cpu nodes, "additionalProperties: true"
> needs to be swapped for "unevaluatedProperties: false". To facilitate
> this in a way that passes dt_binding_check, a reference to the cpu
> schema is required.
>
> Disallow the generic cache-op-block-size property that that drags in,
> since the RISC-V CBO extensions do not require a common size, and have
> individual properties.
>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
Reviewed-by: Rob Herring <[email protected]>
On Tue, Jun 20, 2023 at 10:00:14AM -0700, Palmer Dabbelt wrote:
> On Thu, 15 Jun 2023 15:50:13 PDT (-0700), Conor Dooley wrote:
> > From: Conor Dooley <[email protected]>
> >
> > Do the various bits needed to drop the additionalProperties: true that
> > we currently have in riscv/cpu.yaml, to permit actually enforcing what
> > people put in cpus nodes.
> >
> > Changes in v2:
> > - drop patches 2 -> 5, they're now standard in dt-schema
> >
> > CC: Rob Herring <[email protected]>
> > CC: Krzysztof Kozlowski <[email protected]>
> > CC: Paul Walmsley <[email protected]>
> > CC: Palmer Dabbelt <[email protected]>
> > CC: [email protected]
> > CC: [email protected]
> > CC: [email protected]
> >
> > Conor Dooley (2):
> > dt-bindings: riscv: cpus: add a ref the common cpu schema
> > dt-bindings: riscv: cpus: switch to unevaluatedProperties: false
> >
> > Documentation/devicetree/bindings/riscv/cpus.yaml | 8 +++++++-
> > 1 file changed, 7 insertions(+), 1 deletion(-)
>
> Acked-by: Palmer Dabbelt <[email protected]>
> LMK if you wanted me to pick these up?
That was my hope, please do!
Cheers,
Conor.
On Thu, 15 Jun 2023 23:50:13 +0100, Conor Dooley wrote:
> From: Conor Dooley <[email protected]>
>
> Do the various bits needed to drop the additionalProperties: true that
> we currently have in riscv/cpu.yaml, to permit actually enforcing what
> people put in cpus nodes.
>
> Changes in v2:
> - drop patches 2 -> 5, they're now standard in dt-schema
>
> [...]
Applied, thanks!
[1/2] dt-bindings: riscv: cpus: add a ref the common cpu schema
https://git.kernel.org/palmer/c/3c1b4758a954
[2/2] dt-bindings: riscv: cpus: switch to unevaluatedProperties: false
https://git.kernel.org/palmer/c/1ffe6ddc5c64
Best regards,
--
Palmer Dabbelt <[email protected]>
Hello:
This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <[email protected]>:
On Thu, 15 Jun 2023 23:50:13 +0100 you wrote:
> From: Conor Dooley <[email protected]>
>
> Do the various bits needed to drop the additionalProperties: true that
> we currently have in riscv/cpu.yaml, to permit actually enforcing what
> people put in cpus nodes.
>
> Changes in v2:
> - drop patches 2 -> 5, they're now standard in dt-schema
>
> [...]
Here is the summary with links:
- [v2,1/2] dt-bindings: riscv: cpus: add a ref the common cpu schema
https://git.kernel.org/riscv/c/3c1b4758a954
- [v2,2/2] dt-bindings: riscv: cpus: switch to unevaluatedProperties: false
https://git.kernel.org/riscv/c/1ffe6ddc5c64
You are awesome, thank you!
--
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