The kernel maintains a mask of ISA extensions ANDed together across all
harts. Let's also keep a bitmap of ISA extensions for each CPU. Although
the kernel is currently unlikely to enable a feature that exists only on
some CPUs, we want the ability to report asymmetric CPU extensions
accurately to usermode.
Note that riscv_fill_hwcaps() runs before the per_cpu_offsets are built,
which is why I've used a [NR_CPUS] array rather than per_cpu() data.
Signed-off-by: Evan Green <[email protected]>
---
arch/riscv/include/asm/cpufeature.h | 10 ++++++++++
arch/riscv/kernel/cpufeature.c | 18 ++++++++++++------
2 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
index 808d5403f2ac..23fed53b8815 100644
--- a/arch/riscv/include/asm/cpufeature.h
+++ b/arch/riscv/include/asm/cpufeature.h
@@ -6,6 +6,9 @@
#ifndef _ASM_CPUFEATURE_H
#define _ASM_CPUFEATURE_H
+#include <linux/bitmap.h>
+#include <asm/hwcap.h>
+
/*
* These are probed via a device_initcall(), via either the SBI or directly
* from the corresponding CSRs.
@@ -16,8 +19,15 @@ struct riscv_cpuinfo {
unsigned long mimpid;
};
+struct riscv_isainfo {
+ DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX);
+};
+
DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
DECLARE_PER_CPU(long, misaligned_access_speed);
+/* Per-cpu ISA extensions. */
+extern struct riscv_isainfo hart_isa[NR_CPUS];
+
#endif
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 1a80474e308e..0e9d66580478 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -14,6 +14,7 @@
#include <linux/of.h>
#include <asm/alternative.h>
#include <asm/cacheflush.h>
+#include <asm/cpufeature.h>
#include <asm/hwcap.h>
#include <asm/patch.h>
#include <asm/processor.h>
@@ -25,6 +26,9 @@ unsigned long elf_hwcap __read_mostly;
/* Host ISA bitmap */
static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
+/* Per-cpu ISA extensions. */
+struct riscv_isainfo hart_isa[NR_CPUS];
+
/* Performance information */
DEFINE_PER_CPU(long, misaligned_access_speed);
@@ -112,14 +116,17 @@ void __init riscv_fill_hwcap(void)
bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX);
for_each_of_cpu_node(node) {
+ struct riscv_isainfo *isainfo;
unsigned long this_hwcap = 0;
- DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
const char *temp;
+ unsigned int cpu_id;
rc = riscv_of_processor_hartid(node, &hartid);
if (rc < 0)
continue;
+ cpu_id = riscv_hartid_to_cpuid(hartid);
+ isainfo = &hart_isa[cpu_id];
if (of_property_read_string(node, "riscv,isa", &isa)) {
pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
continue;
@@ -136,7 +143,6 @@ void __init riscv_fill_hwcap(void)
/* The riscv,isa DT property must start with rv64 or rv32 */
if (temp == isa)
continue;
- bitmap_zero(this_isa, RISCV_ISA_EXT_MAX);
for (; *isa; ++isa) {
const char *ext = isa++;
const char *ext_end = isa;
@@ -214,7 +220,7 @@ void __init riscv_fill_hwcap(void)
if ((ext_end - ext == sizeof(name) - 1) && \
!memcmp(ext, name, sizeof(name) - 1) && \
riscv_isa_extension_check(bit)) \
- set_bit(bit, this_isa); \
+ set_bit(bit, isainfo->isa); \
} while (false) \
if (unlikely(ext_err))
@@ -224,7 +230,7 @@ void __init riscv_fill_hwcap(void)
if (riscv_isa_extension_check(nr)) {
this_hwcap |= isa2hwcap[nr];
- set_bit(nr, this_isa);
+ set_bit(nr, isainfo->isa);
}
} else {
/* sorted alphabetically */
@@ -253,9 +259,9 @@ void __init riscv_fill_hwcap(void)
elf_hwcap = this_hwcap;
if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
- bitmap_copy(riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
+ bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
else
- bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
+ bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
}
/* We don't support systems with F but without D, so mask those out
--
2.25.1
On Fri, Apr 28, 2023 at 12:06:07PM -0700, Evan Green wrote:
> @@ -112,14 +116,17 @@ void __init riscv_fill_hwcap(void)
> bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX);
>
> for_each_of_cpu_node(node) {
> + struct riscv_isainfo *isainfo;
> unsigned long this_hwcap = 0;
> - DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
> const char *temp;
> + unsigned int cpu_id;
>
> rc = riscv_of_processor_hartid(node, &hartid);
> if (rc < 0)
> continue;
>
> + cpu_id = riscv_hartid_to_cpuid(hartid);
> + isainfo = &hart_isa[cpu_id];
> if (of_property_read_string(node, "riscv,isa", &isa)) {
Would you mind adding a blank line above the if statement please?
Otherwise,
Reviewed-by: Conor Dooley <[email protected]>
Thanks,
Conor.
> pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
> continue;
On Fri, 28 Apr 2023 12:06:07 PDT (-0700), Evan Green wrote:
> The kernel maintains a mask of ISA extensions ANDed together across all
> harts. Let's also keep a bitmap of ISA extensions for each CPU. Although
> the kernel is currently unlikely to enable a feature that exists only on
> some CPUs, we want the ability to report asymmetric CPU extensions
> accurately to usermode.
>
> Note that riscv_fill_hwcaps() runs before the per_cpu_offsets are built,
> which is why I've used a [NR_CPUS] array rather than per_cpu() data.
>
> Signed-off-by: Evan Green <[email protected]>
> ---
>
> arch/riscv/include/asm/cpufeature.h | 10 ++++++++++
> arch/riscv/kernel/cpufeature.c | 18 ++++++++++++------
> 2 files changed, 22 insertions(+), 6 deletions(-)
>
> diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
> index 808d5403f2ac..23fed53b8815 100644
> --- a/arch/riscv/include/asm/cpufeature.h
> +++ b/arch/riscv/include/asm/cpufeature.h
> @@ -6,6 +6,9 @@
> #ifndef _ASM_CPUFEATURE_H
> #define _ASM_CPUFEATURE_H
>
> +#include <linux/bitmap.h>
> +#include <asm/hwcap.h>
> +
> /*
> * These are probed via a device_initcall(), via either the SBI or directly
> * from the corresponding CSRs.
> @@ -16,8 +19,15 @@ struct riscv_cpuinfo {
> unsigned long mimpid;
> };
>
> +struct riscv_isainfo {
> + DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX);
> +};
> +
> DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
>
> DECLARE_PER_CPU(long, misaligned_access_speed);
>
> +/* Per-cpu ISA extensions. */
> +extern struct riscv_isainfo hart_isa[NR_CPUS];
> +
> #endif
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 1a80474e308e..0e9d66580478 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -14,6 +14,7 @@
> #include <linux/of.h>
> #include <asm/alternative.h>
> #include <asm/cacheflush.h>
> +#include <asm/cpufeature.h>
> #include <asm/hwcap.h>
> #include <asm/patch.h>
> #include <asm/processor.h>
> @@ -25,6 +26,9 @@ unsigned long elf_hwcap __read_mostly;
> /* Host ISA bitmap */
> static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
>
> +/* Per-cpu ISA extensions. */
> +struct riscv_isainfo hart_isa[NR_CPUS];
> +
> /* Performance information */
> DEFINE_PER_CPU(long, misaligned_access_speed);
>
> @@ -112,14 +116,17 @@ void __init riscv_fill_hwcap(void)
> bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX);
>
> for_each_of_cpu_node(node) {
> + struct riscv_isainfo *isainfo;
> unsigned long this_hwcap = 0;
> - DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
> const char *temp;
> + unsigned int cpu_id;
>
> rc = riscv_of_processor_hartid(node, &hartid);
> if (rc < 0)
> continue;
>
> + cpu_id = riscv_hartid_to_cpuid(hartid);
> + isainfo = &hart_isa[cpu_id];
> if (of_property_read_string(node, "riscv,isa", &isa)) {
> pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
> continue;
> @@ -136,7 +143,6 @@ void __init riscv_fill_hwcap(void)
> /* The riscv,isa DT property must start with rv64 or rv32 */
> if (temp == isa)
> continue;
> - bitmap_zero(this_isa, RISCV_ISA_EXT_MAX);
> for (; *isa; ++isa) {
> const char *ext = isa++;
> const char *ext_end = isa;
> @@ -214,7 +220,7 @@ void __init riscv_fill_hwcap(void)
> if ((ext_end - ext == sizeof(name) - 1) && \
> !memcmp(ext, name, sizeof(name) - 1) && \
> riscv_isa_extension_check(bit)) \
> - set_bit(bit, this_isa); \
> + set_bit(bit, isainfo->isa); \
> } while (false) \
>
> if (unlikely(ext_err))
> @@ -224,7 +230,7 @@ void __init riscv_fill_hwcap(void)
>
> if (riscv_isa_extension_check(nr)) {
> this_hwcap |= isa2hwcap[nr];
> - set_bit(nr, this_isa);
> + set_bit(nr, isainfo->isa);
> }
> } else {
> /* sorted alphabetically */
> @@ -253,9 +259,9 @@ void __init riscv_fill_hwcap(void)
> elf_hwcap = this_hwcap;
>
> if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
> - bitmap_copy(riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
> + bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
> else
> - bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
> + bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
> }
>
> /* We don't support systems with F but without D, so mask those out
Reviewed-by: Palmer Dabbelt <[email protected]>