2020-10-29 07:59:39

by Atish Patra

[permalink] [raw]
Subject: [RFC PATCH 3/3] RISC-V: Enable Microchip PolarFire ICICLE SoC

Enable Microchip PolarFire ICICLE soc config in defconfig.
It allows the default upstream kernel to boot on PolarFire ICICLE board.

Signed-off-by: Atish Patra <[email protected]>
---
arch/riscv/configs/defconfig | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index d222d353d86d..2660fa05451e 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -16,6 +16,7 @@ CONFIG_EXPERT=y
CONFIG_BPF_SYSCALL=y
CONFIG_SOC_SIFIVE=y
CONFIG_SOC_VIRT=y
+CONFIG_SOC_MICROCHIP_POLARFIRE=y
CONFIG_SMP=y
CONFIG_JUMP_LABEL=y
CONFIG_MODULES=y
@@ -79,6 +80,9 @@ CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_STORAGE=y
CONFIG_USB_UAS=y
+CONFIG_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_CADENCE=y
CONFIG_MMC=y
CONFIG_MMC_SPI=y
CONFIG_RTC_CLASS=y
--
2.25.1


2020-10-30 09:14:30

by Anup Patel

[permalink] [raw]
Subject: Re: [RFC PATCH 3/3] RISC-V: Enable Microchip PolarFire ICICLE SoC

On Thu, Oct 29, 2020 at 4:58 AM Atish Patra <[email protected]> wrote:
>
> Enable Microchip PolarFire ICICLE soc config in defconfig.
> It allows the default upstream kernel to boot on PolarFire ICICLE board.
>
> Signed-off-by: Atish Patra <[email protected]>
> ---
> arch/riscv/configs/defconfig | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index d222d353d86d..2660fa05451e 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -16,6 +16,7 @@ CONFIG_EXPERT=y
> CONFIG_BPF_SYSCALL=y
> CONFIG_SOC_SIFIVE=y
> CONFIG_SOC_VIRT=y
> +CONFIG_SOC_MICROCHIP_POLARFIRE=y
> CONFIG_SMP=y
> CONFIG_JUMP_LABEL=y
> CONFIG_MODULES=y
> @@ -79,6 +80,9 @@ CONFIG_USB_OHCI_HCD=y
> CONFIG_USB_OHCI_HCD_PLATFORM=y
> CONFIG_USB_STORAGE=y
> CONFIG_USB_UAS=y
> +CONFIG_SDHCI=y
> +CONFIG_MMC_SDHCI_PLTFM=y
> +CONFIG_MMC_SDHCI_CADENCE=y
> CONFIG_MMC=y
> CONFIG_MMC_SPI=y
> CONFIG_RTC_CLASS=y
> --
> 2.25.1
>

Looks good to me.

Reviewed-by: Anup Patel <[email protected]>

Regards,
Anup

2020-10-30 21:47:30

by Ben Dooks

[permalink] [raw]
Subject: Re: [RFC PATCH 3/3] RISC-V: Enable Microchip PolarFire ICICLE SoC

On 30/10/2020 09:09, Anup Patel wrote:
> On Thu, Oct 29, 2020 at 4:58 AM Atish Patra <[email protected]> wrote:
>>
>> Enable Microchip PolarFire ICICLE soc config in defconfig.
>> It allows the default upstream kernel to boot on PolarFire ICICLE board.
>>
>> Signed-off-by: Atish Patra <[email protected]>
>> ---

Is there going to be a git tree with all the necessary support for the
polarfire/icicle boards? I so far have updated yocto patches, a rebase
to v5.9 and the v17 PCIe patches (which still don't work for us)

--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html

2020-11-03 10:04:57

by Bin Meng

[permalink] [raw]
Subject: Re: [RFC PATCH 3/3] RISC-V: Enable Microchip PolarFire ICICLE SoC

On Thu, Oct 29, 2020 at 6:00 PM Atish Patra <[email protected]> wrote:
>
> Enable Microchip PolarFire ICICLE soc config in defconfig.
> It allows the default upstream kernel to boot on PolarFire ICICLE board.
>
> Signed-off-by: Atish Patra <[email protected]>
> ---
> arch/riscv/configs/defconfig | 4 ++++
> 1 file changed, 4 insertions(+)
>

Reviewed-by: Bin Meng <[email protected]>

2020-11-06 07:19:08

by Palmer Dabbelt

[permalink] [raw]
Subject: Re: [RFC PATCH 3/3] RISC-V: Enable Microchip PolarFire ICICLE SoC

On Wed, 28 Oct 2020 16:27:59 PDT (-0700), Atish Patra wrote:
> Enable Microchip PolarFire ICICLE soc config in defconfig.
> It allows the default upstream kernel to boot on PolarFire ICICLE board.

I don't actually have one of these to test on yet. That said, if it boots for
you then I don't really see any reason to delay this -- maybe there's some
issues floating around, but I don't really see any reason to delay putting this
on for-next. I'd even go so far as to say we should take it during the RCs, as
so far it's just build/DT stuff.

Given that this is currently the only production RISC-V Linux board I don't
really any reason not to add it to the defconfigs.

Is there a reason this is an RFC?

>
> Signed-off-by: Atish Patra <[email protected]>
> ---
> arch/riscv/configs/defconfig | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index d222d353d86d..2660fa05451e 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -16,6 +16,7 @@ CONFIG_EXPERT=y
> CONFIG_BPF_SYSCALL=y
> CONFIG_SOC_SIFIVE=y
> CONFIG_SOC_VIRT=y
> +CONFIG_SOC_MICROCHIP_POLARFIRE=y
> CONFIG_SMP=y
> CONFIG_JUMP_LABEL=y
> CONFIG_MODULES=y
> @@ -79,6 +80,9 @@ CONFIG_USB_OHCI_HCD=y
> CONFIG_USB_OHCI_HCD_PLATFORM=y
> CONFIG_USB_STORAGE=y
> CONFIG_USB_UAS=y
> +CONFIG_SDHCI=y
> +CONFIG_MMC_SDHCI_PLTFM=y
> +CONFIG_MMC_SDHCI_CADENCE=y
> CONFIG_MMC=y
> CONFIG_MMC_SPI=y
> CONFIG_RTC_CLASS=y

Reviewed-by: Palmer Dabbelt <[email protected]>