This series extends KVM RISC-V to allow Guest/VM discover and use
conditional operations related ISA extensions (namely XVentanaCondOps
and Zicond).
To try these patches, use KVMTOOL from riscv_zbx_zicntr_smstateen_condops_v1
branch at: https://github.com/avpatel/kvmtool.git
These patches are based upon the latest riscv_kvm_queue and can also be
found in the riscv_kvm_condops_v2 branch at:
https://github.com/avpatel/linux.git
Changes since v1:
- Rebased the series on riscv_kvm_queue
- Split PATCH1 and PATCH2 of v1 series into two patches
- Added separate test configs for XVentanaCondOps and Zicond in PATCH7
of v1 series.
Anup Patel (9):
dt-bindings: riscv: Add XVentanaCondOps extension entry
RISC-V: Detect XVentanaCondOps from ISA string
dt-bindings: riscv: Add Zicond extension entry
RISC-V: Detect Zicond from ISA string
RISC-V: KVM: Allow XVentanaCondOps extension for Guest/VM
RISC-V: KVM: Allow Zicond extension for Guest/VM
KVM: riscv: selftests: Add senvcfg register to get-reg-list test
KVM: riscv: selftests: Add smstateen registers to get-reg-list test
KVM: riscv: selftests: Add condops extensions to get-reg-list test
.../devicetree/bindings/riscv/extensions.yaml | 13 ++++
arch/riscv/include/asm/hwcap.h | 2 +
arch/riscv/include/uapi/asm/kvm.h | 2 +
arch/riscv/kernel/cpufeature.c | 2 +
arch/riscv/kvm/vcpu_onereg.c | 4 ++
.../selftests/kvm/riscv/get-reg-list.c | 71 +++++++++++++++++++
6 files changed, 94 insertions(+)
--
2.34.1
Add an entry for the Zicond extension to the riscv,isa-extensions property.
Signed-off-by: Anup Patel <[email protected]>
---
Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index cad8ef68eca7..3f0b47686080 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -225,6 +225,12 @@ properties:
ratified in the 20191213 version of the unprivileged ISA
specification.
+ - const: zicond
+ description:
+ The standard Zicond extension for conditional arithmetic and
+ conditional-select/move operations as ratified in commit 95cf1f9
+ ("Add changes requested by Ved during signoff") of riscv-zicond.
+
- const: zicsr
description: |
The standard Zicsr extension for control and status register
--
2.34.1
The RISC-V integer conditional (Zicond) operation extension defines
standard conditional arithmetic and conditional-select/move operations
which are inspired from the XVentanaCondOps extension. In fact, QEMU
RISC-V also has support for emulating Zicond extension.
Let us detect Zicond extension from ISA string available through
DT or ACPI.
Signed-off-by: Anup Patel <[email protected]>
---
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/kernel/cpufeature.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index b7efe9e2fa89..15bafc02ffd4 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -60,6 +60,7 @@
#define RISCV_ISA_EXT_ZIHPM 42
#define RISCV_ISA_EXT_SMSTATEEN 43
#define RISCV_ISA_EXT_XVENTANACONDOPS 44
+#define RISCV_ISA_EXT_ZICOND 45
#define RISCV_ISA_EXT_MAX 64
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 3a31d34fe709..7f683916f2c2 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -167,6 +167,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
__RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
__RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR),
+ __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND),
__RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR),
__RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI),
__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
--
2.34.1
We have a new smstateen registers as separate sub-type of CSR ONE_REG
interface so let us add these registers to get-reg-list test.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
---
.../selftests/kvm/riscv/get-reg-list.c | 34 +++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
index 6cec0ef75cc7..625118d53b74 100644
--- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
+++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
@@ -36,6 +36,7 @@ bool filter_reg(__u64 reg)
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_I:
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_M:
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_V:
+ case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SMSTATEEN:
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSAIA:
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSTC:
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVINVAL:
@@ -186,6 +187,8 @@ static const char *core_id_to_str(const char *prefix, __u64 id)
"KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(" #csr ")"
#define RISCV_CSR_AIA(csr) \
"KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_REG(" #csr ")"
+#define RISCV_CSR_SMSTATEEN(csr) \
+ "KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_REG(" #csr ")"
static const char *general_csr_id_to_str(__u64 reg_off)
{
@@ -243,6 +246,18 @@ static const char *aia_csr_id_to_str(__u64 reg_off)
return NULL;
}
+static const char *smstateen_csr_id_to_str(__u64 reg_off)
+{
+ /* reg_off is the offset into struct kvm_riscv_smstateen_csr */
+ switch (reg_off) {
+ case KVM_REG_RISCV_CSR_SMSTATEEN_REG(sstateen0):
+ return RISCV_CSR_SMSTATEEN(sstateen0);
+ }
+
+ TEST_FAIL("Unknown smstateen csr reg: 0x%llx", reg_off);
+ return NULL;
+}
+
static const char *csr_id_to_str(const char *prefix, __u64 id)
{
__u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CSR);
@@ -255,6 +270,8 @@ static const char *csr_id_to_str(const char *prefix, __u64 id)
return general_csr_id_to_str(reg_off);
case KVM_REG_RISCV_CSR_AIA:
return aia_csr_id_to_str(reg_off);
+ case KVM_REG_RISCV_CSR_SMSTATEEN:
+ return smstateen_csr_id_to_str(reg_off);
}
TEST_FAIL("%s: Unknown csr subtype: 0x%llx", prefix, reg_subtype);
@@ -332,6 +349,7 @@ static const char *isa_ext_id_to_str(__u64 id)
KVM_ISA_EXT_ARR(I),
KVM_ISA_EXT_ARR(M),
KVM_ISA_EXT_ARR(V),
+ KVM_ISA_EXT_ARR(SMSTATEEN),
KVM_ISA_EXT_ARR(SSAIA),
KVM_ISA_EXT_ARR(SSTC),
KVM_ISA_EXT_ARR(SVINVAL),
@@ -637,6 +655,11 @@ static __u64 aia_regs[] = {
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSAIA,
};
+static __u64 smstateen_regs[] = {
+ KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_SMSTATEEN_REG(sstateen0),
+ KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SMSTATEEN,
+};
+
static __u64 fp_f_regs[] = {
KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[0]),
KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[1]),
@@ -744,6 +767,8 @@ static __u64 fp_d_regs[] = {
{"zihpm", .feature = KVM_RISCV_ISA_EXT_ZIHPM, .regs = zihpm_regs, .regs_n = ARRAY_SIZE(zihpm_regs),}
#define AIA_REGS_SUBLIST \
{"aia", .feature = KVM_RISCV_ISA_EXT_SSAIA, .regs = aia_regs, .regs_n = ARRAY_SIZE(aia_regs),}
+#define SMSTATEEN_REGS_SUBLIST \
+ {"smstateen", .feature = KVM_RISCV_ISA_EXT_SMSTATEEN, .regs = smstateen_regs, .regs_n = ARRAY_SIZE(smstateen_regs),}
#define FP_F_REGS_SUBLIST \
{"fp_f", .feature = KVM_RISCV_ISA_EXT_F, .regs = fp_f_regs, \
.regs_n = ARRAY_SIZE(fp_f_regs),}
@@ -871,6 +896,14 @@ static struct vcpu_reg_list aia_config = {
},
};
+static struct vcpu_reg_list smstateen_config = {
+ .sublists = {
+ BASE_SUBLIST,
+ SMSTATEEN_REGS_SUBLIST,
+ {0},
+ },
+};
+
static struct vcpu_reg_list fp_f_config = {
.sublists = {
BASE_SUBLIST,
@@ -903,6 +936,7 @@ struct vcpu_reg_list *vcpu_configs[] = {
&zifencei_config,
&zihpm_config,
&aia_config,
+ &smstateen_config,
&fp_f_config,
&fp_d_config,
};
--
2.34.1
Add an entry for the XVentanaCondOps extension to the
riscv,isa-extensions property.
Signed-off-by: Anup Patel <[email protected]>
---
Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 36ff6749fbba..cad8ef68eca7 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -171,6 +171,13 @@ properties:
memory types as ratified in the 20191213 version of the privileged
ISA specification.
+ - const: xventanacondops
+ description: |
+ The Ventana specific XVentanaCondOps extension for conditional
+ arithmetic and conditional-select/move operations defined by the
+ Ventana custom extensions specification v1.0.1 (or higher) at
+ https://github.com/ventanamicro/ventana-custom-extensions/releases.
+
- const: zba
description: |
The standard Zba bit-manipulation extension for address generation
--
2.34.1
On Mon, Sep 25, 2023 at 07:08:53PM +0530, Anup Patel wrote:
> Add an entry for the Zicond extension to the riscv,isa-extensions property.
>
> Signed-off-by: Anup Patel <[email protected]>
> ---
> Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index cad8ef68eca7..3f0b47686080 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -225,6 +225,12 @@ properties:
> ratified in the 20191213 version of the unprivileged ISA
> specification.
>
> + - const: zicond
> + description:
> + The standard Zicond extension for conditional arithmetic and
> + conditional-select/move operations as ratified in commit 95cf1f9
> + ("Add changes requested by Ved during signoff") of riscv-zicond.
> +
> - const: zicsr
> description: |
> The standard Zicsr extension for control and status register
> --
> 2.34.1
>
Reviewed-by: Andrew Jones <[email protected]>
The Veyron-V1 CPU supports custom conditional arithmetic and
conditional-select/move operations referred to as XVentanaCondOps
extension. In fact, QEMU RISC-V also has support for emulating
XVentanaCondOps extension.
Let us detect XVentanaCondOps extension from ISA string available
through DT or ACPI.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
---
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/kernel/cpufeature.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 0f520f7d058a..b7efe9e2fa89 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -59,6 +59,7 @@
#define RISCV_ISA_EXT_ZIFENCEI 41
#define RISCV_ISA_EXT_ZIHPM 42
#define RISCV_ISA_EXT_SMSTATEEN 43
+#define RISCV_ISA_EXT_XVENTANACONDOPS 44
#define RISCV_ISA_EXT_MAX 64
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 3755a8c2a9de..3a31d34fe709 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -182,6 +182,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
__RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
+ __RISCV_ISA_EXT_DATA(xventanacondops, RISCV_ISA_EXT_XVENTANACONDOPS),
};
const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
--
2.34.1
We have a new senvcfg register in the general CSR ONE_REG interface
so let us add it to get-reg-list test.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
---
tools/testing/selftests/kvm/riscv/get-reg-list.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
index a61b706a8778..6cec0ef75cc7 100644
--- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
+++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
@@ -211,6 +211,8 @@ static const char *general_csr_id_to_str(__u64 reg_off)
return RISCV_CSR_GENERAL(satp);
case KVM_REG_RISCV_CSR_REG(scounteren):
return RISCV_CSR_GENERAL(scounteren);
+ case KVM_REG_RISCV_CSR_REG(senvcfg):
+ return RISCV_CSR_GENERAL(senvcfg);
}
TEST_FAIL("Unknown general csr reg: 0x%llx", reg_off);
@@ -540,6 +542,7 @@ static __u64 base_regs[] = {
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sip),
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(satp),
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(scounteren),
+ KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(senvcfg),
KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(frequency),
KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(time),
KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(compare),
--
2.34.1
On Wed, Sep 27, 2023 at 07:54:49PM +0530, Anup Patel wrote:
> On Mon, Sep 25, 2023 at 9:07 PM Conor Dooley <[email protected]> wrote:
> >
> > On Mon, Sep 25, 2023 at 04:33:15PM +0100, Conor Dooley wrote:
> > > On Mon, Sep 25, 2023 at 07:08:50PM +0530, Anup Patel wrote:
> > > > This series extends KVM RISC-V to allow Guest/VM discover and use
> > > > conditional operations related ISA extensions (namely XVentanaCondOps
> > > > and Zicond).
> > > >
> > > > To try these patches, use KVMTOOL from riscv_zbx_zicntr_smstateen_condops_v1
> > > > branch at: https://github.com/avpatel/kvmtool.git
> > > >
> > > > These patches are based upon the latest riscv_kvm_queue and can also be
> > > > found in the riscv_kvm_condops_v2 branch at:
> > > > https://github.com/avpatel/linux.git
> > > >
> > > > Changes since v1:
> > > > - Rebased the series on riscv_kvm_queue
> > > > - Split PATCH1 and PATCH2 of v1 series into two patches
> > > > - Added separate test configs for XVentanaCondOps and Zicond in PATCH7
> > > > of v1 series.
> > > >
> > > > Anup Patel (9):
> > > > dt-bindings: riscv: Add XVentanaCondOps extension entry
> > > > RISC-V: Detect XVentanaCondOps from ISA string
> > > > dt-bindings: riscv: Add Zicond extension entry
> > > > RISC-V: Detect Zicond from ISA string
> > >
> > > For these 4:
> > > Reviewed-by: Conor Dooley <[email protected]>
> >
> > Actually, now that I think of it, I'm going to temporarily un-review this.
> > From patch-acceptance.rst:
> > | Additionally, the RISC-V specification allows implementers to create
> > | their own custom extensions. These custom extensions aren't required
> > | to go through any review or ratification process by the RISC-V
> > | Foundation. To avoid the maintenance complexity and potential
> > | performance impact of adding kernel code for implementor-specific
> > | RISC-V extensions, we'll only consider patches for extensions that either:
> > |
> > | - Have been officially frozen or ratified by the RISC-V Foundation, or
> > | - Have been implemented in hardware that is widely available, per standard
> > | Linux practice.
> >
> > The xventanacondops bits don't qualify under the first entry, and I
> > don't think they qualify under the second yet. Am I wrong?
>
> The Ventana Veyron V1 was announced in Dec 2022 at RISC-V summit
> followed by press releases:
> https://www.ventanamicro.com/ventana-introduces-veyron-worlds-first-data-center-class-risc-v-cpu-product-family/
> https://www.embedded.com/ventana-reveals-risc-v-cpu-compute-chiplet-for-data-center/
> https://www.prnewswire.com/news-releases/ventana-introduces-veyron-worlds-first-data-center-class-risc-v-cpu-product-family-301700985.html
>
> @Palmer if the above looks good to you then please ack PATCH1-to-4
These are announcements AFAICT & not an indication of "being implemented
in hardware that is widely available".
On Wed, 27 Sep 2023 07:45:28 PDT (-0700), Conor Dooley wrote:
> On Wed, Sep 27, 2023 at 07:54:49PM +0530, Anup Patel wrote:
>> On Mon, Sep 25, 2023 at 9:07 PM Conor Dooley <[email protected]> wrote:
>> >
>> > On Mon, Sep 25, 2023 at 04:33:15PM +0100, Conor Dooley wrote:
>> > > On Mon, Sep 25, 2023 at 07:08:50PM +0530, Anup Patel wrote:
>> > > > This series extends KVM RISC-V to allow Guest/VM discover and use
>> > > > conditional operations related ISA extensions (namely XVentanaCondOps
>> > > > and Zicond).
>> > > >
>> > > > To try these patches, use KVMTOOL from riscv_zbx_zicntr_smstateen_condops_v1
>> > > > branch at: https://github.com/avpatel/kvmtool.git
>> > > >
>> > > > These patches are based upon the latest riscv_kvm_queue and can also be
>> > > > found in the riscv_kvm_condops_v2 branch at:
>> > > > https://github.com/avpatel/linux.git
>> > > >
>> > > > Changes since v1:
>> > > > - Rebased the series on riscv_kvm_queue
>> > > > - Split PATCH1 and PATCH2 of v1 series into two patches
>> > > > - Added separate test configs for XVentanaCondOps and Zicond in PATCH7
>> > > > of v1 series.
>> > > >
>> > > > Anup Patel (9):
>> > > > dt-bindings: riscv: Add XVentanaCondOps extension entry
>> > > > RISC-V: Detect XVentanaCondOps from ISA string
>> > > > dt-bindings: riscv: Add Zicond extension entry
>> > > > RISC-V: Detect Zicond from ISA string
>> > >
>> > > For these 4:
>> > > Reviewed-by: Conor Dooley <[email protected]>
>> >
>> > Actually, now that I think of it, I'm going to temporarily un-review this.
>> > From patch-acceptance.rst:
>> > | Additionally, the RISC-V specification allows implementers to create
>> > | their own custom extensions. These custom extensions aren't required
>> > | to go through any review or ratification process by the RISC-V
>> > | Foundation. To avoid the maintenance complexity and potential
>> > | performance impact of adding kernel code for implementor-specific
>> > | RISC-V extensions, we'll only consider patches for extensions that either:
>> > |
>> > | - Have been officially frozen or ratified by the RISC-V Foundation, or
>> > | - Have been implemented in hardware that is widely available, per standard
>> > | Linux practice.
>> >
>> > The xventanacondops bits don't qualify under the first entry, and I
>> > don't think they qualify under the second yet. Am I wrong?
>>
>> The Ventana Veyron V1 was announced in Dec 2022 at RISC-V summit
>> followed by press releases:
>> https://www.ventanamicro.com/ventana-introduces-veyron-worlds-first-data-center-class-risc-v-cpu-product-family/
>> https://www.embedded.com/ventana-reveals-risc-v-cpu-compute-chiplet-for-data-center/
>> https://www.prnewswire.com/news-releases/ventana-introduces-veyron-worlds-first-data-center-class-risc-v-cpu-product-family-301700985.html
>>
>> @Palmer if the above looks good to you then please ack PATCH1-to-4
>
> These are announcements AFAICT & not an indication of "being implemented
> in hardware that is widely available".
The second two look to just be news articles quoting the first without
any real new information, at least just from skimming them -- sorry if I
missed something, though.
The article says "SDK released with necessary software already ported to
Veyron" and "Veyron V1 Development Platform available", but aside from
quotes of the press release I can't find information on either of those
(or anything VT1 related, as there were some naming ambiguities).
Anup said during the call that they're still bringing up the chip and
haven't started sampling yet, which usually means things are far from
publicly availiable. I thought I heard him say that these press
releases would say the chip is sampling 2H23, but I can't find anything
in them about sampling.
Anup also said it's availiable as IP and I remember something at Hot
Chips talking about an example place and route for a VT1, which also
sounds very much like a chip that's not availiable yet -- usually if
there's a chip folks are a lot more concrete about that sort of thing.
So is there you can point to about this chip actually being publicly
availiable?
On Wed, Sep 27, 2023 at 8:31 PM Palmer Dabbelt <[email protected]> wrote:
>
> On Wed, 27 Sep 2023 07:45:28 PDT (-0700), Conor Dooley wrote:
> > On Wed, Sep 27, 2023 at 07:54:49PM +0530, Anup Patel wrote:
> >> On Mon, Sep 25, 2023 at 9:07 PM Conor Dooley <[email protected]> wrote:
> >> >
> >> > On Mon, Sep 25, 2023 at 04:33:15PM +0100, Conor Dooley wrote:
> >> > > On Mon, Sep 25, 2023 at 07:08:50PM +0530, Anup Patel wrote:
> >> > > > This series extends KVM RISC-V to allow Guest/VM discover and use
> >> > > > conditional operations related ISA extensions (namely XVentanaCondOps
> >> > > > and Zicond).
> >> > > >
> >> > > > To try these patches, use KVMTOOL from riscv_zbx_zicntr_smstateen_condops_v1
> >> > > > branch at: https://github.com/avpatel/kvmtool.git
> >> > > >
> >> > > > These patches are based upon the latest riscv_kvm_queue and can also be
> >> > > > found in the riscv_kvm_condops_v2 branch at:
> >> > > > https://github.com/avpatel/linux.git
> >> > > >
> >> > > > Changes since v1:
> >> > > > - Rebased the series on riscv_kvm_queue
> >> > > > - Split PATCH1 and PATCH2 of v1 series into two patches
> >> > > > - Added separate test configs for XVentanaCondOps and Zicond in PATCH7
> >> > > > of v1 series.
> >> > > >
> >> > > > Anup Patel (9):
> >> > > > dt-bindings: riscv: Add XVentanaCondOps extension entry
> >> > > > RISC-V: Detect XVentanaCondOps from ISA string
> >> > > > dt-bindings: riscv: Add Zicond extension entry
> >> > > > RISC-V: Detect Zicond from ISA string
> >> > >
> >> > > For these 4:
> >> > > Reviewed-by: Conor Dooley <[email protected]>
> >> >
> >> > Actually, now that I think of it, I'm going to temporarily un-review this.
> >> > From patch-acceptance.rst:
> >> > | Additionally, the RISC-V specification allows implementers to create
> >> > | their own custom extensions. These custom extensions aren't required
> >> > | to go through any review or ratification process by the RISC-V
> >> > | Foundation. To avoid the maintenance complexity and potential
> >> > | performance impact of adding kernel code for implementor-specific
> >> > | RISC-V extensions, we'll only consider patches for extensions that either:
> >> > |
> >> > | - Have been officially frozen or ratified by the RISC-V Foundation, or
> >> > | - Have been implemented in hardware that is widely available, per standard
> >> > | Linux practice.
> >> >
> >> > The xventanacondops bits don't qualify under the first entry, and I
> >> > don't think they qualify under the second yet. Am I wrong?
> >>
> >> The Ventana Veyron V1 was announced in Dec 2022 at RISC-V summit
> >> followed by press releases:
> >> https://www.ventanamicro.com/ventana-introduces-veyron-worlds-first-data-center-class-risc-v-cpu-product-family/
> >> https://www.embedded.com/ventana-reveals-risc-v-cpu-compute-chiplet-for-data-center/
> >> https://www.prnewswire.com/news-releases/ventana-introduces-veyron-worlds-first-data-center-class-risc-v-cpu-product-family-301700985.html
> >>
> >> @Palmer if the above looks good to you then please ack PATCH1-to-4
> >
> > These are announcements AFAICT & not an indication of "being implemented
> > in hardware that is widely available".
>
> The second two look to just be news articles quoting the first without
> any real new information, at least just from skimming them -- sorry if I
> missed something, though.
>
> The article says "SDK released with necessary software already ported to
> Veyron" and "Veyron V1 Development Platform available", but aside from
> quotes of the press release I can't find information on either of those
> (or anything VT1 related, as there were some naming ambiguities).
>
> Anup said during the call that they're still bringing up the chip and
> haven't started sampling yet, which usually means things are far from
> publicly availiable. I thought I heard him say that these press
> releases would say the chip is sampling 2H23, but I can't find anything
> in them about sampling.
>
> Anup also said it's availiable as IP and I remember something at Hot
> Chips talking about an example place and route for a VT1, which also
> sounds very much like a chip that's not availiable yet -- usually if
> there's a chip folks are a lot more concrete about that sort of thing.
>
> So is there you can point to about this chip actually being publicly
> availiable?
The Veyron V1 chiplet samples are not available publicly at the
moment. Being available as an IP is not the same as chiplet
samples being available.
If this does not satisfy patch acceptance criteria then I will
defer/drop the XVentanaCondOps related patches for now.
Can you ack PATCH2 and PATCH3 which deals with Zicond ?
Regards,
Anup