From: Anup Patel <[email protected]>
This series adds RISC-V CPU Idle support using SBI HSM suspend function.
The RISC-V SBI CPU idle driver added by this series is highly inspired
from the ARM PSCI CPU idle driver.
At high-level, this series includes the following changes:
1) Preparatory arch/riscv patches (Patches 1 to 3)
2) Defines for RISC-V SBI HSM suspend (Patch 4)
3) Preparatory patch to share code between RISC-V SBI CPU idle driver
and ARM PSCI CPU idle driver (Patch 5)
4) RISC-V SBI CPU idle driver and related DT bindings (Patches 6 to 7)
These patches can be found in riscv_sbi_hsm_suspend_v11 branch of
https://github.com/avpatel/linux.git
Special thanks Sandeep Tripathy for providing early feeback on SBI HSM
support in all above projects (RISC-V SBI specification, OpenSBI, and
Linux RISC-V).
Changes since v10:
- Rebased on Linux-5.17-rc3
- Typo fix in commit description of PATCH6
Changes since v9:
- Rebased on Linux-5.17-rc1
Changes since v8:
- Rebased on Linux-5.15-rc5
- Fixed DT schema check errors in PATCH7
Changes since v7:
- Rebased on Linux-5.15-rc3
- Renamed cpuidle-sbi.c to cpuidle-riscv-sbi.c in PATCH6
Changes since v6:
- Fixed error reported by "make DT_CHECKER_FLAGS=-m dt_binding_check"
Changes since v5:
- Rebased on Linux-5.13-rc5
- Removed unnecessary exports from PATCH5
- Removed stray ";" from PATCH5
- Moved sbi_cpuidle_pd_power_off() under "#ifdef CONFIG_DT_IDLE_GENPD"
in PATCH6
Changes since v4:
- Rebased on Linux-5.13-rc2
- Renamed all dt_idle_genpd functions to have "dt_idle_" prefix
- Added MAINTAINERS file entry for dt_idle_genpd
Changes since v3:
- Rebased on Linux-5.13-rc2
- Fixed __cpu_resume_enter() which was broken due to XIP kernel support
- Removed "struct dt_idle_genpd_ops" abstraction which simplifies code
sharing between ARM PSCI and RISC-V SBI drivers in PATCH5
Changes since v2:
- Rebased on Linux-5.12-rc3
- Updated PATCH7 to add common DT bindings for both ARM and RISC-V
idle states
- Added "additionalProperties = false" for both idle-states node and
child nodes in PATCH7
Changes since v1:
- Fixex minor typo in PATCH1
- Use just "idle-states" as DT node name for CPU idle states
- Added documentation for "cpu-idle-states" DT property in
devicetree/bindings/riscv/cpus.yaml
- Added documentation for "riscv,sbi-suspend-param" DT property in
devicetree/bindings/riscv/idle-states.yaml
Anup Patel (8):
RISC-V: Enable CPU_IDLE drivers
RISC-V: Rename relocate() and make it global
RISC-V: Add arch functions for non-retentive suspend entry/exit
RISC-V: Add SBI HSM suspend related defines
cpuidle: Factor-out power domain related code from PSCI domain driver
cpuidle: Add RISC-V SBI CPU idle driver
dt-bindings: Add common bindings for ARM and RISC-V idle states
RISC-V: Enable RISC-V SBI CPU Idle driver for QEMU virt machine
.../bindings/arm/msm/qcom,idle-state.txt | 2 +-
.../devicetree/bindings/arm/psci.yaml | 2 +-
.../bindings/{arm => cpu}/idle-states.yaml | 228 ++++++-
.../devicetree/bindings/riscv/cpus.yaml | 6 +
MAINTAINERS | 14 +
arch/riscv/Kconfig | 7 +
arch/riscv/Kconfig.socs | 3 +
arch/riscv/configs/defconfig | 2 +
arch/riscv/configs/rv32_defconfig | 2 +
arch/riscv/include/asm/asm.h | 27 +
arch/riscv/include/asm/cpuidle.h | 24 +
arch/riscv/include/asm/sbi.h | 27 +-
arch/riscv/include/asm/suspend.h | 36 +
arch/riscv/kernel/Makefile | 2 +
arch/riscv/kernel/asm-offsets.c | 3 +
arch/riscv/kernel/cpu_ops_sbi.c | 2 +-
arch/riscv/kernel/head.S | 28 +-
arch/riscv/kernel/process.c | 3 +-
arch/riscv/kernel/suspend.c | 87 +++
arch/riscv/kernel/suspend_entry.S | 124 ++++
arch/riscv/kvm/vcpu_sbi_hsm.c | 4 +-
drivers/cpuidle/Kconfig | 9 +
drivers/cpuidle/Kconfig.arm | 1 +
drivers/cpuidle/Kconfig.riscv | 15 +
drivers/cpuidle/Makefile | 5 +
drivers/cpuidle/cpuidle-psci-domain.c | 138 +---
drivers/cpuidle/cpuidle-psci.h | 15 +-
drivers/cpuidle/cpuidle-riscv-sbi.c | 627 ++++++++++++++++++
drivers/cpuidle/dt_idle_genpd.c | 178 +++++
drivers/cpuidle/dt_idle_genpd.h | 50 ++
30 files changed, 1484 insertions(+), 187 deletions(-)
rename Documentation/devicetree/bindings/{arm => cpu}/idle-states.yaml (74%)
create mode 100644 arch/riscv/include/asm/cpuidle.h
create mode 100644 arch/riscv/include/asm/suspend.h
create mode 100644 arch/riscv/kernel/suspend.c
create mode 100644 arch/riscv/kernel/suspend_entry.S
create mode 100644 drivers/cpuidle/Kconfig.riscv
create mode 100644 drivers/cpuidle/cpuidle-riscv-sbi.c
create mode 100644 drivers/cpuidle/dt_idle_genpd.c
create mode 100644 drivers/cpuidle/dt_idle_genpd.h
--
2.25.1
From: Anup Patel <[email protected]>
We force select CPU_PM and provide asm/cpuidle.h so that we can
use CPU IDLE drivers for Linux RISC-V kernel.
Signed-off-by: Anup Patel <[email protected]>
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Guo Ren <[email protected]>
---
arch/riscv/Kconfig | 7 +++++++
arch/riscv/configs/defconfig | 1 +
arch/riscv/configs/rv32_defconfig | 1 +
arch/riscv/include/asm/cpuidle.h | 24 ++++++++++++++++++++++++
arch/riscv/kernel/process.c | 3 ++-
5 files changed, 35 insertions(+), 1 deletion(-)
create mode 100644 arch/riscv/include/asm/cpuidle.h
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 5adcbd9b5e88..76976d12b463 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -46,6 +46,7 @@ config RISCV
select CLONE_BACKWARDS
select CLINT_TIMER if !MMU
select COMMON_CLK
+ select CPU_PM if CPU_IDLE
select EDAC_SUPPORT
select GENERIC_ARCH_TOPOLOGY if SMP
select GENERIC_ATOMIC64 if !64BIT
@@ -547,4 +548,10 @@ source "kernel/power/Kconfig"
endmenu
+menu "CPU Power Management"
+
+source "drivers/cpuidle/Kconfig"
+
+endmenu
+
source "arch/riscv/kvm/Kconfig"
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index f120fcc43d0a..a5e0482a4969 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -20,6 +20,7 @@ CONFIG_SOC_SIFIVE=y
CONFIG_SOC_VIRT=y
CONFIG_SMP=y
CONFIG_HOTPLUG_CPU=y
+CONFIG_CPU_IDLE=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=m
CONFIG_JUMP_LABEL=y
diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig
index 8b56a7f1eb06..d1b87db54d68 100644
--- a/arch/riscv/configs/rv32_defconfig
+++ b/arch/riscv/configs/rv32_defconfig
@@ -20,6 +20,7 @@ CONFIG_SOC_VIRT=y
CONFIG_ARCH_RV32I=y
CONFIG_SMP=y
CONFIG_HOTPLUG_CPU=y
+CONFIG_CPU_IDLE=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=m
CONFIG_JUMP_LABEL=y
diff --git a/arch/riscv/include/asm/cpuidle.h b/arch/riscv/include/asm/cpuidle.h
new file mode 100644
index 000000000000..71fdc607d4bc
--- /dev/null
+++ b/arch/riscv/include/asm/cpuidle.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 Allwinner Ltd
+ * Copyright (C) 2021 Western Digital Corporation or its affiliates.
+ */
+
+#ifndef _ASM_RISCV_CPUIDLE_H
+#define _ASM_RISCV_CPUIDLE_H
+
+#include <asm/barrier.h>
+#include <asm/processor.h>
+
+static inline void cpu_do_idle(void)
+{
+ /*
+ * Add mb() here to ensure that all
+ * IO/MEM accesses are completed prior
+ * to entering WFI.
+ */
+ mb();
+ wait_for_interrupt();
+}
+
+#endif
diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c
index 03ac3aa611f5..504b496787aa 100644
--- a/arch/riscv/kernel/process.c
+++ b/arch/riscv/kernel/process.c
@@ -23,6 +23,7 @@
#include <asm/string.h>
#include <asm/switch_to.h>
#include <asm/thread_info.h>
+#include <asm/cpuidle.h>
register unsigned long gp_in_global __asm__("gp");
@@ -37,7 +38,7 @@ extern asmlinkage void ret_from_kernel_thread(void);
void arch_cpu_idle(void)
{
- wait_for_interrupt();
+ cpu_do_idle();
raw_local_irq_enable();
}
--
2.25.1
From: Anup Patel <[email protected]>
We enable RISC-V SBI CPU Idle driver for QEMU virt machine to test
SBI HSM Supend on QEMU.
Signed-off-by: Anup Patel <[email protected]>
Signed-off-by: Anup Patel <[email protected]>
---
arch/riscv/Kconfig.socs | 3 +++
arch/riscv/configs/defconfig | 1 +
arch/riscv/configs/rv32_defconfig | 1 +
3 files changed, 5 insertions(+)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 6ec44a22278a..f4097a815201 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -36,6 +36,9 @@ config SOC_VIRT
select GOLDFISH
select RTC_DRV_GOLDFISH if RTC_CLASS
select SIFIVE_PLIC
+ select PM_GENERIC_DOMAINS if PM
+ select PM_GENERIC_DOMAINS_OF if PM && OF
+ select RISCV_SBI_CPUIDLE if CPU_IDLE
help
This enables support for QEMU Virt Machine.
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index a5e0482a4969..b8c882b70b02 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -20,6 +20,7 @@ CONFIG_SOC_SIFIVE=y
CONFIG_SOC_VIRT=y
CONFIG_SMP=y
CONFIG_HOTPLUG_CPU=y
+CONFIG_PM=y
CONFIG_CPU_IDLE=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=m
diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig
index d1b87db54d68..6f9a7c89bff9 100644
--- a/arch/riscv/configs/rv32_defconfig
+++ b/arch/riscv/configs/rv32_defconfig
@@ -20,6 +20,7 @@ CONFIG_SOC_VIRT=y
CONFIG_ARCH_RV32I=y
CONFIG_SMP=y
CONFIG_HOTPLUG_CPU=y
+CONFIG_PM=y
CONFIG_CPU_IDLE=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=m
--
2.25.1
From: Anup Patel <[email protected]>
The hart registers and CSRs are not preserved in non-retentative
suspend state so we provide arch specific helper functions which
will save/restore hart context upon entry/exit to non-retentive
suspend state. These helper functions can be used by cpuidle
drivers for non-retentive suspend entry/exit.
Signed-off-by: Anup Patel <[email protected]>
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Guo Ren <[email protected]>
---
arch/riscv/include/asm/asm.h | 27 +++++++
arch/riscv/include/asm/suspend.h | 36 +++++++++
arch/riscv/kernel/Makefile | 2 +
arch/riscv/kernel/asm-offsets.c | 3 +
arch/riscv/kernel/head.S | 21 -----
arch/riscv/kernel/suspend.c | 87 +++++++++++++++++++++
arch/riscv/kernel/suspend_entry.S | 124 ++++++++++++++++++++++++++++++
7 files changed, 279 insertions(+), 21 deletions(-)
create mode 100644 arch/riscv/include/asm/suspend.h
create mode 100644 arch/riscv/kernel/suspend.c
create mode 100644 arch/riscv/kernel/suspend_entry.S
diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h
index 618d7c5af1a2..48b4baa4d706 100644
--- a/arch/riscv/include/asm/asm.h
+++ b/arch/riscv/include/asm/asm.h
@@ -67,4 +67,31 @@
#error "Unexpected __SIZEOF_SHORT__"
#endif
+#ifdef __ASSEMBLY__
+
+/* Common assembly source macros */
+
+#ifdef CONFIG_XIP_KERNEL
+.macro XIP_FIXUP_OFFSET reg
+ REG_L t0, _xip_fixup
+ add \reg, \reg, t0
+.endm
+.macro XIP_FIXUP_FLASH_OFFSET reg
+ la t1, __data_loc
+ li t0, XIP_OFFSET_MASK
+ and t1, t1, t0
+ li t1, XIP_OFFSET
+ sub t0, t0, t1
+ sub \reg, \reg, t0
+.endm
+_xip_fixup: .dword CONFIG_PHYS_RAM_BASE - CONFIG_XIP_PHYS_ADDR - XIP_OFFSET
+#else
+.macro XIP_FIXUP_OFFSET reg
+.endm
+.macro XIP_FIXUP_FLASH_OFFSET reg
+.endm
+#endif /* CONFIG_XIP_KERNEL */
+
+#endif /* __ASSEMBLY__ */
+
#endif /* _ASM_RISCV_ASM_H */
diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h
new file mode 100644
index 000000000000..8be391c2aecb
--- /dev/null
+++ b/arch/riscv/include/asm/suspend.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
+ * Copyright (c) 2022 Ventana Micro Systems Inc.
+ */
+
+#ifndef _ASM_RISCV_SUSPEND_H
+#define _ASM_RISCV_SUSPEND_H
+
+#include <asm/ptrace.h>
+
+struct suspend_context {
+ /* Saved and restored by low-level functions */
+ struct pt_regs regs;
+ /* Saved and restored by high-level functions */
+ unsigned long scratch;
+ unsigned long tvec;
+ unsigned long ie;
+#ifdef CONFIG_MMU
+ unsigned long satp;
+#endif
+};
+
+/* Low-level CPU suspend entry function */
+int __cpu_suspend_enter(struct suspend_context *context);
+
+/* High-level CPU suspend which will save context and call finish() */
+int cpu_suspend(unsigned long arg,
+ int (*finish)(unsigned long arg,
+ unsigned long entry,
+ unsigned long context));
+
+/* Low-level CPU resume entry function */
+int __cpu_resume_enter(unsigned long hartid, unsigned long context);
+
+#endif
diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
index 612556faa527..13fa5733f5e7 100644
--- a/arch/riscv/kernel/Makefile
+++ b/arch/riscv/kernel/Makefile
@@ -48,6 +48,8 @@ obj-$(CONFIG_RISCV_BOOT_SPINWAIT) += cpu_ops_spinwait.o
obj-$(CONFIG_MODULES) += module.o
obj-$(CONFIG_MODULE_SECTIONS) += module-sections.o
+obj-$(CONFIG_CPU_PM) += suspend_entry.o suspend.o
+
obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o
obj-$(CONFIG_DYNAMIC_FTRACE) += mcount-dyn.o
diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offsets.c
index df0519a64eaf..df9444397908 100644
--- a/arch/riscv/kernel/asm-offsets.c
+++ b/arch/riscv/kernel/asm-offsets.c
@@ -13,6 +13,7 @@
#include <asm/thread_info.h>
#include <asm/ptrace.h>
#include <asm/cpu_ops_sbi.h>
+#include <asm/suspend.h>
void asm_offsets(void);
@@ -113,6 +114,8 @@ void asm_offsets(void)
OFFSET(PT_BADADDR, pt_regs, badaddr);
OFFSET(PT_CAUSE, pt_regs, cause);
+ OFFSET(SUSPEND_CONTEXT_REGS, suspend_context, regs);
+
OFFSET(KVM_ARCH_GUEST_ZERO, kvm_vcpu_arch, guest_context.zero);
OFFSET(KVM_ARCH_GUEST_RA, kvm_vcpu_arch, guest_context.ra);
OFFSET(KVM_ARCH_GUEST_SP, kvm_vcpu_arch, guest_context.sp);
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 5f4c6b6c4974..893b8bb69391 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -16,27 +16,6 @@
#include <asm/image.h>
#include "efi-header.S"
-#ifdef CONFIG_XIP_KERNEL
-.macro XIP_FIXUP_OFFSET reg
- REG_L t0, _xip_fixup
- add \reg, \reg, t0
-.endm
-.macro XIP_FIXUP_FLASH_OFFSET reg
- la t1, __data_loc
- li t0, XIP_OFFSET_MASK
- and t1, t1, t0
- li t1, XIP_OFFSET
- sub t0, t0, t1
- sub \reg, \reg, t0
-.endm
-_xip_fixup: .dword CONFIG_PHYS_RAM_BASE - CONFIG_XIP_PHYS_ADDR - XIP_OFFSET
-#else
-.macro XIP_FIXUP_OFFSET reg
-.endm
-.macro XIP_FIXUP_FLASH_OFFSET reg
-.endm
-#endif /* CONFIG_XIP_KERNEL */
-
__HEAD
ENTRY(_start)
/*
diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c
new file mode 100644
index 000000000000..9ba24fb8cc93
--- /dev/null
+++ b/arch/riscv/kernel/suspend.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
+ * Copyright (c) 2022 Ventana Micro Systems Inc.
+ */
+
+#include <linux/ftrace.h>
+#include <asm/csr.h>
+#include <asm/suspend.h>
+
+static void suspend_save_csrs(struct suspend_context *context)
+{
+ context->scratch = csr_read(CSR_SCRATCH);
+ context->tvec = csr_read(CSR_TVEC);
+ context->ie = csr_read(CSR_IE);
+
+ /*
+ * No need to save/restore IP CSR (i.e. MIP or SIP) because:
+ *
+ * 1. For no-MMU (M-mode) kernel, the bits in MIP are set by
+ * external devices (such as interrupt controller, timer, etc).
+ * 2. For MMU (S-mode) kernel, the bits in SIP are set by
+ * M-mode firmware and external devices (such as interrupt
+ * controller, etc).
+ */
+
+#ifdef CONFIG_MMU
+ context->satp = csr_read(CSR_SATP);
+#endif
+}
+
+static void suspend_restore_csrs(struct suspend_context *context)
+{
+ csr_write(CSR_SCRATCH, context->scratch);
+ csr_write(CSR_TVEC, context->tvec);
+ csr_write(CSR_IE, context->ie);
+
+#ifdef CONFIG_MMU
+ csr_write(CSR_SATP, context->satp);
+#endif
+}
+
+int cpu_suspend(unsigned long arg,
+ int (*finish)(unsigned long arg,
+ unsigned long entry,
+ unsigned long context))
+{
+ int rc = 0;
+ struct suspend_context context = { 0 };
+
+ /* Finisher should be non-NULL */
+ if (!finish)
+ return -EINVAL;
+
+ /* Save additional CSRs*/
+ suspend_save_csrs(&context);
+
+ /*
+ * Function graph tracer state gets incosistent when the kernel
+ * calls functions that never return (aka finishers) hence disable
+ * graph tracing during their execution.
+ */
+ pause_graph_tracing();
+
+ /* Save context on stack */
+ if (__cpu_suspend_enter(&context)) {
+ /* Call the finisher */
+ rc = finish(arg, __pa_symbol(__cpu_resume_enter),
+ (ulong)&context);
+
+ /*
+ * Should never reach here, unless the suspend finisher
+ * fails. Successful cpu_suspend() should return from
+ * __cpu_resume_entry()
+ */
+ if (!rc)
+ rc = -EOPNOTSUPP;
+ }
+
+ /* Enable function graph tracer */
+ unpause_graph_tracing();
+
+ /* Restore additional CSRs */
+ suspend_restore_csrs(&context);
+
+ return rc;
+}
diff --git a/arch/riscv/kernel/suspend_entry.S b/arch/riscv/kernel/suspend_entry.S
new file mode 100644
index 000000000000..4b07b809a2b8
--- /dev/null
+++ b/arch/riscv/kernel/suspend_entry.S
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
+ * Copyright (c) 2022 Ventana Micro Systems Inc.
+ */
+
+#include <linux/linkage.h>
+#include <asm/asm.h>
+#include <asm/asm-offsets.h>
+#include <asm/csr.h>
+
+ .text
+ .altmacro
+ .option norelax
+
+ENTRY(__cpu_suspend_enter)
+ /* Save registers (except A0 and T0-T6) */
+ REG_S ra, (SUSPEND_CONTEXT_REGS + PT_RA)(a0)
+ REG_S sp, (SUSPEND_CONTEXT_REGS + PT_SP)(a0)
+ REG_S gp, (SUSPEND_CONTEXT_REGS + PT_GP)(a0)
+ REG_S tp, (SUSPEND_CONTEXT_REGS + PT_TP)(a0)
+ REG_S s0, (SUSPEND_CONTEXT_REGS + PT_S0)(a0)
+ REG_S s1, (SUSPEND_CONTEXT_REGS + PT_S1)(a0)
+ REG_S a1, (SUSPEND_CONTEXT_REGS + PT_A1)(a0)
+ REG_S a2, (SUSPEND_CONTEXT_REGS + PT_A2)(a0)
+ REG_S a3, (SUSPEND_CONTEXT_REGS + PT_A3)(a0)
+ REG_S a4, (SUSPEND_CONTEXT_REGS + PT_A4)(a0)
+ REG_S a5, (SUSPEND_CONTEXT_REGS + PT_A5)(a0)
+ REG_S a6, (SUSPEND_CONTEXT_REGS + PT_A6)(a0)
+ REG_S a7, (SUSPEND_CONTEXT_REGS + PT_A7)(a0)
+ REG_S s2, (SUSPEND_CONTEXT_REGS + PT_S2)(a0)
+ REG_S s3, (SUSPEND_CONTEXT_REGS + PT_S3)(a0)
+ REG_S s4, (SUSPEND_CONTEXT_REGS + PT_S4)(a0)
+ REG_S s5, (SUSPEND_CONTEXT_REGS + PT_S5)(a0)
+ REG_S s6, (SUSPEND_CONTEXT_REGS + PT_S6)(a0)
+ REG_S s7, (SUSPEND_CONTEXT_REGS + PT_S7)(a0)
+ REG_S s8, (SUSPEND_CONTEXT_REGS + PT_S8)(a0)
+ REG_S s9, (SUSPEND_CONTEXT_REGS + PT_S9)(a0)
+ REG_S s10, (SUSPEND_CONTEXT_REGS + PT_S10)(a0)
+ REG_S s11, (SUSPEND_CONTEXT_REGS + PT_S11)(a0)
+
+ /* Save CSRs */
+ csrr t0, CSR_EPC
+ REG_S t0, (SUSPEND_CONTEXT_REGS + PT_EPC)(a0)
+ csrr t0, CSR_STATUS
+ REG_S t0, (SUSPEND_CONTEXT_REGS + PT_STATUS)(a0)
+ csrr t0, CSR_TVAL
+ REG_S t0, (SUSPEND_CONTEXT_REGS + PT_BADADDR)(a0)
+ csrr t0, CSR_CAUSE
+ REG_S t0, (SUSPEND_CONTEXT_REGS + PT_CAUSE)(a0)
+
+ /* Return non-zero value */
+ li a0, 1
+
+ /* Return to C code */
+ ret
+END(__cpu_suspend_enter)
+
+ENTRY(__cpu_resume_enter)
+ /* Load the global pointer */
+ .option push
+ .option norelax
+ la gp, __global_pointer$
+ .option pop
+
+#ifdef CONFIG_MMU
+ /* Save A0 and A1 */
+ add t0, a0, zero
+ add t1, a1, zero
+
+ /* Enable MMU */
+ la a0, swapper_pg_dir
+ XIP_FIXUP_OFFSET a0
+ call relocate_enable_mmu
+
+ /* Restore A0 and A1 */
+ add a0, t0, zero
+ add a1, t1, zero
+#endif
+
+ /* Make A0 point to suspend context */
+ add a0, a1, zero
+
+ /* Restore CSRs */
+ REG_L t0, (SUSPEND_CONTEXT_REGS + PT_EPC)(a0)
+ csrw CSR_EPC, t0
+ REG_L t0, (SUSPEND_CONTEXT_REGS + PT_STATUS)(a0)
+ csrw CSR_STATUS, t0
+ REG_L t0, (SUSPEND_CONTEXT_REGS + PT_BADADDR)(a0)
+ csrw CSR_TVAL, t0
+ REG_L t0, (SUSPEND_CONTEXT_REGS + PT_CAUSE)(a0)
+ csrw CSR_CAUSE, t0
+
+ /* Restore registers (except A0 and T0-T6) */
+ REG_L ra, (SUSPEND_CONTEXT_REGS + PT_RA)(a0)
+ REG_L sp, (SUSPEND_CONTEXT_REGS + PT_SP)(a0)
+ REG_L gp, (SUSPEND_CONTEXT_REGS + PT_GP)(a0)
+ REG_L tp, (SUSPEND_CONTEXT_REGS + PT_TP)(a0)
+ REG_L s0, (SUSPEND_CONTEXT_REGS + PT_S0)(a0)
+ REG_L s1, (SUSPEND_CONTEXT_REGS + PT_S1)(a0)
+ REG_L a1, (SUSPEND_CONTEXT_REGS + PT_A1)(a0)
+ REG_L a2, (SUSPEND_CONTEXT_REGS + PT_A2)(a0)
+ REG_L a3, (SUSPEND_CONTEXT_REGS + PT_A3)(a0)
+ REG_L a4, (SUSPEND_CONTEXT_REGS + PT_A4)(a0)
+ REG_L a5, (SUSPEND_CONTEXT_REGS + PT_A5)(a0)
+ REG_L a6, (SUSPEND_CONTEXT_REGS + PT_A6)(a0)
+ REG_L a7, (SUSPEND_CONTEXT_REGS + PT_A7)(a0)
+ REG_L s2, (SUSPEND_CONTEXT_REGS + PT_S2)(a0)
+ REG_L s3, (SUSPEND_CONTEXT_REGS + PT_S3)(a0)
+ REG_L s4, (SUSPEND_CONTEXT_REGS + PT_S4)(a0)
+ REG_L s5, (SUSPEND_CONTEXT_REGS + PT_S5)(a0)
+ REG_L s6, (SUSPEND_CONTEXT_REGS + PT_S6)(a0)
+ REG_L s7, (SUSPEND_CONTEXT_REGS + PT_S7)(a0)
+ REG_L s8, (SUSPEND_CONTEXT_REGS + PT_S8)(a0)
+ REG_L s9, (SUSPEND_CONTEXT_REGS + PT_S9)(a0)
+ REG_L s10, (SUSPEND_CONTEXT_REGS + PT_S10)(a0)
+ REG_L s11, (SUSPEND_CONTEXT_REGS + PT_S11)(a0)
+
+ /* Return zero value */
+ add a0, zero, zero
+
+ /* Return to C code */
+ ret
+END(__cpu_resume_enter)
--
2.25.1
From: Anup Patel <[email protected]>
The low-level relocate() function enables mmu and relocates
execution to link-time addresses. We rename relocate() function
to relocate_enable_mmu() function which is more informative.
Also, the relocate_enable_mmu() function will be used in the
resume path when a CPU wakes-up from a non-retentive suspend
so we make it global symbol.
Signed-off-by: Anup Patel <[email protected]>
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Guo Ren <[email protected]>
---
arch/riscv/kernel/head.S | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 2363b43312fc..5f4c6b6c4974 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -90,7 +90,8 @@ pe_head_start:
.align 2
#ifdef CONFIG_MMU
-relocate:
+ .global relocate_enable_mmu
+relocate_enable_mmu:
/* Relocate return address */
la a1, kernel_map
XIP_FIXUP_OFFSET a1
@@ -185,7 +186,7 @@ secondary_start_sbi:
/* Enable virtual memory and relocate to virtual address */
la a0, swapper_pg_dir
XIP_FIXUP_OFFSET a0
- call relocate
+ call relocate_enable_mmu
#endif
call setup_trap_vector
tail smp_callin
@@ -329,7 +330,7 @@ clear_bss_done:
#ifdef CONFIG_MMU
la a0, early_pg_dir
XIP_FIXUP_OFFSET a0
- call relocate
+ call relocate_enable_mmu
#endif /* CONFIG_MMU */
call setup_trap_vector
--
2.25.1
Hi!
> From: Anup Patel <[email protected]>
>
> We force select CPU_PM and provide asm/cpuidle.h so that we can
> use CPU IDLE drivers for Linux RISC-V kernel.
>
> Signed-off-by: Anup Patel <[email protected]>
> Signed-off-by: Anup Patel <[email protected]>
This is quite... interesting. Normally we have one signoff per
person...
Best regards,
Pavel
--
http://www.livejournal.com/~pavelmachek
On Sat, Feb 12, 2022 at 5:13 PM Pavel Machek <[email protected]> wrote:
>
> Hi!
>
> > From: Anup Patel <[email protected]>
> >
> > We force select CPU_PM and provide asm/cpuidle.h so that we can
> > use CPU IDLE drivers for Linux RISC-V kernel.
> >
> > Signed-off-by: Anup Patel <[email protected]>
> > Signed-off-by: Anup Patel <[email protected]>
>
> This is quite... interesting. Normally we have one signoff per
> person...
I was working for Western Digital (WDC) when I first submitted this
series and recently I joined Ventana Micro Systems.
Regards,
Anup
>
> Best regards,
> Pavel
> --
> http://www.livejournal.com/~pavelmachek
On Wed, Feb 9, 2022 at 9:50 PM Anup Patel <[email protected]> wrote:
>
> From: Anup Patel <[email protected]>
>
> The low-level relocate() function enables mmu and relocates
> execution to link-time addresses. We rename relocate() function
> to relocate_enable_mmu() function which is more informative.
>
> Also, the relocate_enable_mmu() function will be used in the
> resume path when a CPU wakes-up from a non-retentive suspend
> so we make it global symbol.
>
> Signed-off-by: Anup Patel <[email protected]>
> Signed-off-by: Anup Patel <[email protected]>
> Reviewed-by: Guo Ren <[email protected]>
> ---
> arch/riscv/kernel/head.S | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index 2363b43312fc..5f4c6b6c4974 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -90,7 +90,8 @@ pe_head_start:
>
> .align 2
> #ifdef CONFIG_MMU
> -relocate:
> + .global relocate_enable_mmu
> +relocate_enable_mmu:
> /* Relocate return address */
> la a1, kernel_map
> XIP_FIXUP_OFFSET a1
> @@ -185,7 +186,7 @@ secondary_start_sbi:
> /* Enable virtual memory and relocate to virtual address */
> la a0, swapper_pg_dir
> XIP_FIXUP_OFFSET a0
> - call relocate
> + call relocate_enable_mmu
> #endif
> call setup_trap_vector
> tail smp_callin
> @@ -329,7 +330,7 @@ clear_bss_done:
> #ifdef CONFIG_MMU
> la a0, early_pg_dir
> XIP_FIXUP_OFFSET a0
> - call relocate
> + call relocate_enable_mmu
> #endif /* CONFIG_MMU */
>
> call setup_trap_vector
> --
> 2.25.1
>
Reviewed-by: Atish Patra <[email protected]>
--
Regards,
Atish
On Wed, Feb 9, 2022 at 9:50 PM Anup Patel <[email protected]> wrote:
>
> From: Anup Patel <[email protected]>
>
> We force select CPU_PM and provide asm/cpuidle.h so that we can
> use CPU IDLE drivers for Linux RISC-V kernel.
>
> Signed-off-by: Anup Patel <[email protected]>
> Signed-off-by: Anup Patel <[email protected]>
> Reviewed-by: Guo Ren <[email protected]>
> ---
> arch/riscv/Kconfig | 7 +++++++
> arch/riscv/configs/defconfig | 1 +
> arch/riscv/configs/rv32_defconfig | 1 +
> arch/riscv/include/asm/cpuidle.h | 24 ++++++++++++++++++++++++
> arch/riscv/kernel/process.c | 3 ++-
> 5 files changed, 35 insertions(+), 1 deletion(-)
> create mode 100644 arch/riscv/include/asm/cpuidle.h
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 5adcbd9b5e88..76976d12b463 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -46,6 +46,7 @@ config RISCV
> select CLONE_BACKWARDS
> select CLINT_TIMER if !MMU
> select COMMON_CLK
> + select CPU_PM if CPU_IDLE
> select EDAC_SUPPORT
> select GENERIC_ARCH_TOPOLOGY if SMP
> select GENERIC_ATOMIC64 if !64BIT
> @@ -547,4 +548,10 @@ source "kernel/power/Kconfig"
>
> endmenu
>
> +menu "CPU Power Management"
> +
> +source "drivers/cpuidle/Kconfig"
> +
> +endmenu
> +
> source "arch/riscv/kvm/Kconfig"
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index f120fcc43d0a..a5e0482a4969 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -20,6 +20,7 @@ CONFIG_SOC_SIFIVE=y
> CONFIG_SOC_VIRT=y
> CONFIG_SMP=y
> CONFIG_HOTPLUG_CPU=y
> +CONFIG_CPU_IDLE=y
> CONFIG_VIRTUALIZATION=y
> CONFIG_KVM=m
> CONFIG_JUMP_LABEL=y
> diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig
> index 8b56a7f1eb06..d1b87db54d68 100644
> --- a/arch/riscv/configs/rv32_defconfig
> +++ b/arch/riscv/configs/rv32_defconfig
> @@ -20,6 +20,7 @@ CONFIG_SOC_VIRT=y
> CONFIG_ARCH_RV32I=y
> CONFIG_SMP=y
> CONFIG_HOTPLUG_CPU=y
> +CONFIG_CPU_IDLE=y
> CONFIG_VIRTUALIZATION=y
> CONFIG_KVM=m
> CONFIG_JUMP_LABEL=y
> diff --git a/arch/riscv/include/asm/cpuidle.h b/arch/riscv/include/asm/cpuidle.h
> new file mode 100644
> index 000000000000..71fdc607d4bc
> --- /dev/null
> +++ b/arch/riscv/include/asm/cpuidle.h
> @@ -0,0 +1,24 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2021 Allwinner Ltd
> + * Copyright (C) 2021 Western Digital Corporation or its affiliates.
> + */
> +
> +#ifndef _ASM_RISCV_CPUIDLE_H
> +#define _ASM_RISCV_CPUIDLE_H
> +
> +#include <asm/barrier.h>
> +#include <asm/processor.h>
> +
> +static inline void cpu_do_idle(void)
> +{
> + /*
> + * Add mb() here to ensure that all
> + * IO/MEM accesses are completed prior
> + * to entering WFI.
> + */
> + mb();
> + wait_for_interrupt();
> +}
> +
> +#endif
> diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c
> index 03ac3aa611f5..504b496787aa 100644
> --- a/arch/riscv/kernel/process.c
> +++ b/arch/riscv/kernel/process.c
> @@ -23,6 +23,7 @@
> #include <asm/string.h>
> #include <asm/switch_to.h>
> #include <asm/thread_info.h>
> +#include <asm/cpuidle.h>
>
> register unsigned long gp_in_global __asm__("gp");
>
> @@ -37,7 +38,7 @@ extern asmlinkage void ret_from_kernel_thread(void);
>
> void arch_cpu_idle(void)
> {
> - wait_for_interrupt();
> + cpu_do_idle();
> raw_local_irq_enable();
> }
>
> --
> 2.25.1
>
Reviewed-by: Atish Patra <[email protected]>
--
Regards,
Atish
On Sat, 12 Feb 2022 04:49:46 PST (-0800), [email protected] wrote:
> On Sat, Feb 12, 2022 at 5:13 PM Pavel Machek <[email protected]> wrote:
>>
>> Hi!
>>
>> > From: Anup Patel <[email protected]>
>> >
>> > We force select CPU_PM and provide asm/cpuidle.h so that we can
>> > use CPU IDLE drivers for Linux RISC-V kernel.
>> >
>> > Signed-off-by: Anup Patel <[email protected]>
>> > Signed-off-by: Anup Patel <[email protected]>
>>
>> This is quite... interesting. Normally we have one signoff per
>> person...
>
> I was working for Western Digital (WDC) when I first submitted this
> series and recently I joined Ventana Micro Systems.
IIUC that's the correct way to go about this, it's certainly what I'd
do.
>
> Regards,
> Anup
>
>>
>> Best regards,
>> Pavel
>> --
>> http://www.livejournal.com/~pavelmachek
On Wed, 09 Feb 2022 21:49:39 PST (-0800), [email protected] wrote:
> From: Anup Patel <[email protected]>
>
> This series adds RISC-V CPU Idle support using SBI HSM suspend function.
> The RISC-V SBI CPU idle driver added by this series is highly inspired
> from the ARM PSCI CPU idle driver.
>
> At high-level, this series includes the following changes:
> 1) Preparatory arch/riscv patches (Patches 1 to 3)
> 2) Defines for RISC-V SBI HSM suspend (Patch 4)
> 3) Preparatory patch to share code between RISC-V SBI CPU idle driver
> and ARM PSCI CPU idle driver (Patch 5)
> 4) RISC-V SBI CPU idle driver and related DT bindings (Patches 6 to 7)
>
> These patches can be found in riscv_sbi_hsm_suspend_v11 branch of
> https://github.com/avpatel/linux.git
>
> Special thanks Sandeep Tripathy for providing early feeback on SBI HSM
> support in all above projects (RISC-V SBI specification, OpenSBI, and
> Linux RISC-V).
>
> Changes since v10:
> - Rebased on Linux-5.17-rc3
> - Typo fix in commit description of PATCH6
>
> Changes since v9:
> - Rebased on Linux-5.17-rc1
>
> Changes since v8:
> - Rebased on Linux-5.15-rc5
> - Fixed DT schema check errors in PATCH7
>
> Changes since v7:
> - Rebased on Linux-5.15-rc3
> - Renamed cpuidle-sbi.c to cpuidle-riscv-sbi.c in PATCH6
>
> Changes since v6:
> - Fixed error reported by "make DT_CHECKER_FLAGS=-m dt_binding_check"
>
> Changes since v5:
> - Rebased on Linux-5.13-rc5
> - Removed unnecessary exports from PATCH5
> - Removed stray ";" from PATCH5
> - Moved sbi_cpuidle_pd_power_off() under "#ifdef CONFIG_DT_IDLE_GENPD"
> in PATCH6
>
> Changes since v4:
> - Rebased on Linux-5.13-rc2
> - Renamed all dt_idle_genpd functions to have "dt_idle_" prefix
> - Added MAINTAINERS file entry for dt_idle_genpd
>
> Changes since v3:
> - Rebased on Linux-5.13-rc2
> - Fixed __cpu_resume_enter() which was broken due to XIP kernel support
> - Removed "struct dt_idle_genpd_ops" abstraction which simplifies code
> sharing between ARM PSCI and RISC-V SBI drivers in PATCH5
>
> Changes since v2:
> - Rebased on Linux-5.12-rc3
> - Updated PATCH7 to add common DT bindings for both ARM and RISC-V
> idle states
> - Added "additionalProperties = false" for both idle-states node and
> child nodes in PATCH7
>
> Changes since v1:
> - Fixex minor typo in PATCH1
> - Use just "idle-states" as DT node name for CPU idle states
> - Added documentation for "cpu-idle-states" DT property in
> devicetree/bindings/riscv/cpus.yaml
> - Added documentation for "riscv,sbi-suspend-param" DT property in
> devicetree/bindings/riscv/idle-states.yaml
>
> Anup Patel (8):
> RISC-V: Enable CPU_IDLE drivers
> RISC-V: Rename relocate() and make it global
> RISC-V: Add arch functions for non-retentive suspend entry/exit
> RISC-V: Add SBI HSM suspend related defines
> cpuidle: Factor-out power domain related code from PSCI domain driver
> cpuidle: Add RISC-V SBI CPU idle driver
> dt-bindings: Add common bindings for ARM and RISC-V idle states
> RISC-V: Enable RISC-V SBI CPU Idle driver for QEMU virt machine
>
> .../bindings/arm/msm/qcom,idle-state.txt | 2 +-
> .../devicetree/bindings/arm/psci.yaml | 2 +-
> .../bindings/{arm => cpu}/idle-states.yaml | 228 ++++++-
> .../devicetree/bindings/riscv/cpus.yaml | 6 +
> MAINTAINERS | 14 +
> arch/riscv/Kconfig | 7 +
> arch/riscv/Kconfig.socs | 3 +
> arch/riscv/configs/defconfig | 2 +
> arch/riscv/configs/rv32_defconfig | 2 +
> arch/riscv/include/asm/asm.h | 27 +
> arch/riscv/include/asm/cpuidle.h | 24 +
> arch/riscv/include/asm/sbi.h | 27 +-
> arch/riscv/include/asm/suspend.h | 36 +
> arch/riscv/kernel/Makefile | 2 +
> arch/riscv/kernel/asm-offsets.c | 3 +
> arch/riscv/kernel/cpu_ops_sbi.c | 2 +-
> arch/riscv/kernel/head.S | 28 +-
> arch/riscv/kernel/process.c | 3 +-
> arch/riscv/kernel/suspend.c | 87 +++
> arch/riscv/kernel/suspend_entry.S | 124 ++++
> arch/riscv/kvm/vcpu_sbi_hsm.c | 4 +-
> drivers/cpuidle/Kconfig | 9 +
> drivers/cpuidle/Kconfig.arm | 1 +
> drivers/cpuidle/Kconfig.riscv | 15 +
> drivers/cpuidle/Makefile | 5 +
> drivers/cpuidle/cpuidle-psci-domain.c | 138 +---
> drivers/cpuidle/cpuidle-psci.h | 15 +-
> drivers/cpuidle/cpuidle-riscv-sbi.c | 627 ++++++++++++++++++
> drivers/cpuidle/dt_idle_genpd.c | 178 +++++
> drivers/cpuidle/dt_idle_genpd.h | 50 ++
> 30 files changed, 1484 insertions(+), 187 deletions(-)
> rename Documentation/devicetree/bindings/{arm => cpu}/idle-states.yaml (74%)
> create mode 100644 arch/riscv/include/asm/cpuidle.h
> create mode 100644 arch/riscv/include/asm/suspend.h
> create mode 100644 arch/riscv/kernel/suspend.c
> create mode 100644 arch/riscv/kernel/suspend_entry.S
> create mode 100644 drivers/cpuidle/Kconfig.riscv
> create mode 100644 drivers/cpuidle/cpuidle-riscv-sbi.c
> create mode 100644 drivers/cpuidle/dt_idle_genpd.c
> create mode 100644 drivers/cpuidle/dt_idle_genpd.h
Thanks, these are on for-next.
On Wed, Mar 30, 2022 at 7:16 PM Palmer Dabbelt <[email protected]> wrote:
>
> On Wed, 09 Feb 2022 21:49:39 PST (-0800), [email protected] wrote:
> > From: Anup Patel <[email protected]>
> >
> > This series adds RISC-V CPU Idle support using SBI HSM suspend function.
> > The RISC-V SBI CPU idle driver added by this series is highly inspired
> > from the ARM PSCI CPU idle driver.
> >
> > At high-level, this series includes the following changes:
> > 1) Preparatory arch/riscv patches (Patches 1 to 3)
> > 2) Defines for RISC-V SBI HSM suspend (Patch 4)
> > 3) Preparatory patch to share code between RISC-V SBI CPU idle driver
> > and ARM PSCI CPU idle driver (Patch 5)
> > 4) RISC-V SBI CPU idle driver and related DT bindings (Patches 6 to 7)
> >
> > These patches can be found in riscv_sbi_hsm_suspend_v11 branch of
> > https://github.com/avpatel/linux.git
> >
> > Special thanks Sandeep Tripathy for providing early feeback on SBI HSM
> > support in all above projects (RISC-V SBI specification, OpenSBI, and
> > Linux RISC-V).
> >
> > Changes since v10:
> > - Rebased on Linux-5.17-rc3
> > - Typo fix in commit description of PATCH6
> >
> > Changes since v9:
> > - Rebased on Linux-5.17-rc1
> >
> > Changes since v8:
> > - Rebased on Linux-5.15-rc5
> > - Fixed DT schema check errors in PATCH7
> >
> > Changes since v7:
> > - Rebased on Linux-5.15-rc3
> > - Renamed cpuidle-sbi.c to cpuidle-riscv-sbi.c in PATCH6
> >
> > Changes since v6:
> > - Fixed error reported by "make DT_CHECKER_FLAGS=-m dt_binding_check"
> >
> > Changes since v5:
> > - Rebased on Linux-5.13-rc5
> > - Removed unnecessary exports from PATCH5
> > - Removed stray ";" from PATCH5
> > - Moved sbi_cpuidle_pd_power_off() under "#ifdef CONFIG_DT_IDLE_GENPD"
> > in PATCH6
> >
> > Changes since v4:
> > - Rebased on Linux-5.13-rc2
> > - Renamed all dt_idle_genpd functions to have "dt_idle_" prefix
> > - Added MAINTAINERS file entry for dt_idle_genpd
> >
> > Changes since v3:
> > - Rebased on Linux-5.13-rc2
> > - Fixed __cpu_resume_enter() which was broken due to XIP kernel support
> > - Removed "struct dt_idle_genpd_ops" abstraction which simplifies code
> > sharing between ARM PSCI and RISC-V SBI drivers in PATCH5
> >
> > Changes since v2:
> > - Rebased on Linux-5.12-rc3
> > - Updated PATCH7 to add common DT bindings for both ARM and RISC-V
> > idle states
> > - Added "additionalProperties = false" for both idle-states node and
> > child nodes in PATCH7
> >
> > Changes since v1:
> > - Fixex minor typo in PATCH1
> > - Use just "idle-states" as DT node name for CPU idle states
> > - Added documentation for "cpu-idle-states" DT property in
> > devicetree/bindings/riscv/cpus.yaml
> > - Added documentation for "riscv,sbi-suspend-param" DT property in
> > devicetree/bindings/riscv/idle-states.yaml
> >
> > Anup Patel (8):
> > RISC-V: Enable CPU_IDLE drivers
> > RISC-V: Rename relocate() and make it global
> > RISC-V: Add arch functions for non-retentive suspend entry/exit
> > RISC-V: Add SBI HSM suspend related defines
> > cpuidle: Factor-out power domain related code from PSCI domain driver
> > cpuidle: Add RISC-V SBI CPU idle driver
> > dt-bindings: Add common bindings for ARM and RISC-V idle states
> > RISC-V: Enable RISC-V SBI CPU Idle driver for QEMU virt machine
> >
> > .../bindings/arm/msm/qcom,idle-state.txt | 2 +-
> > .../devicetree/bindings/arm/psci.yaml | 2 +-
> > .../bindings/{arm => cpu}/idle-states.yaml | 228 ++++++-
> > .../devicetree/bindings/riscv/cpus.yaml | 6 +
> > MAINTAINERS | 14 +
> > arch/riscv/Kconfig | 7 +
> > arch/riscv/Kconfig.socs | 3 +
> > arch/riscv/configs/defconfig | 2 +
> > arch/riscv/configs/rv32_defconfig | 2 +
> > arch/riscv/include/asm/asm.h | 27 +
> > arch/riscv/include/asm/cpuidle.h | 24 +
> > arch/riscv/include/asm/sbi.h | 27 +-
> > arch/riscv/include/asm/suspend.h | 36 +
> > arch/riscv/kernel/Makefile | 2 +
> > arch/riscv/kernel/asm-offsets.c | 3 +
> > arch/riscv/kernel/cpu_ops_sbi.c | 2 +-
> > arch/riscv/kernel/head.S | 28 +-
> > arch/riscv/kernel/process.c | 3 +-
> > arch/riscv/kernel/suspend.c | 87 +++
> > arch/riscv/kernel/suspend_entry.S | 124 ++++
> > arch/riscv/kvm/vcpu_sbi_hsm.c | 4 +-
> > drivers/cpuidle/Kconfig | 9 +
> > drivers/cpuidle/Kconfig.arm | 1 +
> > drivers/cpuidle/Kconfig.riscv | 15 +
> > drivers/cpuidle/Makefile | 5 +
> > drivers/cpuidle/cpuidle-psci-domain.c | 138 +---
> > drivers/cpuidle/cpuidle-psci.h | 15 +-
> > drivers/cpuidle/cpuidle-riscv-sbi.c | 627 ++++++++++++++++++
> > drivers/cpuidle/dt_idle_genpd.c | 178 +++++
> > drivers/cpuidle/dt_idle_genpd.h | 50 ++
> > 30 files changed, 1484 insertions(+), 187 deletions(-)
> > rename Documentation/devicetree/bindings/{arm => cpu}/idle-states.yaml (74%)
> > create mode 100644 arch/riscv/include/asm/cpuidle.h
> > create mode 100644 arch/riscv/include/asm/suspend.h
> > create mode 100644 arch/riscv/kernel/suspend.c
> > create mode 100644 arch/riscv/kernel/suspend_entry.S
> > create mode 100644 drivers/cpuidle/Kconfig.riscv
> > create mode 100644 drivers/cpuidle/cpuidle-riscv-sbi.c
> > create mode 100644 drivers/cpuidle/dt_idle_genpd.c
> > create mode 100644 drivers/cpuidle/dt_idle_genpd.h
>
> Thanks, these are on for-next.
For 5.18? You are not supposed to put new material into linux-next
during the merge window.
In any case, this now cause warnings on 'cpu-idle-states':
/builds/robherring/linux-dt/Documentation/devicetree/bindings/cpu/idle-states.example.dtb:
cpu@0: cpu-idle-states:0: [1, 2, 3, 4] is too long
From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/arm/cpus.yaml
/builds/robherring/linux-dt/Documentation/devicetree/bindings/cpu/idle-states.example.dtb:
cpu@1: cpu-idle-states:0: [1, 2, 3, 4] is too long
From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/arm/cpus.yaml
/builds/robherring/linux-dt/Documentation/devicetree/bindings/cpu/idle-states.example.dtb:
cpu@100: cpu-idle-states:0: [1, 2, 3, 4] is too long
From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/arm/cpus.yaml
/builds/robherring/linux-dt/Documentation/devicetree/bindings/cpu/idle-states.example.dtb:
cpu@101: cpu-idle-states:0: [1, 2, 3, 4] is too long
From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/arm/cpus.yaml
See commit 39bd2b6a3783 ("dt-bindings: Improve phandle-array schemas")
for how to fix.
Rob
On Fri, 01 Apr 2022 11:13:32 PDT (-0700), [email protected] wrote:
> On Wed, Mar 30, 2022 at 7:16 PM Palmer Dabbelt <[email protected]> wrote:
>>
>> On Wed, 09 Feb 2022 21:49:39 PST (-0800), [email protected] wrote:
>> > From: Anup Patel <[email protected]>
>> >
>> > This series adds RISC-V CPU Idle support using SBI HSM suspend function.
>> > The RISC-V SBI CPU idle driver added by this series is highly inspired
>> > from the ARM PSCI CPU idle driver.
>> >
>> > At high-level, this series includes the following changes:
>> > 1) Preparatory arch/riscv patches (Patches 1 to 3)
>> > 2) Defines for RISC-V SBI HSM suspend (Patch 4)
>> > 3) Preparatory patch to share code between RISC-V SBI CPU idle driver
>> > and ARM PSCI CPU idle driver (Patch 5)
>> > 4) RISC-V SBI CPU idle driver and related DT bindings (Patches 6 to 7)
>> >
>> > These patches can be found in riscv_sbi_hsm_suspend_v11 branch of
>> > https://github.com/avpatel/linux.git
>> >
>> > Special thanks Sandeep Tripathy for providing early feeback on SBI HSM
>> > support in all above projects (RISC-V SBI specification, OpenSBI, and
>> > Linux RISC-V).
>> >
>> > Changes since v10:
>> > - Rebased on Linux-5.17-rc3
>> > - Typo fix in commit description of PATCH6
>> >
>> > Changes since v9:
>> > - Rebased on Linux-5.17-rc1
>> >
>> > Changes since v8:
>> > - Rebased on Linux-5.15-rc5
>> > - Fixed DT schema check errors in PATCH7
>> >
>> > Changes since v7:
>> > - Rebased on Linux-5.15-rc3
>> > - Renamed cpuidle-sbi.c to cpuidle-riscv-sbi.c in PATCH6
>> >
>> > Changes since v6:
>> > - Fixed error reported by "make DT_CHECKER_FLAGS=-m dt_binding_check"
>> >
>> > Changes since v5:
>> > - Rebased on Linux-5.13-rc5
>> > - Removed unnecessary exports from PATCH5
>> > - Removed stray ";" from PATCH5
>> > - Moved sbi_cpuidle_pd_power_off() under "#ifdef CONFIG_DT_IDLE_GENPD"
>> > in PATCH6
>> >
>> > Changes since v4:
>> > - Rebased on Linux-5.13-rc2
>> > - Renamed all dt_idle_genpd functions to have "dt_idle_" prefix
>> > - Added MAINTAINERS file entry for dt_idle_genpd
>> >
>> > Changes since v3:
>> > - Rebased on Linux-5.13-rc2
>> > - Fixed __cpu_resume_enter() which was broken due to XIP kernel support
>> > - Removed "struct dt_idle_genpd_ops" abstraction which simplifies code
>> > sharing between ARM PSCI and RISC-V SBI drivers in PATCH5
>> >
>> > Changes since v2:
>> > - Rebased on Linux-5.12-rc3
>> > - Updated PATCH7 to add common DT bindings for both ARM and RISC-V
>> > idle states
>> > - Added "additionalProperties = false" for both idle-states node and
>> > child nodes in PATCH7
>> >
>> > Changes since v1:
>> > - Fixex minor typo in PATCH1
>> > - Use just "idle-states" as DT node name for CPU idle states
>> > - Added documentation for "cpu-idle-states" DT property in
>> > devicetree/bindings/riscv/cpus.yaml
>> > - Added documentation for "riscv,sbi-suspend-param" DT property in
>> > devicetree/bindings/riscv/idle-states.yaml
>> >
>> > Anup Patel (8):
>> > RISC-V: Enable CPU_IDLE drivers
>> > RISC-V: Rename relocate() and make it global
>> > RISC-V: Add arch functions for non-retentive suspend entry/exit
>> > RISC-V: Add SBI HSM suspend related defines
>> > cpuidle: Factor-out power domain related code from PSCI domain driver
>> > cpuidle: Add RISC-V SBI CPU idle driver
>> > dt-bindings: Add common bindings for ARM and RISC-V idle states
>> > RISC-V: Enable RISC-V SBI CPU Idle driver for QEMU virt machine
>> >
>> > .../bindings/arm/msm/qcom,idle-state.txt | 2 +-
>> > .../devicetree/bindings/arm/psci.yaml | 2 +-
>> > .../bindings/{arm => cpu}/idle-states.yaml | 228 ++++++-
>> > .../devicetree/bindings/riscv/cpus.yaml | 6 +
>> > MAINTAINERS | 14 +
>> > arch/riscv/Kconfig | 7 +
>> > arch/riscv/Kconfig.socs | 3 +
>> > arch/riscv/configs/defconfig | 2 +
>> > arch/riscv/configs/rv32_defconfig | 2 +
>> > arch/riscv/include/asm/asm.h | 27 +
>> > arch/riscv/include/asm/cpuidle.h | 24 +
>> > arch/riscv/include/asm/sbi.h | 27 +-
>> > arch/riscv/include/asm/suspend.h | 36 +
>> > arch/riscv/kernel/Makefile | 2 +
>> > arch/riscv/kernel/asm-offsets.c | 3 +
>> > arch/riscv/kernel/cpu_ops_sbi.c | 2 +-
>> > arch/riscv/kernel/head.S | 28 +-
>> > arch/riscv/kernel/process.c | 3 +-
>> > arch/riscv/kernel/suspend.c | 87 +++
>> > arch/riscv/kernel/suspend_entry.S | 124 ++++
>> > arch/riscv/kvm/vcpu_sbi_hsm.c | 4 +-
>> > drivers/cpuidle/Kconfig | 9 +
>> > drivers/cpuidle/Kconfig.arm | 1 +
>> > drivers/cpuidle/Kconfig.riscv | 15 +
>> > drivers/cpuidle/Makefile | 5 +
>> > drivers/cpuidle/cpuidle-psci-domain.c | 138 +---
>> > drivers/cpuidle/cpuidle-psci.h | 15 +-
>> > drivers/cpuidle/cpuidle-riscv-sbi.c | 627 ++++++++++++++++++
>> > drivers/cpuidle/dt_idle_genpd.c | 178 +++++
>> > drivers/cpuidle/dt_idle_genpd.h | 50 ++
>> > 30 files changed, 1484 insertions(+), 187 deletions(-)
>> > rename Documentation/devicetree/bindings/{arm => cpu}/idle-states.yaml (74%)
>> > create mode 100644 arch/riscv/include/asm/cpuidle.h
>> > create mode 100644 arch/riscv/include/asm/suspend.h
>> > create mode 100644 arch/riscv/kernel/suspend.c
>> > create mode 100644 arch/riscv/kernel/suspend_entry.S
>> > create mode 100644 drivers/cpuidle/Kconfig.riscv
>> > create mode 100644 drivers/cpuidle/cpuidle-riscv-sbi.c
>> > create mode 100644 drivers/cpuidle/dt_idle_genpd.c
>> > create mode 100644 drivers/cpuidle/dt_idle_genpd.h
>>
>> Thanks, these are on for-next.
>
> For 5.18? You are not supposed to put new material into linux-next
> during the merge window.
Ya, I was aiming for these for 5.18 -- I know it's late, but I'd been
trying to chase folks around for reviews and figured it was good enough.
I just sent Linus a PR, it's not merged yet so if this is a problem I
can re-spin it now.
Sorry!
>
> In any case, this now cause warnings on 'cpu-idle-states':
>
> /builds/robherring/linux-dt/Documentation/devicetree/bindings/cpu/idle-states.example.dtb:
> cpu@0: cpu-idle-states:0: [1, 2, 3, 4] is too long
> From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/arm/cpus.yaml
> /builds/robherring/linux-dt/Documentation/devicetree/bindings/cpu/idle-states.example.dtb:
> cpu@1: cpu-idle-states:0: [1, 2, 3, 4] is too long
> From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/arm/cpus.yaml
> /builds/robherring/linux-dt/Documentation/devicetree/bindings/cpu/idle-states.example.dtb:
> cpu@100: cpu-idle-states:0: [1, 2, 3, 4] is too long
> From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/arm/cpus.yaml
> /builds/robherring/linux-dt/Documentation/devicetree/bindings/cpu/idle-states.example.dtb:
> cpu@101: cpu-idle-states:0: [1, 2, 3, 4] is too long
> From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/arm/cpus.yaml
>
> See commit 39bd2b6a3783 ("dt-bindings: Improve phandle-array schemas")
> for how to fix.
>
> Rob