Hello,
On 2023-09-11 at 13:05:16 -0700, Reinette Chatre wrote:
>Hi Maciej,
>> diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
>> index b44c487727d4..782e2700290b 100644
>> --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
>> +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
>> @@ -87,10 +87,13 @@ int parse_bw(struct rdt_parse_data *data, struct resctrl_schema *s,
>>
>> /*
>> * Check whether a cache bit mask is valid.
>> - * For Intel the SDM says:
>> - * Please note that all (and only) contiguous '1' combinations
>> - * are allowed (e.g. FFFFH, 0FF0H, 003CH, etc.).
>> - * Additionally Haswell requires at least two bits set.
>> + * On Intel CPUs, non-contiguous 1s value support is indicated by CPUID:
>> + * - CPUID.0x10.1:ECX[3]: L3 non-contiguous 1s value supported if 1
>> + * - CPUID.0x10.2:ECX[3]: L2 non-contiguous 1s value supported if 1
>> + *
>> + * Additionally Haswell requires at least two bits set. Since it does not
>> + * have CPUID enumeration support for Cache allocation the non-contiguous 1s
>> + * value support is disabled.
>
>The second sentence can be misinterpreted. non-contiguous 1s value support is
>disabled on Haswell because Haswell does not support non-contiguous 1s value,
>not because it does not have CPUID enumeration for RDT.
Would phrasing it like this:
+ * Additionally Haswell requires at least two bits set. Since it does not
+ * allow the non-contiguous 1s for cache allocation the support is
+ * hardcoded to disabled.
be more sensible?
>> * AMD allows non-contiguous bitmasks.
>
>(connecting to comments in following patch on this topic ... notice how the above
>comments use the term "bit mask" and "bitmasks")
I'll change it so the naming is unified, thanks.
>> */
>> static bool cbm_validate(char *buf, u32 *data, struct rdt_resource *r)
>> diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h
>> index 85ceaf9a31ac..c47ef2f13e8e 100644
>> --- a/arch/x86/kernel/cpu/resctrl/internal.h
>> +++ b/arch/x86/kernel/cpu/resctrl/internal.h
>> @@ -492,6 +492,15 @@ union cpuid_0x10_3_eax {
>> unsigned int full;
>> };
>>
>> +/* CPUID.(EAX=10H, ECX=ResID).ECX */
>> +union cpuid_0x10_x_ecx {
>> + struct {
>> + unsigned int reserved:3;
>> + unsigned int noncont:1;
>> + } split;
>> + unsigned int full;
>> +};
>> +
>> /* CPUID.(EAX=10H, ECX=ResID).EDX */
>> union cpuid_0x10_x_edx {
>> struct {
>
>The core of the change looks good to me.
>
>Reinette
Thanks for reviewing!
--
Kind regards
Maciej Wiecz?r-Retman
Hi Maciej,
On 9/11/2023 11:53 PM, Maciej Wieczór-Retman wrote:
> On 2023-09-11 at 13:05:16 -0700, Reinette Chatre wrote:
>> Hi Maciej,
>>> diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
>>> index b44c487727d4..782e2700290b 100644
>>> --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
>>> +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
>>> @@ -87,10 +87,13 @@ int parse_bw(struct rdt_parse_data *data, struct resctrl_schema *s,
>>>
>>> /*
>>> * Check whether a cache bit mask is valid.
>>> - * For Intel the SDM says:
>>> - * Please note that all (and only) contiguous '1' combinations
>>> - * are allowed (e.g. FFFFH, 0FF0H, 003CH, etc.).
>>> - * Additionally Haswell requires at least two bits set.
>>> + * On Intel CPUs, non-contiguous 1s value support is indicated by CPUID:
>>> + * - CPUID.0x10.1:ECX[3]: L3 non-contiguous 1s value supported if 1
>>> + * - CPUID.0x10.2:ECX[3]: L2 non-contiguous 1s value supported if 1
>>> + *
>>> + * Additionally Haswell requires at least two bits set. Since it does not
>>> + * have CPUID enumeration support for Cache allocation the non-contiguous 1s
>>> + * value support is disabled.
>>
>> The second sentence can be misinterpreted. non-contiguous 1s value support is
>> disabled on Haswell because Haswell does not support non-contiguous 1s value,
>> not because it does not have CPUID enumeration for RDT.
>
> Would phrasing it like this:
>
> + * Additionally Haswell requires at least two bits set. Since it does not
> + * allow the non-contiguous 1s for cache allocation the support is
> + * hardcoded to disabled.
>
> be more sensible?
>
I think the above would be sensible as a comment of cache_alloc_hsw_probe()
where the support is hardcoded but here the comment is just used to summarize
what the hardware supports.
Maybe just something like:
Haswell does not support a non-contiguous 1s value and additionally
requires at least two bits set.
Reinette