2015-04-27 15:21:35

by Aravind Gopalakrishnan

Subject: [PATCH] x86, amd: Set X86_FEATURE_EXTD_APICID for future processors

Decision to use a 4-bit mask or 8-bit mask in default_get_apic_id()
is controlled by setting capability bit X86_FEATURE_EXTD_APICID.

Currently, we detect extended APIC ID support by accessing Link
Transaction Control register D18F0x68 in PCI config space.

But, not even that is needed as we can safely postulate that future
AMD processors will support 8-bit APIC IDs and we can simply set that
feature bit on them, without the PCI access.

Signed-off-by: Aravind Gopalakrishnan <[email protected]>
---
arch/x86/kernel/cpu/amd.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index fd470eb..20b6813 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -520,8 +520,16 @@ static void early_init_amd(struct cpuinfo_x86 *c)
set_cpu_cap(c, X86_FEATURE_K6_MTRR);
#endif
#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
- /* check CPU config space for extended APIC ID */
- if (cpu_has_apic && c->x86 >= 0xf) {
+ /*
+ * ApicID can always be treated as a 8bit value for
+ * AMD APIC versions >= 0x10. So, we can safely set
+ * X86_FEATURE_EXTD_APICID unconditionally for
+ * families after 16h.
+ */
+ if (cpu_has_apic && c->x86 > 0x16) {
+ set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
+ } else if (cpu_has_apic && c->x86 >= 0xf) {
+ /* check CPU config space for extended APIC ID */
unsigned int val;
val = read_pci_config(0, 24, 0, 0x68);
if ((val & ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18)))
--
1.9.1

2015-04-29 16:07:25

by Borislav Petkov

Subject: Re: [PATCH] x86, amd: Set X86_FEATURE_EXTD_APICID for future processors

On Mon, Apr 27, 2015 at 10:25:51AM -0500, Aravind Gopalakrishnan wrote:
> Decision to use a 4-bit mask or 8-bit mask in default_get_apic_id()
> is controlled by setting capability bit X86_FEATURE_EXTD_APICID.
>
> Currently, we detect extended APIC ID support by accessing Link
> Transaction Control register D18F0x68 in PCI config space.
>
> But, not even that is needed as we can safely postulate that future
> AMD processors will support 8-bit APIC IDs and we can simply set that
> feature bit on them, without the PCI access.
>
> Signed-off-by: Aravind Gopalakrishnan <[email protected]>
> ---
> arch/x86/kernel/cpu/amd.c | 12 ++++++++++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
> index fd470eb..20b6813 100644
> --- a/arch/x86/kernel/cpu/amd.c
> +++ b/arch/x86/kernel/cpu/amd.c
> @@ -520,8 +520,16 @@ static void early_init_amd(struct cpuinfo_x86 *c)
> set_cpu_cap(c, X86_FEATURE_K6_MTRR);
> #endif
> #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
> - /* check CPU config space for extended APIC ID */
> - if (cpu_has_apic && c->x86 >= 0xf) {
> + /*
> + * ApicID can always be treated as a 8bit value for
> + * AMD APIC versions >= 0x10. So, we can safely set

Expanded the version aspect to:

/*
* ApicID can always be treated as a 8bit value for AMD APIC versions
* >= 0x10 but even old K8s came out of reset with version 0x10. So, we
* can safely set X86_FEATURE_EXTD_APICID unconditionally for families
* after 16h.
*/

and applied.

Thanks.

--
Regards/Gruss,
Boris.

ECO tip #101: Trim your mails when you reply.
--

2015-05-06 10:14:34

by tip-bot for Vasyl Gomonovych

Subject: [tip:x86/cpu] x86/cpu/amd: Set X86_FEATURE_EXTD_APICID for future processors

Commit-ID: b9d16a2a21aa9c264a29dd84d6f7b03581517a03
Gitweb: http://git.kernel.org/tip/b9d16a2a21aa9c264a29dd84d6f7b03581517a03
Author: Aravind Gopalakrishnan <[email protected]>
AuthorDate: Mon, 27 Apr 2015 10:25:51 -0500
Committer: Ingo Molnar <[email protected]>
CommitDate: Wed, 6 May 2015 11:16:53 +0200

x86/cpu/amd: Set X86_FEATURE_EXTD_APICID for future processors

Decision to use a 4-bit mask or 8-bit mask in default_get_apic_id()
is controlled by setting capability bit X86_FEATURE_EXTD_APICID.

Currently, we detect extended APIC ID support by accessing Link
Transaction Control register D18F0x68 in PCI config space.

But, not even that is needed as we can safely postulate that future
AMD processors will support 8-bit APIC IDs and we can simply set that
feature bit on them, without the PCI access.

Signed-off-by: Aravind Gopalakrishnan <[email protected]>
Signed-off-by: Borislav Petkov <[email protected]>
Cc: Borislav Petkov <[email protected]>
Cc: H. Peter Anvin <[email protected]>
Cc: Jacob Shin <[email protected]>
Cc: Paolo Bonzini <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Ingo Molnar <[email protected]>
---
arch/x86/kernel/cpu/amd.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index e4cf633..94e7051 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -520,8 +520,16 @@ static void early_init_amd(struct cpuinfo_x86 *c)
set_cpu_cap(c, X86_FEATURE_K6_MTRR);
#endif
#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
- /* check CPU config space for extended APIC ID */
- if (cpu_has_apic && c->x86 >= 0xf) {
+ /*
+ * ApicID can always be treated as an 8-bit value for AMD APIC versions
+ * >= 0x10, but even old K8s came out of reset with version 0x10. So, we
+ * can safely set X86_FEATURE_EXTD_APICID unconditionally for families
+ * after 16h.
+ */
+ if (cpu_has_apic && c->x86 > 0x16) {
+ set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
+ } else if (cpu_has_apic && c->x86 >= 0xf) {
+ /* check CPU config space for extended APIC ID */
unsigned int val;
val = read_pci_config(0, 24, 0, 0x68);
if ((val & ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18)))