2021-10-18 05:25:48

by Chen Lu

Subject: [PATCH] riscv: fix misalgned trap vector base address

* The trap vector marked by label .Lsecondary_park should align on a
4-byte boundary. If not, CSR_TVEC may be set to an incorrect address.
* This bug is introduced at commit e011995e826f8 ("RISC-V: Move relocate
and few other functions out of __init").
* This bug is exposed with an educational emualtor.

Signed-off-by: Chen Lu <[email protected]>
---
arch/riscv/kernel/head.S | 1 +
1 file changed, 1 insertion(+)

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index fce5184b22c3..52c5ff9804c5 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -193,6 +193,7 @@ setup_trap_vector:
csrw CSR_SCRATCH, zero
ret

+.align 2
.Lsecondary_park:
/* We lack SMP support or have too many harts, so park this hart */
wfi
--
2.30.2

2021-10-18 05:33:52

by Anup Patel

Subject: Re: [PATCH] riscv: fix misalgned trap vector base address

On Mon, Oct 18, 2021 at 10:52 AM Chen Lu <[email protected]> wrote:
>
> * The trap vector marked by label .Lsecondary_park should align on a
> 4-byte boundary. If not, CSR_TVEC may be set to an incorrect address.
> * This bug is introduced at commit e011995e826f8 ("RISC-V: Move relocate
> and few other functions out of __init").
> * This bug is exposed with an educational emualtor.
>

Please add "Fixes:" line here.

> Signed-off-by: Chen Lu <[email protected]>

Otherwise it looks good to me.

Reviewed-by: Anup Patel <[email protected]>

Regards,
Anup

> ---
> arch/riscv/kernel/head.S | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index fce5184b22c3..52c5ff9804c5 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -193,6 +193,7 @@ setup_trap_vector:
> csrw CSR_SCRATCH, zero
> ret
>
> +.align 2
> .Lsecondary_park:
> /* We lack SMP support or have too many harts, so park this hart */
> wfi
> --
> 2.30.2
>
>
>

2021-10-27 21:36:33

by Palmer Dabbelt

Subject: Re: [PATCH] riscv: fix misalgned trap vector base address

On Sun, 17 Oct 2021 22:22:38 PDT (-0700), [email protected] wrote:
> * The trap vector marked by label .Lsecondary_park should align on a
> 4-byte boundary. If not, CSR_TVEC may be set to an incorrect address.
> * This bug is introduced at commit e011995e826f8 ("RISC-V: Move relocate
> and few other functions out of __init").
> * This bug is exposed with an educational emualtor.
>
> Signed-off-by: Chen Lu <[email protected]>
> ---
> arch/riscv/kernel/head.S | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index fce5184b22c3..52c5ff9804c5 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -193,6 +193,7 @@ setup_trap_vector:
> csrw CSR_SCRATCH, zero
> ret
>
> +.align 2
> .Lsecondary_park:
> /* We lack SMP support or have too many harts, so park this hart */
> wfi

Thanks, this is on fixes (with some commit message cleanups).