This series of patches converts the RISC-V CPU interrupt controller to
the newer dt-schema binding.
Patch 1:
This patch is currently at v3 as it has been previously rolled out.
Contains the bindings for the interrupt controller.
Patch 2:
Contains the reference to the above interrupt controller. Thus, making
all the RISC-V interrupt controller bindings in a centralized place.
These patches are interdependent.
Kanak Shilledar (2):
dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema
dt-bindings: riscv: cpus: add ref to interrupt-controller
.../interrupt-controller/riscv,cpu-intc.txt | 52 -------------
.../interrupt-controller/riscv,cpu-intc.yaml | 73 +++++++++++++++++++
.../devicetree/bindings/riscv/cpus.yaml | 22 +-----
3 files changed, 74 insertions(+), 73 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.yaml
base-commit: 20cb38a7af88dc40095da7c2c9094da3873fea23
prerequisite-patch-id: 158157d32a32e765834a0cb4fc6335f9009d9962
prerequisite-patch-id: 4007c7386e66f93b67a2631dddca08cadcee708b
--
2.34.1
removed the redundant properties for interrupt-controller
and provide reference to the riscv,cpu-intc.yaml which defines
the interrupt-controller. making the properties for riscv
interrupt-controller at a central place.
Signed-off-by: Kanak Shilledar <[email protected]>
---
.../devicetree/bindings/riscv/cpus.yaml | 22 +------------------
1 file changed, 1 insertion(+), 21 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d87dd50f1a4b..b90bb83c8e73 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -101,27 +101,7 @@ properties:
timebase-frequency: false
interrupt-controller:
- type: object
- additionalProperties: false
- description: Describes the CPU's local interrupt controller
-
- properties:
- '#interrupt-cells':
- const: 1
-
- compatible:
- oneOf:
- - items:
- - const: andestech,cpu-intc
- - const: riscv,cpu-intc
- - const: riscv,cpu-intc
-
- interrupt-controller: true
-
- required:
- - '#interrupt-cells'
- - compatible
- - interrupt-controller
+ $ref: /schemas/interrupt-controller/riscv,cpu-intc.yaml
cpu-idle-states:
$ref: /schemas/types.yaml#/definitions/phandle-array
--
2.34.1
Convert the RISC-V Hart-Level Interrupt Controller (HLIC) to newer
DT schema, Created DT schema based on the .txt file which had
`compatible`, `#interrupt-cells` and `interrupt-controller` as
required properties.
Changes made with respect to original file:
- Changed the example to just use interrupt-controller instead of
using the whole cpu block
- Changed the example compatible string.
Signed-off-by: Kanak Shilledar <[email protected]>
---
Changes in v3:
- Remove reference to `interrupt-controller` in `riscv/cpus.yaml`.
---
Changes in v2:
- Update the maintainers list.
- Add reference to `interrupt-controller` in `riscv/cpus.yaml`.
- Update compatible property with the reference in `cpus.yaml`.
- Include description for '#interrupt-cells' property.
- Change '#interrupt-cells' property to have `const: 1` as per the
text binding.
- Fixed the warning thrown by `/renesas/r9a07g043f01-smarc.dtb`.
---
.../interrupt-controller/riscv,cpu-intc.txt | 52 -------------
.../interrupt-controller/riscv,cpu-intc.yaml | 73 +++++++++++++++++++
2 files changed, 73 insertions(+), 52 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt
deleted file mode 100644
index 265b223cd978..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt
+++ /dev/null
@@ -1,52 +0,0 @@
-RISC-V Hart-Level Interrupt Controller (HLIC)
----------------------------------------------
-
-RISC-V cores include Control Status Registers (CSRs) which are local to each
-CPU core (HART in RISC-V terminology) and can be read or written by software.
-Some of these CSRs are used to control local interrupts connected to the core.
-Every interrupt is ultimately routed through a hart's HLIC before it
-interrupts that hart.
-
-The RISC-V supervisor ISA manual specifies three interrupt sources that are
-attached to every HLIC: software interrupts, the timer interrupt, and external
-interrupts. Software interrupts are used to send IPIs between cores. The
-timer interrupt comes from an architecturally mandated real-time timer that is
-controlled via Supervisor Binary Interface (SBI) calls and CSR reads. External
-interrupts connect all other device interrupts to the HLIC, which are routed
-via the platform-level interrupt controller (PLIC).
-
-All RISC-V systems that conform to the supervisor ISA specification are
-required to have a HLIC with these three interrupt sources present. Since the
-interrupt map is defined by the ISA it's not listed in the HLIC's device tree
-entry, though external interrupt controllers (like the PLIC, for example) will
-need to define how their interrupts map to the relevant HLICs. This means
-a PLIC interrupt property will typically list the HLICs for all present HARTs
-in the system.
-
-Required properties:
-- compatible : "riscv,cpu-intc"
-- #interrupt-cells : should be <1>. The interrupt sources are defined by the
- RISC-V supervisor ISA manual, with only the following three interrupts being
- defined for supervisor mode:
- - Source 1 is the supervisor software interrupt, which can be sent by an SBI
- call and is reserved for use by software.
- - Source 5 is the supervisor timer interrupt, which can be configured by
- SBI calls and implements a one-shot timer.
- - Source 9 is the supervisor external interrupt, which chains to all other
- device interrupts.
-- interrupt-controller : Identifies the node as an interrupt controller
-
-Furthermore, this interrupt-controller MUST be embedded inside the cpu
-definition of the hart whose CSRs control these local interrupts.
-
-An example device tree entry for a HLIC is show below.
-
- cpu1: cpu@1 {
- compatible = "riscv";
- ...
- cpu1-intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "sifive,fu540-c000-cpu-intc", "riscv,cpu-intc";
- interrupt-controller;
- };
- };
diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.yaml
new file mode 100644
index 000000000000..c9c79e0870ff
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RISC-V Hart-Level Interrupt Controller (HLIC)
+
+description:
+ RISC-V cores include Control Status Registers (CSRs) which are local to
+ each CPU core (HART in RISC-V terminology) and can be read or written by
+ software. Some of these CSRs are used to control local interrupts connected
+ to the core. Every interrupt is ultimately routed through a hart's HLIC
+ before it interrupts that hart.
+
+ The RISC-V supervisor ISA manual specifies three interrupt sources that are
+ attached to every HLIC namely software interrupts, the timer interrupt, and
+ external interrupts. Software interrupts are used to send IPIs between
+ cores. The timer interrupt comes from an architecturally mandated real-
+ time timer that is controlled via Supervisor Binary Interface (SBI) calls
+ and CSR reads. External interrupts connect all other device interrupts to
+ the HLIC, which are routed via the platform-level interrupt controller
+ (PLIC).
+
+ All RISC-V systems that conform to the supervisor ISA specification are
+ required to have a HLIC with these three interrupt sources present. Since
+ the interrupt map is defined by the ISA it's not listed in the HLIC's device
+ tree entry, though external interrupt controllers (like the PLIC, for
+ example) will need to define how their interrupts map to the relevant HLICs.
+ This means a PLIC interrupt property will typically list the HLICs for all
+ present HARTs in the system.
+
+maintainers:
+ - Palmer Dabbelt <[email protected]>
+ - Paul Walmsley <[email protected]>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: andestech,cpu-intc
+ - const: riscv,cpu-intc
+ - const: riscv,cpu-intc
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 1
+ description: |
+ The interrupt sources are defined by the RISC-V supervisor ISA manual,
+ with only the following three interrupts being defined for
+ supervisor mode:
+ - Source 1 is the supervisor software interrupt, which can be sent by
+ an SBI call and is reserved for use by software.
+ - Source 5 is the supervisor timer interrupt, which can be configured
+ by SBI calls and implements a one-shot timer.
+ - Source 9 is the supervisor external interrupt, which chains to all
+ other device interrupts.
+
+required:
+ - compatible
+ - '#interrupt-cells'
+ - interrupt-controller
+
+additionalProperties: false
+
+examples:
+ - |
+ interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
--
2.34.1
On Sun, 19 May 2024 23:29:06 +0530, Kanak Shilledar wrote:
> removed the redundant properties for interrupt-controller
> and provide reference to the riscv,cpu-intc.yaml which defines
> the interrupt-controller. making the properties for riscv
> interrupt-controller at a central place.
>
> Signed-off-by: Kanak Shilledar <[email protected]>
> ---
> .../devicetree/bindings/riscv/cpus.yaml | 22 +------------------
> 1 file changed, 1 insertion(+), 21 deletions(-)
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/riscv/cpus.yaml: properties:interrupt-controller: 'oneOf' conditional failed, one must be fixed:
Additional properties are not allowed ('$ref' was unexpected)
'type' is a required property
hint: DT nodes ("object" type in schemas) can only use a subset of json-schema keywords
from schema $id: http://devicetree.org/meta-schemas/interrupts.yaml#
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
On Mon, May 20, 2024 at 1:02 AM Rob Herring (Arm) <[email protected]> wrote:
>
>
> On Sun, 19 May 2024 23:29:06 +0530, Kanak Shilledar wrote:
> > removed the redundant properties for interrupt-controller
> > and provide reference to the riscv,cpu-intc.yaml which defines
> > the interrupt-controller. making the properties for riscv
> > interrupt-controller at a central place.
> >
> > Signed-off-by: Kanak Shilledar <[email protected]>
> > ---
> > .../devicetree/bindings/riscv/cpus.yaml | 22 +------------------
> > 1 file changed, 1 insertion(+), 21 deletions(-)
> >
>
> My bot found errors running 'make dt_binding_check' on your patch:
>
> yamllint warnings/errors:
>
> dtschema/dtc warnings/errors:
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/riscv/cpus.yaml: properties:interrupt-controller: 'oneOf' conditional failed, one must be fixed:
> Additional properties are not allowed ('$ref' was unexpected)
> 'type' is a required property
> hint: DT nodes ("object" type in schemas) can only use a subset of json-schema keywords
> from schema $id: http://devicetree.org/meta-schemas/interrupts.yaml#
>
> doc reference errors (make refcheckdocs):
>
> See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]
I have fixed the above warning.
> The base for the series is generally the latest rc1. A different dependency
> should be noted in *this* patch.
Can you please clarify this part? Is my base commit ID incorrect?
I am currently using the 6.9.0-rc3 kernel version form
https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git/ repo.
Thanks and Regards,
Kanak Shilledar
On Mon, May 20, 2024 at 03:09:44PM +0530, Kanak Shilledar wrote:
> On Mon, May 20, 2024 at 1:02 AM Rob Herring (Arm) <[email protected]> wrote:
> >
> >
> > On Sun, 19 May 2024 23:29:06 +0530, Kanak Shilledar wrote:
> > > removed the redundant properties for interrupt-controller
> > > and provide reference to the riscv,cpu-intc.yaml which defines
> > > the interrupt-controller. making the properties for riscv
> > > interrupt-controller at a central place.
> > >
> > > Signed-off-by: Kanak Shilledar <[email protected]>
> > > ---
> > > .../devicetree/bindings/riscv/cpus.yaml | 22 +------------------
> > > 1 file changed, 1 insertion(+), 21 deletions(-)
> > >
> >
> > My bot found errors running 'make dt_binding_check' on your patch:
> >
> > yamllint warnings/errors:
> >
> > dtschema/dtc warnings/errors:
> > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/riscv/cpus.yaml: properties:interrupt-controller: 'oneOf' conditional failed, one must be fixed:
> > Additional properties are not allowed ('$ref' was unexpected)
> > 'type' is a required property
> > hint: DT nodes ("object" type in schemas) can only use a subset of json-schema keywords
> > from schema $id: http://devicetree.org/meta-schemas/interrupts.yaml#
> >
> > doc reference errors (make refcheckdocs):
> >
> > See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]
>
> I have fixed the above warning.
>
> > The base for the series is generally the latest rc1. A different dependency
> > should be noted in *this* patch.
>
> Can you please clarify this part? Is my base commit ID incorrect?
The bot says this in case the error is caused by it having applied
patches on top of 6.9-rc1, but in this case I doubt there's any impact.
By "this patch" it means that having the information in the cover
doesn't help, but info about missing deps should go under the --- line
etc.
| base-commit: 20cb38a7af88dc40095da7c2c9094da3873fea23
| prerequisite-patch-id: 158157d32a32e765834a0cb4fc6335f9009d9962
| prerequisite-patch-id: 4007c7386e66f93b67a2631dddca08cadcee708b
That said, why do you have two prerequisite patches? This applies on top
of 6.9-rc3 without any issues (other than trailing whitespace warnings).
Also, you forgot the v3 tag on this patchset, which confuses tooling:
shazam https://lore.kernel.org/linux-riscv/[email protected]/T/#t
Grabbing thread from lore.kernel.org/all/[email protected]/t.mbox.gz
Checking for newer revisions
Grabbing search results from lore.kernel.org
---> Added from v2: 1 patches
Analyzing 10 messages in the thread
---> Will use the latest revision: v2
You can pick other revisions using the -vN flag
Checking attestation on all messages, may take a moment...
Retrieving CI status, may take a moment...
Some CI checks failed, see patchwork for more info:
https://patchwork.kernel.org/project/linux-riscv/list/?series=854147
---
✓ [● PATCH v2] dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema
+ Signed-off-by: Conor Dooley <[email protected]>
---
✓ Signed: DKIM/gmail.com
---
Total patches: 1
---
Applying: dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema
Thanks,
Conor.
Hi Conor,
Thanks for the clarification.
On Mon, May 20, 2024 at 10:34 PM Conor Dooley <[email protected]> wrote:
>
> On Mon, May 20, 2024 at 03:09:44PM +0530, Kanak Shilledar wrote:
> > On Mon, May 20, 2024 at 1:02 AM Rob Herring (Arm) <[email protected]> wrote:
> > >
> By "this patch" it means that having the information in the cover
> doesn't help, but info about missing deps should go under the --- line
> etc.
I am still unable to get this part. I don't see there is any dependency
other than the two patches dependent on each other. In my cover letter
I have mentioned that the two patches are dependent on each other.
> | base-commit: 20cb38a7af88dc40095da7c2c9094da3873fea23
> | prerequisite-patch-id: 158157d32a32e765834a0cb4fc6335f9009d9962
> | prerequisite-patch-id: 4007c7386e66f93b67a2631dddca08cadcee708b
>
> That said, why do you have two prerequisite patches? This applies on top
> of 6.9-rc3 without any issues (other than trailing whitespace warnings).
For generation the patches I am using the command:
`git format-patch -2 -o outgoing/ --cover-letter --base=auto`
It is automatically adding those two preqrequisite-patch-ids
automatically along with the base-commit id.
Is it due to the fact that I am having 2 older patches which I have
rolled out already? Shall I remove those
prerequisite patch id from the coverletter to solve this issue?
> Also, you forgot the v3 tag on this patchset, which confuses tooling:
I will fix it in my next version. I haven't changed anything in the
patch so I will add the v3 tag and send it.
> shazam https://lore.kernel.org/linux-riscv/[email protected]/T/#t
> Grabbing thread from lore.kernel.org/all/[email protected]/t.mbox.gz
> Checking for newer revisions
> Grabbing search results from lore.kernel.org
> ---> Added from v2: 1 patches
> Analyzing 10 messages in the thread
> ---> Will use the latest revision: v2
> You can pick other revisions using the -vN flag
> Checking attestation on all messages, may take a moment...
> Retrieving CI status, may take a moment...
> Some CI checks failed, see patchwork for more info:
> https://patchwork.kernel.org/project/linux-riscv/list/?series=854147
> ---
> ✓ [● PATCH v2] dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema
> + Signed-off-by: Conor Dooley <[email protected]>
> ---
> ✓ Signed: DKIM/gmail.com
> ---
> Total patches: 1
> ---
> Applying: dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema
>
> Thanks,
> Conor.
Thanks and Regards,
Kanak Shilledar
On Tue, May 21, 2024 at 07:26:54PM +0530, Kanak Shilledar wrote:
> Thanks for the clarification.
> On Mon, May 20, 2024 at 10:34 PM Conor Dooley <[email protected]> wrote:
> >
> > On Mon, May 20, 2024 at 03:09:44PM +0530, Kanak Shilledar wrote:
> > > On Mon, May 20, 2024 at 1:02 AM Rob Herring (Arm) <[email protected]> wrote:
>
> > By "this patch" it means that having the information in the cover
> > doesn't help, but info about missing deps should go under the --- line
> > etc.
>
> I am still unable to get this part. I don't see there is any dependency
> other than the two patches dependent on each other. In my cover letter
> I have mentioned that the two patches are dependent on each other.
That's fine, then you didn't do anything wrong in that regard.
Sometimes however, other series have a dependency on other series, which
is what that text was talking about.
> > | base-commit: 20cb38a7af88dc40095da7c2c9094da3873fea23
> > | prerequisite-patch-id: 158157d32a32e765834a0cb4fc6335f9009d9962
> > | prerequisite-patch-id: 4007c7386e66f93b67a2631dddca08cadcee708b
> >
> > That said, why do you have two prerequisite patches? This applies on top
> > of 6.9-rc3 without any issues (other than trailing whitespace warnings).
>
> For generation the patches I am using the command:
> `git format-patch -2 -o outgoing/ --cover-letter --base=auto`
> It is automatically adding those two preqrequisite-patch-ids
> automatically along with the base-commit id.
> Is it due to the fact that I am having 2 older patches which I have
> rolled out already? Shall I remove those
> prerequisite patch id from the coverletter to solve this issue?
If they're not related to what you're working on, then yes.
--base=auto probably picked the last tagged commit, but the applier of
these patches doesn't need to care about the other (unrelated) patches in
your tree so having them is just a potential source of confusion.