LinuxLists.cc - [PATCH 0/5] crypto:s5p-sss: Add DT and Exynos5 support

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Subject: [PATCH 1/5] crypto:s5p-sss: Use platform_get_irq() instead of _byname()

This patch uses the platform_get_irq() instead of the
platform_get_irq_byname(). Making feeder control interrupt
as resource "0" and hash interrupt as "1".

reasons for this change.
1. Cannot find any Arch which is currently using this driver
2. Samsung Exynos5 SoCs only use the feeder control interrupt
3. Patches adding support for DT and H/W version are in pipeline

Signed-off-by: Naveen Krishna Ch <[email protected]>
CC: Herbert Xu <[email protected]>
CC: David S. Miller <[email protected]>
CC: Vladimir Zapolskiy <[email protected]>
TO: <[email protected]>
CC: <[email protected]>
---
drivers/crypto/s5p-sss.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
index cf149b1..dda4551 100644
--- a/drivers/crypto/s5p-sss.c
+++ b/drivers/crypto/s5p-sss.c
@@ -592,29 +592,29 @@ static int s5p_aes_probe(struct platform_device *pdev)
pdata->ioaddr = devm_ioremap(dev, res->start,
resource_size(res));

- pdata->irq_hash = platform_get_irq_byname(pdev, "hash");
- if (pdata->irq_hash < 0) {
+ pdata->irq_fc = platform_get_irq(pdev, 0);
+ if (pdata->irq_fc < 0) {
err = pdata->irq_hash;
- dev_warn(dev, "hash interrupt is not available.\n");
+ dev_warn(dev, "feed control interrupt is not available.\n");
goto err_irq;
}
- err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
+ err = devm_request_irq(dev, pdata->irq_fc, s5p_aes_interrupt,
IRQF_SHARED, pdev->name, pdev);
if (err < 0) {
- dev_warn(dev, "hash interrupt is not available.\n");
+ dev_warn(dev, "feed control interrupt is not available.\n");
goto err_irq;
}

- pdata->irq_fc = platform_get_irq_byname(pdev, "feed control");
- if (pdata->irq_fc < 0) {
- err = pdata->irq_fc;
- dev_warn(dev, "feed control interrupt is not available.\n");
+ pdata->irq_hash = platform_get_irq(pdev, 1);
+ if (pdata->irq_hash < 0) {
+ err = pdata->irq_hash;
+ dev_warn(dev, "hash interrupt is not available.\n");
goto err_irq;
}
- err = devm_request_irq(dev, pdata->irq_fc, s5p_aes_interrupt,
+ err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
IRQF_SHARED, pdev->name, pdev);
if (err < 0) {
- dev_warn(dev, "feed control interrupt is not available.\n");
+ dev_warn(dev, "hash interrupt is not available.\n");
goto err_irq;
}

--
1.7.9.5

2014-01-07 11:51:48

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Subject: [PATCH 4/5] crypto:s5p-sss: Exynos5 SoCs too can select SSS driver

This patch modifies Kconfig such that ARCH_EXYNOS5 SoCs
can also select Samsung SSS(Security SubSystem) driver.

Signed-off-by: Naveen Krishna Ch <[email protected]>
CC: Herbert Xu <[email protected]>
CC: David S. Miller <[email protected]>
CC: Vladimir Zapolskiy <[email protected]>
TO: <[email protected]>
CC: <[email protected]>
---
drivers/crypto/Kconfig | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index f4fd837..137dcd8 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -300,15 +300,15 @@ config CRYPTO_DEV_DCP
capabilities of the DCP co-processor

config CRYPTO_DEV_S5P
- tristate "Support for Samsung S5PV210 crypto accelerator"
- depends on ARCH_S5PV210
+ tristate "Support for Samsung crypto accelerator"
+ depends on ARCH_S5PV210 || ARCH_EXYNOS5
select CRYPTO_AES
select CRYPTO_ALGAPI
select CRYPTO_BLKCIPHER
help
This option allows you to have support for S5P crypto acceleration.
- Select this to offload Samsung S5PV210 or S5PC110 from AES
- algorithms execution.
+ Select this to offload Samsung S5PV210 or S5PC110, Exynos5250
+ and Exynos5420 from AES algorithms execution.

config CRYPTO_DEV_TEGRA_AES
tristate "Support for TEGRA AES hw engine"
--
1.7.9.5

2014-01-07 11:51:38

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Subject: [PATCH 3/5] crypto:s5p-sss: Add support for SSS module on Exynos5

The differences between SSS modules on S5PV210 and Exynos5
(AFA the driver supports)
1. AES register are at an offset of 0x200 on Exynos5
2. hash interrupt is no longer needed on Exynos5

This patch adds code needed to address the above changes.

Signed-off-by: Naveen Krishna Ch <[email protected]>
CC: Herbert Xu <[email protected]>
CC: David S. Miller <[email protected]>
CC: Vladimir Zapolskiy <[email protected]>
TO: <[email protected]>
CC: <[email protected]>
---
drivers/crypto/s5p-sss.c | 59 ++++++++++++++++++++++++++++++++--------------
1 file changed, 41 insertions(+), 18 deletions(-)

diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
index dcb9fc1..a11cd0e 100644
--- a/drivers/crypto/s5p-sss.c
+++ b/drivers/crypto/s5p-sss.c
@@ -106,7 +106,7 @@
#define SSS_REG_FCPKDMAO 0x005C

/* AES registers */
-#define SSS_REG_AES_CONTROL 0x4000
+#define SSS_REG_AES_CONTROL(dev) ((dev)->aes_offset + 0x00)
#define SSS_AES_BYTESWAP_DI _BIT(11)
#define SSS_AES_BYTESWAP_DO _BIT(10)
#define SSS_AES_BYTESWAP_IV _BIT(9)
@@ -122,21 +122,26 @@
#define SSS_AES_CHAIN_MODE_CTR _SBF(1, 0x02)
#define SSS_AES_MODE_DECRYPT _BIT(0)

-#define SSS_REG_AES_STATUS 0x4004
+#define SSS_REG_AES_STATUS(dev) ((dev)->aes_offset + 0x04)
#define SSS_AES_BUSY _BIT(2)
#define SSS_AES_INPUT_READY _BIT(1)
#define SSS_AES_OUTPUT_READY _BIT(0)

-#define SSS_REG_AES_IN_DATA(s) (0x4010 + (s << 2))
-#define SSS_REG_AES_OUT_DATA(s) (0x4020 + (s << 2))
-#define SSS_REG_AES_IV_DATA(s) (0x4030 + (s << 2))
-#define SSS_REG_AES_CNT_DATA(s) (0x4040 + (s << 2))
-#define SSS_REG_AES_KEY_DATA(s) (0x4080 + (s << 2))
+#define SSS_REG_AES_IN_DATA(dev, s) ((dev)->aes_offset + 0x10 + (s << 2))
+#define SSS_REG_AES_OUT_DATA(dev, s) ((dev)->aes_offset + 0x20 + (s << 2))
+#define SSS_REG_AES_IV_DATA(dev, s) ((dev)->aes_offset + 0x30 + (s << 2))
+#define SSS_REG_AES_CNT_DATA(dev, s) ((dev)->aes_offset + 0x40 + (s << 2))
+#define SSS_REG_AES_KEY_DATA(dev, s) ((dev)->aes_offset + 0x80 + (s << 2))

#define SSS_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg))
#define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg))
#define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg))

+#define SSS_AES_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg(dev)))
+#define SSS_AES_READ(dev, reg) __raw_readl(SSS_AES_REG(dev, reg))
+#define SSS_AES_WRITE(dev, reg, val) __raw_writel((val), \
+ SSS_AES_REG(dev, reg))
+
/* HW engine modes */
#define FLAGS_AES_DECRYPT _BIT(0)
#define FLAGS_AES_MODE_MASK _SBF(1, 0x03)
@@ -177,6 +182,13 @@ struct s5p_aes_dev {

/* To support SSS versions across Samsung SoCs */
unsigned int version;
+
+ /*
+ * Register banks corresponding to various algorithms
+ * (Ex: AES, TDES, HASH, TRNG, PKA etc.)
+ * are at an offsets from the base (depending on SSS verion)
+ */
+ unsigned int aes_offset;
};

static struct s5p_aes_dev *s5p_dev;
@@ -358,14 +370,14 @@ static void s5p_set_aes(struct s5p_aes_dev *dev,
{
void __iomem *keystart;

- memcpy(dev->ioaddr + SSS_REG_AES_IV_DATA(0), iv, 0x10);
+ memcpy(dev->ioaddr + SSS_REG_AES_IV_DATA(dev, 0), iv, 0x10);

if (keylen == AES_KEYSIZE_256)
- keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(0);
+ keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(dev, 0);
else if (keylen == AES_KEYSIZE_192)
- keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(2);
+ keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(dev, 2);
else
- keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(4);
+ keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(dev, 4);

memcpy(keystart, key, keylen);
}
@@ -415,7 +427,7 @@ static void s5p_aes_crypt_start(struct s5p_aes_dev *dev, unsigned long mode)
if (err)
goto outdata_error;

- SSS_WRITE(dev, AES_CONTROL, aes_control);
+ SSS_AES_WRITE(dev, AES_CONTROL, aes_control);
s5p_set_aes(dev, dev->ctx->aes_key, req->info, dev->ctx->keylen);

s5p_set_dma_indata(dev, req->src);
@@ -618,6 +630,11 @@ static int s5p_aes_probe(struct platform_device *pdev)

pdata->version = find_s5p_sss_version(pdev);

+ if (pdata->version == SSS_VER_5)
+ pdata->aes_offset = 0x200;
+ else
+ pdata->aes_offset = 0x4000;
+
pdata->clk = devm_clk_get(dev, "secss");
if (IS_ERR(pdata->clk)) {
dev_err(dev, "failed to find secss clock source\n");
@@ -643,17 +660,23 @@ static int s5p_aes_probe(struct platform_device *pdev)
goto err_irq;
}

+ /*
+ * SSS module present in Exynos5 Series SoCs
+ * does not use hash interrupt
+ */
pdata->irq_hash = platform_get_irq(pdev, 1);
- if (pdata->irq_hash < 0) {
+ if ((pdata->version == SSS_VER_4) && (pdata->irq_hash < 0)) {
err = pdata->irq_hash;
dev_warn(dev, "hash interrupt is not available.\n");
goto err_irq;
}
- err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
- IRQF_SHARED, pdev->name, pdev);
- if (err < 0) {
- dev_warn(dev, "hash interrupt is not available.\n");
- goto err_irq;
+ if (pdata->version == SSS_VER_4) {
+ err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
+ IRQF_SHARED, pdev->name, pdev);
+ if (err < 0) {
+ dev_warn(dev, "hash interrupt is not available.\n");
+ goto err_irq;
+ }
}

pdata->dev = dev;
--
1.7.9.5

2014-01-07 11:51:44

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Subject: [PATCH 5/5] ARM: exynos5420: add dt node for sss module

From: Naveen Krishna Chatradhi <[email protected]>

this patch adds the device tree nodes for SSS module found on Exynos5420

Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
TO: <[email protected]>
CC: Kukjin Kim <[email protected]>
CC: <[email protected]>
---
arch/arm/boot/dts/exynos5420.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 11dd202..97045f9 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -652,4 +652,14 @@
clocks = <&clock 319>, <&clock 318>;
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
};
+
+ sss: sss {
+ compatible = "samsung,exynos-secss";
+ reg = <0x10830000 0x10000>;
+ interrupts = <0 112 0>;
+ clocks = <&clock 471>;
+ clock-names = "secss";
+ samsung,power-domain = <&g2d_pd>;
+ };
+
};
--
1.7.9.5

2014-01-07 11:51:46

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Subject: [PATCH 2/5] crypto:s5p-sss: Add device tree and Exynos5 support

This patch adds device tree support along with a new
compatible string to support Exynos5 SoCs (SSS_VER_5).

Also, Documentation under devicetree/bindings added.

Signed-off-by: Naveen Krishna Ch <[email protected]>
CC: Herbert Xu <[email protected]>
CC: David S. Miller <[email protected]>
CC: Vladimir Zapolskiy <[email protected]>
TO: <[email protected]>
CC: <[email protected]>
---
.../devicetree/bindings/crypto/samsung-sss.txt | 24 ++++++++++++
drivers/crypto/s5p-sss.c | 40 ++++++++++++++++++++
2 files changed, 64 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/samsung-sss.txt

diff --git a/Documentation/devicetree/bindings/crypto/samsung-sss.txt b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
new file mode 100644
index 0000000..8871a29
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
@@ -0,0 +1,24 @@
+Samsung SoC SSS crypto Module
+
+Required properties:
+
+- compatible : Should contain entries for this and backward compatible
+ SSS versions:
+ - "samsung,exynos-secss" for S5PV210.
+ - "samsung,s5p-secss" for Exynos5 series SoCs.
+ TBD: SSS module on Exynos5 SoCs supports other algorithms,
+ support for the is yet to be added in the driver.
+- reg : Offset and length of the register set for the module
+- interrupts : the interrupt-specifier for the SSS module.
+- clocks : the required gating clock for the SSS module.
+- clock-names : the gating clock name requested in the SSS driver.
+
+Example:
+ /* SSS_VER_5 */
+ sss: sss {
+ compatible = "samsung,exynos-secss";
+ reg = <0x10830000 0x10000>;
+ interrupts = <0 112 0>;
+ clocks = <&clock 471>;
+ clock-names = "secss";
+ };
diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
index dda4551..dcb9fc1 100644
--- a/drivers/crypto/s5p-sss.c
+++ b/drivers/crypto/s5p-sss.c
@@ -22,6 +22,7 @@
#include <linux/scatterlist.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>
+#include <linux/of.h>
#include <linux/crypto.h>
#include <linux/interrupt.h>

@@ -173,10 +174,45 @@ struct s5p_aes_dev {
struct crypto_queue queue;
bool busy;
spinlock_t lock;
+
+ /* To support SSS versions across Samsung SoCs */
+ unsigned int version;
};

static struct s5p_aes_dev *s5p_dev;

+enum sss_version {
+ SSS_VER_4, /* SSS found on S5PV210 */
+ SSS_VER_5, /* SSS found on Exynos5 Series SoCs */
+};
+
+static struct platform_device_id s5p_sss_ids[] = {
+ {
+ .name = "s5p-secss",
+ .driver_data = SSS_VER_4,
+ }, { },
+};
+MODULE_DEVICE_TABLE(platform, s5p_sss_ids);
+
+static struct of_device_id s5p_sss_dt_match[] = {
+ { .compatible = "samsung,s5p-secss", .data = (void *)SSS_VER_4 },
+ { .compatible = "samsung,exynos-secss", .data = (void *)SSS_VER_5 },
+ { },
+};
+MODULE_DEVICE_TABLE(of, s5p_sss_dt_match);
+
+static inline unsigned int find_s5p_sss_version(struct platform_device *pdev)
+{
+#ifdef CONFIG_OF
+ if (pdev->dev.of_node) {
+ const struct of_device_id *match;
+ match = of_match_node(s5p_sss_dt_match, pdev->dev.of_node);
+ return (unsigned int)match->data;
+ }
+#endif
+ return platform_get_device_id(pdev)->driver_data;
+}
+
static void s5p_set_dma_indata(struct s5p_aes_dev *dev, struct scatterlist *sg)
{
SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg));
@@ -580,6 +616,8 @@ static int s5p_aes_probe(struct platform_device *pdev)
resource_size(res), pdev->name))
return -EBUSY;

+ pdata->version = find_s5p_sss_version(pdev);
+
pdata->clk = devm_clk_get(dev, "secss");
if (IS_ERR(pdata->clk)) {
dev_err(dev, "failed to find secss clock source\n");
@@ -674,9 +712,11 @@ static int s5p_aes_remove(struct platform_device *pdev)
static struct platform_driver s5p_aes_crypto = {
.probe = s5p_aes_probe,
.remove = s5p_aes_remove,
+ .id_table = s5p_sss_ids,
.driver = {
.owner = THIS_MODULE,
.name = "s5p-secss",
+ .of_match_table = s5p_sss_dt_match,
},
};

--
1.7.9.5

2014-01-08 00:14:36

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Subject: Re: [PATCH 1/5] crypto:s5p-sss: Use platform_get_irq() instead of _byname()

Hi Naveen,

Please see my comments inline.

On Tuesday 07 of January 2014 17:21:45 Naveen Krishna Ch wrote:
> This patch uses the platform_get_irq() instead of the
> platform_get_irq_byname(). Making feeder control interrupt
> as resource "0" and hash interrupt as "1".
>
> reasons for this change.
> 1. Cannot find any Arch which is currently using this driver
> 2. Samsung Exynos5 SoCs only use the feeder control interrupt
> 3. Patches adding support for DT and H/W version are in pipeline
>
> Signed-off-by: Naveen Krishna Ch <[email protected]>
> CC: Herbert Xu <[email protected]>
> CC: David S. Miller <[email protected]>
> CC: Vladimir Zapolskiy <[email protected]>
> TO: <[email protected]>
> CC: <[email protected]>
> ---
> drivers/crypto/s5p-sss.c | 22 +++++++++++-----------
> 1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
> index cf149b1..dda4551 100644
> --- a/drivers/crypto/s5p-sss.c
> +++ b/drivers/crypto/s5p-sss.c
> @@ -592,29 +592,29 @@ static int s5p_aes_probe(struct platform_device *pdev)
> pdata->ioaddr = devm_ioremap(dev, res->start,
> resource_size(res));
>
> - pdata->irq_hash = platform_get_irq_byname(pdev, "hash");
> - if (pdata->irq_hash < 0) {
> + pdata->irq_fc = platform_get_irq(pdev, 0);
> + if (pdata->irq_fc < 0) {
> err = pdata->irq_hash;

Shouldn't this be also changed to err = pdata->irq_fc; ?

Best regards,
Tomasz

2014-01-08 00:25:05

[permalink] [raw]

Subject: Re: [PATCH 2/5] crypto:s5p-sss: Add device tree and Exynos5 support

Hi Naveen,

Please see my comments inline.

On Tuesday 07 of January 2014 17:21:46 Naveen Krishna Ch wrote:
> This patch adds device tree support along with a new
> compatible string to support Exynos5 SoCs (SSS_VER_5).
>
> Also, Documentation under devicetree/bindings added.
>
> Signed-off-by: Naveen Krishna Ch <[email protected]>
> CC: Herbert Xu <[email protected]>
> CC: David S. Miller <[email protected]>
> CC: Vladimir Zapolskiy <[email protected]>
> TO: <[email protected]>
> CC: <[email protected]>
> ---
> .../devicetree/bindings/crypto/samsung-sss.txt | 24 ++++++++++++
> drivers/crypto/s5p-sss.c | 40 ++++++++++++++++++++
> 2 files changed, 64 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/crypto/samsung-sss.txt
>
> diff --git a/Documentation/devicetree/bindings/crypto/samsung-sss.txt b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
> new file mode 100644
> index 0000000..8871a29
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
> @@ -0,0 +1,24 @@
> +Samsung SoC SSS crypto Module

A sentence or two explaining what this module is would be nice.

> +
> +Required properties:
> +
> +- compatible : Should contain entries for this and backward compatible
> + SSS versions:
> + - "samsung,exynos-secss" for S5PV210.
> + - "samsung,s5p-secss" for Exynos5 series SoCs.

Hmm, this doesn't make any sense, Exynos for S5PV210 and S5P for
Exynos5...

Please use specific compatible strings containing names of first SoC in
which given compatible IP block appeared. E.g. "samsung,s5pv210-secss"
and "samsung,exynos5250-secss" (if S5PV210 and Exynos5 have been first
respectively).

> + TBD: SSS module on Exynos5 SoCs supports other algorithms,
> + support for the is yet to be added in the driver.

This has nothing to do with DT bindings.

> +- reg : Offset and length of the register set for the module
> +- interrupts : the interrupt-specifier for the SSS module.

It should be specified how many entries should be specified and what are
their meanings.

> +- clocks : the required gating clock for the SSS module.
> +- clock-names : the gating clock name requested in the SSS driver.

The name should be specified and no dependency on the driver should be
made (it's the driver that should follow the bindings, not the other
way around).

> +
> +Example:
> + /* SSS_VER_5 */
> + sss: sss {

Should be sss: sss@10830000 as per ePAPR recommendation about node naming.

> + compatible = "samsung,exynos-secss";
> + reg = <0x10830000 0x10000>;
> + interrupts = <0 112 0>;
> + clocks = <&clock 471>;
> + clock-names = "secss";
> + };
> diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
> index dda4551..dcb9fc1 100644
> --- a/drivers/crypto/s5p-sss.c
> +++ b/drivers/crypto/s5p-sss.c
> @@ -22,6 +22,7 @@
> #include <linux/scatterlist.h>
> #include <linux/dma-mapping.h>
> #include <linux/io.h>
> +#include <linux/of.h>
> #include <linux/crypto.h>
> #include <linux/interrupt.h>
>
> @@ -173,10 +174,45 @@ struct s5p_aes_dev {
> struct crypto_queue queue;
> bool busy;
> spinlock_t lock;
> +
> + /* To support SSS versions across Samsung SoCs */
> + unsigned int version;
> };
>
> static struct s5p_aes_dev *s5p_dev;
>
> +enum sss_version {
> + SSS_VER_4, /* SSS found on S5PV210 */
> + SSS_VER_5, /* SSS found on Exynos5 Series SoCs */
> +};
> +
> +static struct platform_device_id s5p_sss_ids[] = {

static const struct platform_device_id

> + {
> + .name = "s5p-secss",
> + .driver_data = SSS_VER_4,
> + }, { },
> +};
> +MODULE_DEVICE_TABLE(platform, s5p_sss_ids);
> +

#ifdef CONFIG_OF

> +static struct of_device_id s5p_sss_dt_match[] = {

static const struct of_device_id

> + { .compatible = "samsung,s5p-secss", .data = (void *)SSS_VER_4 },
> + { .compatible = "samsung,exynos-secss", .data = (void *)SSS_VER_5 },

Does this driver already support SSS version 5 at this stage? Aren't
further patches needed for this?

> + { },
> +};
> +MODULE_DEVICE_TABLE(of, s5p_sss_dt_match);

#endif

> +
> +static inline unsigned int find_s5p_sss_version(struct platform_device *pdev)
> +{
> +#ifdef CONFIG_OF
> + if (pdev->dev.of_node) {

Please use IS_ENABLED() helper inside the if instead of #ifdef.

> + const struct of_device_id *match;
> + match = of_match_node(s5p_sss_dt_match, pdev->dev.of_node);
> + return (unsigned int)match->data;
> + }
> +#endif
> + return platform_get_device_id(pdev)->driver_data;
> +}
> +
> static void s5p_set_dma_indata(struct s5p_aes_dev *dev, struct scatterlist *sg)
> {
> SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg));
> @@ -580,6 +616,8 @@ static int s5p_aes_probe(struct platform_device *pdev)
> resource_size(res), pdev->name))
> return -EBUSY;
>
> + pdata->version = find_s5p_sss_version(pdev);

Instead of storing a version number, I would rather consider using
a variant struct containing version-specific data.

> +
> pdata->clk = devm_clk_get(dev, "secss");
> if (IS_ERR(pdata->clk)) {
> dev_err(dev, "failed to find secss clock source\n");
> @@ -674,9 +712,11 @@ static int s5p_aes_remove(struct platform_device *pdev)
> static struct platform_driver s5p_aes_crypto = {
> .probe = s5p_aes_probe,
> .remove = s5p_aes_remove,
> + .id_table = s5p_sss_ids,
> .driver = {
> .owner = THIS_MODULE,
> .name = "s5p-secss",
> + .of_match_table = s5p_sss_dt_match,

of_match_ptr() macro should be used instead of passing s5p_sss_dt_match
directly.

Best regards,
Tomasz

2014-01-08 00:29:09

[permalink] [raw]

Subject: Re: [PATCH 3/5] crypto:s5p-sss: Add support for SSS module on Exynos5

Hi Naveen,

Please see my comments inline.

On Tuesday 07 of January 2014 17:21:47 Naveen Krishna Ch wrote:
> The differences between SSS modules on S5PV210 and Exynos5
> (AFA the driver supports)
> 1. AES register are at an offset of 0x200 on Exynos5
> 2. hash interrupt is no longer needed on Exynos5

What about Exynos 4 SoCs? Do they have S5PV210- or Exynos5-style security
block?

>
> This patch adds code needed to address the above changes.
>
> Signed-off-by: Naveen Krishna Ch <[email protected]>
> CC: Herbert Xu <[email protected]>
> CC: David S. Miller <[email protected]>
> CC: Vladimir Zapolskiy <[email protected]>
> TO: <[email protected]>
> CC: <[email protected]>
> ---
> drivers/crypto/s5p-sss.c | 59 ++++++++++++++++++++++++++++++++--------------
> 1 file changed, 41 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
> index dcb9fc1..a11cd0e 100644
> --- a/drivers/crypto/s5p-sss.c
> +++ b/drivers/crypto/s5p-sss.c
> @@ -106,7 +106,7 @@
> #define SSS_REG_FCPKDMAO 0x005C
>
> /* AES registers */
> -#define SSS_REG_AES_CONTROL 0x4000
> +#define SSS_REG_AES_CONTROL(dev) ((dev)->aes_offset + 0x00)

This is ugly. Please consider using a variant struct to store addresses
of registers that depend on IP version.

> #define SSS_AES_BYTESWAP_DI _BIT(11)
> #define SSS_AES_BYTESWAP_DO _BIT(10)
> #define SSS_AES_BYTESWAP_IV _BIT(9)
> @@ -122,21 +122,26 @@
> #define SSS_AES_CHAIN_MODE_CTR _SBF(1, 0x02)
> #define SSS_AES_MODE_DECRYPT _BIT(0)
>
> -#define SSS_REG_AES_STATUS 0x4004
> +#define SSS_REG_AES_STATUS(dev) ((dev)->aes_offset + 0x04)

Ditto.

> #define SSS_AES_BUSY _BIT(2)
> #define SSS_AES_INPUT_READY _BIT(1)
> #define SSS_AES_OUTPUT_READY _BIT(0)
>
> -#define SSS_REG_AES_IN_DATA(s) (0x4010 + (s << 2))
> -#define SSS_REG_AES_OUT_DATA(s) (0x4020 + (s << 2))
> -#define SSS_REG_AES_IV_DATA(s) (0x4030 + (s << 2))
> -#define SSS_REG_AES_CNT_DATA(s) (0x4040 + (s << 2))
> -#define SSS_REG_AES_KEY_DATA(s) (0x4080 + (s << 2))
> +#define SSS_REG_AES_IN_DATA(dev, s) ((dev)->aes_offset + 0x10 + (s << 2))
> +#define SSS_REG_AES_OUT_DATA(dev, s) ((dev)->aes_offset + 0x20 + (s << 2))
> +#define SSS_REG_AES_IV_DATA(dev, s) ((dev)->aes_offset + 0x30 + (s << 2))
> +#define SSS_REG_AES_CNT_DATA(dev, s) ((dev)->aes_offset + 0x40 + (s << 2))
> +#define SSS_REG_AES_KEY_DATA(dev, s) ((dev)->aes_offset + 0x80 + (s << 2))

Ditto.

>
> #define SSS_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg))
> #define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg))
> #define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg))
>
> +#define SSS_AES_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg(dev)))
> +#define SSS_AES_READ(dev, reg) __raw_readl(SSS_AES_REG(dev, reg))
> +#define SSS_AES_WRITE(dev, reg, val) __raw_writel((val), \
> + SSS_AES_REG(dev, reg))
> +
> /* HW engine modes */
> #define FLAGS_AES_DECRYPT _BIT(0)
> #define FLAGS_AES_MODE_MASK _SBF(1, 0x03)
> @@ -177,6 +182,13 @@ struct s5p_aes_dev {
>
> /* To support SSS versions across Samsung SoCs */
> unsigned int version;
> +
> + /*
> + * Register banks corresponding to various algorithms
> + * (Ex: AES, TDES, HASH, TRNG, PKA etc.)
> + * are at an offsets from the base (depending on SSS verion)
> + */
> + unsigned int aes_offset;

This is a candidate to be stored inside a variant struct.

> };
>
> static struct s5p_aes_dev *s5p_dev;
> @@ -358,14 +370,14 @@ static void s5p_set_aes(struct s5p_aes_dev *dev,
> {
> void __iomem *keystart;
>
> - memcpy(dev->ioaddr + SSS_REG_AES_IV_DATA(0), iv, 0x10);
> + memcpy(dev->ioaddr + SSS_REG_AES_IV_DATA(dev, 0), iv, 0x10);
>
> if (keylen == AES_KEYSIZE_256)
> - keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(0);
> + keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(dev, 0);
> else if (keylen == AES_KEYSIZE_192)
> - keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(2);
> + keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(dev, 2);
> else
> - keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(4);
> + keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(dev, 4);
>
> memcpy(keystart, key, keylen);
> }
> @@ -415,7 +427,7 @@ static void s5p_aes_crypt_start(struct s5p_aes_dev *dev, unsigned long mode)
> if (err)
> goto outdata_error;
>
> - SSS_WRITE(dev, AES_CONTROL, aes_control);
> + SSS_AES_WRITE(dev, AES_CONTROL, aes_control);
> s5p_set_aes(dev, dev->ctx->aes_key, req->info, dev->ctx->keylen);
>
> s5p_set_dma_indata(dev, req->src);
> @@ -618,6 +630,11 @@ static int s5p_aes_probe(struct platform_device *pdev)
>
> pdata->version = find_s5p_sss_version(pdev);
>
> + if (pdata->version == SSS_VER_5)
> + pdata->aes_offset = 0x200;
> + else
> + pdata->aes_offset = 0x4000;
> +

Using a variant struct if clauses like this would be eliminated.

> pdata->clk = devm_clk_get(dev, "secss");
> if (IS_ERR(pdata->clk)) {
> dev_err(dev, "failed to find secss clock source\n");
> @@ -643,17 +660,23 @@ static int s5p_aes_probe(struct platform_device *pdev)
> goto err_irq;
> }
>
> + /*
> + * SSS module present in Exynos5 Series SoCs
> + * does not use hash interrupt
> + */
> pdata->irq_hash = platform_get_irq(pdev, 1);
> - if (pdata->irq_hash < 0) {
> + if ((pdata->version == SSS_VER_4) && (pdata->irq_hash < 0)) {

A boolean field "has_hash_irq" in a variant struct could be used to tell
whether this interrupt is needed instead of relying on version.

Best regards,
Tomasz

2014-01-08 00:30:01

[permalink] [raw]

Subject: Re: [PATCH 4/5] crypto:s5p-sss: Exynos5 SoCs too can select SSS driver

On Tuesday 07 of January 2014 17:21:48 Naveen Krishna Ch wrote:
> This patch modifies Kconfig such that ARCH_EXYNOS5 SoCs
> can also select Samsung SSS(Security SubSystem) driver.
>
> Signed-off-by: Naveen Krishna Ch <[email protected]>
> CC: Herbert Xu <[email protected]>
> CC: David S. Miller <[email protected]>
> CC: Vladimir Zapolskiy <[email protected]>
> TO: <[email protected]>
> CC: <[email protected]>
> ---
> drivers/crypto/Kconfig | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
> index f4fd837..137dcd8 100644
> --- a/drivers/crypto/Kconfig
> +++ b/drivers/crypto/Kconfig
> @@ -300,15 +300,15 @@ config CRYPTO_DEV_DCP
> capabilities of the DCP co-processor
>
> config CRYPTO_DEV_S5P
> - tristate "Support for Samsung S5PV210 crypto accelerator"
> - depends on ARCH_S5PV210
> + tristate "Support for Samsung crypto accelerator"
> + depends on ARCH_S5PV210 || ARCH_EXYNOS5
> select CRYPTO_AES
> select CRYPTO_ALGAPI
> select CRYPTO_BLKCIPHER
> help
> This option allows you to have support for S5P crypto acceleration.
> - Select this to offload Samsung S5PV210 or S5PC110 from AES
> - algorithms execution.
> + Select this to offload Samsung S5PV210 or S5PC110, Exynos5250
> + and Exynos5420 from AES algorithms execution.

What about Exynos4 SoCs?

Best regards,
Tomasz

2014-01-08 00:32:41

[permalink] [raw]

Subject: Re: [PATCH 5/5] ARM: exynos5420: add dt node for sss module

On Tuesday 07 of January 2014 17:21:49 Naveen Krishna Ch wrote:
> From: Naveen Krishna Chatradhi <[email protected]>
>
> this patch adds the device tree nodes for SSS module found on Exynos5420

nit: Sentences in English start with a capital letter. Also this patch
adds one node, not few of them as the description suggests.

Also patch subject should start with ARM: dts: prefix.

>
> Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
> TO: <[email protected]>
> CC: Kukjin Kim <[email protected]>
> CC: <[email protected]>
> ---
> arch/arm/boot/dts/exynos5420.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
> index 11dd202..97045f9 100644
> --- a/arch/arm/boot/dts/exynos5420.dtsi
> +++ b/arch/arm/boot/dts/exynos5420.dtsi
> @@ -652,4 +652,14 @@
> clocks = <&clock 319>, <&clock 318>;
> clock-names = "tmu_apbif", "tmu_triminfo_apbif";
> };
> +
> + sss: sss {

Node name should be sss@10830000 as per ePAPR node naming recommendation.

Best regards,
Tomasz

2014-01-09 04:26:13

[permalink] [raw]

Subject: Re: [PATCH 5/5] ARM: exynos5420: add dt node for sss module

Hello Tomasz,

On 8 January 2014 06:02, Tomasz Figa <[email protected]> wrote:
> On Tuesday 07 of January 2014 17:21:49 Naveen Krishna Ch wrote:
>> From: Naveen Krishna Chatradhi <[email protected]>
>>
>> this patch adds the device tree nodes for SSS module found on Exynos5420
>
> nit: Sentences in English start with a capital letter. Also this patch
> adds one node, not few of them as the description suggests.
>
> Also patch subject should start with ARM: dts: prefix.
>
>>
>> Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
>> TO: <[email protected]>
>> CC: Kukjin Kim <[email protected]>
>> CC: <[email protected]>
>> ---
>> arch/arm/boot/dts/exynos5420.dtsi | 10 ++++++++++
>> 1 file changed, 10 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
>> index 11dd202..97045f9 100644
>> --- a/arch/arm/boot/dts/exynos5420.dtsi
>> +++ b/arch/arm/boot/dts/exynos5420.dtsi
>> @@ -652,4 +652,14 @@
>> clocks = <&clock 319>, <&clock 318>;
>> clock-names = "tmu_apbif", "tmu_triminfo_apbif";
>> };
>> +
>> + sss: sss {
>
> Node name should be sss@10830000 as per ePAPR node naming recommendation.
Thanks for the correction, Will correct it and submit. Thanks
>
> Best regards,
> Tomasz
>

--
Shine bright,
(: Nav :)

2014-01-09 04:27:41

[permalink] [raw]

Subject: Re: [PATCH 4/5] crypto:s5p-sss: Exynos5 SoCs too can select SSS driver

Hello Tomasz,

On 8 January 2014 06:00, Tomasz Figa <[email protected]> wrote:
> On Tuesday 07 of January 2014 17:21:48 Naveen Krishna Ch wrote:
>> This patch modifies Kconfig such that ARCH_EXYNOS5 SoCs
>> can also select Samsung SSS(Security SubSystem) driver.
>>
>> Signed-off-by: Naveen Krishna Ch <[email protected]>
>> CC: Herbert Xu <[email protected]>
>> CC: David S. Miller <[email protected]>
>> CC: Vladimir Zapolskiy <[email protected]>
>> TO: <[email protected]>
>> CC: <[email protected]>
>> ---
>> drivers/crypto/Kconfig | 8 ++++----
>> 1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
>> index f4fd837..137dcd8 100644
>> --- a/drivers/crypto/Kconfig
>> +++ b/drivers/crypto/Kconfig
>> @@ -300,15 +300,15 @@ config CRYPTO_DEV_DCP
>> capabilities of the DCP co-processor
>>
>> config CRYPTO_DEV_S5P
>> - tristate "Support for Samsung S5PV210 crypto accelerator"
>> - depends on ARCH_S5PV210
>> + tristate "Support for Samsung crypto accelerator"
>> + depends on ARCH_S5PV210 || ARCH_EXYNOS5
>> select CRYPTO_AES
>> select CRYPTO_ALGAPI
>> select CRYPTO_BLKCIPHER
>> help
>> This option allows you to have support for S5P crypto acceleration.
>> - Select this to offload Samsung S5PV210 or S5PC110 from AES
>> - algorithms execution.
>> + Select this to offload Samsung S5PV210 or S5PC110, Exynos5250
>> + and Exynos5420 from AES algorithms execution.
>
> What about Exynos4 SoCs?
The SSS module as such looks alike on Exynos5250, Exynso5420 and Exynos4210.
I couldn't test it right now. I should also verify on other Exynos4 SoCs.
>
> Best regards,
> Tomasz
>

--
Shine bright,
(: Nav :)

2014-01-09 04:58:21

[permalink] [raw]

Subject: [PATCH 1/6 v2] crypto:s5p-sss: Use platform_get_irq() instead of _byname()

From: Naveen Krishna Ch <[email protected]>

This patch uses the platform_get_irq() instead of the
platform_get_irq_byname(). Making feeder control interrupt
as resource "0" and hash interrupt as "1".

reasons for this change.
1. Cannot find any Arch which is currently using this driver
2. Samsung Exynos4 and 5 SoCs only use the feeder control interrupt
3. Patches adding support for DT and H/W version are in pipeline

Signed-off-by: Naveen Krishna Ch <[email protected]>
CC: Herbert Xu <[email protected]>
CC: David S. Miller <[email protected]>
CC: Vladimir Zapolskiy <[email protected]>
TO: <[email protected]>
CC: <[email protected]>
---
Changes since v1:
A typo fixed, from err "pdata->irq_hash;" to "pdata->irq_fc;"

drivers/crypto/s5p-sss.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
index cf149b1..93cddeb 100644
--- a/drivers/crypto/s5p-sss.c
+++ b/drivers/crypto/s5p-sss.c
@@ -592,29 +592,29 @@ static int s5p_aes_probe(struct platform_device *pdev)
pdata->ioaddr = devm_ioremap(dev, res->start,
resource_size(res));

- pdata->irq_hash = platform_get_irq_byname(pdev, "hash");
- if (pdata->irq_hash < 0) {
- err = pdata->irq_hash;
- dev_warn(dev, "hash interrupt is not available.\n");
+ pdata->irq_fc = platform_get_irq(pdev, 0);
+ if (pdata->irq_fc < 0) {
+ err = pdata->irq_fc;
+ dev_warn(dev, "feed control interrupt is not available.\n");
goto err_irq;
}
- err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
+ err = devm_request_irq(dev, pdata->irq_fc, s5p_aes_interrupt,
IRQF_SHARED, pdev->name, pdev);
if (err < 0) {
- dev_warn(dev, "hash interrupt is not available.\n");
+ dev_warn(dev, "feed control interrupt is not available.\n");
goto err_irq;
}

- pdata->irq_fc = platform_get_irq_byname(pdev, "feed control");
- if (pdata->irq_fc < 0) {
- err = pdata->irq_fc;
- dev_warn(dev, "feed control interrupt is not available.\n");
+ pdata->irq_hash = platform_get_irq(pdev, 1);
+ if (pdata->irq_hash < 0) {
+ err = pdata->irq_hash;
+ dev_warn(dev, "hash interrupt is not available.\n");
goto err_irq;
}
- err = devm_request_irq(dev, pdata->irq_fc, s5p_aes_interrupt,
+ err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
IRQF_SHARED, pdev->name, pdev);
if (err < 0) {
- dev_warn(dev, "feed control interrupt is not available.\n");
+ dev_warn(dev, "hash interrupt is not available.\n");
goto err_irq;
}

--
1.7.9.5

2014-01-09 04:59:01

[permalink] [raw]

Subject: [PATCH 2/6 v2] crypto:s5p-sss: Add device tree support

This patch adds device tree support to the s5p-sss.c crypto driver.
Implements a varient struct to address the changes in SSS hardware
on various SoCs from Samsung.

Also, Documentation under devicetree/bindings added.

Signed-off-by: Naveen Krishna Ch <[email protected]>
CC: Herbert Xu <[email protected]>
CC: David S. Miller <[email protected]>
CC: Vladimir Zapolskiy <[email protected]>
TO: <[email protected]>
CC: <[email protected]>
---
Changes since v1:
1. Added description of the SSS module in Documentation
2. Corrected the interrupts description
3. Added varient struct instead of the version variable

.../devicetree/bindings/crypto/samsung-sss.txt | 20 +++++
drivers/crypto/s5p-sss.c | 81 ++++++++++++++++++--
2 files changed, 95 insertions(+), 6 deletions(-)
create mode 100644 Documentation/devicetree/bindings/crypto/samsung-sss.txt

diff --git a/Documentation/devicetree/bindings/crypto/samsung-sss.txt b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
new file mode 100644
index 0000000..0e45b0d
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
@@ -0,0 +1,20 @@
+Samsung SoC SSS (Security SubSystem) module
+
+The SSS module in S5PV210 SoC supports the following:
+-- Feeder (FeedCtrl)
+-- Advanced Encryption Standard (AES)
+-- Data Encryption Standard (DES)/3DES
+-- Public Key Accelerator (PKA)
+-- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
+-- PRNG: Pseudo Random Number Generator
+
+Required properties:
+
+- compatible : Should contain entries for this and backward compatible
+ SSS versions:
+ - "samsung,s5p-secss" for S5PV210 SoC.
+- reg : Offset and length of the register set for the module
+- interrupts : the interrupt-specifier for the SSS module.
+ Two interrupts "feed control and hash" in case of S5PV210
+- clocks : the required gating clock for the SSS module.
+- clock-names : the gating clock name to be requested in the SSS driver.
diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
index 93cddeb..78e0c37 100644
--- a/drivers/crypto/s5p-sss.c
+++ b/drivers/crypto/s5p-sss.c
@@ -22,6 +22,7 @@
#include <linux/scatterlist.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>
+#include <linux/of.h>
#include <linux/crypto.h>
#include <linux/interrupt.h>

@@ -145,6 +146,20 @@
#define AES_KEY_LEN 16
#define CRYPTO_QUEUE_LEN 1

+/**
+ * struct samsung_aes_varient - platform specific SSS driver data
+ * @has_hash_irq: true if SSS module uses hash interrupt, false otherwise
+ * @aes_offset: AES register offset from SSS module's base.
+ *
+ * Specifies platform specific configuration of SSS module.
+ * Note: A structure for driver specific platform data is used for future
+ * expansion of its usage.
+ */
+struct samsung_aes_varient {
+ bool has_hash_irq;
+ unsigned int aes_offset;
+};
+
struct s5p_aes_reqctx {
unsigned long mode;
};
@@ -173,10 +188,56 @@ struct s5p_aes_dev {
struct crypto_queue queue;
bool busy;
spinlock_t lock;
+
+ struct samsung_aes_varient *varient;
};

static struct s5p_aes_dev *s5p_dev;

+static struct samsung_aes_varient s5p_aes_data = {
+ .has_hash_irq = true,
+ .aes_offset = 0x4000,
+};
+
+static const struct platform_device_id s5p_sss_ids[] = {
+ {
+ .name = "s5p-secss",
+ .driver_data = (kernel_ulong_t)&s5p_aes_data,
+ },
+ { },
+};
+MODULE_DEVICE_TABLE(platform, s5p_sss_ids);
+
+#ifdef CONFIG_OF
+static const struct of_device_id s5p_sss_dt_match[] = {
+ {
+ .compatible = "samsung,s5p-secss",
+ .data = (void *)&s5p_aes_data,
+ },
+ { },
+};
+MODULE_DEVICE_TABLE(of, s5p_sss_dt_match);
+#else
+static struct of_device_id s5p_sss_dt_match[] = {
+ { },
+};
+#endif
+
+static inline struct samsung_aes_varient *find_s5p_sss_version
+ (struct platform_device *pdev)
+{
+ if (IS_ENABLED(CONFIG_OF)) {
+ if (pdev->dev.of_node) {
+ const struct of_device_id *match;
+ match = of_match_node(s5p_sss_dt_match,
+ pdev->dev.of_node);
+ return (struct samsung_aes_varient *)match->data;
+ }
+ }
+ return (struct samsung_aes_varient *)
+ platform_get_device_id(pdev)->driver_data;
+}
+
static void s5p_set_dma_indata(struct s5p_aes_dev *dev, struct scatterlist *sg)
{
SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg));
@@ -564,6 +625,7 @@ static int s5p_aes_probe(struct platform_device *pdev)
struct s5p_aes_dev *pdata;
struct device *dev = &pdev->dev;
struct resource *res;
+ struct samsung_aes_varient *varient;

if (s5p_dev)
return -EEXIST;
@@ -580,6 +642,8 @@ static int s5p_aes_probe(struct platform_device *pdev)
resource_size(res), pdev->name))
return -EBUSY;

+ varient = find_s5p_sss_version(pdev);
+
pdata->clk = devm_clk_get(dev, "secss");
if (IS_ERR(pdata->clk)) {
dev_err(dev, "failed to find secss clock source\n");
@@ -606,18 +670,21 @@ static int s5p_aes_probe(struct platform_device *pdev)
}

pdata->irq_hash = platform_get_irq(pdev, 1);
- if (pdata->irq_hash < 0) {
+ if (varient->has_hash_irq && pdata->irq_hash < 0) {
err = pdata->irq_hash;
dev_warn(dev, "hash interrupt is not available.\n");
goto err_irq;
}
- err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
- IRQF_SHARED, pdev->name, pdev);
- if (err < 0) {
- dev_warn(dev, "hash interrupt is not available.\n");
- goto err_irq;
+ if (varient->has_hash_irq) {
+ err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
+ IRQF_SHARED, pdev->name, pdev);
+ if (err < 0) {
+ dev_warn(dev, "hash interrupt is not available.\n");
+ goto err_irq;
+ }
}

+ pdata->varient = varient;
pdata->dev = dev;
platform_set_drvdata(pdev, pdata);
s5p_dev = pdata;
@@ -674,9 +741,11 @@ static int s5p_aes_remove(struct platform_device *pdev)
static struct platform_driver s5p_aes_crypto = {
.probe = s5p_aes_probe,
.remove = s5p_aes_remove,
+ .id_table = s5p_sss_ids,
.driver = {
.owner = THIS_MODULE,
.name = "s5p-secss",
+ .of_match_table = s5p_sss_dt_match,
},
};

--
1.7.9.5

2014-01-09 04:59:29

[permalink] [raw]

Subject: [PATCH 3/6 v2] crypto:s5p-sss: Add support for SSS module on Exynos

This patch adds new compatible and varient to support the SSS module
on Exynos4 (Exynos4210), Exynos5 (Exynos5420 and Exynos5250) for which
1. AES register are at an offset of 0x200 and
2. hash interrupt is not available

Signed-off-by: Naveen Krishna Ch <[email protected]>
CC: Herbert Xu <[email protected]>
CC: David S. Miller <[email protected]>
CC: Vladimir Zapolskiy <[email protected]>
TO: <[email protected]>
CC: <[email protected]>
---
Changes since v1:
1. Used varient struct
2. Added description in Documentation

.../devicetree/bindings/crypto/samsung-sss.txt | 20 +++++++++
drivers/crypto/s5p-sss.c | 43 ++++++++++++++------
2 files changed, 51 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/crypto/samsung-sss.txt b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
index 0e45b0d..4531da2 100644
--- a/Documentation/devicetree/bindings/crypto/samsung-sss.txt
+++ b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
@@ -8,13 +8,33 @@ The SSS module in S5PV210 SoC supports the following:
-- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
-- PRNG: Pseudo Random Number Generator

+The SSS module in Exynos4 (Exynos4210) and
+Exynos5 (Exynos5420 and Exynos5250) SoCs
+supports the following also:
+-- ARCFOUR (ARC4)
+-- True Random Number Generator (TRNG)
+-- Secure Key Manager
+
Required properties:

- compatible : Should contain entries for this and backward compatible
SSS versions:
- "samsung,s5p-secss" for S5PV210 SoC.
+ - "samsung,exynos-secss" for Exynos4210, Exynos5250 and Exynos5420 SoCs.
- reg : Offset and length of the register set for the module
- interrupts : the interrupt-specifier for the SSS module.
Two interrupts "feed control and hash" in case of S5PV210
+ One interrupts "feed control" in case of Exynos4210,
+ Exynos5250 and Exynos5420 SoCs.
- clocks : the required gating clock for the SSS module.
- clock-names : the gating clock name to be requested in the SSS driver.
+
+Example:
+ /* SSS_VER_5 */
+ sss@10830000 {
+ compatible = "samsung,exynos-secss";
+ reg = <0x10830000 0x10000>;
+ interrupts = <0 112 0>;
+ clocks = <&clock 471>;
+ clock-names = "secss";
+ };
diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
index 78e0c37..7c31a5f 100644
--- a/drivers/crypto/s5p-sss.c
+++ b/drivers/crypto/s5p-sss.c
@@ -106,7 +106,7 @@
#define SSS_REG_FCPKDMAO 0x005C

/* AES registers */
-#define SSS_REG_AES_CONTROL 0x4000
+#define SSS_REG_AES_CONTROL 0x00
#define SSS_AES_BYTESWAP_DI _BIT(11)
#define SSS_AES_BYTESWAP_DO _BIT(10)
#define SSS_AES_BYTESWAP_IV _BIT(9)
@@ -122,21 +122,26 @@
#define SSS_AES_CHAIN_MODE_CTR _SBF(1, 0x02)
#define SSS_AES_MODE_DECRYPT _BIT(0)

-#define SSS_REG_AES_STATUS 0x4004
+#define SSS_REG_AES_STATUS 0x04
#define SSS_AES_BUSY _BIT(2)
#define SSS_AES_INPUT_READY _BIT(1)
#define SSS_AES_OUTPUT_READY _BIT(0)

-#define SSS_REG_AES_IN_DATA(s) (0x4010 + (s << 2))
-#define SSS_REG_AES_OUT_DATA(s) (0x4020 + (s << 2))
-#define SSS_REG_AES_IV_DATA(s) (0x4030 + (s << 2))
-#define SSS_REG_AES_CNT_DATA(s) (0x4040 + (s << 2))
-#define SSS_REG_AES_KEY_DATA(s) (0x4080 + (s << 2))
+#define SSS_REG_AES_IN_DATA(off, s) ((off + 0x10) + (s << 2))
+#define SSS_REG_AES_OUT_DATA(off, s) ((off + 0x20) + (s << 2))
+#define SSS_REG_AES_IV_DATA(off, s) ((off + 0x30) + (s << 2))
+#define SSS_REG_AES_CNT_DATA(off, s) ((off + 0x40) + (s << 2))
+#define SSS_REG_AES_KEY_DATA(off, s) ((off + 0x80) + (s << 2))

#define SSS_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg))
#define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg))
#define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg))

+#define SSS_AES_REG(dev, reg) ((dev)->ioaddr + SSS_REG_##reg + \
+ dev->varient->aes_offset)
+#define SSS_AES_WRITE(dev, reg, val) __raw_writel((val), \
+ SSS_AES_REG(dev, reg))
+
/* HW engine modes */
#define FLAGS_AES_DECRYPT _BIT(0)
#define FLAGS_AES_MODE_MASK _SBF(1, 0x03)
@@ -199,6 +204,11 @@ static struct samsung_aes_varient s5p_aes_data = {
.aes_offset = 0x4000,
};

+static struct samsung_aes_varient exynos_aes_data = {
+ .has_hash_irq = false,
+ .aes_offset = 0x200,
+};
+
static const struct platform_device_id s5p_sss_ids[] = {
{
.name = "s5p-secss",
@@ -214,6 +224,10 @@ static const struct of_device_id s5p_sss_dt_match[] = {
.compatible = "samsung,s5p-secss",
.data = (void *)&s5p_aes_data,
},
+ {
+ .compatible = "samsung,exynos-secss",
+ .data = (void *)&exynos_aes_data,
+ },
{ },
};
MODULE_DEVICE_TABLE(of, s5p_sss_dt_match);
@@ -381,16 +395,21 @@ static irqreturn_t s5p_aes_interrupt(int irq, void *dev_id)
static void s5p_set_aes(struct s5p_aes_dev *dev,
uint8_t *key, uint8_t *iv, unsigned int keylen)
{
+ struct samsung_aes_varient *var = dev->varient;
void __iomem *keystart;

- memcpy(dev->ioaddr + SSS_REG_AES_IV_DATA(0), iv, 0x10);
+ memcpy(dev->ioaddr + SSS_REG_AES_IV_DATA
+ (var->aes_offset, 0), iv, 0x10);

if (keylen == AES_KEYSIZE_256)
- keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(0);
+ keystart = dev->ioaddr +
+ SSS_REG_AES_KEY_DATA(var->aes_offset, 0);
else if (keylen == AES_KEYSIZE_192)
- keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(2);
+ keystart = dev->ioaddr +
+ SSS_REG_AES_KEY_DATA(var->aes_offset, 2);
else
- keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(4);
+ keystart = dev->ioaddr +
+ SSS_REG_AES_KEY_DATA(var->aes_offset, 4);

memcpy(keystart, key, keylen);
}
@@ -440,7 +459,7 @@ static void s5p_aes_crypt_start(struct s5p_aes_dev *dev, unsigned long mode)
if (err)
goto outdata_error;

- SSS_WRITE(dev, AES_CONTROL, aes_control);
+ SSS_AES_WRITE(dev, AES_CONTROL, aes_control);
s5p_set_aes(dev, dev->ctx->aes_key, req->info, dev->ctx->keylen);

s5p_set_dma_indata(dev, req->src);
--
1.7.9.5

2014-01-09 04:59:55

[permalink] [raw]

Subject: [PATCH 4/6 v2] crypto:s5p-sss: Kconfig: Let Exynos SoCs select SSS driver

From: Naveen Krishna Ch <[email protected]>

This patch modifies Kconfig such that ARCH_EXYNOS SoCs
which includes (Exynos4210, Exynos5250 and Exynos5420)
can also select Samsung SSS(Security SubSystem) driver.

Signed-off-by: Naveen Krishna Ch <[email protected]>
CC: Herbert Xu <[email protected]>
CC: David S. Miller <[email protected]>
CC: Vladimir Zapolskiy <[email protected]>
TO: <[email protected]>
CC: <[email protected]>
---
Changes since v1:
SSS module on Exynos4210 and Exynos5250, Exynso5420 are alike
hence, modifying the Kconfig to select the s5p-sss.c driver
for all SoCs supporting ARCH_EXYNOS

drivers/crypto/Kconfig | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index f4fd837..193e8b1 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -300,15 +300,15 @@ config CRYPTO_DEV_DCP
capabilities of the DCP co-processor

config CRYPTO_DEV_S5P
- tristate "Support for Samsung S5PV210 crypto accelerator"
- depends on ARCH_S5PV210
+ tristate "Support for Samsung crypto accelerator"
+ depends on ARCH_S5PV210 || ARCH_EXYNOS
select CRYPTO_AES
select CRYPTO_ALGAPI
select CRYPTO_BLKCIPHER
help
This option allows you to have support for S5P crypto acceleration.
- Select this to offload Samsung S5PV210 or S5PC110 from AES
- algorithms execution.
+ Select this to offload Samsung S5PV210 or S5PC110, Exynos4210,
+ Exynos5250 and Exynos5420 from AES algorithms execution.

config CRYPTO_DEV_TEGRA_AES
tristate "Support for TEGRA AES hw engine"
--
1.7.9.5

2014-01-09 05:00:21

[permalink] [raw]

Subject: [PATCH 5/6 v2] ARM: dts: exynos5420: add dt node for sss module

This patch adds the device tree node for SSS module
found on Exynos5420

Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
TO: <[email protected]>
CC: Kukjin Kim <[email protected]>
CC: <[email protected]>
---
Changes since v1:
Modified dt node name from sss to sss@10830000

arch/arm/boot/dts/exynos5420.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 11dd202..0b27902 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -652,4 +652,14 @@
clocks = <&clock 319>, <&clock 318>;
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
};
+
+ sss@10830000 {
+ compatible = "samsung,exynos-secss";
+ reg = <0x10830000 0x10000>;
+ interrupts = <0 112 0>;
+ clocks = <&clock 471>;
+ clock-names = "secss";
+ samsung,power-domain = <&g2d_pd>;
+ };
+
};
--
1.7.9.5

2014-01-09 09:29:27

by Sachin Kamat

[permalink] [raw]

Subject: Re: [PATCH 4/6 v2] crypto:s5p-sss: Kconfig: Let Exynos SoCs select SSS driver

Hi Naveen,

On 9 January 2014 10:29, Naveen Krishna Chatradhi <[email protected]> wrote:
> From: Naveen Krishna Ch <[email protected]>
>
> This patch modifies Kconfig such that ARCH_EXYNOS SoCs
> which includes (Exynos4210, Exynos5250 and Exynos5420)
> can also select Samsung SSS(Security SubSystem) driver.

What about Exynos4x12 and 5440 as they too come under ARCH_EXYNOS?

--
With warm regards,
Sachin

2014-01-09 09:32:48

by Sachin Kamat

[permalink] [raw]

Subject: Re: [PATCH 3/6 v2] crypto:s5p-sss: Add support for SSS module on Exynos

Hi Naveen,

On 9 January 2014 10:29, Naveen Krishna Chatradhi <[email protected]> wrote:
> This patch adds new compatible and varient to support the SSS module
> on Exynos4 (Exynos4210), Exynos5 (Exynos5420 and Exynos5250) for which
> 1. AES register are at an offset of 0x200 and
> 2. hash interrupt is not available
>
> Signed-off-by: Naveen Krishna Ch <[email protected]>
> CC: Herbert Xu <[email protected]>
> CC: David S. Miller <[email protected]>
> CC: Vladimir Zapolskiy <[email protected]>
> TO: <[email protected]>
> CC: <[email protected]>
> ---
> Changes since v1:
> 1. Used varient struct
> 2. Added description in Documentation
>
> .../devicetree/bindings/crypto/samsung-sss.txt | 20 +++++++++
> drivers/crypto/s5p-sss.c | 43 ++++++++++++++------
> 2 files changed, 51 insertions(+), 12 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/crypto/samsung-sss.txt b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
> index 0e45b0d..4531da2 100644
> --- a/Documentation/devicetree/bindings/crypto/samsung-sss.txt
> +++ b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
> @@ -8,13 +8,33 @@ The SSS module in S5PV210 SoC supports the following:
> -- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
> -- PRNG: Pseudo Random Number Generator
>
> +The SSS module in Exynos4 (Exynos4210) and
> +Exynos5 (Exynos5420 and Exynos5250) SoCs
> +supports the following also:
> +-- ARCFOUR (ARC4)
> +-- True Random Number Generator (TRNG)
> +-- Secure Key Manager
> +
> Required properties:
>
> - compatible : Should contain entries for this and backward compatible
> SSS versions:
> - "samsung,s5p-secss" for S5PV210 SoC.
> + - "samsung,exynos-secss" for Exynos4210, Exynos5250 and Exynos5420 SoCs.

Shouldn't the compatible string be more specific with the name of the
first SoC that had this IP?

--
With warm regards,
Sachin

2014-01-09 14:14:08

[permalink] [raw]

Subject: Re: [PATCH 2/6 v2] crypto:s5p-sss: Add device tree support

Hi Naveen,

On 09.01.2014 05:59, Naveen Krishna Chatradhi wrote:
> This patch adds device tree support to the s5p-sss.c crypto driver.
> Implements a varient struct to address the changes in SSS hardware
> on various SoCs from Samsung.
>
> Also, Documentation under devicetree/bindings added.
>
> Signed-off-by: Naveen Krishna Ch <[email protected]>
> CC: Herbert Xu <[email protected]>
> CC: David S. Miller <[email protected]>
> CC: Vladimir Zapolskiy <[email protected]>
> TO: <[email protected]>
> CC: <[email protected]>
> ---
> Changes since v1:
> 1. Added description of the SSS module in Documentation
> 2. Corrected the interrupts description
> 3. Added varient struct instead of the version variable
>
> .../devicetree/bindings/crypto/samsung-sss.txt | 20 +++++
> drivers/crypto/s5p-sss.c | 81 ++++++++++++++++++--
> 2 files changed, 95 insertions(+), 6 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/crypto/samsung-sss.txt
>
> diff --git a/Documentation/devicetree/bindings/crypto/samsung-sss.txt b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
> new file mode 100644
> index 0000000..0e45b0d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
> @@ -0,0 +1,20 @@
> +Samsung SoC SSS (Security SubSystem) module
> +
> +The SSS module in S5PV210 SoC supports the following:
> +-- Feeder (FeedCtrl)
> +-- Advanced Encryption Standard (AES)
> +-- Data Encryption Standard (DES)/3DES
> +-- Public Key Accelerator (PKA)
> +-- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
> +-- PRNG: Pseudo Random Number Generator
> +
> +Required properties:
> +
> +- compatible : Should contain entries for this and backward compatible
> + SSS versions:
> + - "samsung,s5p-secss" for S5PV210 SoC.

As I wrote in my previous reply, please use specific compatible string
containing name of SoC on which the block described by it appeared
first. Let me say it again, for security block that showed up first on
S5PV210 the string will be "samsung,s5pv210-secss".

> +- reg : Offset and length of the register set for the module
> +- interrupts : the interrupt-specifier for the SSS module.
> + Two interrupts "feed control and hash" in case of S5PV210
> +- clocks : the required gating clock for the SSS module.
> +- clock-names : the gating clock name to be requested in the SSS driver.
> diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
> index 93cddeb..78e0c37 100644
> --- a/drivers/crypto/s5p-sss.c
> +++ b/drivers/crypto/s5p-sss.c
> @@ -22,6 +22,7 @@
> #include <linux/scatterlist.h>
> #include <linux/dma-mapping.h>
> #include <linux/io.h>
> +#include <linux/of.h>
> #include <linux/crypto.h>
> #include <linux/interrupt.h>
>
> @@ -145,6 +146,20 @@
> #define AES_KEY_LEN 16
> #define CRYPTO_QUEUE_LEN 1
>
> +/**
> + * struct samsung_aes_varient - platform specific SSS driver data

typo: s/varient/variant/g

Anyway, I think this should be moved to the patch adding support for
Exynos5, as before it there is no use for this struct and it's not
directly related to DT support.

> + * @has_hash_irq: true if SSS module uses hash interrupt, false otherwise
> + * @aes_offset: AES register offset from SSS module's base.
> + *
> + * Specifies platform specific configuration of SSS module.
> + * Note: A structure for driver specific platform data is used for future
> + * expansion of its usage.
> + */
> +struct samsung_aes_varient {
> + bool has_hash_irq;
> + unsigned int aes_offset;
> +};
> +
> struct s5p_aes_reqctx {
> unsigned long mode;
> };
> @@ -173,10 +188,56 @@ struct s5p_aes_dev {
> struct crypto_queue queue;
> bool busy;
> spinlock_t lock;
> +
> + struct samsung_aes_varient *varient;
> };
>
> static struct s5p_aes_dev *s5p_dev;
>
> +static struct samsung_aes_varient s5p_aes_data = {

Remember to mark constant data as const.

> + .has_hash_irq = true,
> + .aes_offset = 0x4000,
> +};
> +
> +static const struct platform_device_id s5p_sss_ids[] = {
> + {
> + .name = "s5p-secss",
> + .driver_data = (kernel_ulong_t)&s5p_aes_data,
> + },
> + { },
> +};
> +MODULE_DEVICE_TABLE(platform, s5p_sss_ids);
> +
> +#ifdef CONFIG_OF
> +static const struct of_device_id s5p_sss_dt_match[] = {
> + {
> + .compatible = "samsung,s5p-secss",
> + .data = (void *)&s5p_aes_data,

No need to cast pointers to (void *) explicitly.

> + },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, s5p_sss_dt_match);
> +#else
> +static struct of_device_id s5p_sss_dt_match[] = {
> + { },
> +};

Hmm, I don't think there is any need for this.

> +#endif
> +
> +static inline struct samsung_aes_varient *find_s5p_sss_version
> + (struct platform_device *pdev)
> +{
> + if (IS_ENABLED(CONFIG_OF)) {
> + if (pdev->dev.of_node) {

What about using a single if, as follows:

if (IS_ENABLED(CONFIG_IF) && pdev->dev.of_node)

> + const struct of_device_id *match;
> + match = of_match_node(s5p_sss_dt_match,

You can use of_match_ptr(s5p_sss_dt_match) instead of referring to the
table directly to eliminate the need for empty table.

> + pdev->dev.of_node);
> + return (struct samsung_aes_varient *)match->data;
> + }
> + }
> + return (struct samsung_aes_varient *)
> + platform_get_device_id(pdev)->driver_data;
> +}
> +
> static void s5p_set_dma_indata(struct s5p_aes_dev *dev, struct scatterlist *sg)
> {
> SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg));
> @@ -564,6 +625,7 @@ static int s5p_aes_probe(struct platform_device *pdev)
> struct s5p_aes_dev *pdata;
> struct device *dev = &pdev->dev;
> struct resource *res;
> + struct samsung_aes_varient *varient;
>
> if (s5p_dev)
> return -EEXIST;
> @@ -580,6 +642,8 @@ static int s5p_aes_probe(struct platform_device *pdev)
> resource_size(res), pdev->name))
> return -EBUSY;
>
> + varient = find_s5p_sss_version(pdev);
> +
> pdata->clk = devm_clk_get(dev, "secss");
> if (IS_ERR(pdata->clk)) {
> dev_err(dev, "failed to find secss clock source\n");
> @@ -606,18 +670,21 @@ static int s5p_aes_probe(struct platform_device *pdev)
> }
>

The if (variant->has_hash_irq) should start here and cover the whole
block handling second interrupt. This should be more readable.

> pdata->irq_hash = platform_get_irq(pdev, 1);
> - if (pdata->irq_hash < 0) {
> + if (varient->has_hash_irq && pdata->irq_hash < 0) {
> err = pdata->irq_hash;
> dev_warn(dev, "hash interrupt is not available.\n");
> goto err_irq;
> }
> - err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
> - IRQF_SHARED, pdev->name, pdev);
> - if (err < 0) {
> - dev_warn(dev, "hash interrupt is not available.\n");
> - goto err_irq;
> + if (varient->has_hash_irq) {
> + err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
> + IRQF_SHARED, pdev->name, pdev);
> + if (err < 0) {
> + dev_warn(dev, "hash interrupt is not available.\n");
> + goto err_irq;
> + }
> }
>
> + pdata->varient = varient;
> pdata->dev = dev;
> platform_set_drvdata(pdev, pdata);
> s5p_dev = pdata;
> @@ -674,9 +741,11 @@ static int s5p_aes_remove(struct platform_device *pdev)
> static struct platform_driver s5p_aes_crypto = {
> .probe = s5p_aes_probe,
> .remove = s5p_aes_remove,
> + .id_table = s5p_sss_ids,
> .driver = {
> .owner = THIS_MODULE,
> .name = "s5p-secss",
> + .of_match_table = s5p_sss_dt_match,

.of_match_table = of_match_ptr(s5p_sss_dt_match),

Best regards,
Tomasz

2014-01-10 06:07:51

[permalink] [raw]

Subject: Re: [PATCH 2/6 v2] crypto:s5p-sss: Add device tree support

Hello Tomasz,

Thanks for time and review comments they are really helping me a lot
in getting the patches merged.

Secondly, accept my apologies for not giving proper writeup of why i
din't address
few of your comments on v1 of this patchset.

On 9 January 2014 19:44, Tomasz Figa <[email protected]> wrote:
> Hi Naveen,
>
>
> On 09.01.2014 05:59, Naveen Krishna Chatradhi wrote:
>>
>> This patch adds device tree support to the s5p-sss.c crypto driver.
>> Implements a varient struct to address the changes in SSS hardware
>> on various SoCs from Samsung.
>>
>> Also, Documentation under devicetree/bindings added.
>>
>> Signed-off-by: Naveen Krishna Ch <[email protected]>
>> CC: Herbert Xu <[email protected]>
>> CC: David S. Miller <[email protected]>
>> CC: Vladimir Zapolskiy <[email protected]>
>> TO: <[email protected]>
>> CC: <[email protected]>
>> ---
>> Changes since v1:
>> 1. Added description of the SSS module in Documentation
>> 2. Corrected the interrupts description
>> 3. Added varient struct instead of the version variable
>>
>> .../devicetree/bindings/crypto/samsung-sss.txt | 20 +++++
>> drivers/crypto/s5p-sss.c | 81
>> ++++++++++++++++++--
>> 2 files changed, 95 insertions(+), 6 deletions(-)
>> create mode 100644
>> Documentation/devicetree/bindings/crypto/samsung-sss.txt
>>
>> diff --git a/Documentation/devicetree/bindings/crypto/samsung-sss.txt
>> b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
>> new file mode 100644
>> index 0000000..0e45b0d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
>> @@ -0,0 +1,20 @@
>> +Samsung SoC SSS (Security SubSystem) module
>> +
>> +The SSS module in S5PV210 SoC supports the following:
>> +-- Feeder (FeedCtrl)
>> +-- Advanced Encryption Standard (AES)
>> +-- Data Encryption Standard (DES)/3DES
>> +-- Public Key Accelerator (PKA)
>> +-- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
>> +-- PRNG: Pseudo Random Number Generator
>> +
>> +Required properties:
>> +
>> +- compatible : Should contain entries for this and backward compatible
>> + SSS versions:
>> + - "samsung,s5p-secss" for S5PV210 SoC.
>
>
> As I wrote in my previous reply, please use specific compatible string
> containing name of SoC on which the block described by it appeared first.
> Let me say it again, for security block that showed up first on S5PV210 the
> string will be "samsung,s5pv210-secss".
1. .name = "s5p-secss", is the name used in the present driver.
So, i dint modify that.
2. I'm not sure which one is the first soc to have the new varient.
May be Exynos4210. Will modify in the next version.

>
>
>> +- reg : Offset and length of the register set for the module
>> +- interrupts : the interrupt-specifier for the SSS module.
>> + Two interrupts "feed control and hash" in case of S5PV210
>> +- clocks : the required gating clock for the SSS module.
>> +- clock-names : the gating clock name to be requested in the SSS driver.
>> diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
>> index 93cddeb..78e0c37 100644
>> --- a/drivers/crypto/s5p-sss.c
>> +++ b/drivers/crypto/s5p-sss.c
>> @@ -22,6 +22,7 @@
>> #include <linux/scatterlist.h>
>> #include <linux/dma-mapping.h>
>> #include <linux/io.h>
>> +#include <linux/of.h>
>> #include <linux/crypto.h>
>> #include <linux/interrupt.h>
>>
>> @@ -145,6 +146,20 @@
>> #define AES_KEY_LEN 16
>> #define CRYPTO_QUEUE_LEN 1
>>
>> +/**
>> + * struct samsung_aes_varient - platform specific SSS driver data
>
>
> typo: s/varient/variant/g
>
> Anyway, I think this should be moved to the patch adding support for
> Exynos5, as before it there is no use for this struct and it's not directly
> related to DT support.
>
>
>> + * @has_hash_irq: true if SSS module uses hash interrupt, false otherwise
>> + * @aes_offset: AES register offset from SSS module's base.
>> + *
>> + * Specifies platform specific configuration of SSS module.
>> + * Note: A structure for driver specific platform data is used for future
>> + * expansion of its usage.
>> + */
>> +struct samsung_aes_varient {
>> + bool has_hash_irq;
>> + unsigned int aes_offset;
>> +};
>> +
>> struct s5p_aes_reqctx {
>> unsigned long mode;
>> };
>> @@ -173,10 +188,56 @@ struct s5p_aes_dev {
>> struct crypto_queue queue;
>> bool busy;
>> spinlock_t lock;
>> +
>> + struct samsung_aes_varient *varient;
>> };
>>
>> static struct s5p_aes_dev *s5p_dev;
>>
>> +static struct samsung_aes_varient s5p_aes_data = {
>
>
> Remember to mark constant data as const.
>
>
>> + .has_hash_irq = true,
>> + .aes_offset = 0x4000,
>> +};
>> +
>> +static const struct platform_device_id s5p_sss_ids[] = {
>> + {
>> + .name = "s5p-secss",
>> + .driver_data = (kernel_ulong_t)&s5p_aes_data,
>> + },
>> + { },
>> +};
>> +MODULE_DEVICE_TABLE(platform, s5p_sss_ids);
>> +
>> +#ifdef CONFIG_OF
>> +static const struct of_device_id s5p_sss_dt_match[] = {
>> + {
>> + .compatible = "samsung,s5p-secss",
>> + .data = (void *)&s5p_aes_data,
>
>
> No need to cast pointers to (void *) explicitly.
>
>
>> + },
>> + { },
>> +};
>> +MODULE_DEVICE_TABLE(of, s5p_sss_dt_match);
>> +#else
>> +static struct of_device_id s5p_sss_dt_match[] = {
>> + { },
>> +};
>
>
> Hmm, I don't think there is any need for this.
I think all Exynos4 and Exynos5 now supports DT
But, i'm not sure of the S5PV210 series.
>
>
>> +#endif
>> +
>> +static inline struct samsung_aes_varient *find_s5p_sss_version
>> + (struct platform_device *pdev)
>> +{
>> + if (IS_ENABLED(CONFIG_OF)) {
>> + if (pdev->dev.of_node) {
>
>
> What about using a single if, as follows:
>
> if (IS_ENABLED(CONFIG_IF) && pdev->dev.of_node)
>
>
>> + const struct of_device_id *match;
>> + match = of_match_node(s5p_sss_dt_match,
>
>
> You can use of_match_ptr(s5p_sss_dt_match) instead of referring to the table
> directly to eliminate the need for empty table.
>
>
>> + pdev->dev.of_node);
>> + return (struct samsung_aes_varient *)match->data;
>> + }
>> + }
>> + return (struct samsung_aes_varient *)
>> + platform_get_device_id(pdev)->driver_data;
>> +}
>> +
>> static void s5p_set_dma_indata(struct s5p_aes_dev *dev, struct
>> scatterlist *sg)
>> {
>> SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg));
>> @@ -564,6 +625,7 @@ static int s5p_aes_probe(struct platform_device *pdev)
>> struct s5p_aes_dev *pdata;
>> struct device *dev = &pdev->dev;
>> struct resource *res;
>> + struct samsung_aes_varient *varient;
>>
>> if (s5p_dev)
>> return -EEXIST;
>> @@ -580,6 +642,8 @@ static int s5p_aes_probe(struct platform_device *pdev)
>> resource_size(res), pdev->name))
>> return -EBUSY;
>>
>> + varient = find_s5p_sss_version(pdev);
>> +
>> pdata->clk = devm_clk_get(dev, "secss");
>> if (IS_ERR(pdata->clk)) {
>> dev_err(dev, "failed to find secss clock source\n");
>> @@ -606,18 +670,21 @@ static int s5p_aes_probe(struct platform_device
>> *pdev)
>> }
>>
>
> The if (variant->has_hash_irq) should start here and cover the whole block
> handling second interrupt. This should be more readable.
Indeed it is, But, adding extra tab was causing more lines to cross 80char limit
so, I used it this way.. Will modify in the next version.
>
>
>> pdata->irq_hash = platform_get_irq(pdev, 1);
>> - if (pdata->irq_hash < 0) {
>> + if (varient->has_hash_irq && pdata->irq_hash < 0) {
>> err = pdata->irq_hash;
>> dev_warn(dev, "hash interrupt is not available.\n");
>> goto err_irq;
>> }
>> - err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
>> - IRQF_SHARED, pdev->name, pdev);
>> - if (err < 0) {
>> - dev_warn(dev, "hash interrupt is not available.\n");
>> - goto err_irq;
>> + if (varient->has_hash_irq) {
>> + err = devm_request_irq(dev, pdata->irq_hash,
>> s5p_aes_interrupt,
>> + IRQF_SHARED, pdev->name, pdev);
>> + if (err < 0) {
>> + dev_warn(dev, "hash interrupt is not
>> available.\n");
>> + goto err_irq;
>> + }
>> }
>>
>> + pdata->varient = varient;
>> pdata->dev = dev;
>> platform_set_drvdata(pdev, pdata);
>> s5p_dev = pdata;
>> @@ -674,9 +741,11 @@ static int s5p_aes_remove(struct platform_device
>> *pdev)
>> static struct platform_driver s5p_aes_crypto = {
>> .probe = s5p_aes_probe,
>> .remove = s5p_aes_remove,
>> + .id_table = s5p_sss_ids,
>> .driver = {
>> .owner = THIS_MODULE,
>> .name = "s5p-secss",
>> + .of_match_table = s5p_sss_dt_match,
>
>
> .of_match_table = of_match_ptr(s5p_sss_dt_match),
I dint use it, Some time back there was a patchset from Sachin
https://lkml.org/lkml/2013/9/28/61
Please suggest me on this.
>
> Best regards,
> Tomasz

--
Shine bright,
(: Nav :)

2014-01-10 06:20:13

by Sachin Kamat

[permalink] [raw]

Subject: Re: [PATCH 2/6 v2] crypto:s5p-sss: Add device tree support

Hi Naveen,

On 10 January 2014 11:37, Naveen Krishna Ch <[email protected]> wrote:
> Hello Tomasz,
>

[snip]
>>> *pdev)
>>> static struct platform_driver s5p_aes_crypto = {
>>> .probe = s5p_aes_probe,
>>> .remove = s5p_aes_remove,
>>> + .id_table = s5p_sss_ids,
>>> .driver = {
>>> .owner = THIS_MODULE,
>>> .name = "s5p-secss",
>>> + .of_match_table = s5p_sss_dt_match,
>>
>>
>> .of_match_table = of_match_ptr(s5p_sss_dt_match),
> I dint use it, Some time back there was a patchset from Sachin
> https://lkml.org/lkml/2013/9/28/61
> Please suggest me on this.

In those cases the structure was always compiled in. i.e., it was not protected
by #ifdef CONFIG_OF. Hence use of of_match_ptr was not required. of_match_ptr
abstracts this check depending on OF is enabled or not. In the case of
this (sss) driver,
since you are using CONFIG_OF to selectively compile out the code (and esp.
s5p_sss_dt_match structure), use of of_match_ptr will make the code
simpler as it
avoids the use of a dummy structure definition (the #else part of the
struct definition) when OF is
disabled. Hope this clarifies.

--
With warm regards,
Sachin

2014-01-10 11:40:59

[permalink] [raw]

Subject: [PATCH 0/8 v3] crypto:s5p-sss: Add DT and Exynos support

SSS module on Exynos4210, Exynos5250 and Exynos5420 SoCs has added
features to the one on S5PV210. However minor changes to the s5p-sss.c
driver are required to support SSS modules on Exynos4 and 5 SoCs.

This patch set
1. Adds device tree support to the s5p-sss.c driver and Documentation
2. Adds code to support SSS module on Exynos4 and 5 SoCs
3. Adds device tree node to Exynos5250 and Exynos5420
4. Adds variant struct to handle the differences in SSS modules
5. Adds clk_prepare/clk_unprepare clocks to the s5p-sss.c driver

Note: Compatible "exynos4210-secss" should work for Exynos4412 and
Exynos5260 (Exynos5260, for which ARCH code is under review)
I couldn't test on Exynos4412 and Exynos4210 boards, Should be able to
test with addition of DT node and clocks support.

Naveen Krishna Ch (6): [crypto-2.6.git]
crypto:s5p-sss: Use platform_get_irq() instead of _byname()
crypto:s5p-sss: Kconfig: Let Exynos SoCs select SSS driver
crypto:s5p-sss: Add device tree support
crypto:s5p-sss: Add support for SSS module on Exynos
crypto:s5p-sss: validate iv before memcpy
crypto:s5p-sss: Use clk_prepare/clk_unprepare

Naveen Krishna Chatradhi (2): [linuxsamsung.git]
clk:exynos5250: Add gate clock for SSS module
ARM: dts: exynos5250/5420: add dt node for sss module

.../devicetree/bindings/crypto/samsung-sss.txt | 40 ++++++
arch/arm/boot/dts/exynos5250.dtsi | 8 ++
arch/arm/boot/dts/exynos5420.dtsi | 10 ++
drivers/clk/samsung/clk-exynos5250.c | 3 +-
drivers/crypto/Kconfig | 8 +-
drivers/crypto/s5p-sss.c | 131 +++++++++++++++-----
6 files changed, 165 insertions(+), 35 deletions(-)
create mode 100644 Documentation/devicetree/bindings/crypto/samsung-sss.txt

--
1.7.9.5

2014-01-10 11:41:28

[permalink] [raw]

Subject: [PATCH 1/8 v3] crypto:s5p-sss: Use platform_get_irq() instead of _byname()

From: Naveen Krishna Ch <[email protected]>

This patch uses the platform_get_irq() instead of the
platform_get_irq_byname(). Making feeder control interrupt
as resource "0" and hash interrupt as "1".

reasons for this change.
1. Cannot find any Arch which is currently using this driver
2. Samsung Exynos4 and 5 SoCs only use the feeder control interrupt
3. Patches adding support for DT and H/W version are in pipeline

Signed-off-by: Naveen Krishna Ch <[email protected]>
CC: Herbert Xu <[email protected]>
CC: David S. Miller <[email protected]>
CC: Vladimir Zapolskiy <[email protected]>
TO: <[email protected]>
CC: <[email protected]>
---
Changes since v2:
None

drivers/crypto/s5p-sss.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
index cf149b1..93cddeb 100644
--- a/drivers/crypto/s5p-sss.c
+++ b/drivers/crypto/s5p-sss.c
@@ -592,29 +592,29 @@ static int s5p_aes_probe(struct platform_device *pdev)
pdata->ioaddr = devm_ioremap(dev, res->start,
resource_size(res));

- pdata->irq_hash = platform_get_irq_byname(pdev, "hash");
- if (pdata->irq_hash < 0) {
- err = pdata->irq_hash;
- dev_warn(dev, "hash interrupt is not available.\n");
+ pdata->irq_fc = platform_get_irq(pdev, 0);
+ if (pdata->irq_fc < 0) {
+ err = pdata->irq_fc;
+ dev_warn(dev, "feed control interrupt is not available.\n");
goto err_irq;
}
- err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
+ err = devm_request_irq(dev, pdata->irq_fc, s5p_aes_interrupt,
IRQF_SHARED, pdev->name, pdev);
if (err < 0) {
- dev_warn(dev, "hash interrupt is not available.\n");
+ dev_warn(dev, "feed control interrupt is not available.\n");
goto err_irq;
}

- pdata->irq_fc = platform_get_irq_byname(pdev, "feed control");
- if (pdata->irq_fc < 0) {
- err = pdata->irq_fc;
- dev_warn(dev, "feed control interrupt is not available.\n");
+ pdata->irq_hash = platform_get_irq(pdev, 1);
+ if (pdata->irq_hash < 0) {
+ err = pdata->irq_hash;
+ dev_warn(dev, "hash interrupt is not available.\n");
goto err_irq;
}
- err = devm_request_irq(dev, pdata->irq_fc, s5p_aes_interrupt,
+ err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
IRQF_SHARED, pdev->name, pdev);
if (err < 0) {
- dev_warn(dev, "feed control interrupt is not available.\n");
+ dev_warn(dev, "hash interrupt is not available.\n");
goto err_irq;
}

--
1.7.9.5

2014-01-10 11:42:18

[permalink] [raw]

Subject: [PATCH 2/8 v3] crypto:s5p-sss: Add device tree support

This patch adds device tree support to the s5p-sss.c crypto driver.

Also, Documentation under devicetree/bindings added.

Signed-off-by: Naveen Krishna Ch <[email protected]>
CC: Herbert Xu <[email protected]>
CC: David S. Miller <[email protected]>
CC: Vladimir Zapolskiy <[email protected]>
TO: <[email protected]>
CC: <[email protected]>
---
Changes since v2:
1. Moved the variant struct part to the Exynos support patch
2. Changed the compatible strings to s5pv210-secss

.../devicetree/bindings/crypto/samsung-sss.txt | 20 ++++++++++++++++++++
drivers/crypto/s5p-sss.c | 10 +++++++++-
2 files changed, 29 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/crypto/samsung-sss.txt

diff --git a/Documentation/devicetree/bindings/crypto/samsung-sss.txt b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
new file mode 100644
index 0000000..2f9d7e4
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
@@ -0,0 +1,20 @@
+Samsung SoC SSS (Security SubSystem) module
+
+The SSS module in S5PV210 SoC supports the following:
+-- Feeder (FeedCtrl)
+-- Advanced Encryption Standard (AES)
+-- Data Encryption Standard (DES)/3DES
+-- Public Key Accelerator (PKA)
+-- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
+-- PRNG: Pseudo Random Number Generator
+
+Required properties:
+
+- compatible : Should contain entries for this and backward compatible
+ SSS versions:
+ - "samsung,s5pv210-secss" for S5PV210 SoC.
+- reg : Offset and length of the register set for the module
+- interrupts : the interrupt-specifier for the SSS module.
+ Two interrupts "feed control and hash" in case of S5PV210
+- clocks : the required gating clock for the SSS module.
+- clock-names : the gating clock name to be requested in the SSS driver.
diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
index 93cddeb..2da5617 100644
--- a/drivers/crypto/s5p-sss.c
+++ b/drivers/crypto/s5p-sss.c
@@ -22,6 +22,7 @@
#include <linux/scatterlist.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>
+#include <linux/of.h>
#include <linux/crypto.h>
#include <linux/interrupt.h>

@@ -177,6 +178,12 @@ struct s5p_aes_dev {

static struct s5p_aes_dev *s5p_dev;

+static const struct of_device_id s5p_sss_dt_match[] = {
+ { .compatible = "samsung,s5pv210-secss", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, s5p_sss_dt_match);
+
static void s5p_set_dma_indata(struct s5p_aes_dev *dev, struct scatterlist *sg)
{
SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg));
@@ -676,7 +683,8 @@ static struct platform_driver s5p_aes_crypto = {
.remove = s5p_aes_remove,
.driver = {
.owner = THIS_MODULE,
- .name = "s5p-secss",
+ .name = "s5pv210-secss",
+ .of_match_table = s5p_sss_dt_match,
},
};

--
1.7.9.5

2014-01-10 11:42:51

[permalink] [raw]

Subject: [PATCH 3/8 v3] crypto:s5p-sss: Add support for SSS module on Exynos

This patch adds new compatible and variant struct to support the SSS
module on Exynos4 (Exynos4210), Exynos5 (Exynos5420 and Exynos5250)
for which
1. AES register are at an offset of 0x200 and
2. hash interrupt is not available

Signed-off-by: Naveen Krishna Ch <[email protected]>
CC: Herbert Xu <[email protected]>
CC: David S. Miller <[email protected]>
CC: Vladimir Zapolskiy <[email protected]>
TO: <[email protected]>
CC: <[email protected]>
---
Changes since v2:
1. Added variant struct to handle the differences in SSS modules
2. Changed the compatible strings to exynos4210-secss
3. Other changes suggested by Tomasz

.../devicetree/bindings/crypto/samsung-sss.txt | 20 ++++
drivers/crypto/s5p-sss.c | 110 +++++++++++++++-----
2 files changed, 106 insertions(+), 24 deletions(-)

diff --git a/Documentation/devicetree/bindings/crypto/samsung-sss.txt b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
index 2f9d7e4..fdc7d8b 100644
--- a/Documentation/devicetree/bindings/crypto/samsung-sss.txt
+++ b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
@@ -8,13 +8,33 @@ The SSS module in S5PV210 SoC supports the following:
-- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
-- PRNG: Pseudo Random Number Generator

+The SSS module in Exynos4 (Exynos4210) and
+Exynos5 (Exynos5420 and Exynos5250) SoCs
+supports the following also:
+-- ARCFOUR (ARC4)
+-- True Random Number Generator (TRNG)
+-- Secure Key Manager
+
Required properties:

- compatible : Should contain entries for this and backward compatible
SSS versions:
- "samsung,s5pv210-secss" for S5PV210 SoC.
+ - "samsung,exynos4210-secss" for Exynos4210, Exynos5250 and Exynos5420 SoCs.
- reg : Offset and length of the register set for the module
- interrupts : the interrupt-specifier for the SSS module.
Two interrupts "feed control and hash" in case of S5PV210
+ One interrupts "feed control" in case of Exynos4210,
+ Exynos5250 and Exynos5420 SoCs.
- clocks : the required gating clock for the SSS module.
- clock-names : the gating clock name to be requested in the SSS driver.
+
+Example:
+ /* SSS_VER_5 */
+ sss@10830000 {
+ compatible = "samsung,exynos4210-secss";
+ reg = <0x10830000 0x10000>;
+ interrupts = <0 112 0>;
+ clocks = <&clock 471>;
+ clock-names = "secss";
+ };
diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
index 2da5617..f274f5f 100644
--- a/drivers/crypto/s5p-sss.c
+++ b/drivers/crypto/s5p-sss.c
@@ -106,7 +106,7 @@
#define SSS_REG_FCPKDMAO 0x005C

/* AES registers */
-#define SSS_REG_AES_CONTROL 0x4000
+#define SSS_REG_AES_CONTROL 0x00
#define SSS_AES_BYTESWAP_DI _BIT(11)
#define SSS_AES_BYTESWAP_DO _BIT(10)
#define SSS_AES_BYTESWAP_IV _BIT(9)
@@ -122,21 +122,26 @@
#define SSS_AES_CHAIN_MODE_CTR _SBF(1, 0x02)
#define SSS_AES_MODE_DECRYPT _BIT(0)

-#define SSS_REG_AES_STATUS 0x4004
+#define SSS_REG_AES_STATUS 0x04
#define SSS_AES_BUSY _BIT(2)
#define SSS_AES_INPUT_READY _BIT(1)
#define SSS_AES_OUTPUT_READY _BIT(0)

-#define SSS_REG_AES_IN_DATA(s) (0x4010 + (s << 2))
-#define SSS_REG_AES_OUT_DATA(s) (0x4020 + (s << 2))
-#define SSS_REG_AES_IV_DATA(s) (0x4030 + (s << 2))
-#define SSS_REG_AES_CNT_DATA(s) (0x4040 + (s << 2))
-#define SSS_REG_AES_KEY_DATA(s) (0x4080 + (s << 2))
+#define SSS_REG_AES_IN_DATA(off, s) ((off + 0x10) + (s << 2))
+#define SSS_REG_AES_OUT_DATA(off, s) ((off + 0x20) + (s << 2))
+#define SSS_REG_AES_IV_DATA(off, s) ((off + 0x30) + (s << 2))
+#define SSS_REG_AES_CNT_DATA(off, s) ((off + 0x40) + (s << 2))
+#define SSS_REG_AES_KEY_DATA(off, s) ((off + 0x80) + (s << 2))

#define SSS_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg))
#define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg))
#define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg))

+#define SSS_AES_REG(dev, reg) ((dev)->ioaddr + SSS_REG_##reg + \
+ dev->variant->aes_offset)
+#define SSS_AES_WRITE(dev, reg, val) __raw_writel((val), \
+ SSS_AES_REG(dev, reg))
+
/* HW engine modes */
#define FLAGS_AES_DECRYPT _BIT(0)
#define FLAGS_AES_MODE_MASK _SBF(1, 0x03)
@@ -146,6 +151,20 @@
#define AES_KEY_LEN 16
#define CRYPTO_QUEUE_LEN 1

+/**
+ * struct samsung_aes_variant - platform specific SSS driver data
+ * @has_hash_irq: true if SSS module uses hash interrupt, false otherwise
+ * @aes_offset: AES register offset from SSS module's base.
+ *
+ * Specifies platform specific configuration of SSS module.
+ * Note: A structure for driver specific platform data is used for future
+ * expansion of its usage.
+ */
+struct samsung_aes_variant {
+ bool has_hash_irq;
+ unsigned int aes_offset;
+};
+
struct s5p_aes_reqctx {
unsigned long mode;
};
@@ -174,16 +193,48 @@ struct s5p_aes_dev {
struct crypto_queue queue;
bool busy;
spinlock_t lock;
+
+ struct samsung_aes_variant *variant;
};

static struct s5p_aes_dev *s5p_dev;

+static const struct samsung_aes_variant s5p_aes_data = {
+ .has_hash_irq = true,
+ .aes_offset = 0x4000,
+};
+
+static const struct samsung_aes_variant exynos_aes_data = {
+ .has_hash_irq = false,
+ .aes_offset = 0x200,
+};
+
static const struct of_device_id s5p_sss_dt_match[] = {
- { .compatible = "samsung,s5pv210-secss", },
+ {
+ .compatible = "samsung,s5pv210-secss",
+ .data = &s5p_aes_data,
+ },
+ {
+ .compatible = "samsung,exynos4210-secss",
+ .data = &exynos_aes_data,
+ },
{ },
};
MODULE_DEVICE_TABLE(of, s5p_sss_dt_match);

+static inline struct samsung_aes_variant *find_s5p_sss_version
+ (struct platform_device *pdev)
+{
+ if (IS_ENABLED(CONFIG_OF) && (pdev->dev.of_node)) {
+ const struct of_device_id *match;
+ match = of_match_node(s5p_sss_dt_match,
+ pdev->dev.of_node);
+ return (struct samsung_aes_variant *)match->data;
+ }
+ return (struct samsung_aes_variant *)
+ platform_get_device_id(pdev)->driver_data;
+}
+
static void s5p_set_dma_indata(struct s5p_aes_dev *dev, struct scatterlist *sg)
{
SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg));
@@ -327,16 +378,21 @@ static irqreturn_t s5p_aes_interrupt(int irq, void *dev_id)
static void s5p_set_aes(struct s5p_aes_dev *dev,
uint8_t *key, uint8_t *iv, unsigned int keylen)
{
+ struct samsung_aes_variant *var = dev->variant;
void __iomem *keystart;

- memcpy(dev->ioaddr + SSS_REG_AES_IV_DATA(0), iv, 0x10);
+ memcpy(dev->ioaddr + SSS_REG_AES_IV_DATA
+ (var->aes_offset, 0), iv, 0x10);

if (keylen == AES_KEYSIZE_256)
- keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(0);
+ keystart = dev->ioaddr +
+ SSS_REG_AES_KEY_DATA(var->aes_offset, 0);
else if (keylen == AES_KEYSIZE_192)
- keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(2);
+ keystart = dev->ioaddr +
+ SSS_REG_AES_KEY_DATA(var->aes_offset, 2);
else
- keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(4);
+ keystart = dev->ioaddr +
+ SSS_REG_AES_KEY_DATA(var->aes_offset, 4);

memcpy(keystart, key, keylen);
}
@@ -386,7 +442,7 @@ static void s5p_aes_crypt_start(struct s5p_aes_dev *dev, unsigned long mode)
if (err)
goto outdata_error;

- SSS_WRITE(dev, AES_CONTROL, aes_control);
+ SSS_AES_WRITE(dev, AES_CONTROL, aes_control);
s5p_set_aes(dev, dev->ctx->aes_key, req->info, dev->ctx->keylen);

s5p_set_dma_indata(dev, req->src);
@@ -571,6 +627,7 @@ static int s5p_aes_probe(struct platform_device *pdev)
struct s5p_aes_dev *pdata;
struct device *dev = &pdev->dev;
struct resource *res;
+ struct samsung_aes_variant *variant;

if (s5p_dev)
return -EEXIST;
@@ -587,6 +644,8 @@ static int s5p_aes_probe(struct platform_device *pdev)
resource_size(res), pdev->name))
return -EBUSY;

+ variant = find_s5p_sss_version(pdev);
+
pdata->clk = devm_clk_get(dev, "secss");
if (IS_ERR(pdata->clk)) {
dev_err(dev, "failed to find secss clock source\n");
@@ -612,19 +671,22 @@ static int s5p_aes_probe(struct platform_device *pdev)
goto err_irq;
}

- pdata->irq_hash = platform_get_irq(pdev, 1);
- if (pdata->irq_hash < 0) {
- err = pdata->irq_hash;
- dev_warn(dev, "hash interrupt is not available.\n");
- goto err_irq;
- }
- err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
- IRQF_SHARED, pdev->name, pdev);
- if (err < 0) {
- dev_warn(dev, "hash interrupt is not available.\n");
- goto err_irq;
+ if (variant->has_hash_irq) {
+ pdata->irq_hash = platform_get_irq(pdev, 1);
+ if (pdata->irq_hash < 0) {
+ err = pdata->irq_hash;
+ dev_warn(dev, "hash interrupt is not available.\n");
+ goto err_irq;
+ }
+ err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
+ IRQF_SHARED, pdev->name, pdev);
+ if (err < 0) {
+ dev_warn(dev, "hash interrupt is not available.\n");
+ goto err_irq;
+ }
}

+ pdata->variant = variant;
pdata->dev = dev;
platform_set_drvdata(pdev, pdata);
s5p_dev = pdata;
--
1.7.9.5

2014-01-10 11:43:06

[permalink] [raw]

Subject: [PATCH 4/8 v3] crypto:s5p-sss: Kconfig: Let Exynos SoCs select SSS driver

From: Naveen Krishna Ch <[email protected]>

This patch modifies Kconfig such that ARCH_EXYNOS SoCs
which includes (Exynos4210, Exynos5250 and Exynos5420)
can also select Samsung SSS(Security SubSystem) driver.

Signed-off-by: Naveen Krishna Ch <[email protected]>
CC: Herbert Xu <[email protected]>
CC: David S. Miller <[email protected]>
CC: Vladimir Zapolskiy <[email protected]>
TO: <[email protected]>
CC: <[email protected]>
---
Changes since v2:
None

drivers/crypto/Kconfig | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index f4fd837..193e8b1 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -300,15 +300,15 @@ config CRYPTO_DEV_DCP
capabilities of the DCP co-processor

config CRYPTO_DEV_S5P
- tristate "Support for Samsung S5PV210 crypto accelerator"
- depends on ARCH_S5PV210
+ tristate "Support for Samsung crypto accelerator"
+ depends on ARCH_S5PV210 || ARCH_EXYNOS
select CRYPTO_AES
select CRYPTO_ALGAPI
select CRYPTO_BLKCIPHER
help
This option allows you to have support for S5P crypto acceleration.
- Select this to offload Samsung S5PV210 or S5PC110 from AES
- algorithms execution.
+ Select this to offload Samsung S5PV210 or S5PC110, Exynos4210,
+ Exynos5250 and Exynos5420 from AES algorithms execution.

config CRYPTO_DEV_TEGRA_AES
tristate "Support for TEGRA AES hw engine"
--
1.7.9.5

2014-01-10 11:43:33

[permalink] [raw]

Subject: [PATCH 5/8 v3] clk:exynos-5250: Add gate clock for SSS module

This patch adds gating clock for SSS(Security SubSystem)
module on Exynos5250.

Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
---
Changes since v2:
This is a new change to support SSS on Exynos5250

drivers/clk/samsung/clk-exynos5250.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index adf3234..b47bf0a 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -120,7 +120,7 @@ enum exynos5250_clks {
spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
- wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d,
+ wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d, sss,

/* mux clocks */
mout_hdmi = 1024,
@@ -492,6 +492,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
GATE(mixer, "mixer", "mout_aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
GATE(hdmi, "hdmi", "mout_aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
GATE(g2d, "g2d", "aclk200", GATE_IP_ACP, 3, 0, 0),
+ GATE(sss, "sss", "aclk200", GATE_IP_ACP, 2, 0, 0),
};

static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = {
--
1.7.9.5

2014-01-10 11:44:40

[permalink] [raw]

Subject: [PATCH 6/8 v3] ARM: dts: exynos5250/5420: add dt node for sss module

This patch adds the device tree node for SSS module
found on Exynos5420 and Exynos5250

Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
TO: <[email protected]>
CC: Kukjin Kim <[email protected]>
CC: <[email protected]>
---
Changes since v2:
1. Added device tree node for SSS on Exynos5250 aswell

arch/arm/boot/dts/exynos5250.dtsi | 8 ++++++++
arch/arm/boot/dts/exynos5420.dtsi | 10 ++++++++++
2 files changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index c341e55..1d249df 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -704,4 +704,12 @@
io-channel-ranges;
status = "disabled";
};
+
+ sss@10830000 {
+ compatible = "samsung,exynos4210-secss";
+ reg = <0x10830000 0x10000>;
+ interrupts = <0 112 0>;
+ clocks = <&clock 346>;
+ clock-names = "secss";
+ };
};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 11dd202..56a3f3e 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -652,4 +652,14 @@
clocks = <&clock 319>, <&clock 318>;
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
};
+
+ sss@10830000 {
+ compatible = "samsung,exynos4210-secss";
+ reg = <0x10830000 0x10000>;
+ interrupts = <0 112 0>;
+ clocks = <&clock 471>;
+ clock-names = "secss";
+ samsung,power-domain = <&g2d_pd>;
+ };
+
};
--
1.7.9.5

2014-01-10 13:44:24

[permalink] [raw]

Subject: Re: [PATCH 2/6 v2] crypto:s5p-sss: Add device tree support

Hi Naveen,

On 10.01.2014 07:07, Naveen Krishna Ch wrote:
> Hello Tomasz,
>
> Thanks for time and review comments they are really helping me a lot
> in getting the patches merged.
>
> Secondly, accept my apologies for not giving proper writeup of why i
> din't address
> few of your comments on v1 of this patchset.

It's okay.

>
> On 9 January 2014 19:44, Tomasz Figa <[email protected]> wrote:
>> Hi Naveen,
>>
>>
>> On 09.01.2014 05:59, Naveen Krishna Chatradhi wrote:
>>>
>>> This patch adds device tree support to the s5p-sss.c crypto driver.
>>> Implements a varient struct to address the changes in SSS hardware
>>> on various SoCs from Samsung.
>>>
>>> Also, Documentation under devicetree/bindings added.
>>>
>>> Signed-off-by: Naveen Krishna Ch <[email protected]>
>>> CC: Herbert Xu <[email protected]>
>>> CC: David S. Miller <[email protected]>
>>> CC: Vladimir Zapolskiy <[email protected]>
>>> TO: <[email protected]>
>>> CC: <[email protected]>
>>> ---
>>> Changes since v1:
>>> 1. Added description of the SSS module in Documentation
>>> 2. Corrected the interrupts description
>>> 3. Added varient struct instead of the version variable
>>>
>>> .../devicetree/bindings/crypto/samsung-sss.txt | 20 +++++
>>> drivers/crypto/s5p-sss.c | 81
>>> ++++++++++++++++++--
>>> 2 files changed, 95 insertions(+), 6 deletions(-)
>>> create mode 100644
>>> Documentation/devicetree/bindings/crypto/samsung-sss.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/crypto/samsung-sss.txt
>>> b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
>>> new file mode 100644
>>> index 0000000..0e45b0d
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
>>> @@ -0,0 +1,20 @@
>>> +Samsung SoC SSS (Security SubSystem) module
>>> +
>>> +The SSS module in S5PV210 SoC supports the following:
>>> +-- Feeder (FeedCtrl)
>>> +-- Advanced Encryption Standard (AES)
>>> +-- Data Encryption Standard (DES)/3DES
>>> +-- Public Key Accelerator (PKA)
>>> +-- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
>>> +-- PRNG: Pseudo Random Number Generator
>>> +
>>> +Required properties:
>>> +
>>> +- compatible : Should contain entries for this and backward compatible
>>> + SSS versions:
>>> + - "samsung,s5p-secss" for S5PV210 SoC.
>>
>>
>> As I wrote in my previous reply, please use specific compatible string
>> containing name of SoC on which the block described by it appeared first.
>> Let me say it again, for security block that showed up first on S5PV210 the
>> string will be "samsung,s5pv210-secss".
> 1. .name = "s5p-secss", is the name used in the present driver.
> So, i dint modify that.

Please note that compatible strings and platform driver names are
completely different things. There is no relation between them.
Moreover, there are different rules (or recommendation) involved for
creating both, so it's completely fine to add a compatible string of
"samsung,s5pv210-secss", while keeping platform driver named "s5p-secss".

> 2. I'm not sure which one is the first soc to have the new varient.
> May be Exynos4210. Will modify in the next version.

Let's see.

From what I can find in various user's manuals, S5PV210 is the first to
have the first variant, while Exynos4210 already has the new one.

>>
>>> + },
>>> + { },
>>> +};
>>> +MODULE_DEVICE_TABLE(of, s5p_sss_dt_match);
>>> +#else
>>> +static struct of_device_id s5p_sss_dt_match[] = {
>>> + { },
>>> +};
>>
>>
>> Hmm, I don't think there is any need for this.
> I think all Exynos4 and Exynos5 now supports DT
> But, i'm not sure of the S5PV210 series.

S5PV210 does not support DT yet. Work is already in progress, but board
file support will have to be retained for some time, so this driver
should support non-DT probing too.

It doesn't affect my comment, though, as you can use of_match_ptr() macro.

>>> @@ -674,9 +741,11 @@ static int s5p_aes_remove(struct platform_device
>>> *pdev)
>>> static struct platform_driver s5p_aes_crypto = {
>>> .probe = s5p_aes_probe,
>>> .remove = s5p_aes_remove,
>>> + .id_table = s5p_sss_ids,
>>> .driver = {
>>> .owner = THIS_MODULE,
>>> .name = "s5p-secss",
>>> + .of_match_table = s5p_sss_dt_match,
>>
>>
>> .of_match_table = of_match_ptr(s5p_sss_dt_match),
> I dint use it, Some time back there was a patchset from Sachin
> https://lkml.org/lkml/2013/9/28/61
> Please suggest me on this.

I believe Sachin already explained this in his reply to your patch.
Generally the driver from your link is supposed to always support DT,
while this one can be built without DT support.

Best regards,
Tomasz

2014-01-10 15:15:02

[permalink] [raw]

Subject: Re: [PATCH 1/8 v3] crypto:s5p-sss: Use platform_get_irq() instead of _byname()

Hi Naveen,

On 10.01.2014 12:41, Naveen Krishna Chatradhi wrote:
> From: Naveen Krishna Ch <[email protected]>
>
> This patch uses the platform_get_irq() instead of the
> platform_get_irq_byname(). Making feeder control interrupt
> as resource "0" and hash interrupt as "1".
>
> reasons for this change.
> 1. Cannot find any Arch which is currently using this driver
> 2. Samsung Exynos4 and 5 SoCs only use the feeder control interrupt
> 3. Patches adding support for DT and H/W version are in pipeline
>
> Signed-off-by: Naveen Krishna Ch <[email protected]>
> CC: Herbert Xu <[email protected]>
> CC: David S. Miller <[email protected]>
> CC: Vladimir Zapolskiy <[email protected]>
> TO: <[email protected]>
> CC: <[email protected]>
> ---
> Changes since v2:
> None
>
> drivers/crypto/s5p-sss.c | 24 ++++++++++++------------
> 1 file changed, 12 insertions(+), 12 deletions(-)

Reviewed-by: Tomasz Figa <[email protected]>

Best regards,
Tomasz

2014-01-10 15:44:50

[permalink] [raw]

Subject: Re: [PATCH 3/8 v3] crypto:s5p-sss: Add support for SSS module on Exynos

Hi Naveen,

Please see my comments inline.

On 10.01.2014 12:42, Naveen Krishna Chatradhi wrote:
> This patch adds new compatible and variant struct to support the SSS
> module on Exynos4 (Exynos4210), Exynos5 (Exynos5420 and Exynos5250)
> for which
> 1. AES register are at an offset of 0x200 and
> 2. hash interrupt is not available
>
> Signed-off-by: Naveen Krishna Ch <[email protected]>
> CC: Herbert Xu <[email protected]>
> CC: David S. Miller <[email protected]>
> CC: Vladimir Zapolskiy <[email protected]>
> TO: <[email protected]>
> CC: <[email protected]>
> ---
> Changes since v2:
> 1. Added variant struct to handle the differences in SSS modules
> 2. Changed the compatible strings to exynos4210-secss
> 3. Other changes suggested by Tomasz
>
> .../devicetree/bindings/crypto/samsung-sss.txt | 20 ++++
> drivers/crypto/s5p-sss.c | 110 +++++++++++++++-----
> 2 files changed, 106 insertions(+), 24 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/crypto/samsung-sss.txt b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
> index 2f9d7e4..fdc7d8b 100644
> --- a/Documentation/devicetree/bindings/crypto/samsung-sss.txt
> +++ b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
> @@ -8,13 +8,33 @@ The SSS module in S5PV210 SoC supports the following:
> -- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
> -- PRNG: Pseudo Random Number Generator
>
> +The SSS module in Exynos4 (Exynos4210) and
> +Exynos5 (Exynos5420 and Exynos5250) SoCs
> +supports the following also:
> +-- ARCFOUR (ARC4)
> +-- True Random Number Generator (TRNG)
> +-- Secure Key Manager
> +
> Required properties:
>
> - compatible : Should contain entries for this and backward compatible
> SSS versions:
> - "samsung,s5pv210-secss" for S5PV210 SoC.
> + - "samsung,exynos4210-secss" for Exynos4210, Exynos5250 and Exynos5420 SoCs.

You can also add Exynos4212/4412 to the list.

> - reg : Offset and length of the register set for the module
> - interrupts : the interrupt-specifier for the SSS module.
> Two interrupts "feed control and hash" in case of S5PV210
> + One interrupts "feed control" in case of Exynos4210,
> + Exynos5250 and Exynos5420 SoCs.

You can refer to compatible string here instead of listing all the SoCs.

> - clocks : the required gating clock for the SSS module.
> - clock-names : the gating clock name to be requested in the SSS driver.

Again, please specify name of the clock in property description. The
proper description for both clock properties should be:

- clock-names : list of device clock input names; should contain one
entry - "secss".
- clocks : list of clock phandle and specifier pairs for all clocks
listed in clock-names property.

> +
> +Example:
> + /* SSS_VER_5 */
> + sss@10830000 {
> + compatible = "samsung,exynos4210-secss";
> + reg = <0x10830000 0x10000>;
> + interrupts = <0 112 0>;
> + clocks = <&clock 471>;
> + clock-names = "secss";
> + };
> diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
> index 2da5617..f274f5f 100644
> --- a/drivers/crypto/s5p-sss.c
> +++ b/drivers/crypto/s5p-sss.c
> @@ -106,7 +106,7 @@
> #define SSS_REG_FCPKDMAO 0x005C
>
> /* AES registers */
> -#define SSS_REG_AES_CONTROL 0x4000
> +#define SSS_REG_AES_CONTROL 0x00
> #define SSS_AES_BYTESWAP_DI _BIT(11)
> #define SSS_AES_BYTESWAP_DO _BIT(10)
> #define SSS_AES_BYTESWAP_IV _BIT(9)
> @@ -122,21 +122,26 @@
> #define SSS_AES_CHAIN_MODE_CTR _SBF(1, 0x02)
> #define SSS_AES_MODE_DECRYPT _BIT(0)
>
> -#define SSS_REG_AES_STATUS 0x4004
> +#define SSS_REG_AES_STATUS 0x04
> #define SSS_AES_BUSY _BIT(2)
> #define SSS_AES_INPUT_READY _BIT(1)
> #define SSS_AES_OUTPUT_READY _BIT(0)
>
> -#define SSS_REG_AES_IN_DATA(s) (0x4010 + (s << 2))
> -#define SSS_REG_AES_OUT_DATA(s) (0x4020 + (s << 2))
> -#define SSS_REG_AES_IV_DATA(s) (0x4030 + (s << 2))
> -#define SSS_REG_AES_CNT_DATA(s) (0x4040 + (s << 2))
> -#define SSS_REG_AES_KEY_DATA(s) (0x4080 + (s << 2))
> +#define SSS_REG_AES_IN_DATA(off, s) ((off + 0x10) + (s << 2))
> +#define SSS_REG_AES_OUT_DATA(off, s) ((off + 0x20) + (s << 2))
> +#define SSS_REG_AES_IV_DATA(off, s) ((off + 0x30) + (s << 2))
> +#define SSS_REG_AES_CNT_DATA(off, s) ((off + 0x40) + (s << 2))
> +#define SSS_REG_AES_KEY_DATA(off, s) ((off + 0x80) + (s << 2))

I still somehow don't like this. Such macros are only hiding operations
performed by the driver. See my comment below, in the code that
references them, to see my proposal.

>
> #define SSS_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg))
> #define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg))
> #define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg))
>
> +#define SSS_AES_REG(dev, reg) ((dev)->ioaddr + SSS_REG_##reg + \
> + dev->variant->aes_offset)
> +#define SSS_AES_WRITE(dev, reg, val) __raw_writel((val), \
> + SSS_AES_REG(dev, reg))
> +
> /* HW engine modes */
> #define FLAGS_AES_DECRYPT _BIT(0)
> #define FLAGS_AES_MODE_MASK _SBF(1, 0x03)
> @@ -146,6 +151,20 @@
> #define AES_KEY_LEN 16
> #define CRYPTO_QUEUE_LEN 1
>
> +/**
> + * struct samsung_aes_variant - platform specific SSS driver data
> + * @has_hash_irq: true if SSS module uses hash interrupt, false otherwise
> + * @aes_offset: AES register offset from SSS module's base.
> + *
> + * Specifies platform specific configuration of SSS module.
> + * Note: A structure for driver specific platform data is used for future
> + * expansion of its usage.
> + */
> +struct samsung_aes_variant {
> + bool has_hash_irq;
> + unsigned int aes_offset;
> +};
> +
> struct s5p_aes_reqctx {
> unsigned long mode;
> };
> @@ -174,16 +193,48 @@ struct s5p_aes_dev {
> struct crypto_queue queue;
> bool busy;
> spinlock_t lock;
> +
> + struct samsung_aes_variant *variant;
> };
>
> static struct s5p_aes_dev *s5p_dev;
>
> +static const struct samsung_aes_variant s5p_aes_data = {
> + .has_hash_irq = true,
> + .aes_offset = 0x4000,
> +};
> +
> +static const struct samsung_aes_variant exynos_aes_data = {
> + .has_hash_irq = false,
> + .aes_offset = 0x200,
> +};
> +
> static const struct of_device_id s5p_sss_dt_match[] = {
> - { .compatible = "samsung,s5pv210-secss", },
> + {
> + .compatible = "samsung,s5pv210-secss",
> + .data = &s5p_aes_data,
> + },
> + {
> + .compatible = "samsung,exynos4210-secss",
> + .data = &exynos_aes_data,
> + },
> { },
> };
> MODULE_DEVICE_TABLE(of, s5p_sss_dt_match);
>
> +static inline struct samsung_aes_variant *find_s5p_sss_version
> + (struct platform_device *pdev)
> +{
> + if (IS_ENABLED(CONFIG_OF) && (pdev->dev.of_node)) {
> + const struct of_device_id *match;
> + match = of_match_node(s5p_sss_dt_match,
> + pdev->dev.of_node);
> + return (struct samsung_aes_variant *)match->data;
> + }
> + return (struct samsung_aes_variant *)
> + platform_get_device_id(pdev)->driver_data;
> +}
> +
> static void s5p_set_dma_indata(struct s5p_aes_dev *dev, struct scatterlist *sg)
> {
> SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg));
> @@ -327,16 +378,21 @@ static irqreturn_t s5p_aes_interrupt(int irq, void *dev_id)
> static void s5p_set_aes(struct s5p_aes_dev *dev,
> uint8_t *key, uint8_t *iv, unsigned int keylen)
> {
> + struct samsung_aes_variant *var = dev->variant;
> void __iomem *keystart;
>
> - memcpy(dev->ioaddr + SSS_REG_AES_IV_DATA(0), iv, 0x10);
> + memcpy(dev->ioaddr + SSS_REG_AES_IV_DATA
> + (var->aes_offset, 0), iv, 0x10);

What about adding aes_ioaddr to s5p_aes_dev struct? Then you could
access the registers as follows:

memcpy(dev->aes_ioaddr + SSS_REG_AES_IV_DATA(0), iv, 0x10);

The registers would be defined as offsets of AES base, e.g:

#define SSS_REG_AES_IV_DATA(s) (0x10 + (s << 2))

>
> if (keylen == AES_KEYSIZE_256)
> - keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(0);
> + keystart = dev->ioaddr +
> + SSS_REG_AES_KEY_DATA(var->aes_offset, 0);
> else if (keylen == AES_KEYSIZE_192)
> - keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(2);
> + keystart = dev->ioaddr +
> + SSS_REG_AES_KEY_DATA(var->aes_offset, 2);
> else
> - keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(4);
> + keystart = dev->ioaddr +
> + SSS_REG_AES_KEY_DATA(var->aes_offset, 4);
>
> memcpy(keystart, key, keylen);
> }
> @@ -386,7 +442,7 @@ static void s5p_aes_crypt_start(struct s5p_aes_dev *dev, unsigned long mode)
> if (err)
> goto outdata_error;
>
> - SSS_WRITE(dev, AES_CONTROL, aes_control);
> + SSS_AES_WRITE(dev, AES_CONTROL, aes_control);

SSS_AES_WRITE would be define using dev->aes_ioaddr instead of dev->ioaddr.

Otherwise the patch looks fine.

Best regards,
Tomasz

2014-01-10 15:47:49

[permalink] [raw]

Subject: Re: [PATCH 4/8 v3] crypto:s5p-sss: Kconfig: Let Exynos SoCs select SSS driver

Hi Naveen,

On 10.01.2014 12:43, Naveen Krishna Chatradhi wrote:
> From: Naveen Krishna Ch <[email protected]>
>
> This patch modifies Kconfig such that ARCH_EXYNOS SoCs
> which includes (Exynos4210, Exynos5250 and Exynos5420)
> can also select Samsung SSS(Security SubSystem) driver.
>
> Signed-off-by: Naveen Krishna Ch <[email protected]>
> CC: Herbert Xu <[email protected]>
> CC: David S. Miller <[email protected]>
> CC: Vladimir Zapolskiy <[email protected]>
> TO: <[email protected]>
> CC: <[email protected]>
> ---
> Changes since v2:
> None
>
> drivers/crypto/Kconfig | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
> index f4fd837..193e8b1 100644
> --- a/drivers/crypto/Kconfig
> +++ b/drivers/crypto/Kconfig
> @@ -300,15 +300,15 @@ config CRYPTO_DEV_DCP
> capabilities of the DCP co-processor
>
> config CRYPTO_DEV_S5P
> - tristate "Support for Samsung S5PV210 crypto accelerator"
> - depends on ARCH_S5PV210
> + tristate "Support for Samsung crypto accelerator"

I'd make this "Support for Samsung S5PV210/Exynos crypto accelerator"
instead, because there are previous SoCs (S3C64xx and S5PC100) that
contain a different crypto engine IP.

> + depends on ARCH_S5PV210 || ARCH_EXYNOS
> select CRYPTO_AES
> select CRYPTO_ALGAPI
> select CRYPTO_BLKCIPHER
> help
> This option allows you to have support for S5P crypto acceleration.
> - Select this to offload Samsung S5PV210 or S5PC110 from AES
> - algorithms execution.
> + Select this to offload Samsung S5PV210 or S5PC110, Exynos4210,
> + Exynos5250 and Exynos5420 from AES algorithms execution.

I believe you can safely make it S5PV210, S5PC110 and Exynos, without
listing particular SoCs.

Best regards,
Tomasz

2014-01-10 15:58:12

[permalink] [raw]

Subject: Re: [PATCH 5/8 v3] clk:exynos-5250: Add gate clock for SSS module

Hi Naveen,

On 10.01.2014 12:43, Naveen Krishna Chatradhi wrote:
> This patch adds gating clock for SSS(Security SubSystem)
> module on Exynos5250.
>
> Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
> ---
> Changes since v2:
> This is a new change to support SSS on Exynos5250
>
> drivers/clk/samsung/clk-exynos5250.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
> index adf3234..b47bf0a 100644
> --- a/drivers/clk/samsung/clk-exynos5250.c
> +++ b/drivers/clk/samsung/clk-exynos5250.c
> @@ -120,7 +120,7 @@ enum exynos5250_clks {
> spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
> hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
> tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
> - wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d,
> + wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d, sss,

Please base changes to Samsung clock drivers on Mike Turquette's
clk-next [1] or ideally on my samsung-next branch on samsung-clk-tree [2].

By the way, if you assign an ID to a clock, you need to document this in
respective clock bindings documentation.

[1] - https://git.linaro.org/people/mike.turquette/linux.git
[2] - https://git.kernel.org/cgit/linux/kernel/git/tfiga/samsung-clk.git/

Best regards,
Tomasz

2014-01-10 16:01:07

[permalink] [raw]

Subject: Re: [PATCH 6/8 v3] ARM: dts: exynos5250/5420: add dt node for sss module

Hi Naveen,

On 10.01.2014 12:44, Naveen Krishna Chatradhi wrote:
> This patch adds the device tree node for SSS module
> found on Exynos5420 and Exynos5250
>
> Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
> TO: <[email protected]>
> CC: Kukjin Kim <[email protected]>
> CC: <[email protected]>
> ---
> Changes since v2:
> 1. Added device tree node for SSS on Exynos5250 aswell
>
> arch/arm/boot/dts/exynos5250.dtsi | 8 ++++++++
> arch/arm/boot/dts/exynos5420.dtsi | 10 ++++++++++
> 2 files changed, 18 insertions(+)

Reviewed-by: Tomasz Figa <[email protected]>

Best regards,
Tomasz

2014-01-13 21:16:38

by Vladimir Zapolskiy

[permalink] [raw]

Subject: Re: [PATCH 3/8 v3] crypto:s5p-sss: Add support for SSS module on Exynos

Hi Naveen and Tomasz,

On 01/10/14 17:44, Tomasz Figa wrote:
> Hi Naveen,
>
> Please see my comments inline.
>
> On 10.01.2014 12:42, Naveen Krishna Chatradhi wrote:
>> This patch adds new compatible and variant struct to support the SSS
>> module on Exynos4 (Exynos4210), Exynos5 (Exynos5420 and Exynos5250)
>> for which
>> 1. AES register are at an offset of 0x200 and
>> 2. hash interrupt is not available
>>
>> Signed-off-by: Naveen Krishna Ch <[email protected]>
>> CC: Herbert Xu <[email protected]>
>> CC: David S. Miller <[email protected]>
>> CC: Vladimir Zapolskiy <[email protected]>
>> TO: <[email protected]>
>> CC: <[email protected]>
>> ---
>> Changes since v2:
>> 1. Added variant struct to handle the differences in SSS modules
>> 2. Changed the compatible strings to exynos4210-secss
>> 3. Other changes suggested by Tomasz
>>
>> .../devicetree/bindings/crypto/samsung-sss.txt | 20 ++++
>> drivers/crypto/s5p-sss.c | 110 +++++++++++++++-----
>> 2 files changed, 106 insertions(+), 24 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/crypto/samsung-sss.txt
>> b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
>> index 2f9d7e4..fdc7d8b 100644
>> --- a/Documentation/devicetree/bindings/crypto/samsung-sss.txt
>> +++ b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
>> @@ -8,13 +8,33 @@ The SSS module in S5PV210 SoC supports the following:
>> -- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
>> -- PRNG: Pseudo Random Number Generator
>>
>> +The SSS module in Exynos4 (Exynos4210) and
>> +Exynos5 (Exynos5420 and Exynos5250) SoCs
>> +supports the following also:
>> +-- ARCFOUR (ARC4)
>> +-- True Random Number Generator (TRNG)
>> +-- Secure Key Manager
>> +
>> Required properties:
>>
>> - compatible : Should contain entries for this and backward compatible
>> SSS versions:
>> - "samsung,s5pv210-secss" for S5PV210 SoC.
>> + - "samsung,exynos4210-secss" for Exynos4210, Exynos5250 and
>> Exynos5420 SoCs.
>
> You can also add Exynos4212/4412 to the list.
>
>> - reg : Offset and length of the register set for the module
>> - interrupts : the interrupt-specifier for the SSS module.
>> Two interrupts "feed control and hash" in case of S5PV210
>> + One interrupts "feed control" in case of Exynos4210,
>> + Exynos5250 and Exynos5420 SoCs.
>
> You can refer to compatible string here instead of listing all the SoCs.
>
>> - clocks : the required gating clock for the SSS module.
>> - clock-names : the gating clock name to be requested in the SSS driver.
>
> Again, please specify name of the clock in property description. The
> proper description for both clock properties should be:
>
> - clock-names : list of device clock input names; should contain one
> entry - "secss".
> - clocks : list of clock phandle and specifier pairs for all clocks
> listed in clock-names property.
>
>> +
>> +Example:
>> + /* SSS_VER_5 */
>> + sss@10830000 {
>> + compatible = "samsung,exynos4210-secss";
>> + reg = <0x10830000 0x10000>;
>> + interrupts = <0 112 0>;
>> + clocks = <&clock 471>;
>> + clock-names = "secss";
>> + };
>> diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
>> index 2da5617..f274f5f 100644
>> --- a/drivers/crypto/s5p-sss.c
>> +++ b/drivers/crypto/s5p-sss.c
>> @@ -106,7 +106,7 @@
>> #define SSS_REG_FCPKDMAO 0x005C
>>
>> /* AES registers */
>> -#define SSS_REG_AES_CONTROL 0x4000
>> +#define SSS_REG_AES_CONTROL 0x00
>> #define SSS_AES_BYTESWAP_DI _BIT(11)
>> #define SSS_AES_BYTESWAP_DO _BIT(10)
>> #define SSS_AES_BYTESWAP_IV _BIT(9)
>> @@ -122,21 +122,26 @@
>> #define SSS_AES_CHAIN_MODE_CTR _SBF(1, 0x02)
>> #define SSS_AES_MODE_DECRYPT _BIT(0)
>>
>> -#define SSS_REG_AES_STATUS 0x4004
>> +#define SSS_REG_AES_STATUS 0x04
>> #define SSS_AES_BUSY _BIT(2)
>> #define SSS_AES_INPUT_READY _BIT(1)
>> #define SSS_AES_OUTPUT_READY _BIT(0)
>>
>> -#define SSS_REG_AES_IN_DATA(s) (0x4010 + (s << 2))
>> -#define SSS_REG_AES_OUT_DATA(s) (0x4020 + (s << 2))
>> -#define SSS_REG_AES_IV_DATA(s) (0x4030 + (s << 2))
>> -#define SSS_REG_AES_CNT_DATA(s) (0x4040 + (s << 2))
>> -#define SSS_REG_AES_KEY_DATA(s) (0x4080 + (s << 2))
>> +#define SSS_REG_AES_IN_DATA(off, s) ((off + 0x10) + (s << 2))
>> +#define SSS_REG_AES_OUT_DATA(off, s) ((off + 0x20) + (s << 2))
>> +#define SSS_REG_AES_IV_DATA(off, s) ((off + 0x30) + (s << 2))
>> +#define SSS_REG_AES_CNT_DATA(off, s) ((off + 0x40) + (s << 2))
>> +#define SSS_REG_AES_KEY_DATA(off, s) ((off + 0x80) + (s << 2))
>
> I still somehow don't like this. Such macros are only hiding operations
> performed by the driver. See my comment below, in the code that
> references them, to see my proposal.
>
>>
>> #define SSS_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg))
>> #define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg))
>> #define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg))
>>
>> +#define SSS_AES_REG(dev, reg) ((dev)->ioaddr + SSS_REG_##reg + \
>> + dev->variant->aes_offset)
>> +#define SSS_AES_WRITE(dev, reg, val) __raw_writel((val), \
>> + SSS_AES_REG(dev, reg))
>> +
>> /* HW engine modes */
>> #define FLAGS_AES_DECRYPT _BIT(0)
>> #define FLAGS_AES_MODE_MASK _SBF(1, 0x03)
>> @@ -146,6 +151,20 @@
>> #define AES_KEY_LEN 16
>> #define CRYPTO_QUEUE_LEN 1
>>
>> +/**
>> + * struct samsung_aes_variant - platform specific SSS driver data
>> + * @has_hash_irq: true if SSS module uses hash interrupt, false
>> otherwise
>> + * @aes_offset: AES register offset from SSS module's base.
>> + *
>> + * Specifies platform specific configuration of SSS module.
>> + * Note: A structure for driver specific platform data is used for
>> future
>> + * expansion of its usage.
>> + */
>> +struct samsung_aes_variant {
>> + bool has_hash_irq;
>> + unsigned int aes_offset;
>> +};
>> +
>> struct s5p_aes_reqctx {
>> unsigned long mode;
>> };
>> @@ -174,16 +193,48 @@ struct s5p_aes_dev {
>> struct crypto_queue queue;
>> bool busy;
>> spinlock_t lock;
>> +
>> + struct samsung_aes_variant *variant;
>> };
>>
>> static struct s5p_aes_dev *s5p_dev;
>>
>> +static const struct samsung_aes_variant s5p_aes_data = {
>> + .has_hash_irq = true,
>> + .aes_offset = 0x4000,
>> +};
>> +
>> +static const struct samsung_aes_variant exynos_aes_data = {
>> + .has_hash_irq = false,
>> + .aes_offset = 0x200,
>> +};
>> +
>> static const struct of_device_id s5p_sss_dt_match[] = {
>> - { .compatible = "samsung,s5pv210-secss", },
>> + {
>> + .compatible = "samsung,s5pv210-secss",
>> + .data = &s5p_aes_data,
>> + },
>> + {
>> + .compatible = "samsung,exynos4210-secss",
>> + .data = &exynos_aes_data,
>> + },
>> { },
>> };
>> MODULE_DEVICE_TABLE(of, s5p_sss_dt_match);
>>
>> +static inline struct samsung_aes_variant *find_s5p_sss_version
>> + (struct platform_device *pdev)
>> +{
>> + if (IS_ENABLED(CONFIG_OF) && (pdev->dev.of_node)) {
>> + const struct of_device_id *match;
>> + match = of_match_node(s5p_sss_dt_match,
>> + pdev->dev.of_node);
>> + return (struct samsung_aes_variant *)match->data;
>> + }
>> + return (struct samsung_aes_variant *)
>> + platform_get_device_id(pdev)->driver_data;
>> +}
>> +
>> static void s5p_set_dma_indata(struct s5p_aes_dev *dev, struct
>> scatterlist *sg)
>> {
>> SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg));
>> @@ -327,16 +378,21 @@ static irqreturn_t s5p_aes_interrupt(int irq,
>> void *dev_id)
>> static void s5p_set_aes(struct s5p_aes_dev *dev,
>> uint8_t *key, uint8_t *iv, unsigned int keylen)
>> {
>> + struct samsung_aes_variant *var = dev->variant;
>> void __iomem *keystart;
>>
>> - memcpy(dev->ioaddr + SSS_REG_AES_IV_DATA(0), iv, 0x10);
>> + memcpy(dev->ioaddr + SSS_REG_AES_IV_DATA
>> + (var->aes_offset, 0), iv, 0x10);
>
> What about adding aes_ioaddr to s5p_aes_dev struct? Then you could
> access the registers as follows:
>
> memcpy(dev->aes_ioaddr + SSS_REG_AES_IV_DATA(0), iv, 0x10);
>
> The registers would be defined as offsets of AES base, e.g:
>
> #define SSS_REG_AES_IV_DATA(s) (0x10 + (s << 2))

I agree, this variant is more preferable.

>>
>> if (keylen == AES_KEYSIZE_256)
>> - keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(0);
>> + keystart = dev->ioaddr +
>> + SSS_REG_AES_KEY_DATA(var->aes_offset, 0);
>> else if (keylen == AES_KEYSIZE_192)
>> - keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(2);
>> + keystart = dev->ioaddr +
>> + SSS_REG_AES_KEY_DATA(var->aes_offset, 2);
>> else
>> - keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(4);
>> + keystart = dev->ioaddr +
>> + SSS_REG_AES_KEY_DATA(var->aes_offset, 4);
>>
>> memcpy(keystart, key, keylen);
>> }
>> @@ -386,7 +442,7 @@ static void s5p_aes_crypt_start(struct s5p_aes_dev
>> *dev, unsigned long mode)
>> if (err)
>> goto outdata_error;
>>
>> - SSS_WRITE(dev, AES_CONTROL, aes_control);
>> + SSS_AES_WRITE(dev, AES_CONTROL, aes_control);
>
> SSS_AES_WRITE would be define using dev->aes_ioaddr instead of dev->ioaddr.
>
> Otherwise the patch looks fine.
>

Same to me.

With best wishes,
Vladimir

2014-01-14 06:16:43

[permalink] [raw]

Subject: Re: [PATCH 3/8 v3] crypto:s5p-sss: Add support for SSS module on Exynos

Hell Vladimir, Tomasz,

On 14 January 2014 02:36, Vladimir Zapolskiy <[email protected]> wrote:
> Hi Naveen and Tomasz,
>
>
> On 01/10/14 17:44, Tomasz Figa wrote:
>>
>> Hi Naveen,
>>
>> Please see my comments inline.
>>
>> On 10.01.2014 12:42, Naveen Krishna Chatradhi wrote:
>>>
>>> This patch adds new compatible and variant struct to support the SSS
>>> module on Exynos4 (Exynos4210), Exynos5 (Exynos5420 and Exynos5250)
>>> for which
>>> 1. AES register are at an offset of 0x200 and
>>> 2. hash interrupt is not available
>>>
>>> Signed-off-by: Naveen Krishna Ch <[email protected]>
>>> CC: Herbert Xu <[email protected]>
>>> CC: David S. Miller <[email protected]>
>>> CC: Vladimir Zapolskiy <[email protected]>
>>> TO: <[email protected]>
>>> CC: <[email protected]>
>>> ---
>>> Changes since v2:
>>> 1. Added variant struct to handle the differences in SSS modules
>>> 2. Changed the compatible strings to exynos4210-secss
>>> 3. Other changes suggested by Tomasz
>>>
>>> .../devicetree/bindings/crypto/samsung-sss.txt | 20 ++++
>>> drivers/crypto/s5p-sss.c | 110 +++++++++++++++-----
>>> 2 files changed, 106 insertions(+), 24 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/crypto/samsung-sss.txt
>>> b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
>>> index 2f9d7e4..fdc7d8b 100644
>>> --- a/Documentation/devicetree/bindings/crypto/samsung-sss.txt
>>> +++ b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
>>> @@ -8,13 +8,33 @@ The SSS module in S5PV210 SoC supports the following:
>>> -- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
>>> -- PRNG: Pseudo Random Number Generator
>>>
>>> +The SSS module in Exynos4 (Exynos4210) and
>>> +Exynos5 (Exynos5420 and Exynos5250) SoCs
>>> +supports the following also:
>>> +-- ARCFOUR (ARC4)
>>> +-- True Random Number Generator (TRNG)
>>> +-- Secure Key Manager
>>> +
>>> Required properties:
>>>
>>> - compatible : Should contain entries for this and backward compatible
>>> SSS versions:
>>> - "samsung,s5pv210-secss" for S5PV210 SoC.
>>> + - "samsung,exynos4210-secss" for Exynos4210, Exynos5250 and
>>> Exynos5420 SoCs.
>>
>>
>> You can also add Exynos4212/4412 to the list.
>>
>>> - reg : Offset and length of the register set for the module
>>> - interrupts : the interrupt-specifier for the SSS module.
>>> Two interrupts "feed control and hash" in case of S5PV210
>>> + One interrupts "feed control" in case of Exynos4210,
>>> + Exynos5250 and Exynos5420 SoCs.
>>
>>
>> You can refer to compatible string here instead of listing all the SoCs.
>>
>>> - clocks : the required gating clock for the SSS module.
>>> - clock-names : the gating clock name to be requested in the SSS driver.
>>
>>
>> Again, please specify name of the clock in property description. The
>> proper description for both clock properties should be:
>>
>> - clock-names : list of device clock input names; should contain one
>> entry - "secss".
>> - clocks : list of clock phandle and specifier pairs for all clocks
>> listed in clock-names property.
>>
>>> +
>>> +Example:
>>> + /* SSS_VER_5 */
>>> + sss@10830000 {
>>> + compatible = "samsung,exynos4210-secss";
>>> + reg = <0x10830000 0x10000>;
>>> + interrupts = <0 112 0>;
>>> + clocks = <&clock 471>;
>>> + clock-names = "secss";
>>> + };
>>> diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
>>> index 2da5617..f274f5f 100644
>>> --- a/drivers/crypto/s5p-sss.c
>>> +++ b/drivers/crypto/s5p-sss.c
>>> @@ -106,7 +106,7 @@
>>> #define SSS_REG_FCPKDMAO 0x005C
>>>
>>> /* AES registers */
>>> -#define SSS_REG_AES_CONTROL 0x4000
>>> +#define SSS_REG_AES_CONTROL 0x00
>>> #define SSS_AES_BYTESWAP_DI _BIT(11)
>>> #define SSS_AES_BYTESWAP_DO _BIT(10)
>>> #define SSS_AES_BYTESWAP_IV _BIT(9)
>>> @@ -122,21 +122,26 @@
>>> #define SSS_AES_CHAIN_MODE_CTR _SBF(1, 0x02)
>>> #define SSS_AES_MODE_DECRYPT _BIT(0)
>>>
>>> -#define SSS_REG_AES_STATUS 0x4004
>>> +#define SSS_REG_AES_STATUS 0x04
>>> #define SSS_AES_BUSY _BIT(2)
>>> #define SSS_AES_INPUT_READY _BIT(1)
>>> #define SSS_AES_OUTPUT_READY _BIT(0)
>>>
>>> -#define SSS_REG_AES_IN_DATA(s) (0x4010 + (s << 2))
>>> -#define SSS_REG_AES_OUT_DATA(s) (0x4020 + (s << 2))
>>> -#define SSS_REG_AES_IV_DATA(s) (0x4030 + (s << 2))
>>> -#define SSS_REG_AES_CNT_DATA(s) (0x4040 + (s << 2))
>>> -#define SSS_REG_AES_KEY_DATA(s) (0x4080 + (s << 2))
>>> +#define SSS_REG_AES_IN_DATA(off, s) ((off + 0x10) + (s << 2))
>>> +#define SSS_REG_AES_OUT_DATA(off, s) ((off + 0x20) + (s << 2))
>>> +#define SSS_REG_AES_IV_DATA(off, s) ((off + 0x30) + (s << 2))
>>> +#define SSS_REG_AES_CNT_DATA(off, s) ((off + 0x40) + (s << 2))
>>> +#define SSS_REG_AES_KEY_DATA(off, s) ((off + 0x80) + (s << 2))
>>
>>
>> I still somehow don't like this. Such macros are only hiding operations
>> performed by the driver. See my comment below, in the code that
>> references them, to see my proposal.
>>
>>>
>>> #define SSS_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg))
>>> #define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg))
>>> #define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg))
>>>
>>> +#define SSS_AES_REG(dev, reg) ((dev)->ioaddr + SSS_REG_##reg + \
>>> + dev->variant->aes_offset)
>>> +#define SSS_AES_WRITE(dev, reg, val) __raw_writel((val), \
>>> + SSS_AES_REG(dev, reg))
>>> +
>>> /* HW engine modes */
>>> #define FLAGS_AES_DECRYPT _BIT(0)
>>> #define FLAGS_AES_MODE_MASK _SBF(1, 0x03)
>>> @@ -146,6 +151,20 @@
>>> #define AES_KEY_LEN 16
>>> #define CRYPTO_QUEUE_LEN 1
>>>
>>> +/**
>>> + * struct samsung_aes_variant - platform specific SSS driver data
>>> + * @has_hash_irq: true if SSS module uses hash interrupt, false
>>> otherwise
>>> + * @aes_offset: AES register offset from SSS module's base.
>>> + *
>>> + * Specifies platform specific configuration of SSS module.
>>> + * Note: A structure for driver specific platform data is used for
>>> future
>>> + * expansion of its usage.
>>> + */
>>> +struct samsung_aes_variant {
>>> + bool has_hash_irq;
>>> + unsigned int aes_offset;
>>> +};
>>> +
>>> struct s5p_aes_reqctx {
>>> unsigned long mode;
>>> };
>>> @@ -174,16 +193,48 @@ struct s5p_aes_dev {
>>> struct crypto_queue queue;
>>> bool busy;
>>> spinlock_t lock;
>>> +
>>> + struct samsung_aes_variant *variant;
>>> };
>>>
>>> static struct s5p_aes_dev *s5p_dev;
>>>
>>> +static const struct samsung_aes_variant s5p_aes_data = {
>>> + .has_hash_irq = true,
>>> + .aes_offset = 0x4000,
>>> +};
>>> +
>>> +static const struct samsung_aes_variant exynos_aes_data = {
>>> + .has_hash_irq = false,
>>> + .aes_offset = 0x200,
>>> +};
>>> +
>>> static const struct of_device_id s5p_sss_dt_match[] = {
>>> - { .compatible = "samsung,s5pv210-secss", },
>>> + {
>>> + .compatible = "samsung,s5pv210-secss",
>>> + .data = &s5p_aes_data,
>>> + },
>>> + {
>>> + .compatible = "samsung,exynos4210-secss",
>>> + .data = &exynos_aes_data,
>>> + },
>>> { },
>>> };
>>> MODULE_DEVICE_TABLE(of, s5p_sss_dt_match);
>>>
>>> +static inline struct samsung_aes_variant *find_s5p_sss_version
>>> + (struct platform_device *pdev)
>>> +{
>>> + if (IS_ENABLED(CONFIG_OF) && (pdev->dev.of_node)) {
>>> + const struct of_device_id *match;
>>> + match = of_match_node(s5p_sss_dt_match,
>>> + pdev->dev.of_node);
>>> + return (struct samsung_aes_variant *)match->data;
>>> + }
>>> + return (struct samsung_aes_variant *)
>>> + platform_get_device_id(pdev)->driver_data;
>>> +}
>>> +
>>> static void s5p_set_dma_indata(struct s5p_aes_dev *dev, struct
>>> scatterlist *sg)
>>> {
>>> SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg));
>>> @@ -327,16 +378,21 @@ static irqreturn_t s5p_aes_interrupt(int irq,
>>> void *dev_id)
>>> static void s5p_set_aes(struct s5p_aes_dev *dev,
>>> uint8_t *key, uint8_t *iv, unsigned int keylen)
>>> {
>>> + struct samsung_aes_variant *var = dev->variant;
>>> void __iomem *keystart;
>>>
>>> - memcpy(dev->ioaddr + SSS_REG_AES_IV_DATA(0), iv, 0x10);
>>> + memcpy(dev->ioaddr + SSS_REG_AES_IV_DATA
>>> + (var->aes_offset, 0), iv, 0x10);
>>
>>
>> What about adding aes_ioaddr to s5p_aes_dev struct? Then you could
>> access the registers as follows:
>>
>> memcpy(dev->aes_ioaddr + SSS_REG_AES_IV_DATA(0), iv, 0x10);
>>
>> The registers would be defined as offsets of AES base, e.g:
>>
>> #define SSS_REG_AES_IV_DATA(s) (0x10 + (s << 2))
>
>
> I agree, this variant is more preferable.
Sure will implement it.
>
>
>>>
>>> if (keylen == AES_KEYSIZE_256)
>>> - keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(0);
>>> + keystart = dev->ioaddr +
>>> + SSS_REG_AES_KEY_DATA(var->aes_offset, 0);
>>> else if (keylen == AES_KEYSIZE_192)
>>> - keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(2);
>>> + keystart = dev->ioaddr +
>>> + SSS_REG_AES_KEY_DATA(var->aes_offset, 2);
>>> else
>>> - keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(4);
>>> + keystart = dev->ioaddr +
>>> + SSS_REG_AES_KEY_DATA(var->aes_offset, 4);
>>>
>>> memcpy(keystart, key, keylen);
>>> }
>>> @@ -386,7 +442,7 @@ static void s5p_aes_crypt_start(struct s5p_aes_dev
>>> *dev, unsigned long mode)
>>> if (err)
>>> goto outdata_error;
>>>
>>> - SSS_WRITE(dev, AES_CONTROL, aes_control);
>>> + SSS_AES_WRITE(dev, AES_CONTROL, aes_control);
>>
>>
>> SSS_AES_WRITE would be define using dev->aes_ioaddr instead of
>> dev->ioaddr.
>>
>> Otherwise the patch looks fine.
>>
>
> Same to me.
Thanks for the review, Will implement these changes tomorrow.
>
> With best wishes,
> Vladimir

--
Shine bright,
(: Nav :)

2014-01-15 09:05:53

[permalink] [raw]

Subject: Re: [PATCH 5/8 v3] clk:exynos-5250: Add gate clock for SSS module

Hello Tomasz,

On 10 January 2014 21:28, Tomasz Figa <[email protected]> wrote:
> Hi Naveen,
>
>
> On 10.01.2014 12:43, Naveen Krishna Chatradhi wrote:
>>
>> This patch adds gating clock for SSS(Security SubSystem)
>> module on Exynos5250.
>>
>> Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
>> ---
>> Changes since v2:
>> This is a new change to support SSS on Exynos5250
>>
>> drivers/clk/samsung/clk-exynos5250.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos5250.c
>> b/drivers/clk/samsung/clk-exynos5250.c
>> index adf3234..b47bf0a 100644
>> --- a/drivers/clk/samsung/clk-exynos5250.c
>> +++ b/drivers/clk/samsung/clk-exynos5250.c
>> @@ -120,7 +120,7 @@ enum exynos5250_clks {
>> spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1,
>> hsi2c2,
>> hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0,
>> tzpc1,
>> tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec,
>> mct,
>> - wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d,
>> + wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d, sss,
>
>
> Please base changes to Samsung clock drivers on Mike Turquette's clk-next
> [1] or ideally on my samsung-next branch on samsung-clk-tree [2].
>
> By the way, if you assign an ID to a clock, you need to document this in
> respective clock bindings documentation.
>
> [1] - https://git.linaro.org/people/mike.turquette/linux.git
> [2] - https://git.kernel.org/cgit/linux/kernel/git/tfiga/samsung-clk.git/
Sure Tomasz, Will rebase this changes on to your samsung-clk.git tree
>
> Best regards,
> Tomasz

--
Shine bright,
(: Nav :)

2014-01-15 09:14:11

[permalink] [raw]

Subject: [PATCH 1/8 v4] crypto:s5p-sss: Use platform_get_irq() instead of _byname()

From: Naveen Krishna Ch <[email protected]>

This patch uses the platform_get_irq() instead of the
platform_get_irq_byname(). Making feeder control interrupt
as resource "0" and hash interrupt as "1".

reasons for this change.
1. Cannot find any Arch which is currently using this driver
2. Samsung Exynos4 and 5 SoCs only use the feeder control interrupt
3. Patches adding support for DT and H/W version are in pipeline

Signed-off-by: Naveen Krishna Ch <[email protected]>
Reviewed-by: Tomasz Figa <[email protected]>
CC: Herbert Xu <[email protected]>
CC: David S. Miller <[email protected]>
CC: Vladimir Zapolskiy <[email protected]>
TO: <[email protected]>
CC: <[email protected]>
---
Changes since v3:
None

drivers/crypto/s5p-sss.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
index cf149b1..93cddeb 100644
--- a/drivers/crypto/s5p-sss.c
+++ b/drivers/crypto/s5p-sss.c
@@ -592,29 +592,29 @@ static int s5p_aes_probe(struct platform_device *pdev)
pdata->ioaddr = devm_ioremap(dev, res->start,
resource_size(res));

- pdata->irq_hash = platform_get_irq_byname(pdev, "hash");
- if (pdata->irq_hash < 0) {
- err = pdata->irq_hash;
- dev_warn(dev, "hash interrupt is not available.\n");
+ pdata->irq_fc = platform_get_irq(pdev, 0);
+ if (pdata->irq_fc < 0) {
+ err = pdata->irq_fc;
+ dev_warn(dev, "feed control interrupt is not available.\n");
goto err_irq;
}
- err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
+ err = devm_request_irq(dev, pdata->irq_fc, s5p_aes_interrupt,
IRQF_SHARED, pdev->name, pdev);
if (err < 0) {
- dev_warn(dev, "hash interrupt is not available.\n");
+ dev_warn(dev, "feed control interrupt is not available.\n");
goto err_irq;
}

- pdata->irq_fc = platform_get_irq_byname(pdev, "feed control");
- if (pdata->irq_fc < 0) {
- err = pdata->irq_fc;
- dev_warn(dev, "feed control interrupt is not available.\n");
+ pdata->irq_hash = platform_get_irq(pdev, 1);
+ if (pdata->irq_hash < 0) {
+ err = pdata->irq_hash;
+ dev_warn(dev, "hash interrupt is not available.\n");
goto err_irq;
}
- err = devm_request_irq(dev, pdata->irq_fc, s5p_aes_interrupt,
+ err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
IRQF_SHARED, pdev->name, pdev);
if (err < 0) {
- dev_warn(dev, "feed control interrupt is not available.\n");
+ dev_warn(dev, "hash interrupt is not available.\n");
goto err_irq;
}

--
1.7.9.5

2014-01-15 09:14:51

[permalink] [raw]

Subject: [PATCH 2/8 v4] crypto:s5p-sss: Add device tree support

This patch adds device tree support to the s5p-sss.c crypto driver.

Also, Documentation under devicetree/bindings added.

Signed-off-by: Naveen Krishna Ch <[email protected]>
CC: Herbert Xu <[email protected]>
CC: David S. Miller <[email protected]>
CC: Vladimir Zapolskiy <[email protected]>
TO: <[email protected]>
CC: <[email protected]>
---
Changes since v3:
None

.../devicetree/bindings/crypto/samsung-sss.txt | 20 ++++++++++++++++++++
drivers/crypto/s5p-sss.c | 10 +++++++++-
2 files changed, 29 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/crypto/samsung-sss.txt

diff --git a/Documentation/devicetree/bindings/crypto/samsung-sss.txt b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
new file mode 100644
index 0000000..2f9d7e4
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
@@ -0,0 +1,20 @@
+Samsung SoC SSS (Security SubSystem) module
+
+The SSS module in S5PV210 SoC supports the following:
+-- Feeder (FeedCtrl)
+-- Advanced Encryption Standard (AES)
+-- Data Encryption Standard (DES)/3DES
+-- Public Key Accelerator (PKA)
+-- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
+-- PRNG: Pseudo Random Number Generator
+
+Required properties:
+
+- compatible : Should contain entries for this and backward compatible
+ SSS versions:
+ - "samsung,s5pv210-secss" for S5PV210 SoC.
+- reg : Offset and length of the register set for the module
+- interrupts : the interrupt-specifier for the SSS module.
+ Two interrupts "feed control and hash" in case of S5PV210
+- clocks : the required gating clock for the SSS module.
+- clock-names : the gating clock name to be requested in the SSS driver.
diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
index 93cddeb..2da5617 100644
--- a/drivers/crypto/s5p-sss.c
+++ b/drivers/crypto/s5p-sss.c
@@ -22,6 +22,7 @@
#include <linux/scatterlist.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>
+#include <linux/of.h>
#include <linux/crypto.h>
#include <linux/interrupt.h>

@@ -177,6 +178,12 @@ struct s5p_aes_dev {

static struct s5p_aes_dev *s5p_dev;

+static const struct of_device_id s5p_sss_dt_match[] = {
+ { .compatible = "samsung,s5pv210-secss", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, s5p_sss_dt_match);
+
static void s5p_set_dma_indata(struct s5p_aes_dev *dev, struct scatterlist *sg)
{
SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg));
@@ -676,7 +683,8 @@ static struct platform_driver s5p_aes_crypto = {
.remove = s5p_aes_remove,
.driver = {
.owner = THIS_MODULE,
- .name = "s5p-secss",
+ .name = "s5pv210-secss",
+ .of_match_table = s5p_sss_dt_match,
},
};

--
1.7.9.5

2014-01-15 09:15:16

[permalink] [raw]

Subject: [PATCH 3/8 v4] crypto:s5p-sss: Add support for SSS module on Exynos

This patch adds new compatible and variant struct to support the SSS
module on Exynos4 (Exynos4210), Exynos5 (Exynos5420 and Exynos5250)
for which
1. AES register are at an offset of 0x200 and
2. hash interrupt is not available

Signed-off-by: Naveen Krishna Ch <[email protected]>
CC: Herbert Xu <[email protected]>
CC: David S. Miller <[email protected]>
CC: Vladimir Zapolskiy <[email protected]>
TO: <[email protected]>
CC: <[email protected]>
---
Changes since v3:
1. Implemented aes_ioaddr to handle AES register offset, suggested by Tomasz

.../devicetree/bindings/crypto/samsung-sss.txt | 30 +++++-
drivers/crypto/s5p-sss.c | 107 +++++++++++++++-----
2 files changed, 110 insertions(+), 27 deletions(-)

diff --git a/Documentation/devicetree/bindings/crypto/samsung-sss.txt b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
index 2f9d7e4..b99c445 100644
--- a/Documentation/devicetree/bindings/crypto/samsung-sss.txt
+++ b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
@@ -8,13 +8,37 @@ The SSS module in S5PV210 SoC supports the following:
-- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
-- PRNG: Pseudo Random Number Generator

+The SSS module in Exynos4 (Exynos4210) and
+Exynos5 (Exynos5420 and Exynos5250) SoCs
+supports the following also:
+-- ARCFOUR (ARC4)
+-- True Random Number Generator (TRNG)
+-- Secure Key Manager
+
Required properties:

- compatible : Should contain entries for this and backward compatible
SSS versions:
- "samsung,s5pv210-secss" for S5PV210 SoC.
+ - "samsung,exynos4210-secss" for Exynos4210, Exynos4212, Exynos4412, Exynos5250,
+ Exynos5260 and Exynos5420 SoCs.
- reg : Offset and length of the register set for the module
- interrupts : the interrupt-specifier for the SSS module.
- Two interrupts "feed control and hash" in case of S5PV210
-- clocks : the required gating clock for the SSS module.
-- clock-names : the gating clock name to be requested in the SSS driver.
+ -- Two interrupts "feed control and hash" in case of
+ "samsung,s5pv210-secss"
+ -- One interrupts "feed control" in case of
+ "samsung,exynos4210-secss".
+- clocks : list of clock phandle and specifier pairs for all clocks listed in
+ clock-names property.
+- clock-names : list of device clock input names; should contain one entry
+ "secss".
+
+Example:
+ /* SSS_VER_5 */
+ sss@10830000 {
+ compatible = "samsung,exynos4210-secss";
+ reg = <0x10830000 0x10000>;
+ interrupts = <0 112 0>;
+ clocks = <&clock 471>;
+ clock-names = "secss";
+ };
diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
index 2da5617..69130b2 100644
--- a/drivers/crypto/s5p-sss.c
+++ b/drivers/crypto/s5p-sss.c
@@ -106,7 +106,7 @@
#define SSS_REG_FCPKDMAO 0x005C

/* AES registers */
-#define SSS_REG_AES_CONTROL 0x4000
+#define SSS_REG_AES_CONTROL 0x00
#define SSS_AES_BYTESWAP_DI _BIT(11)
#define SSS_AES_BYTESWAP_DO _BIT(10)
#define SSS_AES_BYTESWAP_IV _BIT(9)
@@ -122,21 +122,25 @@
#define SSS_AES_CHAIN_MODE_CTR _SBF(1, 0x02)
#define SSS_AES_MODE_DECRYPT _BIT(0)

-#define SSS_REG_AES_STATUS 0x4004
+#define SSS_REG_AES_STATUS 0x04
#define SSS_AES_BUSY _BIT(2)
#define SSS_AES_INPUT_READY _BIT(1)
#define SSS_AES_OUTPUT_READY _BIT(0)

-#define SSS_REG_AES_IN_DATA(s) (0x4010 + (s << 2))
-#define SSS_REG_AES_OUT_DATA(s) (0x4020 + (s << 2))
-#define SSS_REG_AES_IV_DATA(s) (0x4030 + (s << 2))
-#define SSS_REG_AES_CNT_DATA(s) (0x4040 + (s << 2))
-#define SSS_REG_AES_KEY_DATA(s) (0x4080 + (s << 2))
+#define SSS_REG_AES_IN_DATA(s) (0x10 + (s << 2))
+#define SSS_REG_AES_OUT_DATA(s) (0x20 + (s << 2))
+#define SSS_REG_AES_IV_DATA(s) (0x30 + (s << 2))
+#define SSS_REG_AES_CNT_DATA(s) (0x40 + (s << 2))
+#define SSS_REG_AES_KEY_DATA(s) (0x80 + (s << 2))

#define SSS_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg))
#define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg))
#define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg))

+#define SSS_AES_REG(dev, reg) ((dev)->aes_ioaddr + SSS_REG_##reg)
+#define SSS_AES_WRITE(dev, reg, val) __raw_writel((val), \
+ SSS_AES_REG(dev, reg))
+
/* HW engine modes */
#define FLAGS_AES_DECRYPT _BIT(0)
#define FLAGS_AES_MODE_MASK _SBF(1, 0x03)
@@ -146,6 +150,20 @@
#define AES_KEY_LEN 16
#define CRYPTO_QUEUE_LEN 1

+/**
+ * struct samsung_aes_variant - platform specific SSS driver data
+ * @has_hash_irq: true if SSS module uses hash interrupt, false otherwise
+ * @aes_offset: AES register offset from SSS module's base.
+ *
+ * Specifies platform specific configuration of SSS module.
+ * Note: A structure for driver specific platform data is used for future
+ * expansion of its usage.
+ */
+struct samsung_aes_variant {
+ bool has_hash_irq;
+ unsigned int aes_offset;
+};
+
struct s5p_aes_reqctx {
unsigned long mode;
};
@@ -162,6 +180,7 @@ struct s5p_aes_dev {
struct device *dev;
struct clk *clk;
void __iomem *ioaddr;
+ void __iomem *aes_ioaddr;
int irq_hash;
int irq_fc;

@@ -174,16 +193,48 @@ struct s5p_aes_dev {
struct crypto_queue queue;
bool busy;
spinlock_t lock;
+
+ struct samsung_aes_variant *variant;
};

static struct s5p_aes_dev *s5p_dev;

+static const struct samsung_aes_variant s5p_aes_data = {
+ .has_hash_irq = true,
+ .aes_offset = 0x4000,
+};
+
+static const struct samsung_aes_variant exynos_aes_data = {
+ .has_hash_irq = false,
+ .aes_offset = 0x200,
+};
+
static const struct of_device_id s5p_sss_dt_match[] = {
- { .compatible = "samsung,s5pv210-secss", },
+ {
+ .compatible = "samsung,s5pv210-secss",
+ .data = &s5p_aes_data,
+ },
+ {
+ .compatible = "samsung,exynos4210-secss",
+ .data = &exynos_aes_data,
+ },
{ },
};
MODULE_DEVICE_TABLE(of, s5p_sss_dt_match);

+static inline struct samsung_aes_variant *find_s5p_sss_version
+ (struct platform_device *pdev)
+{
+ if (IS_ENABLED(CONFIG_OF) && (pdev->dev.of_node)) {
+ const struct of_device_id *match;
+ match = of_match_node(s5p_sss_dt_match,
+ pdev->dev.of_node);
+ return (struct samsung_aes_variant *)match->data;
+ }
+ return (struct samsung_aes_variant *)
+ platform_get_device_id(pdev)->driver_data;
+}
+
static void s5p_set_dma_indata(struct s5p_aes_dev *dev, struct scatterlist *sg)
{
SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg));
@@ -329,14 +380,14 @@ static void s5p_set_aes(struct s5p_aes_dev *dev,
{
void __iomem *keystart;

- memcpy(dev->ioaddr + SSS_REG_AES_IV_DATA(0), iv, 0x10);
+ memcpy(dev->aes_ioaddr + SSS_REG_AES_IV_DATA (0), iv, 0x10);

if (keylen == AES_KEYSIZE_256)
- keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(0);
+ keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(0);
else if (keylen == AES_KEYSIZE_192)
- keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(2);
+ keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(2);
else
- keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(4);
+ keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(4);

memcpy(keystart, key, keylen);
}
@@ -386,7 +437,7 @@ static void s5p_aes_crypt_start(struct s5p_aes_dev *dev, unsigned long mode)
if (err)
goto outdata_error;

- SSS_WRITE(dev, AES_CONTROL, aes_control);
+ SSS_AES_WRITE(dev, AES_CONTROL, aes_control);
s5p_set_aes(dev, dev->ctx->aes_key, req->info, dev->ctx->keylen);

s5p_set_dma_indata(dev, req->src);
@@ -571,6 +622,7 @@ static int s5p_aes_probe(struct platform_device *pdev)
struct s5p_aes_dev *pdata;
struct device *dev = &pdev->dev;
struct resource *res;
+ struct samsung_aes_variant *variant;

if (s5p_dev)
return -EEXIST;
@@ -587,6 +639,8 @@ static int s5p_aes_probe(struct platform_device *pdev)
resource_size(res), pdev->name))
return -EBUSY;

+ variant = find_s5p_sss_version(pdev);
+
pdata->clk = devm_clk_get(dev, "secss");
if (IS_ERR(pdata->clk)) {
dev_err(dev, "failed to find secss clock source\n");
@@ -599,6 +653,8 @@ static int s5p_aes_probe(struct platform_device *pdev)
pdata->ioaddr = devm_ioremap(dev, res->start,
resource_size(res));

+ pdata->aes_ioaddr = pdata->ioaddr + variant->aes_offset;
+
pdata->irq_fc = platform_get_irq(pdev, 0);
if (pdata->irq_fc < 0) {
err = pdata->irq_fc;
@@ -612,19 +668,22 @@ static int s5p_aes_probe(struct platform_device *pdev)
goto err_irq;
}

- pdata->irq_hash = platform_get_irq(pdev, 1);
- if (pdata->irq_hash < 0) {
- err = pdata->irq_hash;
- dev_warn(dev, "hash interrupt is not available.\n");
- goto err_irq;
- }
- err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
- IRQF_SHARED, pdev->name, pdev);
- if (err < 0) {
- dev_warn(dev, "hash interrupt is not available.\n");
- goto err_irq;
+ if (variant->has_hash_irq) {
+ pdata->irq_hash = platform_get_irq(pdev, 1);
+ if (pdata->irq_hash < 0) {
+ err = pdata->irq_hash;
+ dev_warn(dev, "hash interrupt is not available.\n");
+ goto err_irq;
+ }
+ err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
+ IRQF_SHARED, pdev->name, pdev);
+ if (err < 0) {
+ dev_warn(dev, "hash interrupt is not available.\n");
+ goto err_irq;
+ }
}

+ pdata->variant = variant;
pdata->dev = dev;
platform_set_drvdata(pdev, pdata);
s5p_dev = pdata;
--
1.7.9.5

2014-01-15 09:15:43

[permalink] [raw]

Subject: [PATCH 4/8 v4] crypto:s5p-sss: Kconfig: Let Exynos SoCs select SSS driver

From: Naveen Krishna Ch <[email protected]>

This patch modifies Kconfig such that ARCH_EXYNOS SoCs
which includes (Exynos4210, Exynos5250 and Exynos5420)
can also select Samsung SSS(Security SubSystem) driver.

Signed-off-by: Naveen Krishna Ch <[email protected]>
CC: Herbert Xu <[email protected]>
CC: David S. Miller <[email protected]>
CC: Vladimir Zapolskiy <[email protected]>
TO: <[email protected]>
CC: <[email protected]>
---
Changes since v3:
Modified description to use "Exynos" instead of individual SoC name

drivers/crypto/Kconfig | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index f4fd837..cb38863 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -300,14 +300,14 @@ config CRYPTO_DEV_DCP
capabilities of the DCP co-processor

config CRYPTO_DEV_S5P
- tristate "Support for Samsung S5PV210 crypto accelerator"
- depends on ARCH_S5PV210
+ tristate "Support for Samsung S5PV210/Exynos crypto accelerator"
+ depends on ARCH_S5PV210 || ARCH_EXYNOS
select CRYPTO_AES
select CRYPTO_ALGAPI
select CRYPTO_BLKCIPHER
help
This option allows you to have support for S5P crypto acceleration.
- Select this to offload Samsung S5PV210 or S5PC110 from AES
+ Select this to offload Samsung S5PV210 or S5PC110, Exynos from AES
algorithms execution.

config CRYPTO_DEV_TEGRA_AES
--
1.7.9.5

2014-01-15 09:16:06

[permalink] [raw]

Subject: [PATCH 5/8 v4] clk: samsung: exynos5250/5420: Add gate clock for SSS module

This patch adds gating clock for SSS(Security SubSystem)
module on Exynos5250/5420.

Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
TO: <[email protected]>
TO: Tomasz Figa <[email protected]>
CC: Kukjin Kim <[email protected]>
CC: <[email protected]>
---
Changes since v3:
1. Rebased on to https://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk.git
2. Added new ID for SSS clock on Exynos5250, with Documentation and
3. Added gate clocks definitions for SSS on Exynos5420 and Exynos5250

.../devicetree/bindings/clock/exynos5250-clock.txt | 1 +
drivers/clk/samsung/clk-exynos5250.c | 1 +
drivers/clk/samsung/clk-exynos5420.c | 4 ++++
include/dt-bindings/clock/exynos5250.h | 1 +
4 files changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
index 492ed09..a845fc6 100644
--- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
@@ -162,6 +162,7 @@ clock which they consume.
g2d 345
mdma0 346
smmu_mdma0 347
+ sss 348

[Clock Muxes]
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index ff4beeb..2c52fe1 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -387,6 +387,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
* CMU_ACP
*/
GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0),
+ GATE(CLK_SSS, "sss", "div_aclk266", GATE_IP_ACP, 2, 0, 0),
GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0),
GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0),

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index ab4f2f7..94915bb 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -26,6 +26,7 @@
#define DIV_CPU1 0x504
#define GATE_BUS_CPU 0x700
#define GATE_SCLK_CPU 0x800
+#define GATE_BUS_G2D 0x8700
#define CPLL_LOCK 0x10020
#define DPLL_LOCK 0x10030
#define EPLL_LOCK 0x10040
@@ -702,6 +703,9 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
0),
GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0,
0),
+
+ /* SSS */
+ GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_BUS_G2D, 2, 0, 0),
};

static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = {
diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h
index 922f2dc..f9b452b 100644
--- a/include/dt-bindings/clock/exynos5250.h
+++ b/include/dt-bindings/clock/exynos5250.h
@@ -150,6 +150,7 @@
#define CLK_G2D 345
#define CLK_MDMA0 346
#define CLK_SMMU_MDMA0 347
+#define CLK_SSS 348

/* mux clocks */
#define CLK_MOUT_HDMI 1024
--
1.7.9.5

2014-01-23 10:19:35

[permalink] [raw]

Subject: Re: [PATCH 1/8 v4] crypto:s5p-sss: Use platform_get_irq() instead of _byname()

Hello All,

On 15 January 2014 14:44, Naveen Krishna Chatradhi
<[email protected]> wrote:
> From: Naveen Krishna Ch <[email protected]>
>
> This patch uses the platform_get_irq() instead of the
> platform_get_irq_byname(). Making feeder control interrupt
> as resource "0" and hash interrupt as "1".
>
> reasons for this change.
> 1. Cannot find any Arch which is currently using this driver
> 2. Samsung Exynos4 and 5 SoCs only use the feeder control interrupt
> 3. Patches adding support for DT and H/W version are in pipeline
>
> Signed-off-by: Naveen Krishna Ch <[email protected]>
> Reviewed-by: Tomasz Figa <[email protected]>
> CC: Herbert Xu <[email protected]>
> CC: David S. Miller <[email protected]>
> CC: Vladimir Zapolskiy <[email protected]>
> TO: <[email protected]>
> CC: <[email protected]>
> ---
> Changes since v3:
> None
>
> drivers/crypto/s5p-sss.c | 24 ++++++++++++------------
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
> index cf149b1..93cddeb 100644
> --- a/drivers/crypto/s5p-sss.c
> +++ b/drivers/crypto/s5p-sss.c
> @@ -592,29 +592,29 @@ static int s5p_aes_probe(struct platform_device *pdev)
> pdata->ioaddr = devm_ioremap(dev, res->start,
> resource_size(res));
>
> - pdata->irq_hash = platform_get_irq_byname(pdev, "hash");
> - if (pdata->irq_hash < 0) {
> - err = pdata->irq_hash;
> - dev_warn(dev, "hash interrupt is not available.\n");
> + pdata->irq_fc = platform_get_irq(pdev, 0);
> + if (pdata->irq_fc < 0) {
> + err = pdata->irq_fc;
> + dev_warn(dev, "feed control interrupt is not available.\n");
> goto err_irq;
> }
> - err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
> + err = devm_request_irq(dev, pdata->irq_fc, s5p_aes_interrupt,
> IRQF_SHARED, pdev->name, pdev);
> if (err < 0) {
> - dev_warn(dev, "hash interrupt is not available.\n");
> + dev_warn(dev, "feed control interrupt is not available.\n");
> goto err_irq;
> }
>
> - pdata->irq_fc = platform_get_irq_byname(pdev, "feed control");
> - if (pdata->irq_fc < 0) {
> - err = pdata->irq_fc;
> - dev_warn(dev, "feed control interrupt is not available.\n");
> + pdata->irq_hash = platform_get_irq(pdev, 1);
> + if (pdata->irq_hash < 0) {
> + err = pdata->irq_hash;
> + dev_warn(dev, "hash interrupt is not available.\n");
> goto err_irq;
> }
> - err = devm_request_irq(dev, pdata->irq_fc, s5p_aes_interrupt,
> + err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
> IRQF_SHARED, pdev->name, pdev);
> if (err < 0) {
> - dev_warn(dev, "feed control interrupt is not available.\n");
> + dev_warn(dev, "hash interrupt is not available.\n");
> goto err_irq;
> }
>
> --
> 1.7.9.5
Any update on this patch, Please
>

--
Shine bright,
(: Nav :)

2014-01-23 10:20:15

[permalink] [raw]

Subject: Re: [PATCH 5/8 v4] clk: samsung: exynos5250/5420: Add gate clock for SSS module

Hello All,

On 15 January 2014 14:46, Naveen Krishna Chatradhi
<[email protected]> wrote:
> This patch adds gating clock for SSS(Security SubSystem)
> module on Exynos5250/5420.
>
> Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
> TO: <[email protected]>
> TO: Tomasz Figa <[email protected]>
> CC: Kukjin Kim <[email protected]>
> CC: <[email protected]>
> ---
> Changes since v3:
> 1. Rebased on to https://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk.git
> 2. Added new ID for SSS clock on Exynos5250, with Documentation and
> 3. Added gate clocks definitions for SSS on Exynos5420 and Exynos5250
>
> .../devicetree/bindings/clock/exynos5250-clock.txt | 1 +
> drivers/clk/samsung/clk-exynos5250.c | 1 +
> drivers/clk/samsung/clk-exynos5420.c | 4 ++++
> include/dt-bindings/clock/exynos5250.h | 1 +
> 4 files changed, 7 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
> index 492ed09..a845fc6 100644
> --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
> @@ -162,6 +162,7 @@ clock which they consume.
> g2d 345
> mdma0 346
> smmu_mdma0 347
> + sss 348
>
>
> [Clock Muxes]
> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
> index ff4beeb..2c52fe1 100644
> --- a/drivers/clk/samsung/clk-exynos5250.c
> +++ b/drivers/clk/samsung/clk-exynos5250.c
> @@ -387,6 +387,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
> * CMU_ACP
> */
> GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0),
> + GATE(CLK_SSS, "sss", "div_aclk266", GATE_IP_ACP, 2, 0, 0),
> GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0),
> GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0),
>
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index ab4f2f7..94915bb 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -26,6 +26,7 @@
> #define DIV_CPU1 0x504
> #define GATE_BUS_CPU 0x700
> #define GATE_SCLK_CPU 0x800
> +#define GATE_BUS_G2D 0x8700
> #define CPLL_LOCK 0x10020
> #define DPLL_LOCK 0x10030
> #define EPLL_LOCK 0x10040
> @@ -702,6 +703,9 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
> 0),
> GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0,
> 0),
> +
> + /* SSS */
> + GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_BUS_G2D, 2, 0, 0),
> };
>
> static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = {
> diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h
> index 922f2dc..f9b452b 100644
> --- a/include/dt-bindings/clock/exynos5250.h
> +++ b/include/dt-bindings/clock/exynos5250.h
> @@ -150,6 +150,7 @@
> #define CLK_G2D 345
> #define CLK_MDMA0 346
> #define CLK_SMMU_MDMA0 347
> +#define CLK_SSS 348
>
> /* mux clocks */
> #define CLK_MOUT_HDMI 1024
> --
> 1.7.9.5
Any update on this patch, Please
>

--
Shine bright,
(: Nav :)

2014-01-23 10:20:53

[permalink] [raw]

Subject: Re: [PATCH 2/8 v4] crypto:s5p-sss: Add device tree support

Hello All,

On 15 January 2014 14:44, Naveen Krishna Chatradhi
<[email protected]> wrote:
> This patch adds device tree support to the s5p-sss.c crypto driver.
>
> Also, Documentation under devicetree/bindings added.
>
> Signed-off-by: Naveen Krishna Ch <[email protected]>
> CC: Herbert Xu <[email protected]>
> CC: David S. Miller <[email protected]>
> CC: Vladimir Zapolskiy <[email protected]>
> TO: <[email protected]>
> CC: <[email protected]>
> ---
> Changes since v3:
> None
>
> .../devicetree/bindings/crypto/samsung-sss.txt | 20 ++++++++++++++++++++
> drivers/crypto/s5p-sss.c | 10 +++++++++-
> 2 files changed, 29 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/devicetree/bindings/crypto/samsung-sss.txt
>
> diff --git a/Documentation/devicetree/bindings/crypto/samsung-sss.txt b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
> new file mode 100644
> index 0000000..2f9d7e4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
> @@ -0,0 +1,20 @@
> +Samsung SoC SSS (Security SubSystem) module
> +
> +The SSS module in S5PV210 SoC supports the following:
> +-- Feeder (FeedCtrl)
> +-- Advanced Encryption Standard (AES)
> +-- Data Encryption Standard (DES)/3DES
> +-- Public Key Accelerator (PKA)
> +-- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
> +-- PRNG: Pseudo Random Number Generator
> +
> +Required properties:
> +
> +- compatible : Should contain entries for this and backward compatible
> + SSS versions:
> + - "samsung,s5pv210-secss" for S5PV210 SoC.
> +- reg : Offset and length of the register set for the module
> +- interrupts : the interrupt-specifier for the SSS module.
> + Two interrupts "feed control and hash" in case of S5PV210
> +- clocks : the required gating clock for the SSS module.
> +- clock-names : the gating clock name to be requested in the SSS driver.
> diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
> index 93cddeb..2da5617 100644
> --- a/drivers/crypto/s5p-sss.c
> +++ b/drivers/crypto/s5p-sss.c
> @@ -22,6 +22,7 @@
> #include <linux/scatterlist.h>
> #include <linux/dma-mapping.h>
> #include <linux/io.h>
> +#include <linux/of.h>
> #include <linux/crypto.h>
> #include <linux/interrupt.h>
>
> @@ -177,6 +178,12 @@ struct s5p_aes_dev {
>
> static struct s5p_aes_dev *s5p_dev;
>
> +static const struct of_device_id s5p_sss_dt_match[] = {
> + { .compatible = "samsung,s5pv210-secss", },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, s5p_sss_dt_match);
> +
> static void s5p_set_dma_indata(struct s5p_aes_dev *dev, struct scatterlist *sg)
> {
> SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg));
> @@ -676,7 +683,8 @@ static struct platform_driver s5p_aes_crypto = {
> .remove = s5p_aes_remove,
> .driver = {
> .owner = THIS_MODULE,
> - .name = "s5p-secss",
> + .name = "s5pv210-secss",
> + .of_match_table = s5p_sss_dt_match,
> },
> };
>
> --
> 1.7.9.5
Any update on this patch, Please
>

--
Shine bright,
(: Nav :)

2014-01-23 10:28:08

by Sylwester Nawrocki

[permalink] [raw]

Subject: Re: [PATCH 2/8 v4] crypto:s5p-sss: Add device tree support

Hi,

(Adding missing devicetre ML list at CC.)

On 15/01/14 10:14, Naveen Krishna Chatradhi wrote:
> This patch adds device tree support to the s5p-sss.c crypto driver.
>
> Also, Documentation under devicetree/bindings added.
>
> Signed-off-by: Naveen Krishna Ch <[email protected]>
> CC: Herbert Xu <[email protected]>
> CC: David S. Miller <[email protected]>
> CC: Vladimir Zapolskiy <[email protected]>
> TO: <[email protected]>
> CC: <[email protected]>
> ---
> Changes since v3:
> None
>
> .../devicetree/bindings/crypto/samsung-sss.txt | 20 ++++++++++++++++++++
> drivers/crypto/s5p-sss.c | 10 +++++++++-
> 2 files changed, 29 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/devicetree/bindings/crypto/samsung-sss.txt
>
> diff --git a/Documentation/devicetree/bindings/crypto/samsung-sss.txt b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
> new file mode 100644
> index 0000000..2f9d7e4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
> @@ -0,0 +1,20 @@
> +Samsung SoC SSS (Security SubSystem) module
> +
> +The SSS module in S5PV210 SoC supports the following:
> +-- Feeder (FeedCtrl)
> +-- Advanced Encryption Standard (AES)
> +-- Data Encryption Standard (DES)/3DES
> +-- Public Key Accelerator (PKA)
> +-- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
> +-- PRNG: Pseudo Random Number Generator
> +
> +Required properties:
> +
> +- compatible : Should contain entries for this and backward compatible
> + SSS versions:
> + - "samsung,s5pv210-secss" for S5PV210 SoC.
> +- reg : Offset and length of the register set for the module
> +- interrupts : the interrupt-specifier for the SSS module.
> + Two interrupts "feed control and hash" in case of S5PV210

It should be described in what order both interrupts are supposed to be
specified.

> +- clocks : the required gating clock for the SSS module.
> +- clock-names : the gating clock name to be requested in the SSS driver.
> diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
> index 93cddeb..2da5617 100644
> --- a/drivers/crypto/s5p-sss.c
> +++ b/drivers/crypto/s5p-sss.c
> @@ -22,6 +22,7 @@
> #include <linux/scatterlist.h>
> #include <linux/dma-mapping.h>
> #include <linux/io.h>
> +#include <linux/of.h>
> #include <linux/crypto.h>
> #include <linux/interrupt.h>
>
> @@ -177,6 +178,12 @@ struct s5p_aes_dev {
>
> static struct s5p_aes_dev *s5p_dev;
>
> +static const struct of_device_id s5p_sss_dt_match[] = {
> + { .compatible = "samsung,s5pv210-secss", },

nit: the first semicolon could be omitted.

> + { },
> +};
> +MODULE_DEVICE_TABLE(of, s5p_sss_dt_match);
> +
> static void s5p_set_dma_indata(struct s5p_aes_dev *dev, struct scatterlist *sg)
> {
> SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg));
> @@ -676,7 +683,8 @@ static struct platform_driver s5p_aes_crypto = {
> .remove = s5p_aes_remove,
> .driver = {
> .owner = THIS_MODULE,
> - .name = "s5p-secss",
> + .name = "s5pv210-secss",

Why you're changing the driver name ? It's not related and not needed AFAICT.

> + .of_match_table = s5p_sss_dt_match,
> },
> };

--
Thanks,
Sylwester

2014-01-23 17:41:35

by Mark Rutland

[permalink] [raw]

Subject: Re: [PATCH 2/8 v4] crypto:s5p-sss: Add device tree support

On Thu, Jan 23, 2014 at 10:28:08AM +0000, Sylwester Nawrocki wrote:
> Hi,
>
> (Adding missing devicetre ML list at CC.)
>
> On 15/01/14 10:14, Naveen Krishna Chatradhi wrote:
> > This patch adds device tree support to the s5p-sss.c crypto driver.
> >
> > Also, Documentation under devicetree/bindings added.
> >
> > Signed-off-by: Naveen Krishna Ch <[email protected]>
> > CC: Herbert Xu <[email protected]>
> > CC: David S. Miller <[email protected]>
> > CC: Vladimir Zapolskiy <[email protected]>
> > TO: <[email protected]>
> > CC: <[email protected]>
> > ---
> > Changes since v3:
> > None
> >
> > .../devicetree/bindings/crypto/samsung-sss.txt | 20 ++++++++++++++++++++
> > drivers/crypto/s5p-sss.c | 10 +++++++++-
> > 2 files changed, 29 insertions(+), 1 deletion(-)
> > create mode 100644 Documentation/devicetree/bindings/crypto/samsung-sss.txt
> >
> > diff --git a/Documentation/devicetree/bindings/crypto/samsung-sss.txt b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
> > new file mode 100644
> > index 0000000..2f9d7e4
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
> > @@ -0,0 +1,20 @@
> > +Samsung SoC SSS (Security SubSystem) module
> > +
> > +The SSS module in S5PV210 SoC supports the following:
> > +-- Feeder (FeedCtrl)
> > +-- Advanced Encryption Standard (AES)
> > +-- Data Encryption Standard (DES)/3DES
> > +-- Public Key Accelerator (PKA)
> > +-- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
> > +-- PRNG: Pseudo Random Number Generator
> > +
> > +Required properties:
> > +
> > +- compatible : Should contain entries for this and backward compatible
> > + SSS versions:
> > + - "samsung,s5pv210-secss" for S5PV210 SoC.
> > +- reg : Offset and length of the register set for the module
> > +- interrupts : the interrupt-specifier for the SSS module.
> > + Two interrupts "feed control and hash" in case of S5PV210
>
> It should be described in what order both interrupts are supposed to be
> specified.
>
> > +- clocks : the required gating clock for the SSS module.
> > +- clock-names : the gating clock name to be requested in the SSS driver.

The _exact_ names expected must be described in the binding, or this
property is useless.

> > diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
> > index 93cddeb..2da5617 100644
> > --- a/drivers/crypto/s5p-sss.c
> > +++ b/drivers/crypto/s5p-sss.c
> > @@ -22,6 +22,7 @@
> > #include <linux/scatterlist.h>
> > #include <linux/dma-mapping.h>
> > #include <linux/io.h>
> > +#include <linux/of.h>
> > #include <linux/crypto.h>
> > #include <linux/interrupt.h>
> >
> > @@ -177,6 +178,12 @@ struct s5p_aes_dev {
> >
> > static struct s5p_aes_dev *s5p_dev;
> >
> > +static const struct of_device_id s5p_sss_dt_match[] = {
> > + { .compatible = "samsung,s5pv210-secss", },
>
> nit: the first semicolon could be omitted.

I assume you mean comma ratehr than semicolon?

Cheers,
Mark.

2014-01-23 17:47:25

by Sylwester Nawrocki

[permalink] [raw]

Subject: Re: [PATCH 2/8 v4] crypto:s5p-sss: Add device tree support

On 23/01/14 18:41, Mark Rutland wrote:
>>> diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
>>> > > index 93cddeb..2da5617 100644
>>> > > --- a/drivers/crypto/s5p-sss.c
>>> > > +++ b/drivers/crypto/s5p-sss.c
>>> > > @@ -22,6 +22,7 @@
>>> > > #include <linux/scatterlist.h>
>>> > > #include <linux/dma-mapping.h>
>>> > > #include <linux/io.h>
>>> > > +#include <linux/of.h>
>>> > > #include <linux/crypto.h>
>>> > > #include <linux/interrupt.h>
>>> > >
>>> > > @@ -177,6 +178,12 @@ struct s5p_aes_dev {
>>> > >
>>> > > static struct s5p_aes_dev *s5p_dev;
>>> > >
>>> > > +static const struct of_device_id s5p_sss_dt_match[] = {
>>> > > + { .compatible = "samsung,s5pv210-secss", },
>> >
>> > nit: the first semicolon could be omitted.
>
> I assume you mean comma ratehr than semicolon?

Indeed...and it's actually the second one :-/

--
Regards,
Sylwester

2014-01-23 17:59:30

by Mark Rutland

[permalink] [raw]

Subject: Re: [PATCH 2/8 v4] crypto:s5p-sss: Add device tree support

On Thu, Jan 23, 2014 at 05:47:25PM +0000, Sylwester Nawrocki wrote:
> On 23/01/14 18:41, Mark Rutland wrote:
> >>> diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
> >>> > > index 93cddeb..2da5617 100644
> >>> > > --- a/drivers/crypto/s5p-sss.c
> >>> > > +++ b/drivers/crypto/s5p-sss.c
> >>> > > @@ -22,6 +22,7 @@
> >>> > > #include <linux/scatterlist.h>
> >>> > > #include <linux/dma-mapping.h>
> >>> > > #include <linux/io.h>
> >>> > > +#include <linux/of.h>
> >>> > > #include <linux/crypto.h>
> >>> > > #include <linux/interrupt.h>
> >>> > >
> >>> > > @@ -177,6 +178,12 @@ struct s5p_aes_dev {
> >>> > >
> >>> > > static struct s5p_aes_dev *s5p_dev;
> >>> > >
> >>> > > +static const struct of_device_id s5p_sss_dt_match[] = {
> >>> > > + { .compatible = "samsung,s5pv210-secss", },
> >> >
> >> > nit: the first semicolon could be omitted.
> >
> > I assume you mean comma ratehr than semicolon?
>
> Indeed...and it's actually the second one :-/

Also, I meant "rather" rather than "ratehr". At least we figured it out
in the end. :)

Thanks,
Mark.

2014-01-24 14:09:58

[permalink] [raw]

Subject: Re: [PATCH 3/8 v4] crypto:s5p-sss: Add support for SSS module on Exynos

Hi Naveen,

On 15.01.2014 10:15, Naveen Krishna Chatradhi wrote:
> This patch adds new compatible and variant struct to support the SSS
> module on Exynos4 (Exynos4210), Exynos5 (Exynos5420 and Exynos5250)
> for which
> 1. AES register are at an offset of 0x200 and
> 2. hash interrupt is not available
[snip]
> Required properties:
>
> - compatible : Should contain entries for this and backward compatible
> SSS versions:
> - "samsung,s5pv210-secss" for S5PV210 SoC.
> + - "samsung,exynos4210-secss" for Exynos4210, Exynos4212, Exynos4412, Exynos5250,
> + Exynos5260 and Exynos5420 SoCs.
> - reg : Offset and length of the register set for the module
> - interrupts : the interrupt-specifier for the SSS module.
> - Two interrupts "feed control and hash" in case of S5PV210
> -- clocks : the required gating clock for the SSS module.
> -- clock-names : the gating clock name to be requested in the SSS driver.
> + -- Two interrupts "feed control and hash" in case of
> + "samsung,s5pv210-secss"
> + -- One interrupts "feed control" in case of
> + "samsung,exynos4210-secss".
> +- clocks : list of clock phandle and specifier pairs for all clocks listed in
> + clock-names property.
> +- clock-names : list of device clock input names; should contain one entry
> + "secss".

Hmm, I guess this is a rebase error, because this should rather be
squashed with patch 2/8.

Otherwise the patch looks good to me.

Best regards,
Tomasz

2014-01-24 15:26:38

[permalink] [raw]

Subject: Re: [PATCH 5/8 v4] clk: samsung: exynos5250/5420: Add gate clock for SSS module

Hi Naveen,

Exynos5250 specific part looks good, but I have a little doubt in case
of Exynos5420.

On 15.01.2014 10:16, Naveen Krishna Chatradhi wrote:
> This patch adds gating clock for SSS(Security SubSystem)
> module on Exynos5250/5420.
>
> Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
> TO: <[email protected]>
> TO: Tomasz Figa <[email protected]>
> CC: Kukjin Kim <[email protected]>
> CC: <[email protected]>
> ---
> Changes since v3:
> 1. Rebased on to https://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk.git
> 2. Added new ID for SSS clock on Exynos5250, with Documentation and
> 3. Added gate clocks definitions for SSS on Exynos5420 and Exynos5250
[snip]
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -26,6 +26,7 @@
> #define DIV_CPU1 0x504
> #define GATE_BUS_CPU 0x700
> #define GATE_SCLK_CPU 0x800
> +#define GATE_BUS_G2D 0x8700
> #define CPLL_LOCK 0x10020
> #define DPLL_LOCK 0x10030
> #define EPLL_LOCK 0x10040
> @@ -702,6 +703,9 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
> 0),
> GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0,
> 0),
> +
> + /* SSS */
> + GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_BUS_G2D, 2, 0, 0),

Isn't there a combined gate for all SSS clocks in one of GATE_IP_*
registers?

Best regards,
Tomasz

2014-01-29 09:19:24

[permalink] [raw]

Subject: [PATCH 1/9 v5] crypto:s5p-sss: Use platform_get_irq() instead of _byname()

From: Naveen Krishna Ch <[email protected]>

This patch uses the platform_get_irq() instead of the
platform_get_irq_byname(). Making feeder control interrupt
as resource "0" and hash interrupt as "1".

reasons for this change.
1. Cannot find any Arch which is currently using this driver
2. Samsung Exynos4 and 5 SoCs only use the feeder control interrupt
3. Patches adding support for DT and H/W version are in pipeline

Signed-off-by: Naveen Krishna Ch <[email protected]>
Reviewed-by: Tomasz Figa <[email protected]>
CC: Herbert Xu <[email protected]>
CC: David S. Miller <[email protected]>
CC: Vladimir Zapolskiy <[email protected]>
TO: <[email protected]>
CC: <[email protected]>
---
Changes since v4:
None
Changes since v3:
None
drivers/crypto/s5p-sss.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
index cf149b1..93cddeb 100644
--- a/drivers/crypto/s5p-sss.c
+++ b/drivers/crypto/s5p-sss.c
@@ -592,29 +592,29 @@ static int s5p_aes_probe(struct platform_device *pdev)
pdata->ioaddr = devm_ioremap(dev, res->start,
resource_size(res));

- pdata->irq_hash = platform_get_irq_byname(pdev, "hash");
- if (pdata->irq_hash < 0) {
- err = pdata->irq_hash;
- dev_warn(dev, "hash interrupt is not available.\n");
+ pdata->irq_fc = platform_get_irq(pdev, 0);
+ if (pdata->irq_fc < 0) {
+ err = pdata->irq_fc;
+ dev_warn(dev, "feed control interrupt is not available.\n");
goto err_irq;
}
- err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
+ err = devm_request_irq(dev, pdata->irq_fc, s5p_aes_interrupt,
IRQF_SHARED, pdev->name, pdev);
if (err < 0) {
- dev_warn(dev, "hash interrupt is not available.\n");
+ dev_warn(dev, "feed control interrupt is not available.\n");
goto err_irq;
}

- pdata->irq_fc = platform_get_irq_byname(pdev, "feed control");
- if (pdata->irq_fc < 0) {
- err = pdata->irq_fc;
- dev_warn(dev, "feed control interrupt is not available.\n");
+ pdata->irq_hash = platform_get_irq(pdev, 1);
+ if (pdata->irq_hash < 0) {
+ err = pdata->irq_hash;
+ dev_warn(dev, "hash interrupt is not available.\n");
goto err_irq;
}
- err = devm_request_irq(dev, pdata->irq_fc, s5p_aes_interrupt,
+ err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
IRQF_SHARED, pdev->name, pdev);
if (err < 0) {
- dev_warn(dev, "feed control interrupt is not available.\n");
+ dev_warn(dev, "hash interrupt is not available.\n");
goto err_irq;
}

--
1.7.9.5

2014-01-29 09:21:07

[permalink] [raw]

Subject: [PATCH 2/9 v5] crypto:s5p-sss: Add device tree support

This patch adds device tree support to the s5p-sss.c crypto driver.

Also, Documentation under devicetree/bindings added.

Signed-off-by: Naveen Krishna Ch <[email protected]>
CC: Herbert Xu <[email protected]>
CC: David S. Miller <[email protected]>
CC: Vladimir Zapolskiy <[email protected]>
TO: <[email protected]>
CC: <[email protected]>
---
Changes since v4:
Modified Documentation to give clock names and example for interrupts

Changes since v3:
None
.../devicetree/bindings/crypto/samsung-sss.txt | 24 ++++++++++++++++++++
drivers/crypto/s5p-sss.c | 8 +++++++
2 files changed, 32 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/samsung-sss.txt

diff --git a/Documentation/devicetree/bindings/crypto/samsung-sss.txt b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
new file mode 100644
index 0000000..d193084
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
@@ -0,0 +1,24 @@
+Samsung SoC SSS (Security SubSystem) module
+
+The SSS module in S5PV210 SoC supports the following:
+-- Feeder (FeedCtrl)
+-- Advanced Encryption Standard (AES)
+-- Data Encryption Standard (DES)/3DES
+-- Public Key Accelerator (PKA)
+-- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
+-- PRNG: Pseudo Random Number Generator
+
+Required properties:
+
+- compatible : Should contain entries for this and backward compatible
+ SSS versions:
+ - "samsung,s5pv210-secss" for S5PV210 SoC.
+- reg : Offset and length of the register set for the module
+- interrupts : the interrupt-specifier for the SSS module.
+ Two interrupts "feed control and hash" in case of S5PV210
+ Eg : interrupts = <0 feed-control 0> <0 hash 0>;
+- clocks : list of clock phandle and specifier pairs for all clocks listed in
+ clock-names property.
+- clock-names : list of device clock input names; should contain one entry
+ "secss".
+
diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
index 93cddeb..73c8b38 100644
--- a/drivers/crypto/s5p-sss.c
+++ b/drivers/crypto/s5p-sss.c
@@ -22,6 +22,7 @@
#include <linux/scatterlist.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>
+#include <linux/of.h>
#include <linux/crypto.h>
#include <linux/interrupt.h>

@@ -177,6 +178,12 @@ struct s5p_aes_dev {

static struct s5p_aes_dev *s5p_dev;

+static const struct of_device_id s5p_sss_dt_match[] = {
+ { .compatible = "samsung,s5pv210-secss" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, s5p_sss_dt_match);
+
static void s5p_set_dma_indata(struct s5p_aes_dev *dev, struct scatterlist *sg)
{
SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg));
@@ -677,6 +684,7 @@ static struct platform_driver s5p_aes_crypto = {
.driver = {
.owner = THIS_MODULE,
.name = "s5p-secss",
+ .of_match_table = s5p_sss_dt_match,
},
};

--
1.7.9.5

2014-01-29 09:21:34

[permalink] [raw]

Subject: [PATCH 3/9 v5] crypto:s5p-sss: Add support for SSS module on Exynos

This patch adds new compatible and variant struct to support the SSS
module on Exynos4 (Exynos4210), Exynos5 (Exynos5420 and Exynos5250)
for which
1. AES register are at an offset of 0x200 and
2. hash interrupt is not available

Signed-off-by: Naveen Krishna Ch <[email protected]>
CC: Herbert Xu <[email protected]>
CC: David S. Miller <[email protected]>
CC: Vladimir Zapolskiy <[email protected]>
TO: <[email protected]>
CC: <[email protected]>
---
Changes since v4:
Fix rebase error because of the patch 2/9

.../devicetree/bindings/crypto/samsung-sss.txt | 21 +++-
drivers/crypto/s5p-sss.c | 107 +++++++++++++++-----
2 files changed, 103 insertions(+), 25 deletions(-)

diff --git a/Documentation/devicetree/bindings/crypto/samsung-sss.txt b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
index d193084..ca578d3 100644
--- a/Documentation/devicetree/bindings/crypto/samsung-sss.txt
+++ b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
@@ -8,17 +8,36 @@ The SSS module in S5PV210 SoC supports the following:
-- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
-- PRNG: Pseudo Random Number Generator

+The SSS module in Exynos4 (Exynos4210) and
+Exynos5 (Exynos5420 and Exynos5250) SoCs
+supports the following also:
+-- ARCFOUR (ARC4)
+-- True Random Number Generator (TRNG)
+-- Secure Key Manager
+
Required properties:

- compatible : Should contain entries for this and backward compatible
SSS versions:
- "samsung,s5pv210-secss" for S5PV210 SoC.
+ - "samsung,exynos4210-secss" for Exynos4210, Exynos4212, Exynos4412, Exynos5250,
+ Exynos5260 and Exynos5420 SoCs.
- reg : Offset and length of the register set for the module
- interrupts : the interrupt-specifier for the SSS module.
Two interrupts "feed control and hash" in case of S5PV210
Eg : interrupts = <0 feed-control 0> <0 hash 0>;
+ -- One interrupts "feed control" in case of
+ "samsung,exynos4210-secss".
- clocks : list of clock phandle and specifier pairs for all clocks listed in
clock-names property.
- clock-names : list of device clock input names; should contain one entry
"secss".
-
+Example:
+ /* SSS_VER_5 */
+ sss@10830000 {
+ compatible = "samsung,exynos4210-secss";
+ reg = <0x10830000 0x10000>;
+ interrupts = <0 112 0>;
+ clocks = <&clock 471>;
+ clock-names = "secss";
+ };
diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
index 73c8b38..da1c8943 100644
--- a/drivers/crypto/s5p-sss.c
+++ b/drivers/crypto/s5p-sss.c
@@ -106,7 +106,7 @@
#define SSS_REG_FCPKDMAO 0x005C

/* AES registers */
-#define SSS_REG_AES_CONTROL 0x4000
+#define SSS_REG_AES_CONTROL 0x00
#define SSS_AES_BYTESWAP_DI _BIT(11)
#define SSS_AES_BYTESWAP_DO _BIT(10)
#define SSS_AES_BYTESWAP_IV _BIT(9)
@@ -122,21 +122,25 @@
#define SSS_AES_CHAIN_MODE_CTR _SBF(1, 0x02)
#define SSS_AES_MODE_DECRYPT _BIT(0)

-#define SSS_REG_AES_STATUS 0x4004
+#define SSS_REG_AES_STATUS 0x04
#define SSS_AES_BUSY _BIT(2)
#define SSS_AES_INPUT_READY _BIT(1)
#define SSS_AES_OUTPUT_READY _BIT(0)

-#define SSS_REG_AES_IN_DATA(s) (0x4010 + (s << 2))
-#define SSS_REG_AES_OUT_DATA(s) (0x4020 + (s << 2))
-#define SSS_REG_AES_IV_DATA(s) (0x4030 + (s << 2))
-#define SSS_REG_AES_CNT_DATA(s) (0x4040 + (s << 2))
-#define SSS_REG_AES_KEY_DATA(s) (0x4080 + (s << 2))
+#define SSS_REG_AES_IN_DATA(s) (0x10 + (s << 2))
+#define SSS_REG_AES_OUT_DATA(s) (0x20 + (s << 2))
+#define SSS_REG_AES_IV_DATA(s) (0x30 + (s << 2))
+#define SSS_REG_AES_CNT_DATA(s) (0x40 + (s << 2))
+#define SSS_REG_AES_KEY_DATA(s) (0x80 + (s << 2))

#define SSS_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg))
#define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg))
#define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg))

+#define SSS_AES_REG(dev, reg) ((dev)->aes_ioaddr + SSS_REG_##reg)
+#define SSS_AES_WRITE(dev, reg, val) __raw_writel((val), \
+ SSS_AES_REG(dev, reg))
+
/* HW engine modes */
#define FLAGS_AES_DECRYPT _BIT(0)
#define FLAGS_AES_MODE_MASK _SBF(1, 0x03)
@@ -146,6 +150,20 @@
#define AES_KEY_LEN 16
#define CRYPTO_QUEUE_LEN 1

+/**
+ * struct samsung_aes_variant - platform specific SSS driver data
+ * @has_hash_irq: true if SSS module uses hash interrupt, false otherwise
+ * @aes_offset: AES register offset from SSS module's base.
+ *
+ * Specifies platform specific configuration of SSS module.
+ * Note: A structure for driver specific platform data is used for future
+ * expansion of its usage.
+ */
+struct samsung_aes_variant {
+ bool has_hash_irq;
+ unsigned int aes_offset;
+};
+
struct s5p_aes_reqctx {
unsigned long mode;
};
@@ -162,6 +180,7 @@ struct s5p_aes_dev {
struct device *dev;
struct clk *clk;
void __iomem *ioaddr;
+ void __iomem *aes_ioaddr;
int irq_hash;
int irq_fc;

@@ -174,16 +193,48 @@ struct s5p_aes_dev {
struct crypto_queue queue;
bool busy;
spinlock_t lock;
+
+ struct samsung_aes_variant *variant;
};

static struct s5p_aes_dev *s5p_dev;

+static const struct samsung_aes_variant s5p_aes_data = {
+ .has_hash_irq = true,
+ .aes_offset = 0x4000,
+};
+
+static const struct samsung_aes_variant exynos_aes_data = {
+ .has_hash_irq = false,
+ .aes_offset = 0x200,
+};
+
static const struct of_device_id s5p_sss_dt_match[] = {
- { .compatible = "samsung,s5pv210-secss" },
+ {
+ .compatible = "samsung,s5pv210-secss",
+ .data = &s5p_aes_data,
+ },
+ {
+ .compatible = "samsung,exynos4210-secss",
+ .data = &exynos_aes_data,
+ },
{ },
};
MODULE_DEVICE_TABLE(of, s5p_sss_dt_match);

+static inline struct samsung_aes_variant *find_s5p_sss_version
+ (struct platform_device *pdev)
+{
+ if (IS_ENABLED(CONFIG_OF) && (pdev->dev.of_node)) {
+ const struct of_device_id *match;
+ match = of_match_node(s5p_sss_dt_match,
+ pdev->dev.of_node);
+ return (struct samsung_aes_variant *)match->data;
+ }
+ return (struct samsung_aes_variant *)
+ platform_get_device_id(pdev)->driver_data;
+}
+
static void s5p_set_dma_indata(struct s5p_aes_dev *dev, struct scatterlist *sg)
{
SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg));
@@ -329,14 +380,14 @@ static void s5p_set_aes(struct s5p_aes_dev *dev,
{
void __iomem *keystart;

- memcpy(dev->ioaddr + SSS_REG_AES_IV_DATA(0), iv, 0x10);
+ memcpy(dev->aes_ioaddr + SSS_REG_AES_IV_DATA (0), iv, 0x10);

if (keylen == AES_KEYSIZE_256)
- keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(0);
+ keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(0);
else if (keylen == AES_KEYSIZE_192)
- keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(2);
+ keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(2);
else
- keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(4);
+ keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(4);

memcpy(keystart, key, keylen);
}
@@ -386,7 +437,7 @@ static void s5p_aes_crypt_start(struct s5p_aes_dev *dev, unsigned long mode)
if (err)
goto outdata_error;

- SSS_WRITE(dev, AES_CONTROL, aes_control);
+ SSS_AES_WRITE(dev, AES_CONTROL, aes_control);
s5p_set_aes(dev, dev->ctx->aes_key, req->info, dev->ctx->keylen);

s5p_set_dma_indata(dev, req->src);
@@ -571,6 +622,7 @@ static int s5p_aes_probe(struct platform_device *pdev)
struct s5p_aes_dev *pdata;
struct device *dev = &pdev->dev;
struct resource *res;
+ struct samsung_aes_variant *variant;

if (s5p_dev)
return -EEXIST;
@@ -587,6 +639,8 @@ static int s5p_aes_probe(struct platform_device *pdev)
resource_size(res), pdev->name))
return -EBUSY;

+ variant = find_s5p_sss_version(pdev);
+
pdata->clk = devm_clk_get(dev, "secss");
if (IS_ERR(pdata->clk)) {
dev_err(dev, "failed to find secss clock source\n");
@@ -599,6 +653,8 @@ static int s5p_aes_probe(struct platform_device *pdev)
pdata->ioaddr = devm_ioremap(dev, res->start,
resource_size(res));

+ pdata->aes_ioaddr = pdata->ioaddr + variant->aes_offset;
+
pdata->irq_fc = platform_get_irq(pdev, 0);
if (pdata->irq_fc < 0) {
err = pdata->irq_fc;
@@ -612,19 +668,22 @@ static int s5p_aes_probe(struct platform_device *pdev)
goto err_irq;
}

- pdata->irq_hash = platform_get_irq(pdev, 1);
- if (pdata->irq_hash < 0) {
- err = pdata->irq_hash;
- dev_warn(dev, "hash interrupt is not available.\n");
- goto err_irq;
- }
- err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
- IRQF_SHARED, pdev->name, pdev);
- if (err < 0) {
- dev_warn(dev, "hash interrupt is not available.\n");
- goto err_irq;
+ if (variant->has_hash_irq) {
+ pdata->irq_hash = platform_get_irq(pdev, 1);
+ if (pdata->irq_hash < 0) {
+ err = pdata->irq_hash;
+ dev_warn(dev, "hash interrupt is not available.\n");
+ goto err_irq;
+ }
+ err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
+ IRQF_SHARED, pdev->name, pdev);
+ if (err < 0) {
+ dev_warn(dev, "hash interrupt is not available.\n");
+ goto err_irq;
+ }
}

+ pdata->variant = variant;
pdata->dev = dev;
platform_set_drvdata(pdev, pdata);
s5p_dev = pdata;
--
1.7.9.5

2014-01-29 09:22:41

[permalink] [raw]

Subject: [PATCH 4/9 v5] crypto:s5p-sss: Kconfig: Let Exynos SoCs select SSS driver

From: Naveen Krishna Ch <[email protected]>

This patch modifies Kconfig such that ARCH_EXYNOS SoCs
which includes (Exynos4210, Exynos5250 and Exynos5420)
can also select Samsung SSS(Security SubSystem) driver.

Signed-off-by: Naveen Krishna Ch <[email protected]>
CC: Herbert Xu <[email protected]>
CC: David S. Miller <[email protected]>
CC: Vladimir Zapolskiy <[email protected]>
TO: <[email protected]>
CC: <[email protected]>
---
Changes since v4:
none
Changes since v3:
Modified description to use "Exynos" instead of individual SoC name
drivers/crypto/Kconfig | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index f4fd837..cb38863 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -300,14 +300,14 @@ config CRYPTO_DEV_DCP
capabilities of the DCP co-processor

config CRYPTO_DEV_S5P
- tristate "Support for Samsung S5PV210 crypto accelerator"
- depends on ARCH_S5PV210
+ tristate "Support for Samsung S5PV210/Exynos crypto accelerator"
+ depends on ARCH_S5PV210 || ARCH_EXYNOS
select CRYPTO_AES
select CRYPTO_ALGAPI
select CRYPTO_BLKCIPHER
help
This option allows you to have support for S5P crypto acceleration.
- Select this to offload Samsung S5PV210 or S5PC110 from AES
+ Select this to offload Samsung S5PV210 or S5PC110, Exynos from AES
algorithms execution.

config CRYPTO_DEV_TEGRA_AES
--
1.7.9.5

2014-01-29 09:24:06

[permalink] [raw]

Subject: [PATCH 5/9 v5] clk: samsung exynos5250/5420: Add gate clock for SSS module

This patch adds gating clock for SSS(Security SubSystem)
module on Exynos5250/5420.

Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
TO: <[email protected]>
TO: Tomasz Figa <[email protected]>
CC: Kukjin Kim <[email protected]>
CC: <[email protected]>
---
Changes since v4:
Use register GATE_IP_G2D instead of GATE_BUS_G2D for Exynos5420
Changes since v3:
1. Rebased on to https://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk.git
2. Added new ID for SSS clock on Exynos5250, with Documentation and
3. Added gate clocks definitions for SSS on Exynos5420 and Exynos5250
.../devicetree/bindings/clock/exynos5250-clock.txt | 1 +
drivers/clk/samsung/clk-exynos5250.c | 1 +
drivers/clk/samsung/clk-exynos5420.c | 4 ++++
include/dt-bindings/clock/exynos5250.h | 1 +
4 files changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
index 492ed09..a845fc6 100644
--- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
@@ -162,6 +162,7 @@ clock which they consume.
g2d 345
mdma0 346
smmu_mdma0 347
+ sss 348

[Clock Muxes]
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index ff4beeb..2c52fe1 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -387,6 +387,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
* CMU_ACP
*/
GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0),
+ GATE(CLK_SSS, "sss", "div_aclk266", GATE_IP_ACP, 2, 0, 0),
GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0),
GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0),

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index ab4f2f7..c93d4d5 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -26,6 +26,7 @@
#define DIV_CPU1 0x504
#define GATE_BUS_CPU 0x700
#define GATE_SCLK_CPU 0x800
+#define GATE_IP_G2D 0x8800
#define CPLL_LOCK 0x10020
#define DPLL_LOCK 0x10030
#define EPLL_LOCK 0x10040
@@ -702,6 +703,9 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
0),
GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0,
0),
+
+ /* SSS */
+ GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
};

static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = {
diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h
index 922f2dc..f9b452b 100644
--- a/include/dt-bindings/clock/exynos5250.h
+++ b/include/dt-bindings/clock/exynos5250.h
@@ -150,6 +150,7 @@
#define CLK_G2D 345
#define CLK_MDMA0 346
#define CLK_SMMU_MDMA0 347
+#define CLK_SSS 348

/* mux clocks */
#define CLK_MOUT_HDMI 1024
--
1.7.9.5

2014-02-06 14:37:02

[permalink] [raw]

Subject: Re: [PATCH 2/9 v5] crypto:s5p-sss: Add device tree support

Hi Naveen,

On 29.01.2014 10:20, Naveen Krishna Chatradhi wrote:
> This patch adds device tree support to the s5p-sss.c crypto driver.
>
> Also, Documentation under devicetree/bindings added.
>
> Signed-off-by: Naveen Krishna Ch <[email protected]>
> CC: Herbert Xu <[email protected]>
> CC: David S. Miller <[email protected]>
> CC: Vladimir Zapolskiy <[email protected]>
> TO: <[email protected]>
> CC: <[email protected]>
> ---
> Changes since v4:
> Modified Documentation to give clock names and example for interrupts
>
> Changes since v3:
> None
> .../devicetree/bindings/crypto/samsung-sss.txt | 24 ++++++++++++++++++++
> drivers/crypto/s5p-sss.c | 8 +++++++
> 2 files changed, 32 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/crypto/samsung-sss.txt
>
> diff --git a/Documentation/devicetree/bindings/crypto/samsung-sss.txt b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
> new file mode 100644
> index 0000000..d193084
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
> @@ -0,0 +1,24 @@
> +Samsung SoC SSS (Security SubSystem) module
> +
> +The SSS module in S5PV210 SoC supports the following:
> +-- Feeder (FeedCtrl)
> +-- Advanced Encryption Standard (AES)
> +-- Data Encryption Standard (DES)/3DES
> +-- Public Key Accelerator (PKA)
> +-- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
> +-- PRNG: Pseudo Random Number Generator
> +
> +Required properties:
> +
> +- compatible : Should contain entries for this and backward compatible
> + SSS versions:
> + - "samsung,s5pv210-secss" for S5PV210 SoC.
> +- reg : Offset and length of the register set for the module
> +- interrupts : the interrupt-specifier for the SSS module.
> + Two interrupts "feed control and hash" in case of S5PV210
> + Eg : interrupts = <0 feed-control 0> <0 hash 0>;

Please rewrite the description of interrupts property sa follows:

- interrupts : interrupt specifiers of SSS module interrupts, should
contain two entries:
- first : feed control interrupt,
- second : hash interrupt.

Then in later patch adding support for Exynos, it shoudl be rewritten to:

- interrupts : interrupt specifiers of SSS module interrupts, should
contain following entries:
- first : feed control interrupt (required for all variants),
- second : hash interrupt (required only for samsung,s5pv210-secss).

Best regards,
Tomasz

2014-02-06 14:39:50

[permalink] [raw]

Subject: Re: [PATCH 3/9 v5] crypto:s5p-sss: Add support for SSS module on Exynos

Hi Naveen,

On 29.01.2014 10:21, Naveen Krishna Chatradhi wrote:
> This patch adds new compatible and variant struct to support the SSS
> module on Exynos4 (Exynos4210), Exynos5 (Exynos5420 and Exynos5250)
> for which
> 1. AES register are at an offset of 0x200 and
> 2. hash interrupt is not available
>
> Signed-off-by: Naveen Krishna Ch <[email protected]>
> CC: Herbert Xu <[email protected]>
> CC: David S. Miller <[email protected]>
> CC: Vladimir Zapolskiy <[email protected]>
> TO: <[email protected]>
> CC: <[email protected]>
> ---
> Changes since v4:
> Fix rebase error because of the patch 2/9
>
> .../devicetree/bindings/crypto/samsung-sss.txt | 21 +++-
> drivers/crypto/s5p-sss.c | 107 +++++++++++++++-----
> 2 files changed, 103 insertions(+), 25 deletions(-)

Reviewed-by: Tomasz Figa <[email protected]>

Best regards,
Tomasz

2014-02-06 14:41:58

[permalink] [raw]

Subject: Re: [PATCH 4/9 v5] crypto:s5p-sss: Kconfig: Let Exynos SoCs select SSS driver

Hi Naveen,

On 29.01.2014 10:22, Naveen Krishna Chatradhi wrote:
> From: Naveen Krishna Ch <[email protected]>
>
> This patch modifies Kconfig such that ARCH_EXYNOS SoCs
> which includes (Exynos4210, Exynos5250 and Exynos5420)
> can also select Samsung SSS(Security SubSystem) driver.
>
> Signed-off-by: Naveen Krishna Ch <[email protected]>
> CC: Herbert Xu <[email protected]>
> CC: David S. Miller <[email protected]>
> CC: Vladimir Zapolskiy <[email protected]>
> TO: <[email protected]>
> CC: <[email protected]>
> ---
> Changes since v4:
> none
> Changes since v3:
> Modified description to use "Exynos" instead of individual SoC name
> drivers/crypto/Kconfig | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)

Reviewed-by: Tomasz Figa <[email protected]>

Best regards,
Tomasz

2014-02-06 14:43:16

[permalink] [raw]

Subject: Re: [PATCH 5/9 v5] clk: samsung exynos5250/5420: Add gate clock for SSS module

Hi Naveen,

On 29.01.2014 10:24, Naveen Krishna Chatradhi wrote:
> This patch adds gating clock for SSS(Security SubSystem)
> module on Exynos5250/5420.
>
> Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
> TO: <[email protected]>
> TO: Tomasz Figa <[email protected]>
> CC: Kukjin Kim <[email protected]>
> CC: <[email protected]>
> ---
> Changes since v4:
> Use register GATE_IP_G2D instead of GATE_BUS_G2D for Exynos5420
> Changes since v3:
> 1. Rebased on to https://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk.git
> 2. Added new ID for SSS clock on Exynos5250, with Documentation and
> 3. Added gate clocks definitions for SSS on Exynos5420 and Exynos5250
> .../devicetree/bindings/clock/exynos5250-clock.txt | 1 +
> drivers/clk/samsung/clk-exynos5250.c | 1 +
> drivers/clk/samsung/clk-exynos5420.c | 4 ++++
> include/dt-bindings/clock/exynos5250.h | 1 +
> 4 files changed, 7 insertions(+)

Reviewed-by: Tomasz Figa <[email protected]>

Best regards,
Tomasz

2014-02-07 05:21:44

[permalink] [raw]

Subject: [PATCH 1/9 v6] crypto:s5p-sss: Use platform_get_irq() instead of _byname()

From: Naveen Krishna Ch <[email protected]>

This patch uses the platform_get_irq() instead of the
platform_get_irq_byname(). Making feeder control interrupt
as resource "0" and hash interrupt as "1".

reasons for this change.
1. Cannot find any Arch which is currently using this driver
2. Samsung Exynos4 and 5 SoCs only use the feeder control interrupt
3. Patches adding support for DT and H/W version are in pipeline

Signed-off-by: Naveen Krishna Ch <[email protected]>
Reviewed-by: Tomasz Figa <[email protected]>
CC: Herbert Xu <[email protected]>
CC: David S. Miller <[email protected]>
CC: Vladimir Zapolskiy <[email protected]>
TO: <[email protected]>
CC: <[email protected]>
---
Changes since v5:
None

drivers/crypto/s5p-sss.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
index cf149b1..93cddeb 100644
--- a/drivers/crypto/s5p-sss.c
+++ b/drivers/crypto/s5p-sss.c
@@ -592,29 +592,29 @@ static int s5p_aes_probe(struct platform_device *pdev)
pdata->ioaddr = devm_ioremap(dev, res->start,
resource_size(res));

- pdata->irq_hash = platform_get_irq_byname(pdev, "hash");
- if (pdata->irq_hash < 0) {
- err = pdata->irq_hash;
- dev_warn(dev, "hash interrupt is not available.\n");
+ pdata->irq_fc = platform_get_irq(pdev, 0);
+ if (pdata->irq_fc < 0) {
+ err = pdata->irq_fc;
+ dev_warn(dev, "feed control interrupt is not available.\n");
goto err_irq;
}
- err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
+ err = devm_request_irq(dev, pdata->irq_fc, s5p_aes_interrupt,
IRQF_SHARED, pdev->name, pdev);
if (err < 0) {
- dev_warn(dev, "hash interrupt is not available.\n");
+ dev_warn(dev, "feed control interrupt is not available.\n");
goto err_irq;
}

- pdata->irq_fc = platform_get_irq_byname(pdev, "feed control");
- if (pdata->irq_fc < 0) {
- err = pdata->irq_fc;
- dev_warn(dev, "feed control interrupt is not available.\n");
+ pdata->irq_hash = platform_get_irq(pdev, 1);
+ if (pdata->irq_hash < 0) {
+ err = pdata->irq_hash;
+ dev_warn(dev, "hash interrupt is not available.\n");
goto err_irq;
}
- err = devm_request_irq(dev, pdata->irq_fc, s5p_aes_interrupt,
+ err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
IRQF_SHARED, pdev->name, pdev);
if (err < 0) {
- dev_warn(dev, "feed control interrupt is not available.\n");
+ dev_warn(dev, "hash interrupt is not available.\n");
goto err_irq;
}

--
1.7.9.5

2014-02-07 05:21:55

[permalink] [raw]

Subject: [PATCH 2/9 v6] crypto:s5p-sss: Add device tree support

This patch adds device tree support to the s5p-sss.c crypto driver.

Signed-off-by: Naveen Krishna Ch <[email protected]>
CC: Herbert Xu <[email protected]>
CC: David S. Miller <[email protected]>
CC: Vladimir Zapolskiy <[email protected]>
TO: <[email protected]>
CC: <[email protected]>
---
Changes since v5:
Rewritten the interrupt definition in the documentation

.../devicetree/bindings/crypto/samsung-sss.txt | 26 ++++++++++++++++++++
drivers/crypto/s5p-sss.c | 8 ++++++
2 files changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/samsung-sss.txt

diff --git a/Documentation/devicetree/bindings/crypto/samsung-sss.txt b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
new file mode 100644
index 0000000..3876f71
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
@@ -0,0 +1,26 @@
+Samsung SoC SSS (Security SubSystem) module
+
+The SSS module in S5PV210 SoC supports the following:
+-- Feeder (FeedCtrl)
+-- Advanced Encryption Standard (AES)
+-- Data Encryption Standard (DES)/3DES
+-- Public Key Accelerator (PKA)
+-- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
+-- PRNG: Pseudo Random Number Generator
+
+Required properties:
+
+- compatible : Should contain entries for this and backward compatible
+ SSS versions:
+ - "samsung,s5pv210-secss" for S5PV210 SoC.
+- reg : Offset and length of the register set for the module
+- interrupts : interrupt specifiers of SSS module interrupts, should contain
+ two entries:
+ - first : feed control interrupt,
+ - second : hash interrupt.
+
+- clocks : list of clock phandle and specifier pairs for all clocks listed in
+ clock-names property.
+- clock-names : list of device clock input names; should contain one entry
+ "secss".
+
diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
index 93cddeb..73c8b38 100644
--- a/drivers/crypto/s5p-sss.c
+++ b/drivers/crypto/s5p-sss.c
@@ -22,6 +22,7 @@
#include <linux/scatterlist.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>
+#include <linux/of.h>
#include <linux/crypto.h>
#include <linux/interrupt.h>

@@ -177,6 +178,12 @@ struct s5p_aes_dev {

static struct s5p_aes_dev *s5p_dev;

+static const struct of_device_id s5p_sss_dt_match[] = {
+ { .compatible = "samsung,s5pv210-secss" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, s5p_sss_dt_match);
+
static void s5p_set_dma_indata(struct s5p_aes_dev *dev, struct scatterlist *sg)
{
SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg));
@@ -677,6 +684,7 @@ static struct platform_driver s5p_aes_crypto = {
.driver = {
.owner = THIS_MODULE,
.name = "s5p-secss",
+ .of_match_table = s5p_sss_dt_match,
},
};

--
1.7.9.5

2014-02-07 05:23:41

[permalink] [raw]

Subject: [PATCH 4/9 v6] crypto:s5p-sss: Kconfig: Let Exynos SoCs select SSS driver

From: Naveen Krishna Ch <[email protected]>

This patch modifies Kconfig such that ARCH_EXYNOS SoCs
which includes (Exynos4210, Exynos5250 and Exynos5420)
can also select Samsung SSS(Security SubSystem) driver.

Signed-off-by: Naveen Krishna Ch <[email protected]>
Reviewed-by: Tomasz Figa <[email protected]>
CC: Herbert Xu <[email protected]>
CC: David S. Miller <[email protected]>
CC: Vladimir Zapolskiy <[email protected]>
TO: <[email protected]>
CC: <[email protected]>
---
Change since v5:
None

drivers/crypto/Kconfig | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 13857f5..e866489 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -290,14 +290,14 @@ config CRYPTO_DEV_SAHARA
found in some Freescale i.MX chips.

config CRYPTO_DEV_S5P
- tristate "Support for Samsung S5PV210 crypto accelerator"
- depends on ARCH_S5PV210
+ tristate "Support for Samsung S5PV210/Exynos crypto accelerator"
+ depends on ARCH_S5PV210 || ARCH_EXYNOS
select CRYPTO_AES
select CRYPTO_ALGAPI
select CRYPTO_BLKCIPHER
help
This option allows you to have support for S5P crypto acceleration.
- Select this to offload Samsung S5PV210 or S5PC110 from AES
+ Select this to offload Samsung S5PV210 or S5PC110, Exynos from AES
algorithms execution.

config CRYPTO_DEV_TEGRA_AES
--
1.7.9.5

2014-02-07 05:24:14

[permalink] [raw]

Subject: [PATCH 5/9 v6] clk: samsung exynos5250/5420: Add gate clock for SSS module

This patch adds gating clock for SSS(Security SubSystem)
module on Exynos5250/5420.

Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
Reviewed-by: Tomasz Figa <[email protected]>
TO: <[email protected]>
CC: Kukjin Kim <[email protected]>
CC: <[email protected]>
---
changes since v5:
1. Added Reviewed-by: Tomasz Figa <[email protected]>

.../devicetree/bindings/clock/exynos5250-clock.txt | 1 +
drivers/clk/samsung/clk-exynos5250.c | 1 +
drivers/clk/samsung/clk-exynos5420.c | 4 ++++
include/dt-bindings/clock/exynos5250.h | 1 +
4 files changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
index 72ce617..87f1539 100644
--- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
@@ -162,6 +162,7 @@ clock which they consume.
g2d 345
mdma0 346
smmu_mdma0 347
+ sss 348

[Clock Muxes]
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index ff4beeb..2c52fe1 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -387,6 +387,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
* CMU_ACP
*/
GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0),
+ GATE(CLK_SSS, "sss", "div_aclk266", GATE_IP_ACP, 2, 0, 0),
GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0),
GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0),

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index ab4f2f7..c93d4d5 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -26,6 +26,7 @@
#define DIV_CPU1 0x504
#define GATE_BUS_CPU 0x700
#define GATE_SCLK_CPU 0x800
+#define GATE_IP_G2D 0x8800
#define CPLL_LOCK 0x10020
#define DPLL_LOCK 0x10030
#define EPLL_LOCK 0x10040
@@ -702,6 +703,9 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
0),
GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0,
0),
+
+ /* SSS */
+ GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
};

static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = {
diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h
index 922f2dc..f9b452b 100644
--- a/include/dt-bindings/clock/exynos5250.h
+++ b/include/dt-bindings/clock/exynos5250.h
@@ -150,6 +150,7 @@
#define CLK_G2D 345
#define CLK_MDMA0 346
#define CLK_SMMU_MDMA0 347
+#define CLK_SSS 348

/* mux clocks */
#define CLK_MOUT_HDMI 1024
--
1.7.9.5

2014-02-07 05:24:55

[permalink] [raw]

Subject: [PATCH 6/9 v6] ARM: dts: exynos5250/5420: add dt node for sss module

This patch adds the device tree node for SSS module
found on Exynos5420 and Exynos5250

Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
Reviewed-by: Tomasz Figa <[email protected]>
TO: <[email protected]>
CC: Kukjin Kim <[email protected]>
CC: <[email protected]>
---
changes since v5:
1. Added Reviewed-by: Tomasz Figa <[email protected]>

arch/arm/boot/dts/exynos5250.dtsi | 8 ++++++++
arch/arm/boot/dts/exynos5420.dtsi | 10 ++++++++++
2 files changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index b7dec41..46b04e8 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -706,4 +706,12 @@
io-channel-ranges;
status = "disabled";
};
+
+ sss@10830000 {
+ compatible = "samsung,exynos4210-secss";
+ reg = <0x10830000 0x10000>;
+ interrupts = <0 112 0>;
+ clocks = <&clock 348>;
+ clock-names = "secss";
+ };
};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 8db792b..b503e96 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -652,4 +652,14 @@
clocks = <&clock 319>, <&clock 318>;
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
};
+
+ sss@10830000 {
+ compatible = "samsung,exynos4210-secss";
+ reg = <0x10830000 0x10000>;
+ interrupts = <0 112 0>;
+ clocks = <&clock 471>;
+ clock-names = "secss";
+ samsung,power-domain = <&g2d_pd>;
+ };
+
};
--
1.7.9.5

2014-02-13 23:28:46

by Kukjin Kim

[permalink] [raw]

Subject: Re: [PATCH 6/9 v6] ARM: dts: exynos5250/5420: add dt node for sss module

On 02/07/14 14:24, Naveen Krishna Chatradhi wrote:
> This patch adds the device tree node for SSS module
> found on Exynos5420 and Exynos5250
>
> Signed-off-by: Naveen Krishna Chatradhi<[email protected]>
> Reviewed-by: Tomasz Figa<[email protected]>
> TO:<[email protected]>
> CC: Kukjin Kim<[email protected]>
> CC:<[email protected]>
> ---
> changes since v5:
> 1. Added Reviewed-by: Tomasz Figa<[email protected]>
>
> arch/arm/boot/dts/exynos5250.dtsi | 8 ++++++++
> arch/arm/boot/dts/exynos5420.dtsi | 10 ++++++++++
> 2 files changed, 18 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
> index b7dec41..46b04e8 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -706,4 +706,12 @@
> io-channel-ranges;
> status = "disabled";
> };
> +
> + sss@10830000 {
> + compatible = "samsung,exynos4210-secss";
> + reg =<0x10830000 0x10000>;
> + interrupts =<0 112 0>;
> + clocks =<&clock 348>;
> + clock-names = "secss";
> + };
> };
> diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
> index 8db792b..b503e96 100644
> --- a/arch/arm/boot/dts/exynos5420.dtsi
> +++ b/arch/arm/boot/dts/exynos5420.dtsi
> @@ -652,4 +652,14 @@
> clocks =<&clock 319>,<&clock 318>;
> clock-names = "tmu_apbif", "tmu_triminfo_apbif";
> };
> +
> + sss@10830000 {
> + compatible = "samsung,exynos4210-secss";
> + reg =<0x10830000 0x10000>;
> + interrupts =<0 112 0>;
> + clocks =<&clock 471>;
> + clock-names = "secss";
> + samsung,power-domain =<&g2d_pd>;
> + };
> +
> };

Applied, thanks.

BTW, I think the numbering is strange...maybe I missed something?
[PATCH 5/5], [PATCH 5/6 V2], [PATCH 6/8 V3] and this [PATCH 6/9 V6]

- Kukjin

2014-02-13 23:32:45

by Kukjin Kim

[permalink] [raw]

Subject: Re: [PATCH 6/9 v6] ARM: dts: exynos5250/5420: add dt node for sss module

On 02/14/14 08:28, Kukjin Kim wrote:
> On 02/07/14 14:24, Naveen Krishna Chatradhi wrote:
>> This patch adds the device tree node for SSS module
>> found on Exynos5420 and Exynos5250
>>
>> Signed-off-by: Naveen Krishna Chatradhi<[email protected]>
>> Reviewed-by: Tomasz Figa<[email protected]>
>> TO:<[email protected]>
>> CC: Kukjin Kim<[email protected]>
>> CC:<[email protected]>
>> ---
>> changes since v5:
>> 1. Added Reviewed-by: Tomasz Figa<[email protected]>
>>
>> arch/arm/boot/dts/exynos5250.dtsi | 8 ++++++++
>> arch/arm/boot/dts/exynos5420.dtsi | 10 ++++++++++
>> 2 files changed, 18 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos5250.dtsi
>> b/arch/arm/boot/dts/exynos5250.dtsi
>> index b7dec41..46b04e8 100644
>> --- a/arch/arm/boot/dts/exynos5250.dtsi
>> +++ b/arch/arm/boot/dts/exynos5250.dtsi
>> @@ -706,4 +706,12 @@
>> io-channel-ranges;
>> status = "disabled";
>> };
>> +
>> + sss@10830000 {
>> + compatible = "samsung,exynos4210-secss";
>> + reg =<0x10830000 0x10000>;
>> + interrupts =<0 112 0>;
>> + clocks =<&clock 348>;
>> + clock-names = "secss";
>> + };
>> };
>> diff --git a/arch/arm/boot/dts/exynos5420.dtsi
>> b/arch/arm/boot/dts/exynos5420.dtsi
>> index 8db792b..b503e96 100644
>> --- a/arch/arm/boot/dts/exynos5420.dtsi
>> +++ b/arch/arm/boot/dts/exynos5420.dtsi
>> @@ -652,4 +652,14 @@
>> clocks =<&clock 319>,<&clock 318>;
>> clock-names = "tmu_apbif", "tmu_triminfo_apbif";
>> };
>> +
>> + sss@10830000 {
>> + compatible = "samsung,exynos4210-secss";
>> + reg =<0x10830000 0x10000>;
>> + interrupts =<0 112 0>;
>> + clocks =<&clock 471>;
>> + clock-names = "secss";
>> + samsung,power-domain =<&g2d_pd>;
>> + };
>> +
>> };
>
> Applied, thanks.
>
> BTW, I think the numbering is strange...maybe I missed something?
> [PATCH 5/5], [PATCH 5/6 V2], [PATCH 6/8 V3] and this [PATCH 6/9 V6]
>
Oops, Naveen, where is bindings doc for "samsung,exynos4210-secss"?

- Kukjin

2014-02-14 04:13:34

[permalink] [raw]

Subject: Re: [PATCH 6/9 v6] ARM: dts: exynos5250/5420: add dt node for sss module

Hello Kukjin,

On 14 February 2014 05:02, Kukjin Kim <[email protected]> wrote:
> On 02/14/14 08:28, Kukjin Kim wrote:
>>
>> On 02/07/14 14:24, Naveen Krishna Chatradhi wrote:
>>>
>>> This patch adds the device tree node for SSS module
>>> found on Exynos5420 and Exynos5250
>>>
>>> Signed-off-by: Naveen Krishna Chatradhi<[email protected]>
>>> Reviewed-by: Tomasz Figa<[email protected]>
>>> TO:<[email protected]>
>>> CC: Kukjin Kim<[email protected]>
>>> CC:<[email protected]>
>>> ---
>>> changes since v5:
>>> 1. Added Reviewed-by: Tomasz Figa<[email protected]>
>>>
>>> arch/arm/boot/dts/exynos5250.dtsi | 8 ++++++++
>>> arch/arm/boot/dts/exynos5420.dtsi | 10 ++++++++++
>>> 2 files changed, 18 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/exynos5250.dtsi
>>> b/arch/arm/boot/dts/exynos5250.dtsi
>>> index b7dec41..46b04e8 100644
>>> --- a/arch/arm/boot/dts/exynos5250.dtsi
>>> +++ b/arch/arm/boot/dts/exynos5250.dtsi
>>> @@ -706,4 +706,12 @@
>>> io-channel-ranges;
>>> status = "disabled";
>>> };
>>> +
>>> + sss@10830000 {
>>> + compatible = "samsung,exynos4210-secss";
>>> + reg =<0x10830000 0x10000>;
>>> + interrupts =<0 112 0>;
>>> + clocks =<&clock 348>;
>>> + clock-names = "secss";
>>> + };
>>> };
>>> diff --git a/arch/arm/boot/dts/exynos5420.dtsi
>>> b/arch/arm/boot/dts/exynos5420.dtsi
>>> index 8db792b..b503e96 100644
>>> --- a/arch/arm/boot/dts/exynos5420.dtsi
>>> +++ b/arch/arm/boot/dts/exynos5420.dtsi
>>> @@ -652,4 +652,14 @@
>>> clocks =<&clock 319>,<&clock 318>;
>>> clock-names = "tmu_apbif", "tmu_triminfo_apbif";
>>> };
>>> +
>>> + sss@10830000 {
>>> + compatible = "samsung,exynos4210-secss";
>>> + reg =<0x10830000 0x10000>;
>>> + interrupts =<0 112 0>;
>>> + clocks =<&clock 471>;
>>> + clock-names = "secss";
>>> + samsung,power-domain =<&g2d_pd>;
>>> + };
>>> +
>>> };
>>
>>
>> Applied, thanks.
>>
>> BTW, I think the numbering is strange...maybe I missed something?
>> [PATCH 5/5], [PATCH 5/6 V2], [PATCH 6/8 V3] and this [PATCH 6/9 V6]
>>
> Oops, Naveen, where is bindings doc for "samsung,exynos4210-secss"?
The binding doc patch is along with the driver patch
https://groups.google.com/forum/#!msg/linux.kernel/9Z02Gg_MzPA/GTc7Csg74L0J
and
http://patchwork.ozlabs.org/patch/314946/
>
> - Kukjin

--
Shine bright,
(: Nav :)

2014-02-14 10:54:55

[permalink] [raw]

Subject: Re: [PATCH 6/9 v6] ARM: dts: exynos5250/5420: add dt node for sss module

Hi Kukjin,

On 14.02.2014 00:28, Kukjin Kim wrote:
> On 02/07/14 14:24, Naveen Krishna Chatradhi wrote:
>> This patch adds the device tree node for SSS module
>> found on Exynos5420 and Exynos5250
>>
>> Signed-off-by: Naveen Krishna Chatradhi<[email protected]>
>> Reviewed-by: Tomasz Figa<[email protected]>
>> TO:<[email protected]>
>> CC: Kukjin Kim<[email protected]>
>> CC:<[email protected]>
>> ---
>> changes since v5:
>> 1. Added Reviewed-by: Tomasz Figa<[email protected]>
>>
>> arch/arm/boot/dts/exynos5250.dtsi | 8 ++++++++
>> arch/arm/boot/dts/exynos5420.dtsi | 10 ++++++++++
>> 2 files changed, 18 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos5250.dtsi
>> b/arch/arm/boot/dts/exynos5250.dtsi
>> index b7dec41..46b04e8 100644
>> --- a/arch/arm/boot/dts/exynos5250.dtsi
>> +++ b/arch/arm/boot/dts/exynos5250.dtsi
>> @@ -706,4 +706,12 @@
>> io-channel-ranges;
>> status = "disabled";
>> };
>> +
>> + sss@10830000 {
>> + compatible = "samsung,exynos4210-secss";
>> + reg =<0x10830000 0x10000>;
>> + interrupts =<0 112 0>;
>> + clocks =<&clock 348>;
>> + clock-names = "secss";
>> + };
>> };
>> diff --git a/arch/arm/boot/dts/exynos5420.dtsi
>> b/arch/arm/boot/dts/exynos5420.dtsi
>> index 8db792b..b503e96 100644
>> --- a/arch/arm/boot/dts/exynos5420.dtsi
>> +++ b/arch/arm/boot/dts/exynos5420.dtsi
>> @@ -652,4 +652,14 @@
>> clocks =<&clock 319>,<&clock 318>;
>> clock-names = "tmu_apbif", "tmu_triminfo_apbif";
>> };
>> +
>> + sss@10830000 {
>> + compatible = "samsung,exynos4210-secss";
>> + reg =<0x10830000 0x10000>;
>> + interrupts =<0 112 0>;
>> + clocks =<&clock 471>;
>> + clock-names = "secss";
>> + samsung,power-domain =<&g2d_pd>;
>> + };
>> +
>> };
>
> Applied, thanks.
>
> BTW, I think the numbering is strange...maybe I missed something?
> [PATCH 5/5], [PATCH 5/6 V2], [PATCH 6/8 V3] and this [PATCH 6/9 V6]

I would wait with applying any patches from this series until they are
acked by crypto subsystem maintainer and DT bindings by DT maintainers.

I'd like Naveen to resend this series in separate thread, with proper
message threading, so we can make sure that we are not missing anything.
Naveen, please also add

David S. Miller <[email protected]>

to Cc list, as he is also listed as crypto maintainer in MAINTAINERS file.

Best regards,
Tomasz

2014-02-17 08:56:31