The patch 'irqchip/gic-v3-its: Balance initial LPI affinity across CPUs'
set the IRQ to an uncentain CPU. If an IRQ is bound to the CPU used by the
thread which is sending request, the throughput will be just half.
So allocate a 'work_queue' and set as 'WQ_UNBOUND' to do the back half work
on some different CPUS.
Signed-off-by: Yang Shen <[email protected]>
Reviewed-by: Zaibo Xu <[email protected]>
---
drivers/crypto/hisilicon/zip/zip_main.c | 26 +++++++++++++++++++++++---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/hisilicon/zip/zip_main.c b/drivers/crypto/hisilicon/zip/zip_main.c
index 3d1524b..4fb5a32b 100644
--- a/drivers/crypto/hisilicon/zip/zip_main.c
+++ b/drivers/crypto/hisilicon/zip/zip_main.c
@@ -747,6 +747,8 @@ static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip)
static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
{
+ int ret;
+
qm->pdev = pdev;
qm->ver = pdev->revision;
qm->algs = "zlib\ngzip";
@@ -772,7 +774,25 @@ static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
qm->qp_num = HZIP_QUEUE_NUM_V1 - HZIP_PF_DEF_Q_NUM;
}
- return hisi_qm_init(qm);
+ qm->wq = alloc_workqueue("%s", WQ_HIGHPRI | WQ_MEM_RECLAIM |
+ WQ_UNBOUND, num_online_cpus(),
+ pci_name(qm->pdev));
+ if (!qm->wq) {
+ pci_err(qm->pdev, "fail to alloc workqueue\n");
+ return -ENOMEM;
+ }
+
+ ret = hisi_qm_init(qm);
+ if (ret)
+ destroy_workqueue(qm->wq);
+
+ return ret;
+}
+
+static void hisi_zip_qm_uninit(struct hisi_qm *qm)
+{
+ hisi_qm_uninit(qm);
+ destroy_workqueue(qm->wq);
}
static int hisi_zip_probe_init(struct hisi_zip *hisi_zip)
@@ -854,7 +874,7 @@ static int hisi_zip_probe(struct pci_dev *pdev, const struct pci_device_id *id)
hisi_qm_dev_err_uninit(qm);
err_qm_uninit:
- hisi_qm_uninit(qm);
+ hisi_zip_qm_uninit(qm);
return ret;
}
@@ -872,7 +892,7 @@ static void hisi_zip_remove(struct pci_dev *pdev)
hisi_zip_debugfs_exit(qm);
hisi_qm_stop(qm, QM_NORMAL);
hisi_qm_dev_err_uninit(qm);
- hisi_qm_uninit(qm);
+ hisi_zip_qm_uninit(qm);
}
static const struct pci_error_handlers hisi_zip_err_handler = {
--
2.7.4
On 2020/11/13 17:32, Yang Shen wrote:
> The patch 'irqchip/gic-v3-its: Balance initial LPI affinity across CPUs'
> set the IRQ to an uncentain CPU. If an IRQ is bound to the CPU used by the
> thread which is sending request, the throughput will be just half.
>
> So allocate a 'work_queue' and set as 'WQ_UNBOUND' to do the back half work
> on some different CPUS.
>
> Signed-off-by: Yang Shen <[email protected]>
> Reviewed-by: Zaibo Xu <[email protected]>
Reviewed-by: Zhou Wang <[email protected]>
Thanks,
Zhou
> ---
> drivers/crypto/hisilicon/zip/zip_main.c | 26 +++++++++++++++++++++++---
> 1 file changed, 23 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/crypto/hisilicon/zip/zip_main.c b/drivers/crypto/hisilicon/zip/zip_main.c
> index 3d1524b..4fb5a32b 100644
> --- a/drivers/crypto/hisilicon/zip/zip_main.c
> +++ b/drivers/crypto/hisilicon/zip/zip_main.c
> @@ -747,6 +747,8 @@ static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip)
>
> static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
> {
> + int ret;
> +
> qm->pdev = pdev;
> qm->ver = pdev->revision;
> qm->algs = "zlib\ngzip";
> @@ -772,7 +774,25 @@ static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
> qm->qp_num = HZIP_QUEUE_NUM_V1 - HZIP_PF_DEF_Q_NUM;
> }
>
> - return hisi_qm_init(qm);
> + qm->wq = alloc_workqueue("%s", WQ_HIGHPRI | WQ_MEM_RECLAIM |
> + WQ_UNBOUND, num_online_cpus(),
> + pci_name(qm->pdev));
> + if (!qm->wq) {
> + pci_err(qm->pdev, "fail to alloc workqueue\n");
> + return -ENOMEM;
> + }
> +
> + ret = hisi_qm_init(qm);
> + if (ret)
> + destroy_workqueue(qm->wq);
> +
> + return ret;
> +}
> +
> +static void hisi_zip_qm_uninit(struct hisi_qm *qm)
> +{
> + hisi_qm_uninit(qm);
> + destroy_workqueue(qm->wq);
> }
>
> static int hisi_zip_probe_init(struct hisi_zip *hisi_zip)
> @@ -854,7 +874,7 @@ static int hisi_zip_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> hisi_qm_dev_err_uninit(qm);
>
> err_qm_uninit:
> - hisi_qm_uninit(qm);
> + hisi_zip_qm_uninit(qm);
>
> return ret;
> }
> @@ -872,7 +892,7 @@ static void hisi_zip_remove(struct pci_dev *pdev)
> hisi_zip_debugfs_exit(qm);
> hisi_qm_stop(qm, QM_NORMAL);
> hisi_qm_dev_err_uninit(qm);
> - hisi_qm_uninit(qm);
> + hisi_zip_qm_uninit(qm);
> }
>
> static const struct pci_error_handlers hisi_zip_err_handler = {
> --
> 2.7.4
>
> .
>
On Fri, Nov 13, 2020 at 05:32:35PM +0800, Yang Shen wrote:
> The patch 'irqchip/gic-v3-its: Balance initial LPI affinity across CPUs'
> set the IRQ to an uncentain CPU. If an IRQ is bound to the CPU used by the
> thread which is sending request, the throughput will be just half.
>
> So allocate a 'work_queue' and set as 'WQ_UNBOUND' to do the back half work
> on some different CPUS.
>
> Signed-off-by: Yang Shen <[email protected]>
> Reviewed-by: Zaibo Xu <[email protected]>
> ---
> drivers/crypto/hisilicon/zip/zip_main.c | 26 +++++++++++++++++++++++---
> 1 file changed, 23 insertions(+), 3 deletions(-)
Patch applied. Thanks.
--
Email: Herbert Xu <[email protected]>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt