The series contains Qualcomm Crypto Engine dts and driver changes,
which modify a set of accepted compatible property values, this is
needed to provide a unified and fine-grained support of the driver
on old and new platforms. In addition due to QCE IP changes on new
Qualcomm platforms, it is reflected in updates to valid device tree
properties, namely added iommu, interconnects and optional clocks.
Changes since v8:
=================
- v8 can be found here: https://lore.kernel.org/all/[email protected]/
- Rebased the series on top of linux-next, sm8550 qce support is already
found in the tree,
- Reduced the list of QCE IP compatibles in the driver, added one more
compatible for backward DTB ABI compatibility,
- Replaced a documentation change from Neil Armstrong by a more advanced
version of it per review comments from Krzysztof Kozlowski about clock
and clock-names properties,
- Added changes to all relevant Qualcomm platform dtsi files according to
the changes in the scheme file,
- Added QCE support on SM8250 platform.
Changes since v7:
=================
- v7 can be found here: https://lore.kernel.org/linux-arm-msm/[email protected]
- Added a change by Neil Armstrong to document clocks and clock-names
properties as optional,
- At the moment do not add Bhupesh as a new QCE driver maintainer,
- Minor updates to device tree binding documentation and qce driver,
in particular added more compatibles and fixed lesser issues.
Changes since v6:
=================
- v6 can be seen here: https://lore.kernel.org/linux-arm-msm/[email protected]/
- As per Krzysztof's suggestion on v6, clubbed the crypto driver and
dt-bindings changes together. Now the overall v5 patchset into 3
separate patchsets, one each for the following areas to allow easier
review and handling from the maintainer:
arm-msm, crypto and dma
Changes since v5:
=================
- v5 can be seen here: https://lore.kernel.org/lkml/[email protected]/
- As per Bjorn's suggestion on irc, broke down the patchset into 4
separate patchsets, one each for the following areas to allow easier
review and handling from the maintainer:
arm-msm, crypto, dma and devicetree
- Addressed Rob's, Vladimir's and Bjorn's review comments received on
v5.
- Added Tested-by from Jordan received on the v5.
Changes since v4:
=================
- v4 for sm8250 can be seen here: https://lore.kernel.org/linux-arm-msm/[email protected]/
- v1 for sm8150 qce enablement can be seen here: https://lore.kernel.org/linux-arm-msm/[email protected]/
- Merged the sm8150 and sm8250 enablement patches in the same patchset,
as per suggestions from Bjorn.
- Dropped a couple of patches from v4, as these have been picked by
Bjorn already via his tree.
- Addressed review comments from Vladimir, Thara and Rob.
- Collect Reviewed-by from Rob and Thara on some of the patches from the
v4 patchset.
Changes since v3:
=================
- v3 can be seen here: https://lore.kernel.org/linux-arm-msm/[email protected]/
- Dropped a couple of patches from v3, on basis of the review comments:
~ [PATCH 13/17] crypto: qce: core: Make clocks optional
~ [PATCH 15/17] crypto: qce: Convert the device found dev_dbg() to dev_info()
- Addressed review comments from Thara, Rob and Stephan Gerhold.
- Collect Reviewed-by from Rob and Thara on some of the patches from the
v3 patchset.
Changes since v2:
=================
- v2 can be seen here: https://lore.kernel.org/dmaengine/[email protected]/
- Drop a couple of patches from v1, which tried to address the defered
probing of qce driver in case bam dma driver is not yet probed.
Replace it instead with a single (simpler) patch [PATCH 16/17].
- Convert bam dma and qce crypto dt-bindings to YAML.
- Addressed review comments from Thara, Bjorn, Vinod and Rob.
Changes since v1:
=================
- v1 can be seen here: https://lore.kernel.org/linux-arm-msm/[email protected]/
- v1 did not work well as reported earlier by Dmitry, so v2 contains the following
changes/fixes:
~ Enable the interconnect path b/w BAM DMA and main memory first
before trying to access the BAM DMA registers.
~ Enable the interconnect path b/w qce crytpo and main memory first
before trying to access the qce crypto registers.
~ Make sure to document the required and optional properties for both
BAM DMA and qce crypto drivers.
~ Add a few debug related print messages in case the qce crypto driver
passes or fails to probe.
~ Convert the qce crypto driver probe to a defered one in case the BAM DMA
or the interconnect driver(s) (needed on specific Qualcomm parts) are not
yet probed.
Qualcomm crypto engine (qce) is available on several Snapdragon SoCs.
The qce block supports hardware accelerated algorithms for encryption
and authentication. It also provides support for aes, des, 3des
encryption algorithms and sha1, sha256, hmac(sha1), hmac(sha256)
authentication algorithms.
Bhupesh Sharma (4):
dt-bindings: qcom-qce: Convert bindings to yaml
MAINTAINERS: Add qcom-qce dt-binding file to QUALCOMM CRYPTO DRIVERS section
dt-bindings: qcom-qce: Add 'interconnects' and 'interconnect-names'
dt-bindings: qcom-qce: Add 'iommus' to optional properties
Thara Gopinath (2):
crypto: qce: core: Add support to initialize interconnect path
crypto: qce: core: Make clocks optional
Vladimir Zapolskiy (8):
dt-bindings: qcom-qce: Add new SoC compatible strings for qcom-qce
dt-bindings: qcom-qce: document optional clocks and clock-names properties
arm: dts: qcom: ipq4019: update a compatible for QCE IP on IPQ4019 SoC
arm64: dts: qcom: msm8996: update QCE compatible according to a new scheme
arm64: dts: qcom: sdm845: update QCE compatible according to a new scheme
arm64: dts: qcom: sm8550: add a family compatible for QCE IP
arm64: dts: qcom: sm8250: add description of Qualcomm Crypto Engine IP
crypto: qce: core: Add a compatible based on a SoC name
.../devicetree/bindings/crypto/qcom-qce.txt | 25 ----
.../devicetree/bindings/crypto/qcom-qce.yaml | 116 ++++++++++++++++++
MAINTAINERS | 1 +
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 24 ++++
arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +-
drivers/crypto/qce/core.c | 24 +++-
drivers/crypto/qce/core.h | 1 +
10 files changed, 166 insertions(+), 33 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.txt
create mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.yaml
--
2.33.0
From: Bhupesh Sharma <[email protected]>
Add the entry for 'Documentation/devicetree/bindings/crypto/qcom-qce.yaml'
to the appropriate section for 'QUALCOMM CRYPTO DRIVERS' in
MAINTAINERS file.
Cc: Bjorn Andersson <[email protected]>
Signed-off-by: Bhupesh Sharma <[email protected]>
Signed-off-by: Vladimir Zapolskiy <[email protected]>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 94971603568b..864bf5b7520f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17199,6 +17199,7 @@ M: Thara Gopinath <[email protected]>
L: [email protected]
L: [email protected]
S: Maintained
+F: Documentation/devicetree/bindings/crypto/qcom-qce.yaml
F: drivers/crypto/qce/
QUALCOMM EMAC GIGABIT ETHERNET DRIVER
--
2.33.0
From: Bhupesh Sharma <[email protected]>
Convert Qualcomm QCE crypto devicetree binding to YAML.
Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Tested-by: Jordan Crouse <[email protected]>
Signed-off-by: Bhupesh Sharma <[email protected]>
Signed-off-by: Vladimir Zapolskiy <[email protected]>
---
.../devicetree/bindings/crypto/qcom-qce.txt | 25 -------
.../devicetree/bindings/crypto/qcom-qce.yaml | 67 +++++++++++++++++++
2 files changed, 67 insertions(+), 25 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.txt
create mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.yaml
diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.txt b/Documentation/devicetree/bindings/crypto/qcom-qce.txt
deleted file mode 100644
index fdd53b184ba8..000000000000
--- a/Documentation/devicetree/bindings/crypto/qcom-qce.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-Qualcomm crypto engine driver
-
-Required properties:
-
-- compatible : should be "qcom,crypto-v5.1"
-- reg : specifies base physical address and size of the registers map
-- clocks : phandle to clock-controller plus clock-specifier pair
-- clock-names : "iface" clocks register interface
- "bus" clocks data transfer interface
- "core" clocks rest of the crypto block
-- dmas : DMA specifiers for tx and rx dma channels. For more see
- Documentation/devicetree/bindings/dma/dma.txt
-- dma-names : DMA request names should be "rx" and "tx"
-
-Example:
- crypto@fd45a000 {
- compatible = "qcom,crypto-v5.1";
- reg = <0xfd45a000 0x6000>;
- clocks = <&gcc GCC_CE2_AHB_CLK>,
- <&gcc GCC_CE2_AXI_CLK>,
- <&gcc GCC_CE2_CLK>;
- clock-names = "iface", "bus", "core";
- dmas = <&cryptobam 2>, <&cryptobam 3>;
- dma-names = "rx", "tx";
- };
diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
new file mode 100644
index 000000000000..8df47e8513b8
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/qcom-qce.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm crypto engine driver
+
+maintainers:
+ - Bhupesh Sharma <[email protected]>
+
+description:
+ This document defines the binding for the QCE crypto
+ controller found on Qualcomm parts.
+
+properties:
+ compatible:
+ const: qcom,crypto-v5.1
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: iface clocks register interface.
+ - description: bus clocks data transfer interface.
+ - description: core clocks rest of the crypto block.
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bus
+ - const: core
+
+ dmas:
+ items:
+ - description: DMA specifiers for rx dma channel.
+ - description: DMA specifiers for tx dma channel.
+
+ dma-names:
+ items:
+ - const: rx
+ - const: tx
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - dmas
+ - dma-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-apq8084.h>
+ crypto-engine@fd45a000 {
+ compatible = "qcom,crypto-v5.1";
+ reg = <0xfd45a000 0x6000>;
+ clocks = <&gcc GCC_CE2_AHB_CLK>,
+ <&gcc GCC_CE2_AXI_CLK>,
+ <&gcc GCC_CE2_CLK>;
+ clock-names = "iface", "bus", "core";
+ dmas = <&cryptobam 2>, <&cryptobam 3>;
+ dma-names = "rx", "tx";
+ };
--
2.33.0
From: Bhupesh Sharma <[email protected]>
Add the missing optional property - 'iommus' to the
device-tree binding documentation for qcom-qce crypto IP.
This property describes the phandle(s) to apps_smmu node with sid mask.
Cc: Bjorn Andersson <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Tested-by: Jordan Crouse <[email protected]>
Signed-off-by: Bhupesh Sharma <[email protected]>
Signed-off-by: Vladimir Zapolskiy <[email protected]>
---
Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
index 94f96ebc5dac..4e00e7925fed 100644
--- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
@@ -32,6 +32,12 @@ properties:
- const: bus
- const: core
+ iommus:
+ minItems: 1
+ maxItems: 8
+ description:
+ phandle to apps_smmu node with sid mask.
+
interconnects:
maxItems: 1
description:
@@ -72,4 +78,8 @@ examples:
clock-names = "iface", "bus", "core";
dmas = <&cryptobam 2>, <&cryptobam 3>;
dma-names = "rx", "tx";
+ iommus = <&apps_smmu 0x584 0x0011>,
+ <&apps_smmu 0x586 0x0011>,
+ <&apps_smmu 0x594 0x0011>,
+ <&apps_smmu 0x596 0x0011>;
};
--
2.33.0
From: Bhupesh Sharma <[email protected]>
Add 'interconnects' and 'interconnect-names' as optional properties
to the device-tree binding documentation for Qualcomm crypto IP.
These properties describe the interconnect path between crypto and main
memory and the interconnect type respectively.
Cc: Bjorn Andersson <[email protected]>
Acked-by: Rob Herring <[email protected]>
Tested-by: Jordan Crouse <[email protected]>
Signed-off-by: Bhupesh Sharma <[email protected]>
Signed-off-by: Vladimir Zapolskiy <[email protected]>
---
Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
index 8df47e8513b8..94f96ebc5dac 100644
--- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
@@ -32,6 +32,14 @@ properties:
- const: bus
- const: core
+ interconnects:
+ maxItems: 1
+ description:
+ Interconnect path between qce crypto and main memory.
+
+ interconnect-names:
+ const: memory
+
dmas:
items:
- description: DMA specifiers for rx dma channel.
--
2.33.0
Change QCE IP version specific compatible to two QCE IP family compatibles
based on SoC name and populate these two IP families with particular SoC
specific IP compatible names, which are known at the moment.
Keep the old compatible 'qcom,crypto-v5.1' for backward compatibility
of DTB ABI, but mark it as deprecated.
The change is based on the original one written by Bhupesh Sharma.
Cc: Bhupesh Sharma <[email protected]>
Signed-off-by: Vladimir Zapolskiy <[email protected]>
---
.../devicetree/bindings/crypto/qcom-qce.yaml | 24 +++++++++++++++++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
index 4e00e7925fed..f6f1759a2f6e 100644
--- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
@@ -15,7 +15,27 @@ description:
properties:
compatible:
- const: qcom,crypto-v5.1
+ oneOf:
+ - const: qcom,crypto-v5.1
+ deprecated: true
+ description: Kept only for ABI backward compatibility
+ - const: qcom,crypto-v5.4
+ deprecated: true
+ description: Kept only for ABI backward compatibility
+ - items:
+ - enum:
+ - qcom,ipq6018-qce
+ - qcom,ipq8074-qce
+ - qcom,msm8996-qce
+ - qcom,sdm845-qce
+ - const: qcom,ipq4019-qce
+ - items:
+ - enum:
+ - qcom,sm8250-qce
+ - qcom,sm8350-qce
+ - qcom,sm8450-qce
+ - qcom,sm8550-qce
+ - const: qcom,sm8150-qce
reg:
maxItems: 1
@@ -70,7 +90,7 @@ examples:
- |
#include <dt-bindings/clock/qcom,gcc-apq8084.h>
crypto-engine@fd45a000 {
- compatible = "qcom,crypto-v5.1";
+ compatible = "qcom,ipq6018-qce", "qcom,ipq4019-qce";
reg = <0xfd45a000 0x6000>;
clocks = <&gcc GCC_CE2_AHB_CLK>,
<&gcc GCC_CE2_AXI_CLK>,
--
2.33.0
On newer Qualcomm SoCs the crypto engine clocks are enabled by default
by security firmware. To drop clocks and clock-names from the list of
required properties use 'qcom,sm8150-qce' compatible name.
The change is based on Neil Armstrong's observation and an original change.
Cc: Neil Armstrong <[email protected]>
Signed-off-by: Vladimir Zapolskiy <[email protected]>
---
.../devicetree/bindings/crypto/qcom-qce.yaml | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
index f6f1759a2f6e..d0f6b830a5dd 100644
--- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
@@ -79,11 +79,22 @@ properties:
required:
- compatible
- reg
- - clocks
- - clock-names
- dmas
- dma-names
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,crypto-v5.1
+ - qcom,crypto-v5.4
+ - qcom,ipq4019-qce
+then:
+ required:
+ - clocks
+ - clock-names
+
additionalProperties: false
examples:
--
2.33.0
Change the old deprecated compatible name to a new one, which is specific
to IPQ4019 SoC.
Signed-off-by: Vladimir Zapolskiy <[email protected]>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index a73c3a17b6a4..c73098d7a4da 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -314,7 +314,7 @@ cryptobam: dma-controller@8e04000 {
};
crypto: crypto@8e3a000 {
- compatible = "qcom,crypto-v5.1";
+ compatible = "qcom,ipq4019-qce";
reg = <0x08e3a000 0x6000>;
clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
<&gcc GCC_CRYPTO_AXI_CLK>,
--
2.33.0
Change the old deprecated compatible name of QCE IP on MSM8996 to new ones
based on SoC name.
Signed-off-by: Vladimir Zapolskiy <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 55180586f7b6..fe9a769afa37 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -784,7 +784,7 @@ cryptobam: dma-controller@644000 {
};
crypto: crypto@67a000 {
- compatible = "qcom,crypto-v5.4";
+ compatible = "qcom,msm8996-qce", "qcom,ipq4019-qce";
reg = <0x0067a000 0x6000>;
clocks = <&gcc GCC_CE1_AHB_CLK>,
<&gcc GCC_CE1_AXI_CLK>,
--
2.33.0
Change the old deprecated compatible name of QCE IP on SDM845 to new
ones based on SoC name.
Signed-off-by: Vladimir Zapolskiy <[email protected]>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 9ffc0fe07c21..2cf19e4d211b 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -2632,7 +2632,7 @@ cryptobam: dma-controller@1dc4000 {
};
crypto: crypto@1dfa000 {
- compatible = "qcom,crypto-v5.4";
+ compatible = "qcom,sdm845-qce", "qcom,ipq4019-qce";
reg = <0 0x01dfa000 0 0x6000>;
clocks = <&gcc GCC_CE1_AHB_CLK>,
<&gcc GCC_CE1_AXI_CLK>,
--
2.33.0
Add a family compatible for QCE IP on SM8550 SoC, which is equal to
QCE IP found on SM8150 SoC and described in the device tree bindings
documentation.
Signed-off-by: Vladimir Zapolskiy <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 1dea055a6815..7da89c478936 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1865,7 +1865,7 @@ cryptobam: dma-controller@1dc4000 {
};
crypto: crypto@1de0000 {
- compatible = "qcom,sm8550-qce";
+ compatible = "qcom,sm8550-qce", "qcom,sm8150-qce";
reg = <0x0 0x01dfa000 0x0 0x6000>;
dmas = <&cryptobam 4>, <&cryptobam 5>;
dma-names = "rx", "tx";
--
2.33.0
Add description of QCE and its corresponding BAM DMA IPs on SM8250 SoC.
Signed-off-by: Vladimir Zapolskiy <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index e59c16f74d17..d8698d18223e 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2215,6 +2215,30 @@ ufs_mem_phy_lanes: phy@1d87400 {
};
};
+ cryptobam: dma-controller@1dc4000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x0 0x01dc4000 0x0 0x24000>;
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ qcom,controlled-remotely;
+ num-channels = <8>;
+ qcom,num-ees = <2>;
+ iommus = <&apps_smmu 0x586 0x11>,
+ <&apps_smmu 0x596 0x11>;
+ };
+
+ crypto: crypto@1dfa000 {
+ compatible = "qcom,sm8250-qce", "qcom,sm8150-qce";
+ reg = <0x0 0x01dfa000 0x0 0x6000>;
+ dmas = <&cryptobam 6>, <&cryptobam 7>;
+ dma-names = "rx", "tx";
+ interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>;
+ interconnect-names = "memory";
+ iommus = <&apps_smmu 0x586 0x11>,
+ <&apps_smmu 0x596 0x11>;
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x40000>;
--
2.33.0
The added 'qcom,ipq4019-qce' and 'qcom,sm8150-qce' compatible values will
serve as QCE IP family compatibles, so that the crypto engine on added
platforms can derive from one of these two. Also the compatibles serve as
a fall-back for currently supported QCE IP variants on Qualcomm platforms.
At the moment there is no need to differentiate or add any other SoC
specific compatible values to the list, however it's known in advance
that the two QCE IP families are not fully compatible between each other.
The IP version based compatibles are left untouched to preserve backward
DTB ABI compatibility.
Signed-off-by: Vladimir Zapolskiy <[email protected]>
---
drivers/crypto/qce/core.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
index 8e496fb2d5e2..627354e772e9 100644
--- a/drivers/crypto/qce/core.c
+++ b/drivers/crypto/qce/core.c
@@ -293,6 +293,8 @@ static int qce_crypto_remove(struct platform_device *pdev)
static const struct of_device_id qce_crypto_of_match[] = {
{ .compatible = "qcom,crypto-v5.1", },
{ .compatible = "qcom,crypto-v5.4", },
+ { .compatible = "qcom,ipq4019-qce", },
+ { .compatible = "qcom,sm8150-qce", },
{}
};
MODULE_DEVICE_TABLE(of, qce_crypto_of_match);
--
2.33.0
From: Thara Gopinath <[email protected]>
Crypto engine on certain Snapdragon processors like sm8150, sm8250, sm8350
etc. requires interconnect path between the engine and memory to be
explicitly enabled and bandwidth set prior to any operations. Add support
in the qce core to enable the interconnect path appropriately.
Tested-by: Jordan Crouse <[email protected]>
Signed-off-by: Thara Gopinath <[email protected]>
[Bhupesh: Make header file inclusion alphabetical and use devm_of_icc_get()]
Signed-off-by: Bhupesh Sharma <[email protected]>
[vladimir: moved icc bandwidth setup closer to its acquisition]
Signed-off-by: Vladimir Zapolskiy <[email protected]>
---
drivers/crypto/qce/core.c | 16 +++++++++++++++-
drivers/crypto/qce/core.h | 1 +
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
index d3780be44a76..336edba2513e 100644
--- a/drivers/crypto/qce/core.c
+++ b/drivers/crypto/qce/core.c
@@ -5,6 +5,7 @@
#include <linux/clk.h>
#include <linux/dma-mapping.h>
+#include <linux/interconnect.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
@@ -22,6 +23,8 @@
#define QCE_MAJOR_VERSION5 0x05
#define QCE_QUEUE_LENGTH 1
+#define QCE_DEFAULT_MEM_BANDWIDTH 393600
+
static const struct qce_algo_ops *qce_ops[] = {
#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
&skcipher_ops,
@@ -218,10 +221,18 @@ static int qce_crypto_probe(struct platform_device *pdev)
if (IS_ERR(qce->bus))
return PTR_ERR(qce->bus);
- ret = clk_prepare_enable(qce->core);
+ qce->mem_path = devm_of_icc_get(qce->dev, "memory");
+ if (IS_ERR(qce->mem_path))
+ return PTR_ERR(qce->mem_path);
+
+ ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH);
if (ret)
return ret;
+ ret = clk_prepare_enable(qce->core);
+ if (ret)
+ goto err_mem_path_disable;
+
ret = clk_prepare_enable(qce->iface);
if (ret)
goto err_clks_core;
@@ -260,6 +271,9 @@ static int qce_crypto_probe(struct platform_device *pdev)
clk_disable_unprepare(qce->iface);
err_clks_core:
clk_disable_unprepare(qce->core);
+err_mem_path_disable:
+ icc_set_bw(qce->mem_path, 0, 0);
+
return ret;
}
diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h
index 085774cdf641..228fcd69ec51 100644
--- a/drivers/crypto/qce/core.h
+++ b/drivers/crypto/qce/core.h
@@ -35,6 +35,7 @@ struct qce_device {
void __iomem *base;
struct device *dev;
struct clk *core, *iface, *bus;
+ struct icc_path *mem_path;
struct qce_dma_data dma;
int burst_size;
unsigned int pipe_pair_id;
--
2.33.0
From: Thara Gopinath <[email protected]>
On certain Snapdragon processors, the crypto engine clocks are enabled by
default by security firmware and the driver should not handle the clocks.
Make acquiring of all the clocks optional in crypto engine driver, so that
the driver initializes properly even if no clocks are specified in the dt.
Tested-by: Jordan Crouse <[email protected]>
Signed-off-by: Thara Gopinath <[email protected]>
Signed-off-by: Bhupesh Sharma <[email protected]>
[Bhupesh: Massage the commit log]
Signed-off-by: Vladimir Zapolskiy <[email protected]>
---
drivers/crypto/qce/core.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
index 336edba2513e..8e496fb2d5e2 100644
--- a/drivers/crypto/qce/core.c
+++ b/drivers/crypto/qce/core.c
@@ -209,15 +209,15 @@ static int qce_crypto_probe(struct platform_device *pdev)
if (ret < 0)
return ret;
- qce->core = devm_clk_get(qce->dev, "core");
+ qce->core = devm_clk_get_optional(qce->dev, "core");
if (IS_ERR(qce->core))
return PTR_ERR(qce->core);
- qce->iface = devm_clk_get(qce->dev, "iface");
+ qce->iface = devm_clk_get_optional(qce->dev, "iface");
if (IS_ERR(qce->iface))
return PTR_ERR(qce->iface);
- qce->bus = devm_clk_get(qce->dev, "bus");
+ qce->bus = devm_clk_get_optional(qce->dev, "bus");
if (IS_ERR(qce->bus))
return PTR_ERR(qce->bus);
--
2.33.0
On 08/02/2023 19:37, Vladimir Zapolskiy wrote:
> Change QCE IP version specific compatible to two QCE IP family compatibles
> based on SoC name and populate these two IP families with particular SoC
> specific IP compatible names, which are known at the moment.
>
> Keep the old compatible 'qcom,crypto-v5.1' for backward compatibility
> of DTB ABI, but mark it as deprecated.
>
> The change is based on the original one written by Bhupesh Sharma.
>
> Cc: Bhupesh Sharma <[email protected]>
> Signed-off-by: Vladimir Zapolskiy <[email protected]>
> ---
> .../devicetree/bindings/crypto/qcom-qce.yaml | 24 +++++++++++++++++--
> 1 file changed, 22 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> index 4e00e7925fed..f6f1759a2f6e 100644
> --- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> @@ -15,7 +15,27 @@ description:
>
> properties:
> compatible:
> - const: qcom,crypto-v5.1
> + oneOf:
> + - const: qcom,crypto-v5.1
> + deprecated: true
> + description: Kept only for ABI backward compatibility
> + - const: qcom,crypto-v5.4
You should mention in commit msg that you document existing compatible
v5.4. Otherwise it looks unrelated/unexplained. Especially adding
deprecated compatible is unexpected.
> + deprecated: true
> + description: Kept only for ABI backward compatibility
Best regards,
Krzysztof
On 09/02/2023 10:18, Krzysztof Kozlowski wrote:
> On 08/02/2023 19:37, Vladimir Zapolskiy wrote:
>> Change QCE IP version specific compatible to two QCE IP family compatibles
>> based on SoC name and populate these two IP families with particular SoC
>> specific IP compatible names, which are known at the moment.
>>
>> Keep the old compatible 'qcom,crypto-v5.1' for backward compatibility
>> of DTB ABI, but mark it as deprecated.
>>
>> The change is based on the original one written by Bhupesh Sharma.
>>
>> Cc: Bhupesh Sharma <[email protected]>
>> Signed-off-by: Vladimir Zapolskiy <[email protected]>
>> ---
>> .../devicetree/bindings/crypto/qcom-qce.yaml | 24 +++++++++++++++++--
>> 1 file changed, 22 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
>> index 4e00e7925fed..f6f1759a2f6e 100644
>> --- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
>> +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
>> @@ -15,7 +15,27 @@ description:
>>
>> properties:
>> compatible:
>> - const: qcom,crypto-v5.1
>> + oneOf:
>> + - const: qcom,crypto-v5.1
>> + deprecated: true
>> + description: Kept only for ABI backward compatibility
>> + - const: qcom,crypto-v5.4
>
> You should mention in commit msg that you document existing compatible
> v5.4. Otherwise it looks unrelated/unexplained. Especially adding
> deprecated compatible is unexpected.
>
With commit msg adjustement for v5.4 compatible:
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 08/02/2023 19:37, Vladimir Zapolskiy wrote:
> On newer Qualcomm SoCs the crypto engine clocks are enabled by default
> by security firmware. To drop clocks and clock-names from the list of
> required properties use 'qcom,sm8150-qce' compatible name.
>
> The change is based on Neil Armstrong's observation and an original change.
>
> Cc: Neil Armstrong <[email protected]>
> Signed-off-by: Vladimir Zapolskiy <[email protected]>
> ---
> .../devicetree/bindings/crypto/qcom-qce.yaml | 15 +++++++++++++--
> 1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> index f6f1759a2f6e..d0f6b830a5dd 100644
> --- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> @@ -79,11 +79,22 @@ properties:
> required:
> - compatible
> - reg
> - - clocks
> - - clock-names
> - dmas
> - dma-names
>
> +if:
This should be in allOf, like I wrote in last discussion.
Best regards,
Krzysztof
On 08/02/2023 19:37, Vladimir Zapolskiy wrote:
> Change the old deprecated compatible name to a new one, which is specific
> to IPQ4019 SoC.
>
Your changeset is not bisectable, but that's expected. What is expected
is to explicitly say in commit msg, that DTS patches must be taken in
next cycle. This patch must wait as it breaks all in-tree and
out-of-tree users.
Also location of this patch in the patchset is not correct - cannot be
taken before the drivers.
Best regards,
Krzysztof
On 08/02/2023 19:37, Vladimir Zapolskiy wrote:
> Change the old deprecated compatible name of QCE IP on MSM8996 to new ones
> based on SoC name.
>
> Signed-off-by: Vladimir Zapolskiy <[email protected]>
> ---
Same dependency comment.
Best regards,
Krzysztof
On 08/02/2023 19:37, Vladimir Zapolskiy wrote:
> Change the old deprecated compatible name of QCE IP on SDM845 to new
> ones based on SoC name.
>
> Signed-off-by: Vladimir Zapolskiy <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Same dependency comment.
Best regards,
Krzysztof
On 08/02/2023 19:37, Vladimir Zapolskiy wrote:
> Add a family compatible for QCE IP on SM8550 SoC, which is equal to
> QCE IP found on SM8150 SoC and described in the device tree bindings
> documentation.
>
> Signed-off-by: Vladimir Zapolskiy <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
This one is ok:
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 08/02/2023 19:37, Vladimir Zapolskiy wrote:
> The added 'qcom,ipq4019-qce' and 'qcom,sm8150-qce' compatible values will
> serve as QCE IP family compatibles, so that the crypto engine on added
> platforms can derive from one of these two. Also the compatibles serve as
> a fall-back for currently supported QCE IP variants on Qualcomm platforms.
>
> At the moment there is no need to differentiate or add any other SoC
> specific compatible values to the list, however it's known in advance
> that the two QCE IP families are not fully compatible between each other.
>
> The IP version based compatibles are left untouched to preserve backward
> DTB ABI compatibility.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
Hi Vladimir,
On 2/9/23 12:07 AM, Vladimir Zapolskiy wrote:
> Add description of QCE and its corresponding BAM DMA IPs on SM8250 SoC.
>
> Signed-off-by: Vladimir Zapolskiy <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm8250.dtsi | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> index e59c16f74d17..d8698d18223e 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> @@ -2215,6 +2215,30 @@ ufs_mem_phy_lanes: phy@1d87400 {
> };
> };
>
> + cryptobam: dma-controller@1dc4000 {
> + compatible = "qcom,bam-v1.7.0";
> + reg = <0x0 0x01dc4000 0x0 0x24000>;
> + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
> + #dma-cells = <1>;
> + qcom,ee = <0>;
> + qcom,controlled-remotely;
> + num-channels = <8>;
> + qcom,num-ees = <2>;
> + iommus = <&apps_smmu 0x586 0x11>,
> + <&apps_smmu 0x596 0x11>;
> + };
> +
> + crypto: crypto@1dfa000 {
> + compatible = "qcom,sm8250-qce", "qcom,sm8150-qce";
> + reg = <0x0 0x01dfa000 0x0 0x6000>;
> + dmas = <&cryptobam 6>, <&cryptobam 7>;
> + dma-names = "rx", "tx";
> + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>;
> + interconnect-names = "memory";
> + iommus = <&apps_smmu 0x586 0x11>,
> + <&apps_smmu 0x596 0x11>;
> + };
> +
> tcsr_mutex: hwlock@1f40000 {
> compatible = "qcom,tcsr-mutex";
> reg = <0x0 0x01f40000 0x0 0x40000>;
This patch was part of the v7 arm64 dts fixes I sent out - see [1].
Probably you can use it as a base and make the changes (interconnect
property for the BAM DMA node and qce-compatible names) directly there
and include it in your patch series.
[1].
https://lore.kernel.org/linux-arm-msm/[email protected]/
Thanks,
Bhupesh
Hi Bhupesh,
On 2/9/23 14:21, Bhupesh Sharma wrote:
> Hi Vladimir,
>
> On 2/9/23 12:07 AM, Vladimir Zapolskiy wrote:
>> Add description of QCE and its corresponding BAM DMA IPs on SM8250 SoC.
>>
>> Signed-off-by: Vladimir Zapolskiy <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/sm8250.dtsi | 24 ++++++++++++++++++++++++
>> 1 file changed, 24 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
>> index e59c16f74d17..d8698d18223e 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
>> @@ -2215,6 +2215,30 @@ ufs_mem_phy_lanes: phy@1d87400 {
>> };
>> };
>>
>> + cryptobam: dma-controller@1dc4000 {
>> + compatible = "qcom,bam-v1.7.0";
>> + reg = <0x0 0x01dc4000 0x0 0x24000>;
>> + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
>> + #dma-cells = <1>;
>> + qcom,ee = <0>;
>> + qcom,controlled-remotely;
>> + num-channels = <8>;
>> + qcom,num-ees = <2>;
>> + iommus = <&apps_smmu 0x586 0x11>,
>> + <&apps_smmu 0x596 0x11>;
>> + };
>> +
>> + crypto: crypto@1dfa000 {
>> + compatible = "qcom,sm8250-qce", "qcom,sm8150-qce";
>> + reg = <0x0 0x01dfa000 0x0 0x6000>;
>> + dmas = <&cryptobam 6>, <&cryptobam 7>;
>> + dma-names = "rx", "tx";
>> + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>;
>> + interconnect-names = "memory";
>> + iommus = <&apps_smmu 0x586 0x11>,
>> + <&apps_smmu 0x596 0x11>;
>> + };
>> +
>> tcsr_mutex: hwlock@1f40000 {
>> compatible = "qcom,tcsr-mutex";
>> reg = <0x0 0x01f40000 0x0 0x40000>;
>
> This patch was part of the v7 arm64 dts fixes I sent out - see [1].
thank you for pointing it out, so there are two different v7 series of related
patches, as it's stated in the cover letter I based my v8 on top of linux-crypto
changes [*], and this particular change was developed independently from yours.
And so, there are some differences, can you please comment on them?
- My change does not have 'interconnects' property under dma-controller@1dc4000
device tree node, I believe it is not needed, but please correct me here.
- My change uses DMA channel number taken from the downstream code [**], is
there a reason to use different ones like in your change?
- My change has a shorter list of IOMMUs also copied from the same downstream
code, is there a reason to use a different extended list like in your change?
- On my end I have to retest your change without 'num-channels' and 'qcom,num-ees'
properties, since this also seems as an important difference between two patches.
Nevertheless, thank you again for bringing my attention to a different patch
series, I'll reuse the changes from it, and also publish all of them together and
in a separate changeset as Krzysztof suggested.
> Probably you can use it as a base and make the changes (interconnect
> property for the BAM DMA node and qce-compatible names) directly there
> and include it in your patch series.
[*] https://lore.kernel.org/linux-arm-msm/[email protected]/
[**] https://source.codeaurora.org/quic/la/kernel/msm-4.19/tree/arch/arm64/boot/dts/qcom/kona.dtsi?h=LA.UM.8.12.3.1&id=f3dd4aaeb34438c877ccd42f5a48ccd554dd765a#n2979
> [1].
> https://lore.kernel.org/linux-arm-msm/[email protected]/
--
Best wishes,
Vladimir
On 2/9/23 11:20, Krzysztof Kozlowski wrote:
> On 08/02/2023 19:37, Vladimir Zapolskiy wrote:
>> On newer Qualcomm SoCs the crypto engine clocks are enabled by default
>> by security firmware. To drop clocks and clock-names from the list of
>> required properties use 'qcom,sm8150-qce' compatible name.
>>
>> The change is based on Neil Armstrong's observation and an original change.
>>
>> Cc: Neil Armstrong <[email protected]>
>> Signed-off-by: Vladimir Zapolskiy <[email protected]>
>> ---
>> .../devicetree/bindings/crypto/qcom-qce.yaml | 15 +++++++++++++--
>> 1 file changed, 13 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
>> index f6f1759a2f6e..d0f6b830a5dd 100644
>> --- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
>> +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
>> @@ -79,11 +79,22 @@ properties:
>> required:
>> - compatible
>> - reg
>> - - clocks
>> - - clock-names
>> - dmas
>> - dma-names
>>
>> +if:
>
> This should be in allOf, like I wrote in last discussion.
In the last discussion you shared two options, and I got an impression
that adding a new "non-clock-requiring" compatible is a better option,
in this series it is "qcom,sm8150-qce".
So, do you wish to see an added allOf: on top of a single if: anyway?
--
Best wishes,
Vladimir
On 10/02/2023 12:17, Vladimir Zapolskiy wrote:
> On 2/9/23 11:20, Krzysztof Kozlowski wrote:
>> On 08/02/2023 19:37, Vladimir Zapolskiy wrote:
>>> On newer Qualcomm SoCs the crypto engine clocks are enabled by default
>>> by security firmware. To drop clocks and clock-names from the list of
>>> required properties use 'qcom,sm8150-qce' compatible name.
>>>
>>> The change is based on Neil Armstrong's observation and an original change.
>>>
>>> Cc: Neil Armstrong <[email protected]>
>>> Signed-off-by: Vladimir Zapolskiy <[email protected]>
>>> ---
>>> .../devicetree/bindings/crypto/qcom-qce.yaml | 15 +++++++++++++--
>>> 1 file changed, 13 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
>>> index f6f1759a2f6e..d0f6b830a5dd 100644
>>> --- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
>>> +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
>>> @@ -79,11 +79,22 @@ properties:
>>> required:
>>> - compatible
>>> - reg
>>> - - clocks
>>> - - clock-names
>>> - dmas
>>> - dma-names
>>>
>>> +if:
>>
>> This should be in allOf, like I wrote in last discussion.
>
> In the last discussion you shared two options, and I got an impression
> that adding a new "non-clock-requiring" compatible is a better option,
> in this series it is "qcom,sm8150-qce".
It's unrelated topic. What compatibles you use in what setup is one
thing. The syntax is second.
>
> So, do you wish to see an added allOf: on top of a single if: anyway?
Yes, because it will grow and then you have useless reindent.
Best regards,
Krzysztof
Hi Vladimir,
On 2/9/23 8:00 PM, Vladimir Zapolskiy wrote:
> Hi Bhupesh,
>
> On 2/9/23 14:21, Bhupesh Sharma wrote:
>> Hi Vladimir,
>>
>> On 2/9/23 12:07 AM, Vladimir Zapolskiy wrote:
>>> Add description of QCE and its corresponding BAM DMA IPs on SM8250 SoC.
>>>
>>> Signed-off-by: Vladimir Zapolskiy <[email protected]>
>>> ---
>>> arch/arm64/boot/dts/qcom/sm8250.dtsi | 24 ++++++++++++++++++++++++
>>> 1 file changed, 24 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
>>> b/arch/arm64/boot/dts/qcom/sm8250.dtsi
>>> index e59c16f74d17..d8698d18223e 100644
>>> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
>>> @@ -2215,6 +2215,30 @@ ufs_mem_phy_lanes: phy@1d87400 {
>>> };
>>> };
>>> + cryptobam: dma-controller@1dc4000 {
>>> + compatible = "qcom,bam-v1.7.0";
>>> + reg = <0x0 0x01dc4000 0x0 0x24000>;
>>> + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
>>> + #dma-cells = <1>;
>>> + qcom,ee = <0>;
>>> + qcom,controlled-remotely;
>>> + num-channels = <8>;
>>> + qcom,num-ees = <2>;
>>> + iommus = <&apps_smmu 0x586 0x11>,
>>> + <&apps_smmu 0x596 0x11>;
>>> + };
>>> +
>>> + crypto: crypto@1dfa000 {
>>> + compatible = "qcom,sm8250-qce", "qcom,sm8150-qce";
>>> + reg = <0x0 0x01dfa000 0x0 0x6000>;
>>> + dmas = <&cryptobam 6>, <&cryptobam 7>;
>>> + dma-names = "rx", "tx";
>>> + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0
>>> &mc_virt SLAVE_EBI_CH0>;
>>> + interconnect-names = "memory";
>>> + iommus = <&apps_smmu 0x586 0x11>,
>>> + <&apps_smmu 0x596 0x11>;
>>> + };
>>> +
>>> tcsr_mutex: hwlock@1f40000 {
>>> compatible = "qcom,tcsr-mutex";
>>> reg = <0x0 0x01f40000 0x0 0x40000>;
>>
>> This patch was part of the v7 arm64 dts fixes I sent out - see [1].
>
> thank you for pointing it out, so there are two different v7 series of
> related
> patches, as it's stated in the cover letter I based my v8 on top of
> linux-crypto
> changes [*], and this particular change was developed independently from
> yours.
>
> And so, there are some differences, can you please comment on them?
>
> - My change does not have 'interconnects' property under
> dma-controller@1dc4000
> device tree node, I believe it is not needed, but please correct me
> here.
> - My change uses DMA channel number taken from the downstream code [**], is
> there a reason to use different ones like in your change?
> - My change has a shorter list of IOMMUs also copied from the same
> downstream
> code, is there a reason to use a different extended list like in your
> change?
> - On my end I have to retest your change without 'num-channels' and
> 'qcom,num-ees'
> properties, since this also seems as an important difference between
> two patches.
>
> Nevertheless, thank you again for bringing my attention to a different
> patch
> series, I'll reuse the changes from it, and also publish all of them
> together and
> in a separate changeset as Krzysztof suggested.
>
>> Probably you can use it as a base and make the changes (interconnect
>> property for the BAM DMA node and qce-compatible names) directly there
>> and include it in your patch series.
>
> [*]
> https://lore.kernel.org/linux-arm-msm/[email protected]/
> [**]
> https://source.codeaurora.org/quic/la/kernel/msm-4.19/tree/arch/arm64/boot/dts/qcom/kona.dtsi?h=LA.UM.8.12.3.1&id=f3dd4aaeb34438c877ccd42f5a48ccd554dd765a#n2979
>
>> [1].
>> https://lore.kernel.org/linux-arm-msm/[email protected]/
Now that you mention it, I am a bit confused. My v7 series had 3
sub-series (one each for the arm64 dts + defconfig, crypto & dma tree):
-
https://lore.kernel.org/linux-arm-msm/[email protected]/
-
https://lore.kernel.org/linux-arm-msm/[email protected]/
-
https://lore.kernel.org/linux-arm-msm/[email protected]/
Where do you propose the v9 of the dma tree patch? I think you have
already clubbed the v9 arm64 dts patchset with this series
(you have left out the defconfig patch from there as it is already
merged and the sm8150 dts change, so that I can send it later), right?
Having said that, with only the v9 crypto series you shared, I am not
able to bring up crypto on either sm8250-mtp or (with one dts patch
added) on sa8155p-adp board(s). So, do I need to make other changes
(include patches from my earlier series) to get the same working?
Thanks,
Bhupesh
Hi Bhupesh,
On 2/13/23 19:12, Bhupesh Sharma wrote:
> Hi Vladimir,
>
> On 2/9/23 8:00 PM, Vladimir Zapolskiy wrote:
>> Hi Bhupesh,
>>
>> On 2/9/23 14:21, Bhupesh Sharma wrote:
>>> Hi Vladimir,
>>>
>>> On 2/9/23 12:07 AM, Vladimir Zapolskiy wrote:
>>>> Add description of QCE and its corresponding BAM DMA IPs on SM8250 SoC.
>>>>
>>>> Signed-off-by: Vladimir Zapolskiy <[email protected]>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/sm8250.dtsi | 24 ++++++++++++++++++++++++
>>>> 1 file changed, 24 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
>>>> b/arch/arm64/boot/dts/qcom/sm8250.dtsi
>>>> index e59c16f74d17..d8698d18223e 100644
>>>> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
>>>> @@ -2215,6 +2215,30 @@ ufs_mem_phy_lanes: phy@1d87400 {
>>>> };
>>>> };
>>>> + cryptobam: dma-controller@1dc4000 {
>>>> + compatible = "qcom,bam-v1.7.0";
>>>> + reg = <0x0 0x01dc4000 0x0 0x24000>;
>>>> + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
>>>> + #dma-cells = <1>;
>>>> + qcom,ee = <0>;
>>>> + qcom,controlled-remotely;
>>>> + num-channels = <8>;
>>>> + qcom,num-ees = <2>;
>>>> + iommus = <&apps_smmu 0x586 0x11>,
>>>> + <&apps_smmu 0x596 0x11>;
>>>> + };
>>>> +
>>>> + crypto: crypto@1dfa000 {
>>>> + compatible = "qcom,sm8250-qce", "qcom,sm8150-qce";
>>>> + reg = <0x0 0x01dfa000 0x0 0x6000>;
>>>> + dmas = <&cryptobam 6>, <&cryptobam 7>;
>>>> + dma-names = "rx", "tx";
>>>> + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0
>>>> &mc_virt SLAVE_EBI_CH0>;
>>>> + interconnect-names = "memory";
>>>> + iommus = <&apps_smmu 0x586 0x11>,
>>>> + <&apps_smmu 0x596 0x11>;
>>>> + };
>>>> +
>>>> tcsr_mutex: hwlock@1f40000 {
>>>> compatible = "qcom,tcsr-mutex";
>>>> reg = <0x0 0x01f40000 0x0 0x40000>;
>>>
>>> This patch was part of the v7 arm64 dts fixes I sent out - see [1].
>>
>> thank you for pointing it out, so there are two different v7 series of
>> related
>> patches, as it's stated in the cover letter I based my v8 on top of
>> linux-crypto
>> changes [*], and this particular change was developed independently from
>> yours.
>>
>> And so, there are some differences, can you please comment on them?
>>
>> - My change does not have 'interconnects' property under
>> dma-controller@1dc4000
>> device tree node, I believe it is not needed, but please correct me
>> here.
>> - My change uses DMA channel number taken from the downstream code [**], is
>> there a reason to use different ones like in your change?
>> - My change has a shorter list of IOMMUs also copied from the same
>> downstream
>> code, is there a reason to use a different extended list like in your
>> change?
>> - On my end I have to retest your change without 'num-channels' and
>> 'qcom,num-ees'
>> properties, since this also seems as an important difference between
>> two patches.
>>
>> Nevertheless, thank you again for bringing my attention to a different
>> patch
>> series, I'll reuse the changes from it, and also publish all of them
>> together and
>> in a separate changeset as Krzysztof suggested.
>>
>>> Probably you can use it as a base and make the changes (interconnect
>>> property for the BAM DMA node and qce-compatible names) directly there
>>> and include it in your patch series.
>>
>> [*]
>> https://lore.kernel.org/linux-arm-msm/[email protected]/
>> [**]
>> https://source.codeaurora.org/quic/la/kernel/msm-4.19/tree/arch/arm64/boot/dts/qcom/kona.dtsi?h=LA.UM.8.12.3.1&id=f3dd4aaeb34438c877ccd42f5a48ccd554dd765a#n2979
>>
>>> [1].
>>> https://lore.kernel.org/linux-arm-msm/[email protected]/
>
> Now that you mention it, I am a bit confused. My v7 series had 3
> sub-series (one each for the arm64 dts + defconfig, crypto & dma tree):
>
> -
> https://lore.kernel.org/linux-arm-msm/[email protected]/
> -
> https://lore.kernel.org/linux-arm-msm/[email protected]/
> -
> https://lore.kernel.org/linux-arm-msm/[email protected]/
Thank you, I will follow these series, the interconnects on DMA BAM
series is slipped from my attention, however I am able to run QCE
without adding interconnects to DMA BAM on available to me hardware.
> Where do you propose the v9 of the dma tree patch? I think you have
> already clubbed the v9 arm64 dts patchset with this series
> (you have left out the defconfig patch from there as it is already
> merged and the sm8150 dts change, so that I can send it later), right?
>
> Having said that, with only the v9 crypto series you shared, I am not
> able to bring up crypto on either sm8250-mtp or (with one dts patch
> added) on sa8155p-adp board(s). So, do I need to make other changes
> (include patches from my earlier series) to get the same working?
No, the shared v9 is complete, and I test it on top of the linux-next.
I'm able to successfully test QCE by running 'cryptsetup benchmark' on
RB5 hardware, the involvement of QCE and DMA BAM IPs can be checked
either by looking at bam_dma interrupt numbers from /proc/interrupts,
by adding qcrypto.dyndbg=+p into the kernel command line or by
registered algos and priorities found at /proc/crypto:
[ 9.515729] qcrypto 1dfa000.crypto: Crypto device found, version 5.5.0
I will be glad to know your opinion about the technical difference
between our two different sm8250.dtsi changes, please find my queries
in the previous email.
--
Best wishes,
Vladimir