Everyone:
Picking up where Chris left off (I chatted with him privately
beforehead), this series adds support for i.MX8MQ to CAAM driver. Just
like [v1], this series is i.MX8MQ only.
Feedback is welcome!
Thanks,
Andrey Smirnov
Changes since [v7]:
- Series rebase on latest cryptodev-2.6 (198429631a85)
- "crypto: caam - force DMA address to 32-bit on 64-bit i.MX SoCs"
converted to use CTPR and MCFGR to determine CAAM pointer width
and renamed to "crypto: caam - select DMA address size at runtime"
- Patch adding corresponding DT node added to the series
Changes since [v6]:
- Fixed build problems in "crypto: caam - make CAAM_PTR_SZ dynamic"
- Collected Reviewied-by from Horia
- "crypto: caam - force DMA address to 32-bit on 64-bit i.MX SoCs"
is changed to check 'caam_ptr_sz' instead of using 'caam_imx'
- Incorporated feedback for "crypto: caam - request JR IRQ as the
last step" and "crypto: caam - simplfy clock initialization"
Changes since [v5]:
- Hunk replacing sizeof(*jrp->inpring) to SIZEOF_JR_INPENTRY in
"crypto: caam - don't hardcode inpentry size", lost in [v5], is
back
- Collected Tested-by from Iuliana
Changes since [v4]:
- Fixed missing sentinel element in "crypto: caam - simplfy clock
initialization"
- Squashed all of the devers related patches into a single one and
converted IRQ allocation to use devres while at it
- Added "crypto: caam - request JR IRQ as the last step" as
discussed
Changes since [v3]:
- Patchset changed to select DMA size at runtime in order to enable
support for both i.MX8MQ and Layerscape at the same time. I only
tested the patches on i.MX6,7 and 8MQ, since I don't have access
to any of the Layerscape HW. Any help in that regard would be
appareciated.
- Bulk clocks and their number are now stored as a part of struct
caam_drv_private to simplify allocation and cleanup code (no
special context needed)
- Renamed 'soc_attr' -> 'imx_soc_match' for clarity
Changes since [v2]:
- Dropped "crypto: caam - do not initialise clocks on the i.MX8" and
replaced it with "crypto: caam - simplfy clock initialization" and
"crypto: caam - add clock entry for i.MX8MQ"
Changes since [v1]
- Series reworked to continue using register based interface for
queueing RNG initialization job, dropping "crypto: caam - use job
ring for RNG instantiation instead of DECO"
- Added a patch to share DMA mask selection code
- Added missing Signed-off-by for authors of original NXP tree
commits that this sereis is based on
[v7] lore.kernel.org/r/[email protected]
[v6] lore.kernel.org/r/[email protected]
[v5] lore.kernel.org/r/[email protected]
[v4] lore.kernel.org/r/[email protected]
[v3] lore.kernel.org/r/[email protected]
[v2] lore.kernel.org/r/[email protected]
[v1] https://patchwork.kernel.org/cover/10825625/
Andrey Smirnov (16):
crypto: caam - move DMA mask selection into a function
crypto: caam - simplfy clock initialization
crypto: caam - convert caam_jr_init() to use devres
crypto: caam - request JR IRQ as the last step
crytpo: caam - make use of iowrite64*_hi_lo in wr_reg64
crypto: caam - use ioread64*_hi_lo in rd_reg64
crypto: caam - drop 64-bit only wr/rd_reg64()
crypto: caam - share definition for MAX_SDLEN
crypto: caam - make CAAM_PTR_SZ dynamic
crypto: caam - move cpu_to_caam_dma() selection to runtime
crypto: caam - drop explicit usage of struct jr_outentry
crypto: caam - don't hardcode inpentry size
crypto: caam - select DMA address size at runtime
crypto: caam - always select job ring via RSR on i.MX8MQ
crypto: caam - add clock entry for i.MX8MQ
arm64: dts: imx8mq: Add CAAM node
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 30 +++
drivers/crypto/caam/caamalg.c | 2 +-
drivers/crypto/caam/caamalg_qi2.h | 27 ---
drivers/crypto/caam/caamhash.c | 2 +-
drivers/crypto/caam/caampkc.c | 8 +-
drivers/crypto/caam/caamrng.c | 2 +-
drivers/crypto/caam/ctrl.c | 221 ++++++++++------------
drivers/crypto/caam/desc_constr.h | 47 ++++-
drivers/crypto/caam/error.c | 3 +
drivers/crypto/caam/intern.h | 32 +++-
drivers/crypto/caam/jr.c | 93 +++------
drivers/crypto/caam/pdb.h | 16 +-
drivers/crypto/caam/pkc_desc.c | 8 +-
drivers/crypto/caam/qi.h | 26 ---
drivers/crypto/caam/regs.h | 140 ++++++++++----
15 files changed, 359 insertions(+), 298 deletions(-)
--
2.21.0
Use devres to allocate all of the resources in caam_jr_init() (DMA
coherent and regular memory, IRQs) drop calls to corresponding
deallocation routines. No functional change intended.
Signed-off-by: Andrey Smirnov <[email protected]>
Reviewed-by: Horia Geantă <[email protected]>
Cc: Cory Tusar <[email protected]>
Cc: Chris Healy <[email protected]>
Cc: Lucas Stach <[email protected]>
Cc: Horia Geantă <[email protected]>
Cc: Aymen Sghaier <[email protected]>
Cc: [email protected]
Cc: [email protected]
---
drivers/crypto/caam/jr.c | 48 ++++++++++++----------------------------
1 file changed, 14 insertions(+), 34 deletions(-)
diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c
index 4b25b2fa3d02..ea02f7774f7c 100644
--- a/drivers/crypto/caam/jr.c
+++ b/drivers/crypto/caam/jr.c
@@ -108,25 +108,12 @@ static int caam_reset_hw_jr(struct device *dev)
static int caam_jr_shutdown(struct device *dev)
{
struct caam_drv_private_jr *jrp = dev_get_drvdata(dev);
- dma_addr_t inpbusaddr, outbusaddr;
int ret;
ret = caam_reset_hw_jr(dev);
tasklet_kill(&jrp->irqtask);
- /* Release interrupt */
- free_irq(jrp->irq, dev);
-
- /* Free rings */
- inpbusaddr = rd_reg64(&jrp->rregs->inpring_base);
- outbusaddr = rd_reg64(&jrp->rregs->outring_base);
- dma_free_coherent(dev, sizeof(dma_addr_t) * JOBR_DEPTH,
- jrp->inpring, inpbusaddr);
- dma_free_coherent(dev, sizeof(struct jr_outentry) * JOBR_DEPTH,
- jrp->outring, outbusaddr);
- kfree(jrp->entinfo);
-
return ret;
}
@@ -444,8 +431,8 @@ static int caam_jr_init(struct device *dev)
tasklet_init(&jrp->irqtask, caam_jr_dequeue, (unsigned long)dev);
/* Connect job ring interrupt handler. */
- error = request_irq(jrp->irq, caam_jr_interrupt, IRQF_SHARED,
- dev_name(dev), dev);
+ error = devm_request_irq(dev, jrp->irq, caam_jr_interrupt, IRQF_SHARED,
+ dev_name(dev), dev);
if (error) {
dev_err(dev, "can't connect JobR %d interrupt (%d)\n",
jrp->ridx, jrp->irq);
@@ -454,22 +441,25 @@ static int caam_jr_init(struct device *dev)
error = caam_reset_hw_jr(dev);
if (error)
- goto out_free_irq;
+ goto out_kill_deq;
error = -ENOMEM;
- jrp->inpring = dma_alloc_coherent(dev, sizeof(*jrp->inpring) *
- JOBR_DEPTH, &inpbusaddr, GFP_KERNEL);
+ jrp->inpring = dmam_alloc_coherent(dev, sizeof(*jrp->inpring) *
+ JOBR_DEPTH, &inpbusaddr,
+ GFP_KERNEL);
if (!jrp->inpring)
- goto out_free_irq;
+ goto out_kill_deq;
- jrp->outring = dma_alloc_coherent(dev, sizeof(*jrp->outring) *
- JOBR_DEPTH, &outbusaddr, GFP_KERNEL);
+ jrp->outring = dmam_alloc_coherent(dev, sizeof(*jrp->outring) *
+ JOBR_DEPTH, &outbusaddr,
+ GFP_KERNEL);
if (!jrp->outring)
- goto out_free_inpring;
+ goto out_kill_deq;
- jrp->entinfo = kcalloc(JOBR_DEPTH, sizeof(*jrp->entinfo), GFP_KERNEL);
+ jrp->entinfo = devm_kcalloc(dev, JOBR_DEPTH, sizeof(*jrp->entinfo),
+ GFP_KERNEL);
if (!jrp->entinfo)
- goto out_free_outring;
+ goto out_kill_deq;
for (i = 0; i < JOBR_DEPTH; i++)
jrp->entinfo[i].desc_addr_dma = !0;
@@ -494,16 +484,6 @@ static int caam_jr_init(struct device *dev)
(JOBR_INTC_TIME_THLD << JRCFG_ICTT_SHIFT));
return 0;
-
-out_free_outring:
- dma_free_coherent(dev, sizeof(struct jr_outentry) * JOBR_DEPTH,
- jrp->outring, outbusaddr);
-out_free_inpring:
- dma_free_coherent(dev, sizeof(dma_addr_t) * JOBR_DEPTH,
- jrp->inpring, inpbusaddr);
- dev_err(dev, "can't allocate job rings for %d\n", jrp->ridx);
-out_free_irq:
- free_irq(jrp->irq, dev);
out_kill_deq:
tasklet_kill(&jrp->irqtask);
return error;
--
2.21.0
Using dma_addr_t for elements of JobR input ring is not appropriate on
all 64-bit SoCs, some of which, like i.MX8MQ, use only 32-bit wide
pointers there. Convert all of the code to use explicit helper
function that can be later extended to support i.MX8MQ. No functional
change intended.
Signed-off-by: Andrey Smirnov <[email protected]>
Cc: Chris Spencer <[email protected]>
Cc: Cory Tusar <[email protected]>
Cc: Chris Healy <[email protected]>
Cc: Lucas Stach <[email protected]>
Cc: Horia Geantă <[email protected]>
Cc: Aymen Sghaier <[email protected]>
Cc: Leonard Crestez <[email protected]>
Cc: [email protected]
Cc: [email protected]
---
drivers/crypto/caam/intern.h | 3 ++-
drivers/crypto/caam/jr.c | 4 ++--
drivers/crypto/caam/regs.h | 9 +++++++++
3 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/caam/intern.h b/drivers/crypto/caam/intern.h
index 081805c0f88b..c00c7c84ec84 100644
--- a/drivers/crypto/caam/intern.h
+++ b/drivers/crypto/caam/intern.h
@@ -55,7 +55,8 @@ struct caam_drv_private_jr {
spinlock_t inplock ____cacheline_aligned; /* Input ring index lock */
u32 inpring_avail; /* Number of free entries in input ring */
int head; /* entinfo (s/w ring) head index */
- dma_addr_t *inpring; /* Base of input ring, alloc DMA-safe */
+ void *inpring; /* Base of input ring, alloc
+ * DMA-safe */
int out_ring_read_index; /* Output index "tail" */
int tail; /* entinfo (s/w ring) tail index */
void *outring; /* Base of output ring, DMA-safe */
diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c
index 6c91f38862e4..417ad52615c6 100644
--- a/drivers/crypto/caam/jr.c
+++ b/drivers/crypto/caam/jr.c
@@ -388,7 +388,7 @@ int caam_jr_enqueue(struct device *dev, u32 *desc,
head_entry->cbkarg = areq;
head_entry->desc_addr_dma = desc_dma;
- jrp->inpring[head] = cpu_to_caam_dma(desc_dma);
+ jr_inpentry_set(jrp->inpring, head, cpu_to_caam_dma(desc_dma));
/*
* Guarantee that the descriptor's DMA address has been written to
@@ -434,7 +434,7 @@ static int caam_jr_init(struct device *dev)
if (error)
return error;
- jrp->inpring = dmam_alloc_coherent(dev, sizeof(*jrp->inpring) *
+ jrp->inpring = dmam_alloc_coherent(dev, SIZEOF_JR_INPENTRY *
JOBR_DEPTH, &inpbusaddr,
GFP_KERNEL);
if (!jrp->inpring)
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index cf73015b3be0..6dbb269a3e7e 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -244,6 +244,15 @@ static inline u32 jr_outentry_jrstatus(void *outring, int hw_idx)
return jrstatus;
}
+static inline void jr_inpentry_set(void *inpring, int hw_idx, dma_addr_t val)
+{
+ dma_addr_t *inpentry = inpring;
+
+ inpentry[hw_idx] = val;
+}
+
+#define SIZEOF_JR_INPENTRY caam_ptr_sz
+
/* Version registers (Era 10+) e80-eff */
struct version_regs {
--
2.21.0
Add node for CAAM - Cryptographic Acceleration and Assurance Module.
Signed-off-by: Horia Geantă <[email protected]>
Signed-off-by: Andrey Smirnov <[email protected]>
Cc: Chris Spencer <[email protected]>
Cc: Cory Tusar <[email protected]>
Cc: Chris Healy <[email protected]>
Cc: Lucas Stach <[email protected]>
Cc: Horia Geantă <[email protected]>
Cc: Aymen Sghaier <[email protected]>
Cc: Leonard Crestez <[email protected]>
Cc: [email protected]
Cc: [email protected]
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 30 +++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index d09b808eff87..752d5a61878c 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -728,6 +728,36 @@
status = "disabled";
};
+ crypto: crypto@30900000 {
+ compatible = "fsl,sec-v4.0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x30900000 0x40000>;
+ ranges = <0 0x30900000 0x40000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_AHB>,
+ <&clk IMX8MQ_CLK_IPG_ROOT>;
+ clock-names = "aclk", "ipg";
+
+ sec_jr0: jr@1000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr@2000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr2: jr@3000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x3000 0x1000>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
i2c1: i2c@30a20000 {
compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
reg = <0x30a20000 0x10000>;
--
2.21.0
Add clock entry needed to support i.MX8MQ.
Signed-off-by: Andrey Smirnov <[email protected]>
Cc: Chris Spencer <[email protected]>
Cc: Cory Tusar <[email protected]>
Cc: Chris Healy <[email protected]>
Cc: Lucas Stach <[email protected]>
Cc: Horia Geantă <[email protected]>
Cc: Aymen Sghaier <[email protected]>
Cc: Leonard Crestez <[email protected]>
Cc: [email protected]
Cc: [email protected]
---
drivers/crypto/caam/ctrl.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 3b18e7e8da1f..3c059d0e4207 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -527,6 +527,7 @@ static const struct soc_device_attribute caam_imx_soc_table[] = {
{ .soc_id = "i.MX6UL", .data = &caam_imx6ul_data },
{ .soc_id = "i.MX6*", .data = &caam_imx6_data },
{ .soc_id = "i.MX7*", .data = &caam_imx7_data },
+ { .soc_id = "i.MX8MQ", .data = &caam_imx7_data },
{ .family = "Freescale i.MX" },
{ /* sentinel */ }
};
--
2.21.0
i.MX8 mScale SoC still use 32-bit addresses in its CAAM implmentation,
so we can't rely on sizeof(dma_addr_t) to detemine CAAM pointer
size. Convert the code to query CTPR and MCFGR for that during driver
probing.
Signed-off-by: Andrey Smirnov <[email protected]>
Cc: Chris Spencer <[email protected]>
Cc: Cory Tusar <[email protected]>
Cc: Chris Healy <[email protected]>
Cc: Lucas Stach <[email protected]>
Cc: Horia Geantă <[email protected]>
Cc: Aymen Sghaier <[email protected]>
Cc: Leonard Crestez <[email protected]>
Cc: [email protected]
Cc: [email protected]
---
drivers/crypto/caam/caampkc.c | 8 +++----
drivers/crypto/caam/ctrl.c | 5 +++-
drivers/crypto/caam/desc_constr.h | 10 ++++++--
drivers/crypto/caam/intern.h | 2 +-
drivers/crypto/caam/pdb.h | 16 +++++++++----
drivers/crypto/caam/pkc_desc.c | 8 +++----
drivers/crypto/caam/regs.h | 40 +++++++++++++++++++++++--------
7 files changed, 63 insertions(+), 26 deletions(-)
diff --git a/drivers/crypto/caam/caampkc.c b/drivers/crypto/caam/caampkc.c
index 5b12b232ee5e..83f96d4f86e0 100644
--- a/drivers/crypto/caam/caampkc.c
+++ b/drivers/crypto/caam/caampkc.c
@@ -17,13 +17,13 @@
#include "sg_sw_sec4.h"
#include "caampkc.h"
-#define DESC_RSA_PUB_LEN (2 * CAAM_CMD_SZ + sizeof(struct rsa_pub_pdb))
+#define DESC_RSA_PUB_LEN (2 * CAAM_CMD_SZ + SIZEOF_RSA_PUB_PDB)
#define DESC_RSA_PRIV_F1_LEN (2 * CAAM_CMD_SZ + \
- sizeof(struct rsa_priv_f1_pdb))
+ SIZEOF_RSA_PRIV_F1_PDB)
#define DESC_RSA_PRIV_F2_LEN (2 * CAAM_CMD_SZ + \
- sizeof(struct rsa_priv_f2_pdb))
+ SIZEOF_RSA_PRIV_F2_PDB)
#define DESC_RSA_PRIV_F3_LEN (2 * CAAM_CMD_SZ + \
- sizeof(struct rsa_priv_f3_pdb))
+ SIZEOF_RSA_PRIV_F3_PDB)
#define CAAM_RSA_MAX_INPUT_SIZE 512 /* for a 4096-bit modulus */
/* buffer filled with zeros, used for padding */
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 47b92451756f..4b7f95f64e34 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -602,7 +602,10 @@ static int caam_probe(struct platform_device *pdev)
caam_imx = (bool)imx_soc_match;
comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);
- caam_ptr_sz = sizeof(dma_addr_t);
+ if (comp_params & CTPR_MS_PS && rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR)
+ caam_ptr_sz = sizeof(u64);
+ else
+ caam_ptr_sz = sizeof(u32);
caam_dpaa2 = !!(comp_params & CTPR_MS_DPAA2);
ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK);
diff --git a/drivers/crypto/caam/desc_constr.h b/drivers/crypto/caam/desc_constr.h
index 89187831d74f..62ce6421bb3f 100644
--- a/drivers/crypto/caam/desc_constr.h
+++ b/drivers/crypto/caam/desc_constr.h
@@ -136,9 +136,15 @@ static inline void init_job_desc_pdb(u32 * const desc, u32 options,
static inline void append_ptr(u32 * const desc, dma_addr_t ptr)
{
- dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
+ if (caam_ptr_sz == sizeof(dma_addr_t)) {
+ dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
- *offset = cpu_to_caam_dma(ptr);
+ *offset = cpu_to_caam_dma(ptr);
+ } else {
+ u32 *offset = (u32 *)desc_end(desc);
+
+ *offset = cpu_to_caam_dma(ptr);
+ }
(*desc) = cpu_to_caam32(caam32_to_cpu(*desc) +
CAAM_PTR_SZ / CAAM_CMD_SZ);
diff --git a/drivers/crypto/caam/intern.h b/drivers/crypto/caam/intern.h
index c00c7c84ec84..731b06becd9c 100644
--- a/drivers/crypto/caam/intern.h
+++ b/drivers/crypto/caam/intern.h
@@ -219,7 +219,7 @@ static inline u64 caam_get_dma_mask(struct device *dev)
{
struct device_node *nprop = dev->of_node;
- if (sizeof(dma_addr_t) != sizeof(u64))
+ if (caam_ptr_sz != sizeof(u64))
return DMA_BIT_MASK(32);
if (caam_dpaa2)
diff --git a/drivers/crypto/caam/pdb.h b/drivers/crypto/caam/pdb.h
index 810f0bef0652..68c1fd5dee5d 100644
--- a/drivers/crypto/caam/pdb.h
+++ b/drivers/crypto/caam/pdb.h
@@ -512,7 +512,9 @@ struct rsa_pub_pdb {
dma_addr_t n_dma;
dma_addr_t e_dma;
u32 f_len;
-} __packed;
+};
+
+#define SIZEOF_RSA_PUB_PDB (2 * sizeof(u32) + 4 * caam_ptr_sz)
/**
* RSA Decrypt PDB - Private Key Form #1
@@ -528,7 +530,9 @@ struct rsa_priv_f1_pdb {
dma_addr_t f_dma;
dma_addr_t n_dma;
dma_addr_t d_dma;
-} __packed;
+};
+
+#define SIZEOF_RSA_PRIV_F1_PDB (sizeof(u32) + 4 * caam_ptr_sz)
/**
* RSA Decrypt PDB - Private Key Form #2
@@ -554,7 +558,9 @@ struct rsa_priv_f2_pdb {
dma_addr_t tmp1_dma;
dma_addr_t tmp2_dma;
u32 p_q_len;
-} __packed;
+};
+
+#define SIZEOF_RSA_PRIV_F2_PDB (2 * sizeof(u32) + 7 * caam_ptr_sz)
/**
* RSA Decrypt PDB - Private Key Form #3
@@ -586,6 +592,8 @@ struct rsa_priv_f3_pdb {
dma_addr_t tmp1_dma;
dma_addr_t tmp2_dma;
u32 p_q_len;
-} __packed;
+};
+
+#define SIZEOF_RSA_PRIV_F3_PDB (2 * sizeof(u32) + 9 * caam_ptr_sz)
#endif
diff --git a/drivers/crypto/caam/pkc_desc.c b/drivers/crypto/caam/pkc_desc.c
index 2a8d87ea94bf..0d5ee762e036 100644
--- a/drivers/crypto/caam/pkc_desc.c
+++ b/drivers/crypto/caam/pkc_desc.c
@@ -13,7 +13,7 @@
/* Descriptor for RSA Public operation */
void init_rsa_pub_desc(u32 *desc, struct rsa_pub_pdb *pdb)
{
- init_job_desc_pdb(desc, 0, sizeof(*pdb));
+ init_job_desc_pdb(desc, 0, SIZEOF_RSA_PUB_PDB);
append_cmd(desc, pdb->sgf);
append_ptr(desc, pdb->f_dma);
append_ptr(desc, pdb->g_dma);
@@ -26,7 +26,7 @@ void init_rsa_pub_desc(u32 *desc, struct rsa_pub_pdb *pdb)
/* Descriptor for RSA Private operation - Private Key Form #1 */
void init_rsa_priv_f1_desc(u32 *desc, struct rsa_priv_f1_pdb *pdb)
{
- init_job_desc_pdb(desc, 0, sizeof(*pdb));
+ init_job_desc_pdb(desc, 0, SIZEOF_RSA_PRIV_F1_PDB);
append_cmd(desc, pdb->sgf);
append_ptr(desc, pdb->g_dma);
append_ptr(desc, pdb->f_dma);
@@ -39,7 +39,7 @@ void init_rsa_priv_f1_desc(u32 *desc, struct rsa_priv_f1_pdb *pdb)
/* Descriptor for RSA Private operation - Private Key Form #2 */
void init_rsa_priv_f2_desc(u32 *desc, struct rsa_priv_f2_pdb *pdb)
{
- init_job_desc_pdb(desc, 0, sizeof(*pdb));
+ init_job_desc_pdb(desc, 0, SIZEOF_RSA_PRIV_F2_PDB);
append_cmd(desc, pdb->sgf);
append_ptr(desc, pdb->g_dma);
append_ptr(desc, pdb->f_dma);
@@ -56,7 +56,7 @@ void init_rsa_priv_f2_desc(u32 *desc, struct rsa_priv_f2_pdb *pdb)
/* Descriptor for RSA Private operation - Private Key Form #3 */
void init_rsa_priv_f3_desc(u32 *desc, struct rsa_priv_f3_pdb *pdb)
{
- init_job_desc_pdb(desc, 0, sizeof(*pdb));
+ init_job_desc_pdb(desc, 0, SIZEOF_RSA_PRIV_F3_PDB);
append_cmd(desc, pdb->sgf);
append_ptr(desc, pdb->g_dma);
append_ptr(desc, pdb->f_dma);
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index 6dbb269a3e7e..05127b70527d 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -191,7 +191,8 @@ static inline u64 caam_dma64_to_cpu(u64 value)
static inline u64 cpu_to_caam_dma(u64 value)
{
- if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
+ if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) &&
+ caam_ptr_sz == sizeof(u64))
return cpu_to_caam_dma64(value);
else
return cpu_to_caam32(value);
@@ -199,7 +200,8 @@ static inline u64 cpu_to_caam_dma(u64 value)
static inline u64 caam_dma_to_cpu(u64 value)
{
- if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
+ if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) &&
+ caam_ptr_sz == sizeof(u64))
return caam_dma64_to_cpu(value);
else
return caam32_to_cpu(value);
@@ -213,13 +215,24 @@ static inline u64 caam_dma_to_cpu(u64 value)
static inline void jr_outentry_get(void *outring, int hw_idx, dma_addr_t *desc,
u32 *jrstatus)
{
- struct {
- dma_addr_t desc;/* Pointer to completed descriptor */
- u32 jrstatus; /* Status for completed descriptor */
- } __packed *outentry = outring;
- *desc = outentry[hw_idx].desc;
- *jrstatus = outentry[hw_idx].jrstatus;
+ if (caam_ptr_sz == sizeof(u32)) {
+ struct {
+ u32 desc;
+ u32 jrstatus;
+ } __packed *outentry = outring;
+
+ *desc = outentry[hw_idx].desc;
+ *jrstatus = outentry[hw_idx].jrstatus;
+ } else {
+ struct {
+ dma_addr_t desc;/* Pointer to completed descriptor */
+ u32 jrstatus; /* Status for completed descriptor */
+ } __packed *outentry = outring;
+
+ *desc = outentry[hw_idx].desc;
+ *jrstatus = outentry[hw_idx].jrstatus;
+ }
}
#define SIZEOF_JR_OUTENTRY (caam_ptr_sz + sizeof(u32))
@@ -246,9 +259,15 @@ static inline u32 jr_outentry_jrstatus(void *outring, int hw_idx)
static inline void jr_inpentry_set(void *inpring, int hw_idx, dma_addr_t val)
{
- dma_addr_t *inpentry = inpring;
+ if (caam_ptr_sz == sizeof(u32)) {
+ u32 *inpentry = inpring;
- inpentry[hw_idx] = val;
+ inpentry[hw_idx] = val;
+ } else {
+ dma_addr_t *inpentry = inpring;
+
+ inpentry[hw_idx] = val;
+ }
}
#define SIZEOF_JR_INPENTRY caam_ptr_sz
@@ -380,6 +399,7 @@ struct caam_perfmon {
u32 cha_rev_ls; /* CRNR - CHA Rev No. Least significant half*/
#define CTPR_MS_QI_SHIFT 25
#define CTPR_MS_QI_MASK (0x1ull << CTPR_MS_QI_SHIFT)
+#define CTPR_MS_PS BIT(17)
#define CTPR_MS_DPAA2 BIT(13)
#define CTPR_MS_VIRT_EN_INCL 0x00000001
#define CTPR_MS_VIRT_EN_POR 0x00000002
--
2.21.0
Instead of selecting the implementation of
cpu_to_caam_dma()/caam_dma_to_cpu() at build time using the
preprocessor, convert the code to do that at run-time using IS_ENABLED
macro. This is needed to add support for i.MX8MQ. No functional change
intended.
Signed-off-by: Andrey Smirnov <[email protected]>
Cc: Chris Spencer <[email protected]>
Cc: Cory Tusar <[email protected]>
Cc: Chris Healy <[email protected]>
Cc: Lucas Stach <[email protected]>
Cc: Horia Geantă <[email protected]>
Cc: Aymen Sghaier <[email protected]>
Cc: Leonard Crestez <[email protected]>
Cc: [email protected]
Cc: [email protected]
---
drivers/crypto/caam/regs.h | 22 +++++++++++++++-------
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index 489d6c1eec7d..0df4cf32fe78 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -188,13 +188,21 @@ static inline u64 caam_dma64_to_cpu(u64 value)
return caam64_to_cpu(value);
}
-#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
-#define cpu_to_caam_dma(value) cpu_to_caam_dma64(value)
-#define caam_dma_to_cpu(value) caam_dma64_to_cpu(value)
-#else
-#define cpu_to_caam_dma(value) cpu_to_caam32(value)
-#define caam_dma_to_cpu(value) caam32_to_cpu(value)
-#endif /* CONFIG_ARCH_DMA_ADDR_T_64BIT */
+static inline u64 cpu_to_caam_dma(u64 value)
+{
+ if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
+ return cpu_to_caam_dma64(value);
+ else
+ return cpu_to_caam32(value);
+}
+
+static inline u64 caam_dma_to_cpu(u64 value)
+{
+ if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
+ return caam_dma64_to_cpu(value);
+ else
+ return caam32_to_cpu(value);
+}
/*
* jr_outentry
--
2.21.0
Both qi.h and cammalg_qi2.h seem to define identical versions of
MAX_SDLEN. Move it to desc_constr.h to avoid duplication.
Signed-off-by: Andrey Smirnov <[email protected]>
Cc: Chris Spencer <[email protected]>
Cc: Cory Tusar <[email protected]>
Cc: Chris Healy <[email protected]>
Cc: Lucas Stach <[email protected]>
Cc: Horia Geantă <[email protected]>
Cc: Aymen Sghaier <[email protected]>
Cc: Leonard Crestez <[email protected]>
Cc: [email protected]
Cc: [email protected]
---
drivers/crypto/caam/caamalg_qi2.h | 27 ---------------------------
drivers/crypto/caam/desc_constr.h | 27 +++++++++++++++++++++++++++
drivers/crypto/caam/qi.h | 26 --------------------------
3 files changed, 27 insertions(+), 53 deletions(-)
diff --git a/drivers/crypto/caam/caamalg_qi2.h b/drivers/crypto/caam/caamalg_qi2.h
index b450e2a25c1f..706736776b47 100644
--- a/drivers/crypto/caam/caamalg_qi2.h
+++ b/drivers/crypto/caam/caamalg_qi2.h
@@ -92,33 +92,6 @@ struct dpaa2_caam_priv_per_cpu {
struct dpaa2_io *dpio;
};
-/*
- * The CAAM QI hardware constructs a job descriptor which points
- * to shared descriptor (as pointed by context_a of FQ to CAAM).
- * When the job descriptor is executed by deco, the whole job
- * descriptor together with shared descriptor gets loaded in
- * deco buffer which is 64 words long (each 32-bit).
- *
- * The job descriptor constructed by QI hardware has layout:
- *
- * HEADER (1 word)
- * Shdesc ptr (1 or 2 words)
- * SEQ_OUT_PTR (1 word)
- * Out ptr (1 or 2 words)
- * Out length (1 word)
- * SEQ_IN_PTR (1 word)
- * In ptr (1 or 2 words)
- * In length (1 word)
- *
- * The shdesc ptr is used to fetch shared descriptor contents
- * into deco buffer.
- *
- * Apart from shdesc contents, the total number of words that
- * get loaded in deco buffer are '8' or '11'. The remaining words
- * in deco buffer can be used for storing shared descriptor.
- */
-#define MAX_SDLEN ((CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN) / CAAM_CMD_SZ)
-
/* Length of a single buffer in the QI driver memory cache */
#define CAAM_QI_MEMCACHE_SIZE 512
diff --git a/drivers/crypto/caam/desc_constr.h b/drivers/crypto/caam/desc_constr.h
index 536f360bf131..1fe50a4fefaa 100644
--- a/drivers/crypto/caam/desc_constr.h
+++ b/drivers/crypto/caam/desc_constr.h
@@ -18,6 +18,33 @@
#define CAAM_DESC_BYTES_MAX (CAAM_CMD_SZ * MAX_CAAM_DESCSIZE)
#define DESC_JOB_IO_LEN (CAAM_CMD_SZ * 5 + CAAM_PTR_SZ * 3)
+/*
+ * The CAAM QI hardware constructs a job descriptor which points
+ * to shared descriptor (as pointed by context_a of FQ to CAAM).
+ * When the job descriptor is executed by deco, the whole job
+ * descriptor together with shared descriptor gets loaded in
+ * deco buffer which is 64 words long (each 32-bit).
+ *
+ * The job descriptor constructed by QI hardware has layout:
+ *
+ * HEADER (1 word)
+ * Shdesc ptr (1 or 2 words)
+ * SEQ_OUT_PTR (1 word)
+ * Out ptr (1 or 2 words)
+ * Out length (1 word)
+ * SEQ_IN_PTR (1 word)
+ * In ptr (1 or 2 words)
+ * In length (1 word)
+ *
+ * The shdesc ptr is used to fetch shared descriptor contents
+ * into deco buffer.
+ *
+ * Apart from shdesc contents, the total number of words that
+ * get loaded in deco buffer are '8' or '11'. The remaining words
+ * in deco buffer can be used for storing shared descriptor.
+ */
+#define MAX_SDLEN ((CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN) / CAAM_CMD_SZ)
+
#ifdef DEBUG
#define PRINT_POS do { printk(KERN_DEBUG "%02d: %s\n", desc_len(desc),\
&__func__[sizeof("append")]); } while (0)
diff --git a/drivers/crypto/caam/qi.h b/drivers/crypto/caam/qi.h
index f93c9c7ed430..db0549549e3b 100644
--- a/drivers/crypto/caam/qi.h
+++ b/drivers/crypto/caam/qi.h
@@ -14,32 +14,6 @@
#include "desc.h"
#include "desc_constr.h"
-/*
- * CAAM hardware constructs a job descriptor which points to a shared descriptor
- * (as pointed by context_a of to-CAAM FQ).
- * When the job descriptor is executed by DECO, the whole job descriptor
- * together with shared descriptor gets loaded in DECO buffer, which is
- * 64 words (each 32-bit) long.
- *
- * The job descriptor constructed by CAAM hardware has the following layout:
- *
- * HEADER (1 word)
- * Shdesc ptr (1 or 2 words)
- * SEQ_OUT_PTR (1 word)
- * Out ptr (1 or 2 words)
- * Out length (1 word)
- * SEQ_IN_PTR (1 word)
- * In ptr (1 or 2 words)
- * In length (1 word)
- *
- * The shdesc ptr is used to fetch shared descriptor contents into DECO buffer.
- *
- * Apart from shdesc contents, the total number of words that get loaded in DECO
- * buffer are '8' or '11'. The remaining words in DECO buffer can be used for
- * storing shared descriptor.
- */
-#define MAX_SDLEN ((CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN) / CAAM_CMD_SZ)
-
/* Length of a single buffer in the QI driver memory cache */
#define CAAM_QI_MEMCACHE_SIZE 768
--
2.21.0
Following the same transformation logic as outlined in previous commit
converting wr_reg64, convert rd_reg64 to use helpers from
<linux/io-64-nonatomic-hi-lo.h> first. No functional change intended.
Signed-off-by: Andrey Smirnov <[email protected]>
Reviewed-by: Horia Geantă <[email protected]>
Cc: Chris Spencer <[email protected]>
Cc: Cory Tusar <[email protected]>
Cc: Chris Healy <[email protected]>
Cc: Lucas Stach <[email protected]>
Cc: Horia Geantă <[email protected]>
Cc: Aymen Sghaier <[email protected]>
Cc: Leonard Crestez <[email protected]>
Cc: [email protected]
Cc: [email protected]
---
drivers/crypto/caam/regs.h | 18 +++++++++++++-----
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index 6acfef30a90c..4efc10534873 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -172,12 +172,20 @@ static inline void wr_reg64(void __iomem *reg, u64 data)
static inline u64 rd_reg64(void __iomem *reg)
{
- if (!caam_imx && caam_little_end)
- return ((u64)rd_reg32((u32 __iomem *)(reg) + 1) << 32 |
- (u64)rd_reg32((u32 __iomem *)(reg)));
+ if (caam_little_end) {
+ if (caam_imx) {
+ u32 low, high;
- return ((u64)rd_reg32((u32 __iomem *)(reg)) << 32 |
- (u64)rd_reg32((u32 __iomem *)(reg) + 1));
+ high = ioread32(reg);
+ low = ioread32(reg + sizeof(u32));
+
+ return low + ((u64)high << 32);
+ } else {
+ return ioread64(reg);
+ }
+ } else {
+ return ioread64be(reg);
+ }
}
#endif /* CONFIG_64BIT */
--
2.21.0
Simplify clock initialization code by converting it to use clk-bulk,
devres and soc_device_match() match table. No functional change
intended.
Signed-off-by: Andrey Smirnov <[email protected]>
Reviewed-by: Leonard Crestez <[email protected]>
Tested-by: Iuliana Prodan <[email protected]>
Cc: Chris Spencer <[email protected]>
Cc: Cory Tusar <[email protected]>
Cc: Chris Healy <[email protected]>
Cc: Lucas Stach <[email protected]>
Cc: Horia Geantă <[email protected]>
Cc: Aymen Sghaier <[email protected]>
Cc: Leonard Crestez <[email protected]>
Cc: [email protected]
Cc: [email protected]
---
drivers/crypto/caam/ctrl.c | 198 ++++++++++++++++-------------------
drivers/crypto/caam/intern.h | 7 +-
2 files changed, 95 insertions(+), 110 deletions(-)
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 50336494f285..0b4007068c31 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -25,16 +25,6 @@ EXPORT_SYMBOL(caam_dpaa2);
#include "qi.h"
#endif
-/*
- * i.MX targets tend to have clock control subsystems that can
- * enable/disable clocking to our device.
- */
-static inline struct clk *caam_drv_identify_clk(struct device *dev,
- char *clk_name)
-{
- return caam_imx ? devm_clk_get(dev, clk_name) : NULL;
-}
-
/*
* Descriptor to instantiate RNG State Handle 0 in normal mode and
* load the JDKEK, TDKEK and TDSK registers
@@ -342,13 +332,6 @@ static int caam_remove(struct platform_device *pdev)
/* Unmap controller region */
iounmap(ctrl);
- /* shut clocks off before finalizing shutdown */
- clk_disable_unprepare(ctrlpriv->caam_ipg);
- if (ctrlpriv->caam_mem)
- clk_disable_unprepare(ctrlpriv->caam_mem);
- clk_disable_unprepare(ctrlpriv->caam_aclk);
- if (ctrlpriv->caam_emi_slow)
- clk_disable_unprepare(ctrlpriv->caam_emi_slow);
return 0;
}
@@ -497,20 +480,98 @@ static const struct of_device_id caam_match[] = {
};
MODULE_DEVICE_TABLE(of, caam_match);
+struct caam_imx_data {
+ const struct clk_bulk_data *clks;
+ int num_clks;
+};
+
+static const struct clk_bulk_data caam_imx6_clks[] = {
+ { .id = "ipg" },
+ { .id = "mem" },
+ { .id = "aclk" },
+ { .id = "emi_slow" },
+};
+
+static const struct caam_imx_data caam_imx6_data = {
+ .clks = caam_imx6_clks,
+ .num_clks = ARRAY_SIZE(caam_imx6_clks),
+};
+
+static const struct clk_bulk_data caam_imx7_clks[] = {
+ { .id = "ipg" },
+ { .id = "aclk" },
+};
+
+static const struct caam_imx_data caam_imx7_data = {
+ .clks = caam_imx7_clks,
+ .num_clks = ARRAY_SIZE(caam_imx7_clks),
+};
+
+static const struct clk_bulk_data caam_imx6ul_clks[] = {
+ { .id = "ipg" },
+ { .id = "mem" },
+ { .id = "aclk" },
+};
+
+static const struct caam_imx_data caam_imx6ul_data = {
+ .clks = caam_imx6ul_clks,
+ .num_clks = ARRAY_SIZE(caam_imx6ul_clks),
+};
+
+static const struct soc_device_attribute caam_imx_soc_table[] = {
+ { .soc_id = "i.MX6UL", .data = &caam_imx6ul_data },
+ { .soc_id = "i.MX6*", .data = &caam_imx6_data },
+ { .soc_id = "i.MX7*", .data = &caam_imx7_data },
+ { .family = "Freescale i.MX" },
+ { /* sentinel */ }
+};
+
+static void disable_clocks(void *data)
+{
+ struct caam_drv_private *ctrlpriv = data;
+
+ clk_bulk_disable_unprepare(ctrlpriv->num_clks, ctrlpriv->clks);
+}
+
+static int init_clocks(struct device *dev, const struct caam_imx_data *data)
+{
+ struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
+ int ret;
+
+ ctrlpriv->num_clks = data->num_clks;
+ ctrlpriv->clks = devm_kmemdup(dev, data->clks,
+ data->num_clks * sizeof(data->clks[0]),
+ GFP_KERNEL);
+ if (!ctrlpriv->clks)
+ return -ENOMEM;
+
+ ret = devm_clk_bulk_get(dev, ctrlpriv->num_clks, ctrlpriv->clks);
+ if (ret) {
+ dev_err(dev,
+ "Failed to request all necessary clocks\n");
+ return ret;
+ }
+
+ ret = clk_bulk_prepare_enable(ctrlpriv->num_clks, ctrlpriv->clks);
+ if (ret) {
+ dev_err(dev,
+ "Failed to prepare/enable all necessary clocks\n");
+ return ret;
+ }
+
+ return devm_add_action_or_reset(dev, disable_clocks, ctrlpriv);
+}
+
/* Probe routine for CAAM top (controller) level */
static int caam_probe(struct platform_device *pdev)
{
int ret, ring, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
u64 caam_id;
- static const struct soc_device_attribute imx_soc[] = {
- {.family = "Freescale i.MX"},
- {},
- };
+ const struct soc_device_attribute *imx_soc_match;
struct device *dev;
struct device_node *nprop, *np;
struct caam_ctrl __iomem *ctrl;
struct caam_drv_private *ctrlpriv;
- struct clk *clk;
#ifdef CONFIG_DEBUG_FS
struct caam_perfmon *perfmon;
#endif
@@ -537,7 +598,8 @@ static int caam_probe(struct platform_device *pdev)
caam_little_end = !(bool)(rd_reg32(&ctrl->perfmon.status) &
(CSTA_PLEND | CSTA_ALT_PLEND));
- caam_imx = (bool)soc_device_match(imx_soc);
+ imx_soc_match = soc_device_match(caam_imx_soc_table);
+ caam_imx = (bool)imx_soc_match;
comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);
caam_dpaa2 = !!(comp_params & CTPR_MS_DPAA2);
@@ -568,81 +630,17 @@ static int caam_probe(struct platform_device *pdev)
}
#endif
- /* Enable clocking */
- clk = caam_drv_identify_clk(&pdev->dev, "ipg");
- if (IS_ERR(clk)) {
- ret = PTR_ERR(clk);
- dev_err(&pdev->dev,
- "can't identify CAAM ipg clk: %d\n", ret);
- goto iounmap_ctrl;
- }
- ctrlpriv->caam_ipg = clk;
-
- if (!of_machine_is_compatible("fsl,imx7d") &&
- !of_machine_is_compatible("fsl,imx7s") &&
- !of_machine_is_compatible("fsl,imx7ulp")) {
- clk = caam_drv_identify_clk(&pdev->dev, "mem");
- if (IS_ERR(clk)) {
- ret = PTR_ERR(clk);
- dev_err(&pdev->dev,
- "can't identify CAAM mem clk: %d\n", ret);
- goto iounmap_ctrl;
+ if (imx_soc_match) {
+ if (!imx_soc_match->data) {
+ dev_err(dev, "No clock data provided for i.MX SoC");
+ return -EINVAL;
}
- ctrlpriv->caam_mem = clk;
- }
- clk = caam_drv_identify_clk(&pdev->dev, "aclk");
- if (IS_ERR(clk)) {
- ret = PTR_ERR(clk);
- dev_err(&pdev->dev,
- "can't identify CAAM aclk clk: %d\n", ret);
- goto iounmap_ctrl;
- }
- ctrlpriv->caam_aclk = clk;
-
- if (!of_machine_is_compatible("fsl,imx6ul") &&
- !of_machine_is_compatible("fsl,imx7d") &&
- !of_machine_is_compatible("fsl,imx7s") &&
- !of_machine_is_compatible("fsl,imx7ulp")) {
- clk = caam_drv_identify_clk(&pdev->dev, "emi_slow");
- if (IS_ERR(clk)) {
- ret = PTR_ERR(clk);
- dev_err(&pdev->dev,
- "can't identify CAAM emi_slow clk: %d\n", ret);
- goto iounmap_ctrl;
- }
- ctrlpriv->caam_emi_slow = clk;
- }
-
- ret = clk_prepare_enable(ctrlpriv->caam_ipg);
- if (ret < 0) {
- dev_err(&pdev->dev, "can't enable CAAM ipg clock: %d\n", ret);
- goto iounmap_ctrl;
- }
-
- if (ctrlpriv->caam_mem) {
- ret = clk_prepare_enable(ctrlpriv->caam_mem);
- if (ret < 0) {
- dev_err(&pdev->dev, "can't enable CAAM secure mem clock: %d\n",
- ret);
- goto disable_caam_ipg;
- }
+ ret = init_clocks(dev, imx_soc_match->data);
+ if (ret)
+ return ret;
}
- ret = clk_prepare_enable(ctrlpriv->caam_aclk);
- if (ret < 0) {
- dev_err(&pdev->dev, "can't enable CAAM aclk clock: %d\n", ret);
- goto disable_caam_mem;
- }
-
- if (ctrlpriv->caam_emi_slow) {
- ret = clk_prepare_enable(ctrlpriv->caam_emi_slow);
- if (ret < 0) {
- dev_err(&pdev->dev, "can't enable CAAM emi slow clock: %d\n",
- ret);
- goto disable_caam_aclk;
- }
- }
/* Allocating the BLOCK_OFFSET based on the supported page size on
* the platform
@@ -714,7 +712,7 @@ static int caam_probe(struct platform_device *pdev)
ret = dma_set_mask_and_coherent(dev, caam_get_dma_mask(dev));
if (ret) {
dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret);
- goto disable_caam_emi_slow;
+ goto iounmap_ctrl;
}
ctrlpriv->era = caam_get_era(ctrl);
@@ -919,16 +917,6 @@ static int caam_probe(struct platform_device *pdev)
if (ctrlpriv->qi_init)
caam_qi_shutdown(dev);
#endif
-disable_caam_emi_slow:
- if (ctrlpriv->caam_emi_slow)
- clk_disable_unprepare(ctrlpriv->caam_emi_slow);
-disable_caam_aclk:
- clk_disable_unprepare(ctrlpriv->caam_aclk);
-disable_caam_mem:
- if (ctrlpriv->caam_mem)
- clk_disable_unprepare(ctrlpriv->caam_mem);
-disable_caam_ipg:
- clk_disable_unprepare(ctrlpriv->caam_ipg);
iounmap_ctrl:
iounmap(ctrl);
return ret;
diff --git a/drivers/crypto/caam/intern.h b/drivers/crypto/caam/intern.h
index ec25d260fa40..1f01703f510a 100644
--- a/drivers/crypto/caam/intern.h
+++ b/drivers/crypto/caam/intern.h
@@ -94,11 +94,8 @@ struct caam_drv_private {
Handles of the RNG4 block are initialized
by this driver */
- struct clk *caam_ipg;
- struct clk *caam_mem;
- struct clk *caam_aclk;
- struct clk *caam_emi_slow;
-
+ struct clk_bulk_data *clks;
+ int num_clks;
/*
* debugfs entries for developer view into driver/device
* variables at runtime.
--
2.21.0
Since 32-bit of both wr_reg64 and rd_reg64 now use 64-bit IO helpers,
these functions should no longer be necessary. No functional change intended.
Signed-off-by: Andrey Smirnov <[email protected]>
Reviewed-by: Horia Geantă <[email protected]>
Cc: Chris Spencer <[email protected]>
Cc: Cory Tusar <[email protected]>
Cc: Chris Healy <[email protected]>
Cc: Lucas Stach <[email protected]>
Cc: Horia Geantă <[email protected]>
Cc: Aymen Sghaier <[email protected]>
Cc: Leonard Crestez <[email protected]>
Cc: [email protected]
Cc: [email protected]
---
drivers/crypto/caam/regs.h | 19 -------------------
1 file changed, 19 deletions(-)
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index 4efc10534873..489d6c1eec7d 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -138,24 +138,6 @@ static inline void clrsetbits_32(void __iomem *reg, u32 clear, u32 set)
* base + 0x0000 : least-significant 32 bits
* base + 0x0004 : most-significant 32 bits
*/
-#ifdef CONFIG_64BIT
-static inline void wr_reg64(void __iomem *reg, u64 data)
-{
- if (caam_little_end)
- iowrite64(data, reg);
- else
- iowrite64be(data, reg);
-}
-
-static inline u64 rd_reg64(void __iomem *reg)
-{
- if (caam_little_end)
- return ioread64(reg);
- else
- return ioread64be(reg);
-}
-
-#else /* CONFIG_64BIT */
static inline void wr_reg64(void __iomem *reg, u64 data)
{
if (caam_little_end) {
@@ -187,7 +169,6 @@ static inline u64 rd_reg64(void __iomem *reg)
return ioread64be(reg);
}
}
-#endif /* CONFIG_64BIT */
static inline u64 cpu_to_caam_dma64(dma_addr_t value)
{
--
2.21.0
On Tue, Aug 20, 2019 at 1:24 PM Andrey Smirnov <[email protected]> wrote:
>
> i.MX8 mScale SoC still use 32-bit addresses in its CAAM implmentation,
> so we can't rely on sizeof(dma_addr_t) to detemine CAAM pointer
> size. Convert the code to query CTPR and MCFGR for that during driver
> probing.
>
> Signed-off-by: Andrey Smirnov <[email protected]>
> Cc: Chris Spencer <[email protected]>
> Cc: Cory Tusar <[email protected]>
> Cc: Chris Healy <[email protected]>
> Cc: Lucas Stach <[email protected]>
> Cc: Horia Geantă <[email protected]>
> Cc: Aymen Sghaier <[email protected]>
> Cc: Leonard Crestez <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> ---
> drivers/crypto/caam/caampkc.c | 8 +++----
> drivers/crypto/caam/ctrl.c | 5 +++-
> drivers/crypto/caam/desc_constr.h | 10 ++++++--
> drivers/crypto/caam/intern.h | 2 +-
> drivers/crypto/caam/pdb.h | 16 +++++++++----
> drivers/crypto/caam/pkc_desc.c | 8 +++----
> drivers/crypto/caam/regs.h | 40 +++++++++++++++++++++++--------
> 7 files changed, 63 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/crypto/caam/caampkc.c b/drivers/crypto/caam/caampkc.c
> index 5b12b232ee5e..83f96d4f86e0 100644
> --- a/drivers/crypto/caam/caampkc.c
> +++ b/drivers/crypto/caam/caampkc.c
> @@ -17,13 +17,13 @@
> #include "sg_sw_sec4.h"
> #include "caampkc.h"
>
> -#define DESC_RSA_PUB_LEN (2 * CAAM_CMD_SZ + sizeof(struct rsa_pub_pdb))
> +#define DESC_RSA_PUB_LEN (2 * CAAM_CMD_SZ + SIZEOF_RSA_PUB_PDB)
> #define DESC_RSA_PRIV_F1_LEN (2 * CAAM_CMD_SZ + \
> - sizeof(struct rsa_priv_f1_pdb))
> + SIZEOF_RSA_PRIV_F1_PDB)
> #define DESC_RSA_PRIV_F2_LEN (2 * CAAM_CMD_SZ + \
> - sizeof(struct rsa_priv_f2_pdb))
> + SIZEOF_RSA_PRIV_F2_PDB)
> #define DESC_RSA_PRIV_F3_LEN (2 * CAAM_CMD_SZ + \
> - sizeof(struct rsa_priv_f3_pdb))
> + SIZEOF_RSA_PRIV_F3_PDB)
> #define CAAM_RSA_MAX_INPUT_SIZE 512 /* for a 4096-bit modulus */
>
> /* buffer filled with zeros, used for padding */
> diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
> index 47b92451756f..4b7f95f64e34 100644
> --- a/drivers/crypto/caam/ctrl.c
> +++ b/drivers/crypto/caam/ctrl.c
> @@ -602,7 +602,10 @@ static int caam_probe(struct platform_device *pdev)
> caam_imx = (bool)imx_soc_match;
>
> comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);
> - caam_ptr_sz = sizeof(dma_addr_t);
> + if (comp_params & CTPR_MS_PS && rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR)
Horia:
As I previously mentioned, i.MX8MQ SRM I have doesn't document MCFGR
bits related to this. If you don't mind, please double check that
using MCFGR_LONG_PTR here is correct.
Thanks,
Andrey Smirnov
On 8/20/2019 11:24 PM, Andrey Smirnov wrote:
> Everyone:
>
> Picking up where Chris left off (I chatted with him privately
> beforehead), this series adds support for i.MX8MQ to CAAM driver. Just
> like [v1], this series is i.MX8MQ only.
>
> Feedback is welcome!
> Thanks,
> Andrey Smirnov
>
For the series:
Reviewed-by: Iuliana Prodan <[email protected]>
Thanks,
Iulia
Andrey Smirnov <[email protected]> wrote:
> Everyone:
>
> Picking up where Chris left off (I chatted with him privately
> beforehead), this series adds support for i.MX8MQ to CAAM driver. Just
> like [v1], this series is i.MX8MQ only.
>
> Feedback is welcome!
> Thanks,
> Andrey Smirnov
>
> Changes since [v7]:
>
> - Series rebase on latest cryptodev-2.6 (198429631a85)
>
> - "crypto: caam - force DMA address to 32-bit on 64-bit i.MX SoCs"
> converted to use CTPR and MCFGR to determine CAAM pointer width
> and renamed to "crypto: caam - select DMA address size at runtime"
>
> - Patch adding corresponding DT node added to the series
>
> Changes since [v6]:
>
> - Fixed build problems in "crypto: caam - make CAAM_PTR_SZ dynamic"
>
> - Collected Reviewied-by from Horia
>
> - "crypto: caam - force DMA address to 32-bit on 64-bit i.MX SoCs"
> is changed to check 'caam_ptr_sz' instead of using 'caam_imx'
>
> - Incorporated feedback for "crypto: caam - request JR IRQ as the
> last step" and "crypto: caam - simplfy clock initialization"
>
> Changes since [v5]:
>
> - Hunk replacing sizeof(*jrp->inpring) to SIZEOF_JR_INPENTRY in
> "crypto: caam - don't hardcode inpentry size", lost in [v5], is
> back
>
> - Collected Tested-by from Iuliana
>
> Changes since [v4]:
>
> - Fixed missing sentinel element in "crypto: caam - simplfy clock
> initialization"
>
> - Squashed all of the devers related patches into a single one and
> converted IRQ allocation to use devres while at it
>
> - Added "crypto: caam - request JR IRQ as the last step" as
> discussed
>
> Changes since [v3]:
>
> - Patchset changed to select DMA size at runtime in order to enable
> support for both i.MX8MQ and Layerscape at the same time. I only
> tested the patches on i.MX6,7 and 8MQ, since I don't have access
> to any of the Layerscape HW. Any help in that regard would be
> appareciated.
>
> - Bulk clocks and their number are now stored as a part of struct
> caam_drv_private to simplify allocation and cleanup code (no
> special context needed)
>
> - Renamed 'soc_attr' -> 'imx_soc_match' for clarity
>
> Changes since [v2]:
>
> - Dropped "crypto: caam - do not initialise clocks on the i.MX8" and
> replaced it with "crypto: caam - simplfy clock initialization" and
> "crypto: caam - add clock entry for i.MX8MQ"
>
>
> Changes since [v1]
>
> - Series reworked to continue using register based interface for
> queueing RNG initialization job, dropping "crypto: caam - use job
> ring for RNG instantiation instead of DECO"
>
> - Added a patch to share DMA mask selection code
>
> - Added missing Signed-off-by for authors of original NXP tree
> commits that this sereis is based on
>
> [v7] lore.kernel.org/r/[email protected]
> [v6] lore.kernel.org/r/[email protected]
> [v5] lore.kernel.org/r/[email protected]
> [v4] lore.kernel.org/r/[email protected]
> [v3] lore.kernel.org/r/[email protected]
> [v2] lore.kernel.org/r/[email protected]
> [v1] https://patchwork.kernel.org/cover/10825625/
>
> Andrey Smirnov (16):
> crypto: caam - move DMA mask selection into a function
> crypto: caam - simplfy clock initialization
> crypto: caam - convert caam_jr_init() to use devres
> crypto: caam - request JR IRQ as the last step
> crytpo: caam - make use of iowrite64*_hi_lo in wr_reg64
> crypto: caam - use ioread64*_hi_lo in rd_reg64
> crypto: caam - drop 64-bit only wr/rd_reg64()
> crypto: caam - share definition for MAX_SDLEN
> crypto: caam - make CAAM_PTR_SZ dynamic
> crypto: caam - move cpu_to_caam_dma() selection to runtime
> crypto: caam - drop explicit usage of struct jr_outentry
> crypto: caam - don't hardcode inpentry size
> crypto: caam - select DMA address size at runtime
> crypto: caam - always select job ring via RSR on i.MX8MQ
> crypto: caam - add clock entry for i.MX8MQ
> arm64: dts: imx8mq: Add CAAM node
>
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 30 +++
> drivers/crypto/caam/caamalg.c | 2 +-
> drivers/crypto/caam/caamalg_qi2.h | 27 ---
> drivers/crypto/caam/caamhash.c | 2 +-
> drivers/crypto/caam/caampkc.c | 8 +-
> drivers/crypto/caam/caamrng.c | 2 +-
> drivers/crypto/caam/ctrl.c | 221 ++++++++++------------
> drivers/crypto/caam/desc_constr.h | 47 ++++-
> drivers/crypto/caam/error.c | 3 +
> drivers/crypto/caam/intern.h | 32 +++-
> drivers/crypto/caam/jr.c | 93 +++------
> drivers/crypto/caam/pdb.h | 16 +-
> drivers/crypto/caam/pkc_desc.c | 8 +-
> drivers/crypto/caam/qi.h | 26 ---
> drivers/crypto/caam/regs.h | 140 ++++++++++----
> 15 files changed, 359 insertions(+), 298 deletions(-)
Patches 1-15 applied. Thanks.
--
Email: Herbert Xu <[email protected]>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
On 8/30/2019 11:23 AM, Herbert Xu wrote:
> Andrey Smirnov <[email protected]> wrote:
>> Everyone:
>>
>> Picking up where Chris left off (I chatted with him privately
>> beforehead), this series adds support for i.MX8MQ to CAAM driver. Just
>> like [v1], this series is i.MX8MQ only.
>>
>> Feedback is welcome!
>> Thanks,
>> Andrey Smirnov
>>
>> Changes since [v7]:
>>
>> - Series rebase on latest cryptodev-2.6 (198429631a85)
>>
>> - "crypto: caam - force DMA address to 32-bit on 64-bit i.MX SoCs"
>> converted to use CTPR and MCFGR to determine CAAM pointer width
>> and renamed to "crypto: caam - select DMA address size at runtime"
>>
>> - Patch adding corresponding DT node added to the series
>>
>> Changes since [v6]:
>>
>> - Fixed build problems in "crypto: caam - make CAAM_PTR_SZ dynamic"
>>
>> - Collected Reviewied-by from Horia
>>
>> - "crypto: caam - force DMA address to 32-bit on 64-bit i.MX SoCs"
>> is changed to check 'caam_ptr_sz' instead of using 'caam_imx'
>>
>> - Incorporated feedback for "crypto: caam - request JR IRQ as the
>> last step" and "crypto: caam - simplfy clock initialization"
>>
>> Changes since [v5]:
>>
>> - Hunk replacing sizeof(*jrp->inpring) to SIZEOF_JR_INPENTRY in
>> "crypto: caam - don't hardcode inpentry size", lost in [v5], is
>> back
>>
>> - Collected Tested-by from Iuliana
>>
>> Changes since [v4]:
>>
>> - Fixed missing sentinel element in "crypto: caam - simplfy clock
>> initialization"
>>
>> - Squashed all of the devers related patches into a single one and
>> converted IRQ allocation to use devres while at it
>>
>> - Added "crypto: caam - request JR IRQ as the last step" as
>> discussed
>>
>> Changes since [v3]:
>>
>> - Patchset changed to select DMA size at runtime in order to enable
>> support for both i.MX8MQ and Layerscape at the same time. I only
>> tested the patches on i.MX6,7 and 8MQ, since I don't have access
>> to any of the Layerscape HW. Any help in that regard would be
>> appareciated.
>>
>> - Bulk clocks and their number are now stored as a part of struct
>> caam_drv_private to simplify allocation and cleanup code (no
>> special context needed)
>>
>> - Renamed 'soc_attr' -> 'imx_soc_match' for clarity
>>
>> Changes since [v2]:
>>
>> - Dropped "crypto: caam - do not initialise clocks on the i.MX8" and
>> replaced it with "crypto: caam - simplfy clock initialization" and
>> "crypto: caam - add clock entry for i.MX8MQ"
>>
>>
>> Changes since [v1]
>>
>> - Series reworked to continue using register based interface for
>> queueing RNG initialization job, dropping "crypto: caam - use job
>> ring for RNG instantiation instead of DECO"
>>
>> - Added a patch to share DMA mask selection code
>>
>> - Added missing Signed-off-by for authors of original NXP tree
>> commits that this sereis is based on
>>
>> [v7] lore.kernel.org/r/[email protected]
>> [v6] lore.kernel.org/r/[email protected]
>> [v5] lore.kernel.org/r/[email protected]
>> [v4] lore.kernel.org/r/[email protected]
>> [v3] lore.kernel.org/r/[email protected]
>> [v2] lore.kernel.org/r/[email protected]
>> [v1] https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.kernel.org%2Fcover%2F10825625%2F&data=02%7C01%7Ciuliana.prodan%40nxp.com%7C33d82b783fe44b7397a108d72d2361d7%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637027502298978288&sdata=Tc%2FSuS60cL8%2FLisYBtfarPAVmcx7ITpNgaiLMq5YLIs%3D&reserved=0
>>
>> Andrey Smirnov (16):
>> crypto: caam - move DMA mask selection into a function
>> crypto: caam - simplfy clock initialization
>> crypto: caam - convert caam_jr_init() to use devres
>> crypto: caam - request JR IRQ as the last step
>> crytpo: caam - make use of iowrite64*_hi_lo in wr_reg64
>> crypto: caam - use ioread64*_hi_lo in rd_reg64
>> crypto: caam - drop 64-bit only wr/rd_reg64()
>> crypto: caam - share definition for MAX_SDLEN
>> crypto: caam - make CAAM_PTR_SZ dynamic
>> crypto: caam - move cpu_to_caam_dma() selection to runtime
>> crypto: caam - drop explicit usage of struct jr_outentry
>> crypto: caam - don't hardcode inpentry size
>> crypto: caam - select DMA address size at runtime
>> crypto: caam - always select job ring via RSR on i.MX8MQ
>> crypto: caam - add clock entry for i.MX8MQ
>> arm64: dts: imx8mq: Add CAAM node
>>
>> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 30 +++
>> drivers/crypto/caam/caamalg.c | 2 +-
>> drivers/crypto/caam/caamalg_qi2.h | 27 ---
>> drivers/crypto/caam/caamhash.c | 2 +-
>> drivers/crypto/caam/caampkc.c | 8 +-
>> drivers/crypto/caam/caamrng.c | 2 +-
>> drivers/crypto/caam/ctrl.c | 221 ++++++++++------------
>> drivers/crypto/caam/desc_constr.h | 47 ++++-
>> drivers/crypto/caam/error.c | 3 +
>> drivers/crypto/caam/intern.h | 32 +++-
>> drivers/crypto/caam/jr.c | 93 +++------
>> drivers/crypto/caam/pdb.h | 16 +-
>> drivers/crypto/caam/pkc_desc.c | 8 +-
>> drivers/crypto/caam/qi.h | 26 ---
>> drivers/crypto/caam/regs.h | 140 ++++++++++----
>> 15 files changed, 359 insertions(+), 298 deletions(-)
>
> Patches 1-15 applied. Thanks.
>
Hi Herbert,
Can you, please, add, also, the device tree patch ("arm64: dts: imx8mq:
Add CAAM node") in cryptodev tree?
Unfortunately Shawn Guo wasn't cc-ed on this patch and, to have the
complete support for imx8mq, in kernel v5.4, we need the node in dts.
Thank you,
Iulia
On Fri, Aug 30, 2019 at 09:15:12AM +0000, Iuliana Prodan wrote:
>
> Can you, please, add, also, the device tree patch ("arm64: dts: imx8mq:
> Add CAAM node") in cryptodev tree?
> Unfortunately Shawn Guo wasn't cc-ed on this patch and, to have the
> complete support for imx8mq, in kernel v5.4, we need the node in dts.
If Shawn can ack this then I'm happy to apply this patch.
Thanks,
--
Email: Herbert Xu <[email protected]>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
On 8/30/2019 4:16 PM, Herbert Xu wrote:
> On Fri, Aug 30, 2019 at 09:15:12AM +0000, Iuliana Prodan wrote:
>>
>> Can you, please, add, also, the device tree patch ("arm64: dts: imx8mq:
>> Add CAAM node") in cryptodev tree?
>> Unfortunately Shawn Guo wasn't cc-ed on this patch and, to have the
>> complete support for imx8mq, in kernel v5.4, we need the node in dts.
>
> If Shawn can ack this then I'm happy to apply this patch.
>
> Thanks,
>
Thanks, Herbert!
Andrey can you, please, resend the dts patch and cc Shawn Guo?
Thanks,
Iulia
On Fri, Aug 30, 2019 at 6:35 AM Iuliana Prodan <[email protected]> wrote:
>
> On 8/30/2019 4:16 PM, Herbert Xu wrote:
> > On Fri, Aug 30, 2019 at 09:15:12AM +0000, Iuliana Prodan wrote:
> >>
> >> Can you, please, add, also, the device tree patch ("arm64: dts: imx8mq:
> >> Add CAAM node") in cryptodev tree?
> >> Unfortunately Shawn Guo wasn't cc-ed on this patch and, to have the
> >> complete support for imx8mq, in kernel v5.4, we need the node in dts.
> >
> > If Shawn can ack this then I'm happy to apply this patch.
> >
> > Thanks,
> >
>
> Thanks, Herbert!
>
> Andrey can you, please, resend the dts patch and cc Shawn Guo?
>
Will do.
Thanks,
Andrey Smirnov