2022-09-17 17:04:11

by Daniel Golle

[permalink] [raw]
Subject: [PATCH v2 00/16] rt2x00: OpenWrt patches improving MT7620

Over the years we have been accumulating a number of patches improving
support for the IEEE 802.11bgn 2T2R wireless interface built into the
MediaTek MT7620 MIPS SoCs. Many of them have not been in shape for
being submitted to Linux and changes were needed to make checkpatch.pl
all happy. Now they look as good as it gets, given that most code deals
with undocumented registers and was adapted from the vendor driver.

Patch 1/1 also has been previously submitted and then (imho wrongly)
rejected, so I've included it in this series.

Alltogether rt2x00 now performs almost as good as the vendor driver,
see benchmark of HT20 client below:

Accepted connection from 192.168.5.133, port 37382
[ 5] local 192.168.5.175 port 5201 connected to 192.168.5.133 port 37384
[ ID] Interval Transfer Bitrate
[ 5] 0.00-1.00 sec 9.57 MBytes 80.3 Mbits/sec
[ 5] 1.00-2.00 sec 9.68 MBytes 81.2 Mbits/sec
[ 5] 2.00-3.00 sec 9.98 MBytes 83.7 Mbits/sec
[ 5] 3.00-4.00 sec 9.72 MBytes 81.6 Mbits/sec
[ 5] 4.00-5.00 sec 9.49 MBytes 79.6 Mbits/sec
[ 5] 5.00-6.00 sec 9.88 MBytes 82.9 Mbits/sec
[ 5] 6.00-7.00 sec 9.76 MBytes 81.8 Mbits/sec
[ 5] 7.00-8.00 sec 9.96 MBytes 83.6 Mbits/sec
[ 5] 8.00-9.00 sec 9.76 MBytes 81.9 Mbits/sec
[ 5] 9.00-10.00 sec 9.86 MBytes 82.7 Mbits/sec
[ 5] 10.00-10.03 sec 243 KBytes 78.4 Mbits/sec
- - - - - - - - - - - - - - - - - - - - - - - - -
[ ID] Interval Transfer Bitrate
[ 5] 0.00-10.03 sec 97.9 MBytes 81.9 Mbits/sec receiver

Accepted connection from 192.168.5.133, port 49588
[ 5] local 192.168.5.175 port 5201 connected to 192.168.5.133 port 49598
[ ID] Interval Transfer Bitrate Retr Cwnd
[ 5] 0.00-1.00 sec 12.7 MBytes 106 Mbits/sec 0 557 KBytes
[ 5] 1.00-2.00 sec 11.1 MBytes 93.0 Mbits/sec 0 1020 KBytes
[ 5] 2.00-3.00 sec 11.2 MBytes 94.4 Mbits/sec 0 1.57 MBytes
[ 5] 3.00-4.00 sec 11.2 MBytes 94.4 Mbits/sec 0 1.58 MBytes
[ 5] 4.00-5.00 sec 10.0 MBytes 83.9 Mbits/sec 0 1.58 MBytes
[ 5] 5.00-6.00 sec 11.2 MBytes 94.4 Mbits/sec 0 1.58 MBytes
[ 5] 6.00-7.00 sec 11.2 MBytes 94.4 Mbits/sec 0 1.58 MBytes
[ 5] 7.00-8.00 sec 10.0 MBytes 83.9 Mbits/sec 0 1.58 MBytes
[ 5] 8.00-9.00 sec 12.5 MBytes 105 Mbits/sec 0 1.58 MBytes
[ 5] 9.00-10.00 sec 10.0 MBytes 83.9 Mbits/sec 0 1.58 MBytes
[ 5] 10.00-10.03 sec 1.25 MBytes 381 Mbits/sec 0 1.58 MBytes
- - - - - - - - - - - - - - - - - - - - - - - - -
[ ID] Interval Transfer Bitrate Retr
[ 5] 0.00-10.03 sec 112 MBytes 94.1 Mbits/sec 0 sender

v2: comments from Stanislaw Gruszka have been addressed.

Daniel Golle (8):
rt2x00: add support for external PA on MT7620
rt2x00: don't run Rt5592 IQ calibration on MT7620
rt2x00: move helper functions up in file
rt2x00: fix HT20/HT40 bandwidth switch on MT7620
rt2x00: set correct TX_SW_CFG1 MAC register for MT7620
rt2x00: set VGC gain for both chains of MT7620
rt2x00: set SoC wmac clock register
rt2x00: correctly set BBP register 86 for MT7620

David Bauer (1):
rt2x00: add throughput LED trigger

Tomislav Požega (6):
rt2x00: define RF5592 in init_eeprom routine
rt2x00: add RF self TXDC calibration for MT7620
rt2x00: add r calibration for MT7620
rt2x00: add RXDCOC calibration for MT7620
rt2x00: add RXIQ calibration for MT7620
rt2x00: add TX LOFT calibration for MT7620

.../net/wireless/ralink/rt2x00/rt2800lib.c | 1705 ++++++++++++++++-
.../net/wireless/ralink/rt2x00/rt2800lib.h | 10 +
drivers/net/wireless/ralink/rt2x00/rt2x00.h | 5 +
.../net/wireless/ralink/rt2x00/rt2x00dev.c | 18 +
6 files changed, 1787 insertions(+), 25 deletions(-)

--
2.37.3


Daniel Golle (9):
rt2x00: add support for external PA on MT7620
rt2x00: move up and reuse busy wait functions
rt2x00: don't run Rt5592 IQ calibration on MT7620
rt2x00: move helper functions up in file
rt2x00: fix HT20/HT40 bandwidth switch on MT7620
rt2x00: set correct TX_SW_CFG1 MAC register for MT7620
rt2x00: set VGC gain for both chains of MT7620
rt2x00: set SoC wmac clock register
rt2x00: correctly set BBP register 86 for MT7620

David Bauer (1):
rt2x00: add throughput LED trigger

Tomislav Požega (6):
rt2x00: define RF5592 in init_eeprom routine
rt2x00: add RF self TXDC calibration for MT7620
rt2x00: add r calibration for MT7620
rt2x00: add RXDCOC calibration for MT7620
rt2x00: add RXIQ calibration for MT7620
rt2x00: add TX LOFT calibration for MT7620

drivers/net/wireless/ralink/rt2x00/rt2800.h | 3 +
.../net/wireless/ralink/rt2x00/rt2800lib.c | 1753 ++++++++++++++++-
.../net/wireless/ralink/rt2x00/rt2800lib.h | 10 +
.../net/wireless/ralink/rt2x00/rt2x00dev.c | 18 +
4 files changed, 1706 insertions(+), 78 deletions(-)

--
2.37.3


2022-09-17 17:04:39

by Daniel Golle

[permalink] [raw]
Subject: [PATCH v2 12/16] rt2x00: fix HT20/HT40 bandwidth switch on MT7620

Add missing configuration of the channel bandwidth filter to the
channel setup function for MT7620.

Reported-by: Serge Vasilugin <[email protected]>
Signed-off-by: Daniel Golle <[email protected]>
Acked-by: Stanislaw Gruszka <[email protected]>
---
drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 8 ++++++++
1 file changed, 8 insertions(+)

diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
index fce63feb249449..64032d342966d3 100644
--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
@@ -3855,6 +3855,14 @@ static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev,
rfcsr |= tx_agc_fc;
rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
}
+
+ if (conf_is_ht40(conf)) {
+ rt2800_bbp_glrt_write(rt2x00dev, 141, 0x10);
+ rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2f);
+ } else {
+ rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1a);
+ rt2800_bbp_glrt_write(rt2x00dev, 157, 0x40);
+ }
}

static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev,
--
2.37.3

2022-09-17 17:04:48

by Daniel Golle

[permalink] [raw]
Subject: [PATCH v2 05/16] rt2x00: add RF self TXDC calibration for MT7620

From: Tomislav Požega <[email protected]>

Add TX self calibration based on mtk driver.

Signed-off-by: Tomislav Požega <[email protected]>
Signed-off-by: Daniel Golle <[email protected]>
Acked-by: Stanislaw Gruszka <[email protected]>
---
v2: use ++i instead of i = i + 1 in loops

.../net/wireless/ralink/rt2x00/rt2800lib.c | 48 +++++++++++++++++++
1 file changed, 48 insertions(+)

diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
index cf5463cb7b642b..ed2c6105899b8d 100644
--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
@@ -8428,6 +8428,53 @@ static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
rt2800_led_open_drain_enable(rt2x00dev);
}

+static void rt2800_rf_self_txdc_cal(struct rt2x00_dev *rt2x00dev)
+{
+ u8 rfb5r1_org, rfb7r1_org, rfvalue;
+ u32 mac0518, mac051c, mac0528, mac052c;
+ u8 i;
+
+ mac0518 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
+ mac051c = rt2800_register_read(rt2x00dev, RF_BYPASS0);
+ mac0528 = rt2800_register_read(rt2x00dev, RF_CONTROL2);
+ mac052c = rt2800_register_read(rt2x00dev, RF_BYPASS2);
+
+ rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x0);
+ rt2800_register_write(rt2x00dev, RF_BYPASS2, 0x0);
+
+ rt2800_register_write(rt2x00dev, RF_CONTROL0, 0xC);
+ rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x3306);
+ rt2800_register_write(rt2x00dev, RF_CONTROL2, 0x3330);
+ rt2800_register_write(rt2x00dev, RF_BYPASS2, 0xfffff);
+ rfb5r1_org = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
+ rfb7r1_org = rt2800_rfcsr_read_bank(rt2x00dev, 7, 1);
+
+ rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, 0x4);
+ for (i = 0; i < 100; ++i) {
+ usleep_range(50, 100);
+ rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
+ if ((rfvalue & 0x04) != 0x4)
+ break;
+ }
+ rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rfb5r1_org);
+
+ rt2800_rfcsr_write_bank(rt2x00dev, 7, 1, 0x4);
+ for (i = 0; i < 100; ++i) {
+ usleep_range(50, 100);
+ rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 1);
+ if ((rfvalue & 0x04) != 0x4)
+ break;
+ }
+ rt2800_rfcsr_write_bank(rt2x00dev, 7, 1, rfb7r1_org);
+
+ rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x0);
+ rt2800_register_write(rt2x00dev, RF_BYPASS2, 0x0);
+ rt2800_register_write(rt2x00dev, RF_CONTROL0, mac0518);
+ rt2800_register_write(rt2x00dev, RF_BYPASS0, mac051c);
+ rt2800_register_write(rt2x00dev, RF_CONTROL2, mac0528);
+ rt2800_register_write(rt2x00dev, RF_BYPASS2, mac052c);
+}
+
static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
bool set_bw, bool is_ht40)
{
@@ -9035,6 +9082,7 @@ static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev)
rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);

+ rt2800_rf_self_txdc_cal(rt2x00dev);
rt2800_bw_filter_calibration(rt2x00dev, true);
rt2800_bw_filter_calibration(rt2x00dev, false);
}
--
2.37.3

2022-09-17 17:05:46

by Daniel Golle

[permalink] [raw]
Subject: [PATCH v2 15/16] rt2x00: set SoC wmac clock register

Instead of using the default value 33 (pci), set US_CYC_CNT init based
on Programming guide:
If available, set chipset bus clock with fallback to cpu clock/3.

Reported-by: Serge Vasilugin <[email protected]>
Signed-off-by: Daniel Golle <[email protected]>
Acked-by: Stanislaw Gruszka <[email protected]>
---
.../net/wireless/ralink/rt2x00/rt2800lib.c | 21 +++++++++++++++++++
1 file changed, 21 insertions(+)

diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
index a721d4833aed05..2390ffc3998826 100644
--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
@@ -6229,6 +6229,27 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
+ } else if (rt2x00_is_soc(rt2x00dev)) {
+ struct clk *clk = clk_get_sys("bus", NULL);
+ int rate;
+
+ if (IS_ERR(clk)) {
+ clk = clk_get_sys("cpu", NULL);
+
+ if (IS_ERR(clk)) {
+ rate = 125;
+ } else {
+ rate = clk_get_rate(clk) / 3000000;
+ clk_put(clk);
+ }
+ } else {
+ rate = clk_get_rate(clk) / 1000000;
+ clk_put(clk);
+ }
+
+ reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
+ rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, rate);
+ rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
}

reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0);
--
2.37.3

2022-09-17 17:05:46

by Daniel Golle

[permalink] [raw]
Subject: [PATCH v2 07/16] rt2x00: add RXDCOC calibration for MT7620

From: Tomislav Požega <[email protected]>

Add RXDCOC calibration code from mtk driver.

Signed-off-by: Tomislav Požega <[email protected]>
[fixed typo reported by Serge Vasilugin <[email protected]>]
Signed-off-by: Daniel Golle <[email protected]>
---
.../net/wireless/ralink/rt2x00/rt2800lib.c | 60 +++++++++++++++++++
1 file changed, 60 insertions(+)

diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
index df5038a59046fe..a785e6616c748a 100644
--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
@@ -8607,6 +8607,65 @@ static void rt2800_r_calibration(struct rt2x00_dev *rt2x00dev)
rt2800_register_write(rt2x00dev, PWR_PIN_CFG, MAC_PWR_PIN_CFG);
}

+static void rt2800_rxdcoc_calibration(struct rt2x00_dev *rt2x00dev)
+{
+ u8 bbpreg = 0;
+ u32 macvalue = 0;
+ u8 saverfb0r2, saverfb5r4, saverfb7r4, rfvalue;
+ int i;
+
+ saverfb0r2 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
+ rfvalue = saverfb0r2;
+ rfvalue |= 0x03;
+ rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfvalue);
+
+ rt2800_bbp_write(rt2x00dev, 158, 141);
+ bbpreg = rt2800_bbp_read(rt2x00dev, 159);
+ bbpreg |= 0x10;
+ rt2800_bbp_write(rt2x00dev, 159, bbpreg);
+
+ macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
+ rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x8);
+
+ if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
+ rt2x00_warn(rt2x00dev, "RF TX busy in RX RXDCOC calibration\n");
+
+ saverfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
+ saverfb7r4 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4);
+ saverfb5r4 = saverfb5r4 & (~0x40);
+ saverfb7r4 = saverfb7r4 & (~0x40);
+ rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x64);
+ rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r4);
+ rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, saverfb7r4);
+
+ rt2800_bbp_write(rt2x00dev, 158, 141);
+ bbpreg = rt2800_bbp_read(rt2x00dev, 159);
+ bbpreg = bbpreg & (~0x40);
+ rt2800_bbp_write(rt2x00dev, 159, bbpreg);
+ bbpreg |= 0x48;
+ rt2800_bbp_write(rt2x00dev, 159, bbpreg);
+
+ for (i = 0; i < 10000; i++) {
+ bbpreg = rt2800_bbp_read(rt2x00dev, 159);
+ if ((bbpreg & 0x40) == 0)
+ break;
+ usleep_range(50, 100);
+ }
+
+ bbpreg = rt2800_bbp_read(rt2x00dev, 159);
+ bbpreg = bbpreg & (~0x40);
+ rt2800_bbp_write(rt2x00dev, 159, bbpreg);
+
+ rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
+
+ rt2800_bbp_write(rt2x00dev, 158, 141);
+ bbpreg = rt2800_bbp_read(rt2x00dev, 159);
+ bbpreg &= (~0x10);
+ rt2800_bbp_write(rt2x00dev, 159, bbpreg);
+
+ rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, saverfb0r2);
+}
+
static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
bool set_bw, bool is_ht40)
{
@@ -9216,6 +9275,7 @@ static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev)

rt2800_r_calibration(rt2x00dev);
rt2800_rf_self_txdc_cal(rt2x00dev);
+ rt2800_rxdcoc_calibration(rt2x00dev);
rt2800_bw_filter_calibration(rt2x00dev, true);
rt2800_bw_filter_calibration(rt2x00dev, false);
}
--
2.37.3

2022-09-17 17:06:00

by Daniel Golle

[permalink] [raw]
Subject: [PATCH v2 09/16] rt2x00: don't run Rt5592 IQ calibration on MT7620

The function rt2800_iq_calibrate is intended for Rt5592 only.
Don't call it for MT7620 which has it's own calibration functions.

Reported-by: Serge Vasilugin <[email protected]>
Signed-off-by: Daniel Golle <[email protected]>
---
v2: test for RT5592 instead of !RT6352

drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
index 2dc197b508ad32..f51bf27f9f7942 100644
--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
@@ -4398,7 +4398,8 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2*rt2x00dev->lna_gain;
rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);

- rt2800_iq_calibrate(rt2x00dev, rf->channel);
+ if (rt2x00_rt(rt2x00dev, RT5592))
+ rt2800_iq_calibrate(rt2x00dev, rf->channel);
}

if (rt2x00_rt(rt2x00dev, RT6352)) {
--
2.37.3

2022-09-17 18:17:05

by Stanislaw Gruszka

[permalink] [raw]
Subject: Re: [PATCH v2 00/16] rt2x00: OpenWrt patches improving MT7620

On Sat, Sep 17, 2022 at 05:43:44PM +0100, Daniel Golle wrote:
> Over the years we have been accumulating a number of patches improving
> support for the IEEE 802.11bgn 2T2R wireless interface built into the
> MediaTek MT7620 MIPS SoCs. Many of them have not been in shape for
> being submitted to Linux and changes were needed to make checkpatch.pl
> all happy. Now they look as good as it gets, given that most code deals
> with undocumented registers and was adapted from the vendor driver.
>
> Patch 1/1 also has been previously submitted and then (imho wrongly)
> rejected, so I've included it in this series.
>
> Alltogether rt2x00 now performs almost as good as the vendor driver,
> see benchmark of HT20 client below:
>
> Accepted connection from 192.168.5.133, port 37382
> [ 5] local 192.168.5.175 port 5201 connected to 192.168.5.133 port 37384
> [ ID] Interval Transfer Bitrate
> [ 5] 0.00-1.00 sec 9.57 MBytes 80.3 Mbits/sec
> [ 5] 1.00-2.00 sec 9.68 MBytes 81.2 Mbits/sec
> [ 5] 2.00-3.00 sec 9.98 MBytes 83.7 Mbits/sec
> [ 5] 3.00-4.00 sec 9.72 MBytes 81.6 Mbits/sec
> [ 5] 4.00-5.00 sec 9.49 MBytes 79.6 Mbits/sec
> [ 5] 5.00-6.00 sec 9.88 MBytes 82.9 Mbits/sec
> [ 5] 6.00-7.00 sec 9.76 MBytes 81.8 Mbits/sec
> [ 5] 7.00-8.00 sec 9.96 MBytes 83.6 Mbits/sec
> [ 5] 8.00-9.00 sec 9.76 MBytes 81.9 Mbits/sec
> [ 5] 9.00-10.00 sec 9.86 MBytes 82.7 Mbits/sec
> [ 5] 10.00-10.03 sec 243 KBytes 78.4 Mbits/sec
> - - - - - - - - - - - - - - - - - - - - - - - - -
> [ ID] Interval Transfer Bitrate
> [ 5] 0.00-10.03 sec 97.9 MBytes 81.9 Mbits/sec receiver
>
> Accepted connection from 192.168.5.133, port 49588
> [ 5] local 192.168.5.175 port 5201 connected to 192.168.5.133 port 49598
> [ ID] Interval Transfer Bitrate Retr Cwnd
> [ 5] 0.00-1.00 sec 12.7 MBytes 106 Mbits/sec 0 557 KBytes
> [ 5] 1.00-2.00 sec 11.1 MBytes 93.0 Mbits/sec 0 1020 KBytes
> [ 5] 2.00-3.00 sec 11.2 MBytes 94.4 Mbits/sec 0 1.57 MBytes
> [ 5] 3.00-4.00 sec 11.2 MBytes 94.4 Mbits/sec 0 1.58 MBytes
> [ 5] 4.00-5.00 sec 10.0 MBytes 83.9 Mbits/sec 0 1.58 MBytes
> [ 5] 5.00-6.00 sec 11.2 MBytes 94.4 Mbits/sec 0 1.58 MBytes
> [ 5] 6.00-7.00 sec 11.2 MBytes 94.4 Mbits/sec 0 1.58 MBytes
> [ 5] 7.00-8.00 sec 10.0 MBytes 83.9 Mbits/sec 0 1.58 MBytes
> [ 5] 8.00-9.00 sec 12.5 MBytes 105 Mbits/sec 0 1.58 MBytes
> [ 5] 9.00-10.00 sec 10.0 MBytes 83.9 Mbits/sec 0 1.58 MBytes
> [ 5] 10.00-10.03 sec 1.25 MBytes 381 Mbits/sec 0 1.58 MBytes
> - - - - - - - - - - - - - - - - - - - - - - - - -
> [ ID] Interval Transfer Bitrate Retr
> [ 5] 0.00-10.03 sec 112 MBytes 94.1 Mbits/sec 0 sender
>
> v2: comments from Stanislaw Gruszka have been addressed.

For the series:
Acked-by: Stanislaw Gruszka <[email protected]>