From: Bo Jiao <[email protected]>
This adds support for mt7916 PCIe-based device, which shares the same
driver with MT7915. The maximum number of client connections is extended
to 512. mt7916 is capable of WIFI6@160MHz, simultaneous dual-band and
all WiFi6 R2 features.
Bo Jiao (11):
mt76: mt7915: add mt7915_mmio_probe() as a common probing function
mt76: mt7915: refine register definition
mt76: mt7915: rework dma.c to adapt mt7916 changes
mt76: mt7915: add firmware support for mt7916
mt76: mt7915: rework eeprom.c to adapt mt7916 changes
mt76: mt7915: enlarge wcid size to 544
mt76: mt7915: add txfree event v3
mt76: mt7915: update rx rate reporting for mt7916
mt76: mt7915: update mt7915_chan_mib_offs for mt7916
mt76: mt7915: add mt7916 calibrated data support
mt76: mt7915: add device id for mt7916
drivers/net/wireless/mediatek/mt76/dma.c | 13 +-
drivers/net/wireless/mediatek/mt76/mt76.h | 3 +-
.../wireless/mediatek/mt76/mt7915/debugfs.c | 20 +-
.../net/wireless/mediatek/mt76/mt7915/dma.c | 380 ++++++---
.../wireless/mediatek/mt76/mt7915/eeprom.c | 87 +-
.../wireless/mediatek/mt76/mt7915/eeprom.h | 9 +-
.../net/wireless/mediatek/mt76/mt7915/init.c | 141 ++--
.../net/wireless/mediatek/mt76/mt7915/mac.c | 273 ++++---
.../net/wireless/mediatek/mt76/mt7915/mac.h | 14 +-
.../net/wireless/mediatek/mt76/mt7915/main.c | 11 +-
.../net/wireless/mediatek/mt76/mt7915/mcu.c | 101 ++-
.../net/wireless/mediatek/mt76/mt7915/mcu.h | 8 +-
.../net/wireless/mediatek/mt76/mt7915/mmio.c | 757 ++++++++++++++++--
.../wireless/mediatek/mt76/mt7915/mt7915.h | 37 +-
.../net/wireless/mediatek/mt76/mt7915/pci.c | 243 +-----
.../net/wireless/mediatek/mt76/mt7915/regs.h | 672 +++++++++++-----
.../wireless/mediatek/mt76/mt7915/testmode.c | 58 +-
17 files changed, 1950 insertions(+), 877 deletions(-)
--
2.18.0
From: Bo Jiao <[email protected]>
Update firmware initialization for mt7916.
This is an intermediate patch to add mt7916 support.
Co-developed-by: Sujuan Chen <[email protected]>
Signed-off-by: Sujuan Chen <[email protected]>
Co-developed-by: Ryder Lee <[email protected]>
Signed-off-by: Ryder Lee <[email protected]>
Signed-off-by: Bo Jiao <[email protected]>
---
v3:
- modify the function mt7915_wfsys_reset to support mt7916
---
.../net/wireless/mediatek/mt76/mt7915/init.c | 71 ++++++++--------
.../net/wireless/mediatek/mt76/mt7915/mcu.c | 81 ++++++++++++++-----
.../wireless/mediatek/mt76/mt7915/mt7915.h | 4 +
.../net/wireless/mediatek/mt76/mt7915/pci.c | 3 +
.../net/wireless/mediatek/mt76/mt7915/regs.h | 7 +-
5 files changed, 114 insertions(+), 52 deletions(-)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/init.c b/drivers/net/wireless/mediatek/mt76/mt7915/init.c
index 21f1337..324263e 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/init.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/init.c
@@ -507,41 +507,52 @@ static void mt7915_init_work(struct work_struct *work)
static void mt7915_wfsys_reset(struct mt7915_dev *dev)
{
- u32 val = MT_TOP_PWR_KEY | MT_TOP_PWR_SW_PWR_ON | MT_TOP_PWR_PWR_ON;
+ u32 val;
#define MT_MCU_DUMMY_RANDOM GENMASK(15, 0)
#define MT_MCU_DUMMY_DEFAULT GENMASK(31, 16)
+ if (is_mt7915(&dev->mt76)) {
+ mt76_wr(dev, MT_MCU_WFDMA0_DUMMY_CR, MT_MCU_DUMMY_RANDOM);
+
+ /* change to software control */
+ val |= MT_TOP_PWR_SW_RST;
+ mt76_wr(dev, MT_TOP_PWR_CTRL, val);
+
+ /* reset wfsys */
+ val &= ~MT_TOP_PWR_SW_RST;
+ mt76_wr(dev, MT_TOP_PWR_CTRL, val);
+
+ /* release wfsys then mcu re-excutes romcode */
+ val |= MT_TOP_PWR_SW_RST;
+ mt76_wr(dev, MT_TOP_PWR_CTRL, val);
+
+ /* switch to hw control */
+ val &= ~MT_TOP_PWR_SW_RST;
+ val |= MT_TOP_PWR_HW_CTRL;
+ mt76_wr(dev, MT_TOP_PWR_CTRL, val);
+
+ /* check whether mcu resets to default */
+ if (!mt76_poll_msec(dev, MT_MCU_WFDMA0_DUMMY_CR, MT_MCU_DUMMY_DEFAULT,
+ MT_MCU_DUMMY_DEFAULT, 1000)) {
+ dev_err(dev->mt76.dev, "wifi subsystem reset failure\n");
+ return;
+ }
- mt76_wr(dev, MT_MCU_WFDMA0_DUMMY_CR, MT_MCU_DUMMY_RANDOM);
-
- /* change to software control */
- val |= MT_TOP_PWR_SW_RST;
- mt76_wr(dev, MT_TOP_PWR_CTRL, val);
-
- /* reset wfsys */
- val &= ~MT_TOP_PWR_SW_RST;
- mt76_wr(dev, MT_TOP_PWR_CTRL, val);
+ /* wfsys reset won't clear host registers */
+ mt76_clear(dev, MT_TOP_MISC, MT_TOP_MISC_FW_STATE);
- /* release wfsys then mcu re-excutes romcode */
- val |= MT_TOP_PWR_SW_RST;
- mt76_wr(dev, MT_TOP_PWR_CTRL, val);
+ msleep(100);
+ } else {
+ val = mt76_rr(dev, MT_WF_SUBSYS_RST);
- /* switch to hw control */
- val &= ~MT_TOP_PWR_SW_RST;
- val |= MT_TOP_PWR_HW_CTRL;
- mt76_wr(dev, MT_TOP_PWR_CTRL, val);
+ val |= 0x1;
+ mt76_wr(dev, MT_WF_SUBSYS_RST, val);
+ msleep(20);
- /* check whether mcu resets to default */
- if (!mt76_poll_msec(dev, MT_MCU_WFDMA0_DUMMY_CR, MT_MCU_DUMMY_DEFAULT,
- MT_MCU_DUMMY_DEFAULT, 1000)) {
- dev_err(dev->mt76.dev, "wifi subsystem reset failure\n");
- return;
+ val &= ~0x1;
+ mt76_wr(dev, MT_WF_SUBSYS_RST, val);
+ msleep(20);
}
-
- /* wfsys reset won't clear host registers */
- mt76_clear(dev, MT_TOP_MISC, MT_TOP_MISC_FW_STATE);
-
- msleep(100);
}
static int mt7915_init_hardware(struct mt7915_dev *dev)
@@ -564,12 +575,6 @@ static int mt7915_init_hardware(struct mt7915_dev *dev)
set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state);
- /*
- * force firmware operation mode into normal state,
- * which should be set before firmware download stage.
- */
- mt76_wr(dev, MT_SWDEF_MODE, MT_SWDEF_NORMAL_MODE);
-
ret = mt7915_mcu_init(dev);
if (ret) {
/* Reset and try again */
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mcu.c b/drivers/net/wireless/mediatek/mt76/mt7915/mcu.c
index 7bb6443..fd1df7e 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mcu.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mcu.c
@@ -2676,15 +2676,20 @@ static int mt7915_mcu_start_patch(struct mt7915_dev *dev)
sizeof(req), true);
}
-static int mt7915_driver_own(struct mt7915_dev *dev)
+static int mt7915_driver_own(struct mt7915_dev *dev, u8 band)
{
- mt76_wr(dev, MT_TOP_LPCR_HOST_BAND0, MT_TOP_LPCR_HOST_DRV_OWN);
- if (!mt76_poll_msec(dev, MT_TOP_LPCR_HOST_BAND0,
- MT_TOP_LPCR_HOST_FW_OWN, 0, 500)) {
+ mt76_wr(dev, MT_TOP_LPCR_HOST_BAND(band), MT_TOP_LPCR_HOST_DRV_OWN);
+ if (!mt76_poll_msec(dev, MT_TOP_LPCR_HOST_BAND(band),
+ MT_TOP_LPCR_HOST_FW_OWN_STAT,
+ 0, 500)) {
dev_err(dev->mt76.dev, "Timeout for driver own\n");
return -EIO;
}
+ /* clear irq when the driver own success */
+ mt76_wr(dev, MT_TOP_LPCR_HOST_BAND_IRQ_STAT(band),
+ MT_TOP_LPCR_HOST_BAND_STAT);
+
return 0;
}
@@ -2714,6 +2719,7 @@ static int mt7915_load_patch(struct mt7915_dev *dev)
{
const struct mt7915_patch_hdr *hdr;
const struct firmware *fw = NULL;
+ const char *patch;
int i, ret, sem;
sem = mt7915_mcu_patch_sem_ctrl(dev, 1);
@@ -2727,7 +2733,8 @@ static int mt7915_load_patch(struct mt7915_dev *dev)
return -EAGAIN;
}
- ret = request_firmware(&fw, MT7915_ROM_PATCH, dev->mt76.dev);
+ patch = is_mt7915(&dev->mt76) ? MT7915_ROM_PATCH : MT7916_ROM_PATCH;
+ ret = request_firmware(&fw, patch, dev->mt76.dev);
if (ret)
goto out;
@@ -2858,9 +2865,11 @@ static int mt7915_load_ram(struct mt7915_dev *dev)
{
const struct mt7915_fw_trailer *hdr;
const struct firmware *fw;
+ const char *mcu;
int ret;
- ret = request_firmware(&fw, MT7915_FIRMWARE_WM, dev->mt76.dev);
+ mcu = is_mt7915(&dev->mt76) ? MT7915_FIRMWARE_WM : MT7916_FIRMWARE_WM;
+ ret = request_firmware(&fw, mcu, dev->mt76.dev);
if (ret)
return ret;
@@ -2884,7 +2893,8 @@ static int mt7915_load_ram(struct mt7915_dev *dev)
release_firmware(fw);
- ret = request_firmware(&fw, MT7915_FIRMWARE_WA, dev->mt76.dev);
+ mcu = is_mt7915(&dev->mt76) ? MT7915_FIRMWARE_WA : MT7916_FIRMWARE_WA;
+ ret = request_firmware(&fw, mcu, dev->mt76.dev);
if (ret)
return ret;
@@ -2916,10 +2926,36 @@ out:
return ret;
}
+static int
+mt7915_firmware_state(struct mt7915_dev *dev, bool wa)
+{
+ u32 state = FIELD_PREP(MT_TOP_MISC_FW_STATE,
+ wa ? FW_STATE_WACPU_RDY : FW_STATE_FW_DOWNLOAD);
+
+ if (!mt76_poll_msec(dev, MT_TOP_MISC, MT_TOP_MISC_FW_STATE,
+ state, 1000)) {
+ dev_err(dev->mt76.dev, "Timeout for initializing firmware\n");
+ return -EIO;
+ }
+ return 0;
+}
+
static int mt7915_load_firmware(struct mt7915_dev *dev)
{
int ret;
+ /* make sure fw is download state */
+ if (mt7915_firmware_state(dev, false)) {
+ /* restart firmware once */
+ __mt76_mcu_restart(&dev->mt76);
+ ret = mt7915_firmware_state(dev, false);
+ if (ret) {
+ dev_err(dev->mt76.dev,
+ "Firmware is not ready for download\n");
+ return ret;
+ }
+ }
+
ret = mt7915_load_patch(dev);
if (ret)
return ret;
@@ -2928,12 +2964,9 @@ static int mt7915_load_firmware(struct mt7915_dev *dev)
if (ret)
return ret;
- if (!mt76_poll_msec(dev, MT_TOP_MISC, MT_TOP_MISC_FW_STATE,
- FIELD_PREP(MT_TOP_MISC_FW_STATE,
- FW_STATE_WACPU_RDY), 1000)) {
- dev_err(dev->mt76.dev, "Timeout for initializing firmware\n");
- return -EIO;
- }
+ ret = mt7915_firmware_state(dev, true);
+ if (ret)
+ return ret;
mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_FWDL], false);
@@ -3058,9 +3091,20 @@ int mt7915_mcu_init(struct mt7915_dev *dev)
dev->mt76.mcu_ops = &mt7915_mcu_ops;
- ret = mt7915_driver_own(dev);
+ /* force firmware operation mode into normal state,
+ * which should be set before firmware download stage.
+ */
+ mt76_wr(dev, MT_SWDEF_MODE, MT_SWDEF_NORMAL_MODE);
+
+ ret = mt7915_driver_own(dev, 0);
if (ret)
return ret;
+ /* set driver own for band1 when two hif exist */
+ if (dev->hif2) {
+ ret = mt7915_driver_own(dev, 1);
+ if (ret)
+ return ret;
+ }
ret = mt7915_load_firmware(dev);
if (ret)
@@ -3095,14 +3139,15 @@ int mt7915_mcu_init(struct mt7915_dev *dev)
void mt7915_mcu_exit(struct mt7915_dev *dev)
{
__mt76_mcu_restart(&dev->mt76);
- if (!mt76_poll_msec(dev, MT_TOP_MISC, MT_TOP_MISC_FW_STATE,
- FIELD_PREP(MT_TOP_MISC_FW_STATE,
- FW_STATE_FW_DOWNLOAD), 1000)) {
+ if (mt7915_firmware_state(dev, false)) {
dev_err(dev->mt76.dev, "Failed to exit mcu\n");
return;
}
- mt76_wr(dev, MT_TOP_LPCR_HOST_BAND0, MT_TOP_LPCR_HOST_FW_OWN);
+ mt76_wr(dev, MT_TOP_LPCR_HOST_BAND(0), MT_TOP_LPCR_HOST_FW_OWN);
+ if (dev->hif2)
+ mt76_wr(dev, MT_TOP_LPCR_HOST_BAND(1),
+ MT_TOP_LPCR_HOST_FW_OWN);
skb_queue_purge(&dev->mt76.mcu.res_q);
}
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
index 8adb069..cee719f 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
@@ -30,6 +30,10 @@
#define MT7915_FIRMWARE_WM "mediatek/mt7915_wm.bin"
#define MT7915_ROM_PATCH "mediatek/mt7915_rom_patch.bin"
+#define MT7916_FIRMWARE_WA "mediatek/mt7916_wa.bin"
+#define MT7916_FIRMWARE_WM "mediatek/mt7916_wm.bin"
+#define MT7916_ROM_PATCH "mediatek/mt7916_rom_patch.bin"
+
#define MT7915_EEPROM_DEFAULT "mediatek/mt7915_eeprom.bin"
#define MT7915_EEPROM_DEFAULT_DBDC "mediatek/mt7915_eeprom_dbdc.bin"
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/pci.c b/drivers/net/wireless/mediatek/mt76/mt7915/pci.c
index 2aba79a..3134b46 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/pci.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/pci.c
@@ -168,3 +168,6 @@ MODULE_DEVICE_TABLE(pci, mt7915_hif_device_table);
MODULE_FIRMWARE(MT7915_FIRMWARE_WA);
MODULE_FIRMWARE(MT7915_FIRMWARE_WM);
MODULE_FIRMWARE(MT7915_ROM_PATCH);
+MODULE_FIRMWARE(MT7916_FIRMWARE_WA);
+MODULE_FIRMWARE(MT7916_FIRMWARE_WM);
+MODULE_FIRMWARE(MT7916_ROM_PATCH);
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/regs.h b/drivers/net/wireless/mediatek/mt76/mt7915/regs.h
index 0105cc4..1ac5b2a 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/regs.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/regs.h
@@ -787,9 +787,13 @@ enum bit_rev {
#define MT_TOP_BASE 0x18060000
#define MT_TOP(ofs) (MT_TOP_BASE + (ofs))
-#define MT_TOP_LPCR_HOST_BAND0 MT_TOP(0x10)
+#define MT_TOP_LPCR_HOST_BAND(_band) MT_TOP(0x10 + ((_band) * 0x10))
#define MT_TOP_LPCR_HOST_FW_OWN BIT(0)
#define MT_TOP_LPCR_HOST_DRV_OWN BIT(1)
+#define MT_TOP_LPCR_HOST_FW_OWN_STAT BIT(2)
+
+#define MT_TOP_LPCR_HOST_BAND_IRQ_STAT(_band) MT_TOP(0x14 + ((_band) * 0x10))
+#define MT_TOP_LPCR_HOST_BAND_STAT BIT(0)
#define MT_TOP_MISC MT_TOP(0xf0)
#define MT_TOP_MISC_FW_STATE GENMASK(2, 0)
@@ -797,6 +801,7 @@ enum bit_rev {
#define MT_HW_BOUND 0x70010020
#define MT_HW_CHIPID 0x70010200
#define MT_HW_REV 0x70010204
+#define MT_WF_SUBSYS_RST 0x70002600
/* PCIE MAC */
#define MT_PCIE_MAC(ofs) __REG_MAP(dev, MT_PCIE_MAC_BASE, (ofs))
--
2.18.0
From: Bo Jiao <[email protected]>
The mt7916 can support up to 544 wcid entries.
This is an intermediate patch to add mt7916 support.
Co-developed-by: Sujuan Chen <[email protected]>
Signed-off-by: Sujuan Chen <[email protected]>
Co-developed-by: Ryder Lee <[email protected]>
Signed-off-by: Ryder Lee <[email protected]>
Signed-off-by: Bo Jiao <[email protected]>
---
drivers/net/wireless/mediatek/mt76/mt76.h | 2 +-
drivers/net/wireless/mediatek/mt76/mt7915/init.c | 2 +-
drivers/net/wireless/mediatek/mt76/mt7915/mac.c | 2 +-
drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h | 8 +++++++-
4 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/net/wireless/mediatek/mt76/mt76.h b/drivers/net/wireless/mediatek/mt76/mt76.h
index 8fd6890..814ed21 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76.h
+++ b/drivers/net/wireless/mediatek/mt76/mt76.h
@@ -225,7 +225,7 @@ enum mt76_wcid_flags {
MT_WCID_FLAG_HDR_TRANS,
};
-#define MT76_N_WCIDS 288
+#define MT76_N_WCIDS 544
/* stored in ieee80211_tx_info::hw_queue */
#define MT_TX_HW_QUEUE_EXT_PHY BIT(3)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/init.c b/drivers/net/wireless/mediatek/mt76/mt7915/init.c
index c2eae36..1b8a47c 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/init.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/init.c
@@ -427,7 +427,7 @@ static void mt7915_mac_init(struct mt7915_dev *dev)
/* enable hardware de-agg */
mt76_set(dev, MT_MDP_DCR0, MT_MDP_DCR0_DAMSDU_EN);
- for (i = 0; i < MT7915_WTBL_SIZE; i++)
+ for (i = 0; i < mt7915_wtbl_size(dev); i++)
mt7915_mac_wtbl_update(dev, i,
MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
for (i = 0; i < 2; i++)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
index 311d17d..40e8252 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
@@ -1576,7 +1576,7 @@ static void mt7915_mac_add_txs(struct mt7915_dev *dev, void *data)
if (pid < MT_PACKET_ID_FIRST)
return;
- if (wcidx >= MT7915_WTBL_SIZE)
+ if (wcidx >= mt7915_wtbl_size(dev))
return;
rcu_read_lock();
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
index 3e2e900..e8fbe69 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
@@ -12,7 +12,8 @@
#define MT7915_MAX_INTERFACES 19
#define MT7915_MAX_WMM_SETS 4
#define MT7915_WTBL_SIZE 288
-#define MT7915_WTBL_RESERVED (MT7915_WTBL_SIZE - 1)
+#define MT7916_WTBL_SIZE 544
+#define MT7915_WTBL_RESERVED (mt7915_wtbl_size(dev) - 1)
#define MT7915_WTBL_STA (MT7915_WTBL_RESERVED - \
MT7915_MAX_INTERFACES)
@@ -477,6 +478,11 @@ static inline bool is_mt7915(struct mt76_dev *dev)
return mt76_chip(dev) == 0x7915;
}
+static inline u16 mt7915_wtbl_size(struct mt7915_dev *dev)
+{
+ return is_mt7915(&dev->mt76) ? MT7915_WTBL_SIZE : MT7916_WTBL_SIZE;
+}
+
void mt7915_dual_hif_set_irq_mask(struct mt7915_dev *dev, bool write_reg,
u32 clear, u32 set);
--
2.18.0
From: Bo Jiao <[email protected]>
Add mt7915_mmio_probe() which will be used for the upcoming devices.
This is an intermediate patch to add mt7916 support.
Co-developed-by: Sujuan Chen <[email protected]>
Signed-off-by: Sujuan Chen <[email protected]>
Co-developed-by: Ryder Lee <[email protected]>
Signed-off-by: Ryder Lee <[email protected]>
Signed-off-by: Bo Jiao <[email protected]>
---
.../net/wireless/mediatek/mt76/mt7915/mmio.c | 232 ++++++++++++++++-
.../wireless/mediatek/mt76/mt7915/mt7915.h | 7 +-
.../net/wireless/mediatek/mt76/mt7915/pci.c | 233 ++----------------
3 files changed, 255 insertions(+), 217 deletions(-)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mmio.c b/drivers/net/wireless/mediatek/mt76/mt7915/mmio.c
index 1f6ba30..2f8b72b 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mmio.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mmio.c
@@ -1,7 +1,14 @@
// SPDX-License-Identifier: ISC
/* Copyright (C) 2020 MediaTek Inc. */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+
#include "mt7915.h"
+#include "mac.h"
+#include "../trace.h"
static u32 mt7915_reg_map_l1(struct mt7915_dev *dev, u32 addr)
{
@@ -125,7 +132,9 @@ static u32 mt7915_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
return dev->bus_ops->rmw(mdev, addr, mask, val);
}
-int mt7915_mmio_init(struct mt76_dev *mdev, void __iomem *mem_base, int irq)
+static int mt7915_mmio_init(struct mt76_dev *mdev,
+ void __iomem *mem_base,
+ u32 device_id)
{
struct mt76_bus_ops *bus_ops;
struct mt7915_dev *dev;
@@ -148,7 +157,228 @@ int mt7915_mmio_init(struct mt76_dev *mdev, void __iomem *mem_base, int irq)
(mt76_rr(dev, MT_HW_REV) & 0xff);
dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
+ return 0;
+}
+
+void mt7915_dual_hif_set_irq_mask(struct mt7915_dev *dev,
+ bool write_reg,
+ u32 clear, u32 set)
+{
+ struct mt76_dev *mdev = &dev->mt76;
+ unsigned long flags;
+
+ spin_lock_irqsave(&mdev->mmio.irq_lock, flags);
+
+ mdev->mmio.irqmask &= ~clear;
+ mdev->mmio.irqmask |= set;
+
+ if (write_reg) {
+ mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask);
+ mt76_wr(dev, MT_INT1_MASK_CSR, mdev->mmio.irqmask);
+ }
+
+ spin_unlock_irqrestore(&mdev->mmio.irq_lock, flags);
+}
+
+static void mt7915_rx_poll_complete(struct mt76_dev *mdev,
+ enum mt76_rxq_id q)
+{
+ struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
+ static const u32 rx_irq_mask[] = {
+ [MT_RXQ_MAIN] = MT_INT_RX_DONE_DATA0,
+ [MT_RXQ_EXT] = MT_INT_RX_DONE_DATA1,
+ [MT_RXQ_MCU] = MT_INT_RX_DONE_WM,
+ [MT_RXQ_MCU_WA] = MT_INT_RX_DONE_WA,
+ [MT_RXQ_EXT_WA] = MT_INT_RX_DONE_WA_EXT,
+ };
+
+ mt7915_irq_enable(dev, rx_irq_mask[q]);
+}
+
+/* TODO: support 2/4/6/8 MSI-X vectors */
+static void mt7915_irq_tasklet(struct tasklet_struct *t)
+{
+ struct mt7915_dev *dev = from_tasklet(dev, t, irq_tasklet);
+ u32 intr, intr1, mask;
+
mt76_wr(dev, MT_INT_MASK_CSR, 0);
+ if (dev->hif2)
+ mt76_wr(dev, MT_INT1_MASK_CSR, 0);
+
+ intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
+ intr &= dev->mt76.mmio.irqmask;
+ mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
+
+ if (dev->hif2) {
+ intr1 = mt76_rr(dev, MT_INT1_SOURCE_CSR);
+ intr1 &= dev->mt76.mmio.irqmask;
+ mt76_wr(dev, MT_INT1_SOURCE_CSR, intr1);
+
+ intr |= intr1;
+ }
+
+ trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
+
+ mask = intr & MT_INT_RX_DONE_ALL;
+ if (intr & MT_INT_TX_DONE_MCU)
+ mask |= MT_INT_TX_DONE_MCU;
+
+ mt7915_irq_disable(dev, mask);
+
+ if (intr & MT_INT_TX_DONE_MCU)
+ napi_schedule(&dev->mt76.tx_napi);
+
+ if (intr & MT_INT_RX_DONE_DATA0)
+ napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]);
+
+ if (intr & MT_INT_RX_DONE_DATA1)
+ napi_schedule(&dev->mt76.napi[MT_RXQ_EXT]);
+
+ if (intr & MT_INT_RX_DONE_WM)
+ napi_schedule(&dev->mt76.napi[MT_RXQ_MCU]);
+
+ if (intr & MT_INT_RX_DONE_WA)
+ napi_schedule(&dev->mt76.napi[MT_RXQ_MCU_WA]);
+
+ if (intr & MT_INT_RX_DONE_WA_EXT)
+ napi_schedule(&dev->mt76.napi[MT_RXQ_EXT_WA]);
+
+ if (intr & MT_INT_MCU_CMD) {
+ u32 val = mt76_rr(dev, MT_MCU_CMD);
+
+ mt76_wr(dev, MT_MCU_CMD, val);
+ if (val & MT_MCU_CMD_ERROR_MASK) {
+ dev->reset_state = val;
+ ieee80211_queue_work(mt76_hw(dev), &dev->reset_work);
+ wake_up(&dev->reset_wait);
+ }
+ }
+}
+
+static irqreturn_t mt7915_irq_handler(int irq, void *dev_instance)
+{
+ struct mt7915_dev *dev = dev_instance;
+
+ mt76_wr(dev, MT_INT_MASK_CSR, 0);
+ if (dev->hif2)
+ mt76_wr(dev, MT_INT1_MASK_CSR, 0);
+
+ if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
+ return IRQ_NONE;
+
+ tasklet_schedule(&dev->irq_tasklet);
+
+ return IRQ_HANDLED;
+}
+
+int mt7915_mmio_probe(struct device *pdev,
+ void __iomem *mem_base,
+ u32 device_id,
+ int irq, struct mt7915_hif *hif2)
+{
+ static const struct mt76_driver_ops drv_ops = {
+ /* txwi_size = txd size + txp size */
+ .txwi_size = MT_TXD_SIZE + sizeof(struct mt7915_txp),
+ .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ,
+ .survey_flags = SURVEY_INFO_TIME_TX |
+ SURVEY_INFO_TIME_RX |
+ SURVEY_INFO_TIME_BSS_RX,
+ .token_size = MT7915_TOKEN_SIZE,
+ .tx_prepare_skb = mt7915_tx_prepare_skb,
+ .tx_complete_skb = mt7915_tx_complete_skb,
+ .rx_skb = mt7915_queue_rx_skb,
+ .rx_poll_complete = mt7915_rx_poll_complete,
+ .sta_ps = mt7915_sta_ps,
+ .sta_add = mt7915_mac_sta_add,
+ .sta_remove = mt7915_mac_sta_remove,
+ .update_survey = mt7915_update_channel,
+ };
+ struct ieee80211_ops *ops;
+ struct mt7915_dev *dev;
+ struct mt76_dev *mdev;
+ int ret;
+
+ ops = devm_kmemdup(pdev, &mt7915_ops, sizeof(mt7915_ops), GFP_KERNEL);
+ if (!ops)
+ return -ENOMEM;
+
+ mdev = mt76_alloc_device(pdev, sizeof(*dev), ops, &drv_ops);
+ if (!mdev)
+ return -ENOMEM;
+
+ dev = container_of(mdev, struct mt7915_dev, mt76);
+
+ ret = mt7915_mmio_init(mdev, mem_base, device_id);
+ if (ret)
+ goto error;
+
+ tasklet_setup(&dev->irq_tasklet, mt7915_irq_tasklet);
+
+ mt76_wr(dev, MT_INT_MASK_CSR, 0);
+ /* master switch of PCIe tnterrupt enable */
+ if (dev_is_pci(pdev))
+ mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
+
+ ret = devm_request_irq(mdev->dev, irq, mt7915_irq_handler,
+ IRQF_SHARED, KBUILD_MODNAME, dev);
+ if (ret)
+ goto error;
+
+ if (hif2) {
+ dev->hif2 = hif2;
+
+ mt76_wr(dev, MT_INT1_MASK_CSR, 0);
+ /* master switch of PCIe tnterrupt enable */
+ if (dev_is_pci(pdev))
+ mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE, 0xff);
+
+ ret = devm_request_irq(mdev->dev, dev->hif2->irq,
+ mt7915_irq_handler, IRQF_SHARED,
+ KBUILD_MODNAME "-hif", dev);
+ if (ret) {
+ put_device(dev->hif2->dev);
+ goto free_irq;
+ }
+ }
+
+ ret = mt7915_register_device(dev);
+ if (ret)
+ goto free_hif2_irq;
return 0;
+
+free_hif2_irq:
+ if (dev->hif2)
+ devm_free_irq(mdev->dev, dev->hif2->irq, dev);
+free_irq:
+ devm_free_irq(mdev->dev, irq, dev);
+error:
+ mt76_free_device(&dev->mt76);
+
+ return ret;
}
+
+static int __init mt7915_init(void)
+{
+ int ret;
+
+ ret = pci_register_driver(&mt7915_hif_driver);
+ if (ret)
+ return ret;
+
+ ret = pci_register_driver(&mt7915_pci_driver);
+ if (ret)
+ pci_unregister_driver(&mt7915_hif_driver);
+
+ return ret;
+}
+
+static void __exit mt7915_exit(void)
+{
+ pci_unregister_driver(&mt7915_pci_driver);
+ pci_unregister_driver(&mt7915_hif_driver);
+}
+
+module_init(mt7915_init);
+module_exit(mt7915_exit);
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
index c6c846d..05a28c2 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
@@ -369,7 +369,13 @@ static inline u8 mt7915_lmac_mapping(struct mt7915_dev *dev, u8 ac)
extern const struct ieee80211_ops mt7915_ops;
extern const struct mt76_testmode_ops mt7915_testmode_ops;
+extern struct pci_driver mt7915_pci_driver;
+extern struct pci_driver mt7915_hif_driver;
+int mt7915_mmio_probe(struct device *pdev,
+ void __iomem *mem_base,
+ u32 device_id,
+ int irq, struct mt7915_hif *hif2);
u32 mt7915_reg_map(struct mt7915_dev *dev, u32 addr);
u64 __mt7915_get_tsf(struct ieee80211_hw *hw, struct mt7915_vif *mvif);
int mt7915_register_device(struct mt7915_dev *dev);
@@ -503,7 +509,6 @@ void mt7915_mac_work(struct work_struct *work);
void mt7915_mac_reset_work(struct work_struct *work);
void mt7915_mac_sta_rc_work(struct work_struct *work);
void mt7915_mac_update_stats(struct mt7915_phy *phy);
-int mt7915_mmio_init(struct mt76_dev *mdev, void __iomem *mem_base, int irq);
void mt7915_mac_twt_teardown_flow(struct mt7915_dev *dev,
struct mt7915_sta *msta,
u8 flowid);
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/pci.c b/drivers/net/wireless/mediatek/mt76/mt7915/pci.c
index 0af4cdb..2aba79a 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/pci.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/pci.c
@@ -26,27 +26,7 @@ static const struct pci_device_id mt7915_hif_device_table[] = {
{ },
};
-void mt7915_dual_hif_set_irq_mask(struct mt7915_dev *dev, bool write_reg,
- u32 clear, u32 set)
-{
- struct mt76_dev *mdev = &dev->mt76;
- unsigned long flags;
-
- spin_lock_irqsave(&mdev->mmio.irq_lock, flags);
-
- mdev->mmio.irqmask &= ~clear;
- mdev->mmio.irqmask |= set;
-
- if (write_reg) {
- mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask);
- mt76_wr(dev, MT_INT1_MASK_CSR, mdev->mmio.irqmask);
- }
-
- spin_unlock_irqrestore(&mdev->mmio.irq_lock, flags);
-}
-
-static struct mt7915_hif *
-mt7915_pci_get_hif2(struct mt7915_dev *dev)
+static struct mt7915_hif *mt7915_pci_get_hif2(u32 idx)
{
struct mt7915_hif *hif;
u32 val;
@@ -56,7 +36,7 @@ mt7915_pci_get_hif2(struct mt7915_dev *dev)
list_for_each_entry(hif, &hif_list, list) {
val = readl(hif->regs + MT_PCIE_RECOG_ID);
val &= MT_PCIE_RECOG_ID_MASK;
- if (val != dev->hif_idx)
+ if (val != idx)
continue;
get_device(hif->dev);
@@ -78,123 +58,16 @@ static void mt7915_put_hif2(struct mt7915_hif *hif)
put_device(hif->dev);
}
-static void
-mt7915_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q)
-{
- struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
- static const u32 rx_irq_mask[] = {
- [MT_RXQ_MAIN] = MT_INT_RX_DONE_DATA0,
- [MT_RXQ_EXT] = MT_INT_RX_DONE_DATA1,
- [MT_RXQ_MCU] = MT_INT_RX_DONE_WM,
- [MT_RXQ_MCU_WA] = MT_INT_RX_DONE_WA,
- [MT_RXQ_EXT_WA] = MT_INT_RX_DONE_WA_EXT,
- };
-
- mt7915_irq_enable(dev, rx_irq_mask[q]);
-}
-
-/* TODO: support 2/4/6/8 MSI-X vectors */
-static void mt7915_irq_tasklet(struct tasklet_struct *t)
-{
- struct mt7915_dev *dev = from_tasklet(dev, t, irq_tasklet);
- u32 intr, intr1, mask;
-
- mt76_wr(dev, MT_INT_MASK_CSR, 0);
- if (dev->hif2)
- mt76_wr(dev, MT_INT1_MASK_CSR, 0);
-
- intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
- intr &= dev->mt76.mmio.irqmask;
- mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
-
- if (dev->hif2) {
- intr1 = mt76_rr(dev, MT_INT1_SOURCE_CSR);
- intr1 &= dev->mt76.mmio.irqmask;
- mt76_wr(dev, MT_INT1_SOURCE_CSR, intr1);
-
- intr |= intr1;
- }
-
- trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
-
- mask = intr & MT_INT_RX_DONE_ALL;
- if (intr & MT_INT_TX_DONE_MCU)
- mask |= MT_INT_TX_DONE_MCU;
-
- mt7915_irq_disable(dev, mask);
-
- if (intr & MT_INT_TX_DONE_MCU)
- napi_schedule(&dev->mt76.tx_napi);
-
- if (intr & MT_INT_RX_DONE_DATA0)
- napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]);
-
- if (intr & MT_INT_RX_DONE_DATA1)
- napi_schedule(&dev->mt76.napi[MT_RXQ_EXT]);
-
- if (intr & MT_INT_RX_DONE_WM)
- napi_schedule(&dev->mt76.napi[MT_RXQ_MCU]);
-
- if (intr & MT_INT_RX_DONE_WA)
- napi_schedule(&dev->mt76.napi[MT_RXQ_MCU_WA]);
-
- if (intr & MT_INT_RX_DONE_WA_EXT)
- napi_schedule(&dev->mt76.napi[MT_RXQ_EXT_WA]);
-
- if (intr & MT_INT_MCU_CMD) {
- u32 val = mt76_rr(dev, MT_MCU_CMD);
-
- mt76_wr(dev, MT_MCU_CMD, val);
- if (val & MT_MCU_CMD_ERROR_MASK) {
- dev->reset_state = val;
- ieee80211_queue_work(mt76_hw(dev), &dev->reset_work);
- wake_up(&dev->reset_wait);
- }
- }
-}
-
-static irqreturn_t mt7915_irq_handler(int irq, void *dev_instance)
-{
- struct mt7915_dev *dev = dev_instance;
-
- mt76_wr(dev, MT_INT_MASK_CSR, 0);
- if (dev->hif2)
- mt76_wr(dev, MT_INT1_MASK_CSR, 0);
-
- if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
- return IRQ_NONE;
-
- tasklet_schedule(&dev->irq_tasklet);
-
- return IRQ_HANDLED;
-}
-
-static void mt7915_pci_init_hif2(struct mt7915_dev *dev)
+static struct mt7915_hif *mt7915_pci_init_hif2(struct pci_dev *pdev)
{
- struct mt7915_hif *hif;
-
- dev->hif_idx = ++hif_idx;
+ hif_idx++;
if (!pci_get_device(PCI_VENDOR_ID_MEDIATEK, 0x7916, NULL))
- return;
-
- mt76_wr(dev, MT_PCIE_RECOG_ID, dev->hif_idx | MT_PCIE_RECOG_ID_SEM);
-
- hif = mt7915_pci_get_hif2(dev);
- if (!hif)
- return;
+ return NULL;
- dev->hif2 = hif;
+ writel(hif_idx | MT_PCIE_RECOG_ID_SEM,
+ pcim_iomap_table(pdev)[0] + MT_PCIE_RECOG_ID);
- mt76_wr(dev, MT_INT1_MASK_CSR, 0);
-
- if (devm_request_irq(dev->mt76.dev, hif->irq, mt7915_irq_handler,
- IRQF_SHARED, KBUILD_MODNAME "-hif", dev)) {
- mt7915_put_hif2(hif);
- hif = NULL;
- }
-
- /* master switch of PCIe tnterrupt enable */
- mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE, 0xff);
+ return mt7915_pci_get_hif2(hif_idx);
}
static int mt7915_pci_hif2_probe(struct pci_dev *pdev)
@@ -219,25 +92,8 @@ static int mt7915_pci_hif2_probe(struct pci_dev *pdev)
static int mt7915_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
- static const struct mt76_driver_ops drv_ops = {
- /* txwi_size = txd size + txp size */
- .txwi_size = MT_TXD_SIZE + sizeof(struct mt7915_txp),
- .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ,
- .survey_flags = SURVEY_INFO_TIME_TX |
- SURVEY_INFO_TIME_RX |
- SURVEY_INFO_TIME_BSS_RX,
- .token_size = MT7915_TOKEN_SIZE,
- .tx_prepare_skb = mt7915_tx_prepare_skb,
- .tx_complete_skb = mt7915_tx_complete_skb,
- .rx_skb = mt7915_queue_rx_skb,
- .rx_poll_complete = mt7915_rx_poll_complete,
- .sta_ps = mt7915_sta_ps,
- .sta_add = mt7915_mac_sta_add,
- .sta_remove = mt7915_mac_sta_remove,
- .update_survey = mt7915_update_channel,
- };
- struct mt7915_dev *dev;
- struct mt76_dev *mdev;
+ struct mt7915_hif *hif2;
+
int ret;
ret = pcim_enable_device(pdev);
@@ -259,46 +115,18 @@ static int mt7915_pci_probe(struct pci_dev *pdev,
if (id->device == 0x7916)
return mt7915_pci_hif2_probe(pdev);
- mdev = mt76_alloc_device(&pdev->dev, sizeof(*dev), &mt7915_ops,
- &drv_ops);
- if (!mdev)
- return -ENOMEM;
-
- dev = container_of(mdev, struct mt7915_dev, mt76);
-
ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
if (ret < 0)
- goto free;
-
- ret = mt7915_mmio_init(mdev, pcim_iomap_table(pdev)[0], pdev->irq);
- if (ret)
- goto error;
-
- tasklet_setup(&dev->irq_tasklet, mt7915_irq_tasklet);
-
- mt76_wr(dev, MT_INT_MASK_CSR, 0);
-
- /* master switch of PCIe tnterrupt enable */
- mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
+ return ret;
- ret = devm_request_irq(mdev->dev, pdev->irq, mt7915_irq_handler,
- IRQF_SHARED, KBUILD_MODNAME, dev);
- if (ret)
- goto error;
+ hif2 = mt7915_pci_init_hif2(pdev);
- mt7915_pci_init_hif2(dev);
+ ret = mt7915_mmio_probe(&pdev->dev, pcim_iomap_table(pdev)[0],
+ id->device, pdev->irq, hif2);
+ if (!ret)
+ return 0;
- ret = mt7915_register_device(dev);
- if (ret)
- goto free_irq;
-
- return 0;
-free_irq:
- devm_free_irq(mdev->dev, pdev->irq, dev);
-error:
pci_free_irq_vectors(pdev);
-free:
- mt76_free_device(&dev->mt76);
return ret;
}
@@ -321,47 +149,22 @@ static void mt7915_pci_remove(struct pci_dev *pdev)
mt7915_unregister_device(dev);
}
-static struct pci_driver mt7915_hif_driver = {
+struct pci_driver mt7915_hif_driver = {
.name = KBUILD_MODNAME "_hif",
.id_table = mt7915_hif_device_table,
.probe = mt7915_pci_probe,
.remove = mt7915_hif_remove,
};
-static struct pci_driver mt7915_pci_driver = {
+struct pci_driver mt7915_pci_driver = {
.name = KBUILD_MODNAME,
.id_table = mt7915_pci_device_table,
.probe = mt7915_pci_probe,
.remove = mt7915_pci_remove,
};
-static int __init mt7915_init(void)
-{
- int ret;
-
- ret = pci_register_driver(&mt7915_hif_driver);
- if (ret)
- return ret;
-
- ret = pci_register_driver(&mt7915_pci_driver);
- if (ret)
- pci_unregister_driver(&mt7915_hif_driver);
-
- return ret;
-}
-
-static void __exit mt7915_exit(void)
-{
- pci_unregister_driver(&mt7915_pci_driver);
- pci_unregister_driver(&mt7915_hif_driver);
-}
-
-module_init(mt7915_init);
-module_exit(mt7915_exit);
-
MODULE_DEVICE_TABLE(pci, mt7915_pci_device_table);
MODULE_DEVICE_TABLE(pci, mt7915_hif_device_table);
MODULE_FIRMWARE(MT7915_FIRMWARE_WA);
MODULE_FIRMWARE(MT7915_FIRMWARE_WM);
MODULE_FIRMWARE(MT7915_ROM_PATCH);
-MODULE_LICENSE("Dual BSD/GPL");
--
2.18.0
From: Bo Jiao <[email protected]>
The RXQ of mt7916 are separated to MT_RXQ_MAIN_WA and MT_RXQ_MCU_WA,
which causes a hole for queue iteration so modify it accordingly.
This is an intermediate patch to add mt7916 support.
Co-developed-by: Sujuan Chen <[email protected]>
Signed-off-by: Sujuan Chen <[email protected]>
Co-developed-by: Ryder Lee <[email protected]>
Signed-off-by: Ryder Lee <[email protected]>
Signed-off-by: Bo Jiao <[email protected]>
---
v2:
- revert the modify to mt76_for_each_q_rx() which may cause
not work for sdo/usb chip.
---
drivers/net/wireless/mediatek/mt76/dma.c | 13 +-
drivers/net/wireless/mediatek/mt76/mt76.h | 1 +
.../net/wireless/mediatek/mt76/mt7915/dma.c | 375 ++++++++++++------
.../net/wireless/mediatek/mt76/mt7915/init.c | 9 +-
.../net/wireless/mediatek/mt76/mt7915/mac.c | 4 +
.../net/wireless/mediatek/mt76/mt7915/mmio.c | 38 +-
.../wireless/mediatek/mt76/mt7915/mt7915.h | 3 +-
.../net/wireless/mediatek/mt76/mt7915/regs.h | 60 ++-
8 files changed, 358 insertions(+), 145 deletions(-)
diff --git a/drivers/net/wireless/mediatek/mt76/dma.c b/drivers/net/wireless/mediatek/mt76/dma.c
index 5e1c150..3cc1acf 100644
--- a/drivers/net/wireless/mediatek/mt76/dma.c
+++ b/drivers/net/wireless/mediatek/mt76/dma.c
@@ -93,7 +93,7 @@ mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q)
{
int i;
- if (!q)
+ if (!q || !q->ndesc)
return;
/* clear descriptors */
@@ -233,7 +233,7 @@ mt76_dma_tx_cleanup(struct mt76_dev *dev, struct mt76_queue *q, bool flush)
struct mt76_queue_entry entry;
int last;
- if (!q)
+ if (!q || !q->ndesc)
return;
spin_lock_bh(&q->cleanup_lock);
@@ -448,6 +448,9 @@ mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
int len = SKB_WITH_OVERHEAD(q->buf_size);
int offset = q->buf_offset;
+ if (!q->ndesc)
+ return 0;
+
spin_lock_bh(&q->lock);
while (q->queued < q->ndesc - 1) {
@@ -484,6 +487,9 @@ mt76_dma_rx_cleanup(struct mt76_dev *dev, struct mt76_queue *q)
void *buf;
bool more;
+ if (!q->ndesc)
+ return;
+
spin_lock_bh(&q->lock);
do {
buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more);
@@ -508,6 +514,9 @@ mt76_dma_rx_reset(struct mt76_dev *dev, enum mt76_rxq_id qid)
struct mt76_queue *q = &dev->q_rx[qid];
int i;
+ if (!q->ndesc)
+ return;
+
for (i = 0; i < q->ndesc; i++)
q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE);
diff --git a/drivers/net/wireless/mediatek/mt76/mt76.h b/drivers/net/wireless/mediatek/mt76/mt76.h
index e2da720..8fd6890 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76.h
+++ b/drivers/net/wireless/mediatek/mt76/mt76.h
@@ -85,6 +85,7 @@ enum mt76_rxq_id {
MT_RXQ_MCU_WA,
MT_RXQ_EXT,
MT_RXQ_EXT_WA,
+ MT_RXQ_MAIN_WA,
__MT_RXQ_MAX
};
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/dma.c b/drivers/net/wireless/mediatek/mt76/mt7915/dma.c
index ad9678b..05104b1 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/dma.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/dma.c
@@ -44,31 +44,52 @@ static int mt7915_poll_tx(struct napi_struct *napi, int budget)
static void __mt7915_dma_prefetch(struct mt7915_dev *dev, u32 ofs)
{
#define PREFETCH(base, depth) ((base) << 16 | (depth))
-
- mt76_wr(dev, MT_WFDMA0_RX_RING0_EXT_CTRL + ofs, PREFETCH(0x0, 0x4));
- mt76_wr(dev, MT_WFDMA0_RX_RING1_EXT_CTRL + ofs, PREFETCH(0x40, 0x4));
- mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL + ofs, PREFETCH(0x80, 0x0));
-
- mt76_wr(dev, MT_WFDMA1_TX_RING0_EXT_CTRL + ofs, PREFETCH(0x80, 0x4));
- mt76_wr(dev, MT_WFDMA1_TX_RING1_EXT_CTRL + ofs, PREFETCH(0xc0, 0x4));
- mt76_wr(dev, MT_WFDMA1_TX_RING2_EXT_CTRL + ofs, PREFETCH(0x100, 0x4));
- mt76_wr(dev, MT_WFDMA1_TX_RING3_EXT_CTRL + ofs, PREFETCH(0x140, 0x4));
- mt76_wr(dev, MT_WFDMA1_TX_RING4_EXT_CTRL + ofs, PREFETCH(0x180, 0x4));
- mt76_wr(dev, MT_WFDMA1_TX_RING5_EXT_CTRL + ofs, PREFETCH(0x1c0, 0x4));
- mt76_wr(dev, MT_WFDMA1_TX_RING6_EXT_CTRL + ofs, PREFETCH(0x200, 0x4));
- mt76_wr(dev, MT_WFDMA1_TX_RING7_EXT_CTRL + ofs, PREFETCH(0x240, 0x4));
-
- mt76_wr(dev, MT_WFDMA1_TX_RING16_EXT_CTRL + ofs, PREFETCH(0x280, 0x4));
- mt76_wr(dev, MT_WFDMA1_TX_RING17_EXT_CTRL + ofs, PREFETCH(0x2c0, 0x4));
- mt76_wr(dev, MT_WFDMA1_TX_RING18_EXT_CTRL + ofs, PREFETCH(0x300, 0x4));
- mt76_wr(dev, MT_WFDMA1_TX_RING19_EXT_CTRL + ofs, PREFETCH(0x340, 0x4));
- mt76_wr(dev, MT_WFDMA1_TX_RING20_EXT_CTRL + ofs, PREFETCH(0x380, 0x4));
- mt76_wr(dev, MT_WFDMA1_TX_RING21_EXT_CTRL + ofs, PREFETCH(0x3c0, 0x0));
-
- mt76_wr(dev, MT_WFDMA1_RX_RING0_EXT_CTRL + ofs, PREFETCH(0x3c0, 0x4));
- mt76_wr(dev, MT_WFDMA1_RX_RING1_EXT_CTRL + ofs, PREFETCH(0x400, 0x4));
- mt76_wr(dev, MT_WFDMA1_RX_RING2_EXT_CTRL + ofs, PREFETCH(0x440, 0x4));
- mt76_wr(dev, MT_WFDMA1_RX_RING3_EXT_CTRL + ofs, PREFETCH(0x480, 0x0));
+ struct mt76_dev *mdev = &dev->mt76;
+ u32 base_ofs = 0;
+
+ /* prefetch SRAM wrapping boundary for tx/rx ring. */
+ mt76_wr(dev, MT_WFDMA_TX_RING_EXT_CTRL_FWDL + ofs,
+ PREFETCH(0x0, 0x4));
+ mt76_wr(dev, MT_WFDMA_TX_RING_EXT_CTRL_WM + ofs,
+ PREFETCH(0x40, 0x4));
+ mt76_wr(dev, MT_WFDMA_TX_RING_EXT_CTRL_BAND0 + ofs,
+ PREFETCH(0x80, 0x4));
+ mt76_wr(dev, MT_WFDMA_TX_RING_EXT_CTRL_BAND1 + ofs,
+ PREFETCH(0xc0, 0x4));
+ mt76_wr(dev, MT_WFDMA_TX_RING_EXT_CTRL_WA + ofs,
+ PREFETCH(0x100, 0x4));
+ mt76_wr(dev, MT_WFDMA1_TX_RING21_EXT_CTRL + ofs,
+ PREFETCH(0x140, 0x0));
+
+ mt76_wr(dev, MT_WFDMA_RX_RING_EXT_CTRL_WM + ofs,
+ PREFETCH(0x140, 0x4));
+ if (!is_mt7915(mdev)) {
+ mt76_wr(dev, MT_WFDMA_RX_RING_EXT_CTRL_WA + ofs,
+ PREFETCH(0x180, 0x4));
+ base_ofs = 0x40;
+ }
+ mt76_wr(dev, MT_WFDMA_RX_RING_EXT_CTRL_STS0 + ofs,
+ PREFETCH(0x180 + base_ofs, 0x4));
+ mt76_wr(dev, MT_WFDMA_RX_RING_EXT_CTRL_STS1 + ofs,
+ PREFETCH(0x1c0 + base_ofs, 0x4));
+ mt76_wr(dev, MT_WFDMA_RX_RING_EXT_CTRL_BAND0 + ofs,
+ PREFETCH(0x200 + base_ofs, 0x4));
+ mt76_wr(dev, MT_WFDMA_RX_RING_EXT_CTRL_BAND1 + ofs,
+ PREFETCH(0x240 + base_ofs, 0x4));
+
+ /* for mt7915, the ring which is next the last
+ * used ring must be initialized.
+ */
+ if (is_mt7915(mdev)) {
+ mt76_wr(dev, MT_WFDMA1_TX_RING21_EXT_CTRL + ofs,
+ PREFETCH(0x140, 0x0));
+
+ mt76_wr(dev, MT_WFDMA1_RX_RING3_EXT_CTRL + ofs,
+ PREFETCH(0x200 + base_ofs, 0x0));
+
+ mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL + ofs,
+ PREFETCH(0x280 + base_ofs, 0x0));
+ }
}
void mt7915_dma_prefetch(struct mt7915_dev *dev)
@@ -78,43 +99,219 @@ void mt7915_dma_prefetch(struct mt7915_dev *dev)
__mt7915_dma_prefetch(dev, MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0));
}
-int mt7915_dma_init(struct mt7915_dev *dev)
+static void mt7915_dma_disable(struct mt7915_dev *dev, bool rst)
{
+ struct mt76_dev *mdev = &dev->mt76;
u32 hif1_ofs = 0;
- int ret;
-
- mt76_dma_attach(&dev->mt76);
if (dev->hif2)
hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
- /* configure global setting */
- mt76_set(dev, MT_WFDMA1_GLO_CFG,
- MT_WFDMA1_GLO_CFG_OMIT_TX_INFO |
- MT_WFDMA1_GLO_CFG_OMIT_RX_INFO);
+ /* reset */
+ if (rst) {
+ mt76_clear(dev, MT_WFDMA0_RST,
+ MT_WFDMA0_RST_DMASHDL_ALL_RST |
+ MT_WFDMA0_RST_LOGIC_RST);
+
+ mt76_set(dev, MT_WFDMA0_RST,
+ MT_WFDMA0_RST_DMASHDL_ALL_RST |
+ MT_WFDMA0_RST_LOGIC_RST);
+
+ if (is_mt7915(mdev)) {
+ mt76_clear(dev, MT_WFDMA1_RST,
+ MT_WFDMA1_RST_DMASHDL_ALL_RST |
+ MT_WFDMA1_RST_LOGIC_RST);
+
+ mt76_set(dev, MT_WFDMA1_RST,
+ MT_WFDMA1_RST_DMASHDL_ALL_RST |
+ MT_WFDMA1_RST_LOGIC_RST);
+ }
+
+ if (dev->hif2) {
+ mt76_clear(dev, MT_WFDMA0_RST + hif1_ofs,
+ MT_WFDMA0_RST_DMASHDL_ALL_RST |
+ MT_WFDMA0_RST_LOGIC_RST);
+
+ mt76_set(dev, MT_WFDMA0_RST + hif1_ofs,
+ MT_WFDMA0_RST_DMASHDL_ALL_RST |
+ MT_WFDMA0_RST_LOGIC_RST);
+
+ if (is_mt7915(mdev)) {
+ mt76_clear(dev, MT_WFDMA1_RST + hif1_ofs,
+ MT_WFDMA1_RST_DMASHDL_ALL_RST |
+ MT_WFDMA1_RST_LOGIC_RST);
+
+ mt76_set(dev, MT_WFDMA1_RST + hif1_ofs,
+ MT_WFDMA1_RST_DMASHDL_ALL_RST |
+ MT_WFDMA1_RST_LOGIC_RST);
+ }
+ }
+ }
+
+ /* disable */
+ mt76_clear(dev, MT_WFDMA0_GLO_CFG,
+ MT_WFDMA0_GLO_CFG_TX_DMA_EN |
+ MT_WFDMA0_GLO_CFG_RX_DMA_EN |
+ MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
+ MT_WFDMA0_GLO_CFG_OMIT_RX_INFO |
+ MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
+
+ if (is_mt7915(mdev))
+ mt76_clear(dev, MT_WFDMA1_GLO_CFG,
+ MT_WFDMA1_GLO_CFG_TX_DMA_EN |
+ MT_WFDMA1_GLO_CFG_RX_DMA_EN |
+ MT_WFDMA1_GLO_CFG_OMIT_TX_INFO |
+ MT_WFDMA1_GLO_CFG_OMIT_RX_INFO |
+ MT_WFDMA1_GLO_CFG_OMIT_RX_INFO_PFET2);
+
+ if (dev->hif2) {
+ mt76_clear(dev, MT_WFDMA0_GLO_CFG + hif1_ofs,
+ MT_WFDMA0_GLO_CFG_TX_DMA_EN |
+ MT_WFDMA0_GLO_CFG_RX_DMA_EN |
+ MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
+ MT_WFDMA0_GLO_CFG_OMIT_RX_INFO |
+ MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
+
+ if (is_mt7915(mdev))
+ mt76_clear(dev, MT_WFDMA1_GLO_CFG + hif1_ofs,
+ MT_WFDMA1_GLO_CFG_TX_DMA_EN |
+ MT_WFDMA1_GLO_CFG_RX_DMA_EN |
+ MT_WFDMA1_GLO_CFG_OMIT_TX_INFO |
+ MT_WFDMA1_GLO_CFG_OMIT_RX_INFO |
+ MT_WFDMA1_GLO_CFG_OMIT_RX_INFO_PFET2);
+ }
+}
+
+static int mt7915_dma_enable(struct mt7915_dev *dev)
+{
+ struct mt76_dev *mdev = &dev->mt76;
+ u32 hif1_ofs = 0;
+ u32 irq_mask;
+
+ if (dev->hif2)
+ hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
/* reset dma idx */
mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR, ~0);
- mt76_wr(dev, MT_WFDMA1_RST_DTX_PTR, ~0);
+ if (is_mt7915(mdev))
+ mt76_wr(dev, MT_WFDMA1_RST_DTX_PTR, ~0);
+ if (dev->hif2) {
+ mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR + hif1_ofs, ~0);
+ if (is_mt7915(mdev))
+ mt76_wr(dev, MT_WFDMA1_RST_DTX_PTR + hif1_ofs, ~0);
+ }
- /* configure delay interrupt */
+ /* configure delay interrupt off */
mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0, 0);
- mt76_wr(dev, MT_WFDMA1_PRI_DLY_INT_CFG0, 0);
+ if (is_mt7915(mdev)) {
+ mt76_wr(dev, MT_WFDMA1_PRI_DLY_INT_CFG0, 0);
+ } else {
+ mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG1, 0);
+ mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG2, 0);
+ }
if (dev->hif2) {
- mt76_set(dev, MT_WFDMA1_GLO_CFG + hif1_ofs,
+ mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0 + hif1_ofs, 0);
+ if (is_mt7915(mdev)) {
+ mt76_wr(dev, MT_WFDMA1_PRI_DLY_INT_CFG0 +
+ hif1_ofs, 0);
+ } else {
+ mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG1 +
+ hif1_ofs, 0);
+ mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG2 +
+ hif1_ofs, 0);
+ }
+ }
+
+ /* configure perfetch settings */
+ mt7915_dma_prefetch(dev);
+
+ /* hif wait WFDMA idle */
+ mt76_set(dev, MT_WFDMA0_BUSY_ENA,
+ MT_WFDMA0_BUSY_ENA_TX_FIFO0 |
+ MT_WFDMA0_BUSY_ENA_TX_FIFO1 |
+ MT_WFDMA0_BUSY_ENA_RX_FIFO);
+
+ if (is_mt7915(mdev))
+ mt76_set(dev, MT_WFDMA1_BUSY_ENA,
+ MT_WFDMA1_BUSY_ENA_TX_FIFO0 |
+ MT_WFDMA1_BUSY_ENA_TX_FIFO1 |
+ MT_WFDMA1_BUSY_ENA_RX_FIFO);
+
+ if (dev->hif2) {
+ mt76_set(dev, MT_WFDMA0_BUSY_ENA + hif1_ofs,
+ MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 |
+ MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 |
+ MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO);
+
+ if (is_mt7915(mdev))
+ mt76_set(dev, MT_WFDMA1_BUSY_ENA + hif1_ofs,
+ MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO0 |
+ MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO1 |
+ MT_WFDMA1_PCIE1_BUSY_ENA_RX_FIFO);
+ }
+
+ mt76_poll(dev, MT_WFDMA_EXT_CSR_HIF_MISC,
+ MT_WFDMA_EXT_CSR_HIF_MISC_BUSY, 0, 1000);
+
+ /* set WFDMA Tx/Rx */
+ mt76_set(dev, MT_WFDMA0_GLO_CFG,
+ MT_WFDMA0_GLO_CFG_TX_DMA_EN |
+ MT_WFDMA0_GLO_CFG_RX_DMA_EN |
+ MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
+ MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
+
+ if (is_mt7915(mdev))
+ mt76_set(dev, MT_WFDMA1_GLO_CFG,
+ MT_WFDMA1_GLO_CFG_TX_DMA_EN |
+ MT_WFDMA1_GLO_CFG_RX_DMA_EN |
MT_WFDMA1_GLO_CFG_OMIT_TX_INFO |
MT_WFDMA1_GLO_CFG_OMIT_RX_INFO);
- mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR + hif1_ofs, ~0);
- mt76_wr(dev, MT_WFDMA1_RST_DTX_PTR + hif1_ofs, ~0);
+ if (dev->hif2) {
+ mt76_set(dev, MT_WFDMA0_GLO_CFG + hif1_ofs,
+ MT_WFDMA0_GLO_CFG_TX_DMA_EN |
+ MT_WFDMA0_GLO_CFG_RX_DMA_EN |
+ MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
+ MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
+
+ if (is_mt7915(mdev))
+ mt76_set(dev, MT_WFDMA1_GLO_CFG + hif1_ofs,
+ MT_WFDMA1_GLO_CFG_TX_DMA_EN |
+ MT_WFDMA1_GLO_CFG_RX_DMA_EN |
+ MT_WFDMA1_GLO_CFG_OMIT_TX_INFO |
+ MT_WFDMA1_GLO_CFG_OMIT_RX_INFO);
- mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0 + hif1_ofs, 0);
- mt76_wr(dev, MT_WFDMA1_PRI_DLY_INT_CFG0 + hif1_ofs, 0);
+ mt76_set(dev, MT_WFDMA_HOST_CONFIG,
+ MT_WFDMA_HOST_CONFIG_PDMA_BAND);
}
- /* configure perfetch settings */
- mt7915_dma_prefetch(dev);
+ /* enable interrupts for TX/RX rings */
+ irq_mask = MT_INT_RX_DONE_MCU |
+ MT_INT_TX_DONE_MCU |
+ MT_INT_MCU_CMD |
+ MT_INT_BAND0_RX_DONE;
+
+ if (dev->dbdc_support)
+ irq_mask |= MT_INT_BAND1_RX_DONE;
+
+ mt7915_irq_enable(dev, irq_mask);
+
+ return 0;
+}
+
+int mt7915_dma_init(struct mt7915_dev *dev)
+{
+ struct mt76_dev *mdev = &dev->mt76;
+ u32 hif1_ofs = 0;
+ int ret;
+
+ mt76_dma_attach(&dev->mt76);
+
+ if (dev->hif2)
+ hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
+
+ mt7915_dma_disable(dev, true);
/* init tx queue */
ret = mt7915_init_tx_queues(&dev->phy, MT7915_TXQ_BAND0,
@@ -149,19 +346,31 @@ int mt7915_dma_init(struct mt7915_dev *dev)
/* event from WA */
ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA],
- MT7915_RXQ_MCU_WA, MT7915_RX_MCU_RING_SIZE,
+ MT7915_RXQ_MCU_WA,
+ MT7915_RX_MCU_RING_SIZE,
MT_RX_BUF_SIZE, MT_RX_EVENT_RING_BASE);
if (ret)
return ret;
- /* rx data queue */
+ /* rx data queue for band0 */
ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN],
MT7915_RXQ_BAND0, MT7915_RX_RING_SIZE,
MT_RX_BUF_SIZE, MT_RX_DATA_RING_BASE);
if (ret)
return ret;
+ /* tx free notify event from WA for band0 */
+ if (!is_mt7915(mdev)) {
+ ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN_WA],
+ MT7915_RXQ_WA_BAND0,
+ MT7915_RX_MCU_RING_SIZE,
+ MT_RX_BUF_SIZE, MT_RX_STS_RING_BASE);
+ if (ret)
+ return ret;
+ }
+
if (dev->dbdc_support) {
+ /* rx data queue for band1 */
ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_EXT],
MT7915_RXQ_BAND1, MT7915_RX_RING_SIZE,
MT_RX_BUF_SIZE,
@@ -169,12 +378,12 @@ int mt7915_dma_init(struct mt7915_dev *dev)
if (ret)
return ret;
- /* event from WA */
+ /* tx free notify event from WA for band1 */
ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_EXT_WA],
- MT7915_RXQ_MCU_WA_EXT,
+ MT7915_RXQ_WA_BAND1,
MT7915_RX_MCU_RING_SIZE,
MT_RX_BUF_SIZE,
- MT_RX_EVENT_RING_BASE + hif1_ofs);
+ MT_RX_STS_RING_BASE + hif1_ofs);
if (ret)
return ret;
}
@@ -187,80 +396,14 @@ int mt7915_dma_init(struct mt7915_dev *dev)
mt7915_poll_tx, NAPI_POLL_WEIGHT);
napi_enable(&dev->mt76.tx_napi);
- /* hif wait WFDMA idle */
- mt76_set(dev, MT_WFDMA0_BUSY_ENA,
- MT_WFDMA0_BUSY_ENA_TX_FIFO0 |
- MT_WFDMA0_BUSY_ENA_TX_FIFO1 |
- MT_WFDMA0_BUSY_ENA_RX_FIFO);
-
- mt76_set(dev, MT_WFDMA1_BUSY_ENA,
- MT_WFDMA1_BUSY_ENA_TX_FIFO0 |
- MT_WFDMA1_BUSY_ENA_TX_FIFO1 |
- MT_WFDMA1_BUSY_ENA_RX_FIFO);
-
- mt76_set(dev, MT_WFDMA0_PCIE1_BUSY_ENA,
- MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 |
- MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 |
- MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO);
-
- mt76_set(dev, MT_WFDMA1_PCIE1_BUSY_ENA,
- MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO0 |
- MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO1 |
- MT_WFDMA1_PCIE1_BUSY_ENA_RX_FIFO);
-
- mt76_poll(dev, MT_WFDMA_EXT_CSR_HIF_MISC,
- MT_WFDMA_EXT_CSR_HIF_MISC_BUSY, 0, 1000);
-
- /* set WFDMA Tx/Rx */
- mt76_set(dev, MT_WFDMA0_GLO_CFG,
- MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
- mt76_set(dev, MT_WFDMA1_GLO_CFG,
- MT_WFDMA1_GLO_CFG_TX_DMA_EN | MT_WFDMA1_GLO_CFG_RX_DMA_EN);
-
- if (dev->hif2) {
- mt76_set(dev, MT_WFDMA0_GLO_CFG + hif1_ofs,
- (MT_WFDMA0_GLO_CFG_TX_DMA_EN |
- MT_WFDMA0_GLO_CFG_RX_DMA_EN));
- mt76_set(dev, MT_WFDMA1_GLO_CFG + hif1_ofs,
- (MT_WFDMA1_GLO_CFG_TX_DMA_EN |
- MT_WFDMA1_GLO_CFG_RX_DMA_EN));
- mt76_set(dev, MT_WFDMA_HOST_CONFIG,
- MT_WFDMA_HOST_CONFIG_PDMA_BAND);
- }
-
- /* enable interrupts for TX/RX rings */
- mt7915_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_MCU |
- MT_INT_MCU_CMD);
+ mt7915_dma_enable(dev);
return 0;
}
void mt7915_dma_cleanup(struct mt7915_dev *dev)
{
- /* disable */
- mt76_clear(dev, MT_WFDMA0_GLO_CFG,
- MT_WFDMA0_GLO_CFG_TX_DMA_EN |
- MT_WFDMA0_GLO_CFG_RX_DMA_EN);
- mt76_clear(dev, MT_WFDMA1_GLO_CFG,
- MT_WFDMA1_GLO_CFG_TX_DMA_EN |
- MT_WFDMA1_GLO_CFG_RX_DMA_EN);
-
- /* reset */
- mt76_clear(dev, MT_WFDMA1_RST,
- MT_WFDMA1_RST_DMASHDL_ALL_RST |
- MT_WFDMA1_RST_LOGIC_RST);
-
- mt76_set(dev, MT_WFDMA1_RST,
- MT_WFDMA1_RST_DMASHDL_ALL_RST |
- MT_WFDMA1_RST_LOGIC_RST);
-
- mt76_clear(dev, MT_WFDMA0_RST,
- MT_WFDMA0_RST_DMASHDL_ALL_RST |
- MT_WFDMA0_RST_LOGIC_RST);
-
- mt76_set(dev, MT_WFDMA0_RST,
- MT_WFDMA0_RST_DMASHDL_ALL_RST |
- MT_WFDMA0_RST_LOGIC_RST);
+ mt7915_dma_disable(dev, true);
mt76_dma_cleanup(&dev->mt76);
}
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/init.c b/drivers/net/wireless/mediatek/mt76/mt7915/init.c
index 4fa8e7b..21f1337 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/init.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/init.c
@@ -394,8 +394,15 @@ mt7915_mac_init_band(struct mt7915_dev *dev, u8 band)
static void mt7915_mac_init(struct mt7915_dev *dev)
{
int i;
+ u32 rx_len = is_mt7915(&dev->mt76) ? 0x400 : 0x680;
+
+ /* config pse qid6 wfdma port selection */
+ if (!is_mt7915(&dev->mt76) && dev->hif2)
+ mt76_rmw(dev, MT_WF_PP_TOP_RXQ_WFDMA_CF_5, 0,
+ MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK);
+
+ mt76_rmw_field(dev, MT_MDP_DCR1, MT_MDP_DCR1_MAX_RX_LEN, rx_len);
- mt76_rmw_field(dev, MT_MDP_DCR1, MT_MDP_DCR1_MAX_RX_LEN, 0x400);
/* enable hardware de-agg */
mt76_set(dev, MT_MDP_DCR0, MT_MDP_DCR0_DAMSDU_EN);
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
index d808437..311d17d 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
@@ -780,6 +780,10 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
if (!status->wcid || !ieee80211_is_data_qos(fc))
return 0;
+ /* drop no data frame */
+ if (fc & cpu_to_le16(IEEE80211_STYPE_NULLFUNC))
+ return -EINVAL;
+
status->aggr = unicast &&
!ieee80211_is_qos_nullfunc(fc);
status->qos_ctl = qos_ctl;
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mmio.c b/drivers/net/wireless/mediatek/mt76/mt7915/mmio.c
index 0d67321..7ba5b1f 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mmio.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mmio.c
@@ -55,8 +55,20 @@ static const struct __reg mt7915_reg[] = {
[INT1_MASK_CSR] = { MT_WFDMA_EXT_CSR_BASE, 0x8c },
[INT_MCU_CMD_SOURCE] = { MT_WFDMA1_BASE, 0x1f0 },
[INT_MCU_CMD_EVENT] = { MT_MCU_WFDMA1_BASE, 0x108 },
+ [TX_RING_CTRL_FWDL] = { MT_WFDMA1_BASE, 0x640 },
+ [TX_RING_CTRL_WM] = { MT_WFDMA1_BASE, 0x644 },
+ [TX_RING_CTRL_BAND0] = { MT_WFDMA1_BASE, 0x648 },
+ [TX_RING_CTRL_BAND1] = { MT_WFDMA1_BASE, 0x64c },
+ [TX_RING_CTRL_WA] = { MT_WFDMA1_BASE, 0x650 },
+ [RX_RING_CTRL_WM] = { MT_WFDMA1_BASE, 0x680 },
+ [RX_RING_CTRL_WA] = { INVALID_BASE, INVALID_OFFSET },
+ [RX_RING_CTRL_STS0] = { MT_WFDMA1_BASE, 0x684 },
+ [RX_RING_CTRL_STS1] = { MT_WFDMA1_BASE, 0x688 },
+ [RX_RING_CTRL_BAND0] = { MT_WFDMA0_BASE, 0x680 },
+ [RX_RING_CTRL_BAND1] = { MT_WFDMA0_BASE, 0x684 },
[TX_RING_BASE] = { MT_WFDMA1_BASE, 0x400 },
[RX_EVENT_RING_BASE] = { MT_WFDMA1_BASE, 0x500 },
+ [RX_STS_RING_BASE] = { MT_WFDMA1_BASE, 0x510 },
[RX_DATA_RING_BASE] = { MT_WFDMA0_BASE, 0x500 },
[TMAC_CDTR] = { INVALID_BASE, 0x090 },
[TMAC_ODTR] = { INVALID_BASE, 0x094 },
@@ -137,8 +149,20 @@ static const struct __reg mt7916_reg[] = {
[INT1_MASK_CSR] = { MT_WFDMA0_PCIE1_BASE, 0x204 },
[INT_MCU_CMD_SOURCE] = { MT_WFDMA0_BASE, 0x1f0 },
[INT_MCU_CMD_EVENT] = { MT_MCU_WFDMA0_BASE, 0x108 },
+ [TX_RING_CTRL_FWDL] = { MT_WFDMA0_BASE, 0x640 },
+ [TX_RING_CTRL_WM] = { MT_WFDMA0_BASE, 0x644 },
+ [TX_RING_CTRL_BAND0] = { MT_WFDMA0_BASE, 0x648 },
+ [TX_RING_CTRL_BAND1] = { MT_WFDMA0_BASE, 0x64c },
+ [TX_RING_CTRL_WA] = { MT_WFDMA0_BASE, 0x650 },
+ [RX_RING_CTRL_WM] = { MT_WFDMA0_BASE, 0x680 },
+ [RX_RING_CTRL_WA] = { MT_WFDMA0_BASE, 0x684 },
+ [RX_RING_CTRL_STS0] = { MT_WFDMA0_BASE, 0x688 },
+ [RX_RING_CTRL_STS1] = { MT_WFDMA0_BASE, 0x68c },
+ [RX_RING_CTRL_BAND0] = { MT_WFDMA0_BASE, 0x690 },
+ [RX_RING_CTRL_BAND1] = { MT_WFDMA0_BASE, 0x694 },
[TX_RING_BASE] = { MT_WFDMA0_BASE, 0x400 },
[RX_EVENT_RING_BASE] = { MT_WFDMA0_BASE, 0x500 },
+ [RX_STS_RING_BASE] = { MT_WFDMA0_BASE, 0x520 },
[RX_DATA_RING_BASE] = { MT_WFDMA0_BASE, 0x540 },
[TMAC_CDTR] = { INVALID_BASE, 0x0c8 },
[TMAC_ODTR] = { INVALID_BASE, 0x0cc },
@@ -547,18 +571,21 @@ static void mt7915_rx_poll_complete(struct mt76_dev *mdev,
case MT_RXQ_MAIN:
rx_irq_mask = MT_INT_RX_DONE_DATA0;
break;
- case MT_RXQ_EXT:
- rx_irq_mask = MT_INT_RX_DONE_DATA1;
- break;
case MT_RXQ_MCU:
rx_irq_mask = MT_INT_RX_DONE_WM;
break;
case MT_RXQ_MCU_WA:
rx_irq_mask = MT_INT_RX_DONE_WA;
break;
+ case MT_RXQ_EXT:
+ rx_irq_mask = MT_INT_RX_DONE_DATA1;
+ break;
case MT_RXQ_EXT_WA:
rx_irq_mask = MT_INT_RX_DONE_WA_EXT;
break;
+ case MT_RXQ_MAIN_WA:
+ rx_irq_mask = MT_INT_RX_DONE_WA_MAIN;
+ break;
default:
break;
}
@@ -611,6 +638,11 @@ static void mt7915_irq_tasklet(struct tasklet_struct *t)
if (intr & MT_INT_RX_DONE_WA)
napi_schedule(&dev->mt76.napi[MT_RXQ_MCU_WA]);
+ if (!is_mt7915(&dev->mt76)) {
+ if (intr & MT_INT_RX_DONE_WA_MAIN)
+ napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN_WA]);
+ }
+
if (intr & MT_INT_RX_DONE_WA_EXT)
napi_schedule(&dev->mt76.napi[MT_RXQ_EXT_WA]);
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
index b69e00d..8adb069 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
@@ -65,7 +65,8 @@ enum mt7915_rxq_id {
MT7915_RXQ_BAND1,
MT7915_RXQ_MCU_WM = 0,
MT7915_RXQ_MCU_WA,
- MT7915_RXQ_MCU_WA_EXT,
+ MT7915_RXQ_WA_BAND0 = 0,
+ MT7915_RXQ_WA_BAND1,
};
struct mt7915_sta_key_conf {
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/regs.h b/drivers/net/wireless/mediatek/mt76/mt7915/regs.h
index c80d16a..0105cc4 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/regs.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/regs.h
@@ -62,8 +62,20 @@ enum reg_rev {
INT1_MASK_CSR,
INT_MCU_CMD_SOURCE,
INT_MCU_CMD_EVENT,
+ TX_RING_CTRL_FWDL,
+ TX_RING_CTRL_WM,
+ TX_RING_CTRL_BAND0,
+ TX_RING_CTRL_BAND1,
+ TX_RING_CTRL_WA,
+ RX_RING_CTRL_WM,
+ RX_RING_CTRL_WA,
+ RX_RING_CTRL_STS0,
+ RX_RING_CTRL_STS1,
+ RX_RING_CTRL_BAND0,
+ RX_RING_CTRL_BAND1,
TX_RING_BASE,
RX_EVENT_RING_BASE,
+ RX_STS_RING_BASE,
RX_DATA_RING_BASE,
TMAC_CDTR,
TMAC_ODTR,
@@ -574,12 +586,15 @@ enum bit_rev {
#define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208)
#define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0)
#define MT_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2)
+#define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO BIT(28)
+#define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO BIT(27)
+#define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21)
#define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)
#define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0)
+#define MT_WFDMA0_PRI_DLY_INT_CFG1 MT_WFDMA0(0x2f4)
+#define MT_WFDMA0_PRI_DLY_INT_CFG2 MT_WFDMA0(0x2f8)
-#define MT_WFDMA0_RX_RING0_EXT_CTRL MT_WFDMA0(0x680)
-#define MT_WFDMA0_RX_RING1_EXT_CTRL MT_WFDMA0(0x684)
#define MT_WFDMA0_RX_RING2_EXT_CTRL MT_WFDMA0(0x688)
/* WFDMA1 */
@@ -599,31 +614,12 @@ enum bit_rev {
#define MT_WFDMA1_GLO_CFG_RX_DMA_EN BIT(2)
#define MT_WFDMA1_GLO_CFG_OMIT_TX_INFO BIT(28)
#define MT_WFDMA1_GLO_CFG_OMIT_RX_INFO BIT(27)
+#define MT_WFDMA1_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21)
#define MT_WFDMA1_RST_DTX_PTR MT_WFDMA1(0x20c)
#define MT_WFDMA1_PRI_DLY_INT_CFG0 MT_WFDMA1(0x2f0)
-#define MT_WFDMA1_TX_RING0_EXT_CTRL MT_WFDMA1(0x600)
-#define MT_WFDMA1_TX_RING1_EXT_CTRL MT_WFDMA1(0x604)
-#define MT_WFDMA1_TX_RING2_EXT_CTRL MT_WFDMA1(0x608)
-#define MT_WFDMA1_TX_RING3_EXT_CTRL MT_WFDMA1(0x60c)
-#define MT_WFDMA1_TX_RING4_EXT_CTRL MT_WFDMA1(0x610)
-#define MT_WFDMA1_TX_RING5_EXT_CTRL MT_WFDMA1(0x614)
-#define MT_WFDMA1_TX_RING6_EXT_CTRL MT_WFDMA1(0x618)
-#define MT_WFDMA1_TX_RING7_EXT_CTRL MT_WFDMA1(0x61c)
-
-#define MT_WFDMA1_TX_RING16_EXT_CTRL MT_WFDMA1(0x640)
-#define MT_WFDMA1_TX_RING17_EXT_CTRL MT_WFDMA1(0x644)
-#define MT_WFDMA1_TX_RING18_EXT_CTRL MT_WFDMA1(0x648)
-#define MT_WFDMA1_TX_RING19_EXT_CTRL MT_WFDMA1(0x64c)
-#define MT_WFDMA1_TX_RING20_EXT_CTRL MT_WFDMA1(0x650)
#define MT_WFDMA1_TX_RING21_EXT_CTRL MT_WFDMA1(0x654)
-#define MT_WFDMA1_TX_RING22_EXT_CTRL MT_WFDMA1(0x658)
-#define MT_WFDMA1_TX_RING23_EXT_CTRL MT_WFDMA1(0x65c)
-
-#define MT_WFDMA1_RX_RING0_EXT_CTRL MT_WFDMA1(0x680)
-#define MT_WFDMA1_RX_RING1_EXT_CTRL MT_WFDMA1(0x684)
-#define MT_WFDMA1_RX_RING2_EXT_CTRL MT_WFDMA1(0x688)
#define MT_WFDMA1_RX_RING3_EXT_CTRL MT_WFDMA1(0x68c)
/* WFDMA CSR */
@@ -662,8 +658,21 @@ enum bit_rev {
#define MT_INT1_SOURCE_CSR __REG(dev, INT1_SOURCE_CSR)
#define MT_INT1_MASK_CSR __REG(dev, INT1_MASK_CSR)
+#define MT_WFDMA_TX_RING_EXT_CTRL_FWDL __REG(dev, TX_RING_CTRL_FWDL)
+#define MT_WFDMA_TX_RING_EXT_CTRL_WM __REG(dev, TX_RING_CTRL_WM)
+#define MT_WFDMA_TX_RING_EXT_CTRL_BAND0 __REG(dev, TX_RING_CTRL_BAND0)
+#define MT_WFDMA_TX_RING_EXT_CTRL_BAND1 __REG(dev, TX_RING_CTRL_BAND1)
+#define MT_WFDMA_TX_RING_EXT_CTRL_WA __REG(dev, TX_RING_CTRL_WA)
+#define MT_WFDMA_RX_RING_EXT_CTRL_WM __REG(dev, RX_RING_CTRL_WM)
+#define MT_WFDMA_RX_RING_EXT_CTRL_WA __REG(dev, RX_RING_CTRL_WA)
+#define MT_WFDMA_RX_RING_EXT_CTRL_STS0 __REG(dev, RX_RING_CTRL_STS0)
+#define MT_WFDMA_RX_RING_EXT_CTRL_STS1 __REG(dev, RX_RING_CTRL_STS1)
+#define MT_WFDMA_RX_RING_EXT_CTRL_BAND0 __REG(dev, RX_RING_CTRL_BAND0)
+#define MT_WFDMA_RX_RING_EXT_CTRL_BAND1 __REG(dev, RX_RING_CTRL_BAND1)
+
#define MT_TX_RING_BASE __REG(dev, TX_RING_BASE)
#define MT_RX_EVENT_RING_BASE __REG(dev, RX_EVENT_RING_BASE)
+#define MT_RX_STS_RING_BASE __REG(dev, RX_STS_RING_BASE)
#define MT_RX_DATA_RING_BASE __REG(dev, RX_DATA_RING_BASE)
#define MT_INT_RX_DONE_DATA0 __BIT(dev, RX_DONE_DAND0)
@@ -796,6 +805,13 @@ enum bit_rev {
#define MT_PCIE1_MAC(ofs) __REG_MAP(dev, MT_PCIE1_MAC_BASE, (ofs))
#define MT_PCIE1_MAC_INT_ENABLE MT_PCIE1_MAC(0x188)
+/* PP TOP */
+#define MT_WF_PP_TOP_BASE 0x820cc000
+#define MT_WF_PP_TOP(ofs) (MT_WF_PP_TOP_BASE + (ofs))
+
+#define MT_WF_PP_TOP_RXQ_WFDMA_CF_5 MT_WF_PP_TOP(0x0e8)
+#define MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK BIT(6)
+
#define MT_WF_IRPI_BASE 0x83006000
#define MT_WF_IRPI(ofs) (MT_WF_IRPI_BASE + ((ofs) << 16))
--
2.18.0
From: Bo Jiao <[email protected]>
Update txfree v3 format.
This is an intermediate patch to add mt7916 support.
Co-developed-by: Sujuan Chen <[email protected]>
Signed-off-by: Sujuan Chen <[email protected]>
Co-developed-by: Ryder Lee <[email protected]>
Signed-off-by: Ryder Lee <[email protected]>
Signed-off-by: Bo Jiao <[email protected]>
Reviewed-by: Shayne Chen <[email protected]>
---
.../net/wireless/mediatek/mt76/mt7915/mac.c | 42 ++++++++++++-------
.../net/wireless/mediatek/mt76/mt7915/mac.h | 8 ++--
2 files changed, 32 insertions(+), 18 deletions(-)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
index 40e8252..8e3901b 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
@@ -1366,8 +1366,10 @@ mt7915_mac_tx_free(struct mt7915_dev *dev, struct sk_buff *skb)
struct ieee80211_sta *sta = NULL;
LIST_HEAD(free_list);
struct sk_buff *tmp;
- u8 i, count;
- bool wake = false;
+ bool v3, wake = false;
+ u16 total, count = 0;
+ u32 txd = le32_to_cpu(free->txd);
+ u32 *cur_info;
/* clean DMA queues and unmap buffers first */
mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false);
@@ -1377,14 +1379,12 @@ mt7915_mac_tx_free(struct mt7915_dev *dev, struct sk_buff *skb)
mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_BE], false);
}
- /*
- * TODO: MT_TX_FREE_LATENCY is msdu time from the TXD is queued into PLE,
- * to the time ack is received or dropped by hw (air + hw queue time).
- * Should avoid accessing WTBL to get Tx airtime, and use it instead.
- */
- count = FIELD_GET(MT_TX_FREE_MSDU_CNT, le16_to_cpu(free->ctrl));
- for (i = 0; i < count; i++) {
- u32 msdu, info = le32_to_cpu(free->info[i]);
+ total = FIELD_GET(MT_TX_FREE_MSDU_CNT, le16_to_cpu(free->ctrl));
+ v3 = (FIELD_GET(MT_TX_FREE_VER, txd) == 0x4);
+
+ for (cur_info = &free->info[0]; count < total; cur_info++) {
+ u32 msdu, info = le32_to_cpu(*cur_info);
+ u8 i;
/*
* 1'b1: new wcid pair.
@@ -1395,7 +1395,6 @@ mt7915_mac_tx_free(struct mt7915_dev *dev, struct sk_buff *skb)
struct mt76_wcid *wcid;
u16 idx;
- count++;
idx = FIELD_GET(MT_TX_FREE_WLAN_ID, info);
wcid = rcu_dereference(dev->mt76.wcid[idx]);
sta = wcid_to_sta(wcid);
@@ -1410,12 +1409,25 @@ mt7915_mac_tx_free(struct mt7915_dev *dev, struct sk_buff *skb)
continue;
}
- msdu = FIELD_GET(MT_TX_FREE_MSDU_ID, info);
- txwi = mt76_token_release(mdev, msdu, &wake);
- if (!txwi)
+ if (v3 && (info & MT_TX_FREE_MPDU_HEADER))
continue;
- mt7915_txwi_free(dev, txwi, sta, &free_list);
+ for (i = 0; i < 1 + v3; i++) {
+ if (v3) {
+ msdu = (info >> (15 * i)) & MT_TX_FREE_MSDU_ID_V3;
+ if (msdu == MT_TX_FREE_MSDU_ID_V3)
+ continue;
+ } else {
+ msdu = FIELD_GET(MT_TX_FREE_MSDU_ID, info);
+ }
+
+ txwi = mt76_token_release(mdev, msdu, &wake);
+ if (!txwi)
+ continue;
+
+ mt7915_txwi_free(dev, txwi, sta, &free_list);
+ count++;
+ }
}
mt7915_mac_sta_poll(dev);
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mac.h b/drivers/net/wireless/mediatek/mt76/mt7915/mac.h
index 7a2c740..4504ebc 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mac.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mac.h
@@ -298,18 +298,20 @@ struct mt7915_txp {
struct mt7915_tx_free {
__le16 rx_byte_cnt;
__le16 ctrl;
- u8 txd_cnt;
- u8 rsv[3];
+ __le32 txd;
__le32 info[];
} __packed __aligned(4);
+#define MT_TX_FREE_VER GENMASK(18, 16)
#define MT_TX_FREE_MSDU_CNT GENMASK(9, 0)
#define MT_TX_FREE_WLAN_ID GENMASK(23, 14)
#define MT_TX_FREE_LATENCY GENMASK(12, 0)
/* 0: success, others: dropped */
-#define MT_TX_FREE_STATUS GENMASK(14, 13)
#define MT_TX_FREE_MSDU_ID GENMASK(30, 16)
#define MT_TX_FREE_PAIR BIT(31)
+#define MT_TX_FREE_MPDU_HEADER BIT(30)
+#define MT_TX_FREE_MSDU_ID_V3 GENMASK(14, 0)
+
/* will support this field in further revision */
#define MT_TX_FREE_RATE GENMASK(13, 0)
--
2.18.0
From: Bo Jiao <[email protected]>
Add mt7915_reg_desc to differentiate chip generations.
This is an intermediate patch to introduce mt7916 support.
Co-developed-by: Sujuan Chen <[email protected]>
Signed-off-by: Sujuan Chen <[email protected]>
Co-developed-by: Ryder Lee <[email protected]>
Signed-off-by: Ryder Lee <[email protected]>
Signed-off-by: Bo Jiao <[email protected]>
---
.../wireless/mediatek/mt76/mt7915/debugfs.c | 20 +-
.../net/wireless/mediatek/mt76/mt7915/dma.c | 5 +-
.../net/wireless/mediatek/mt76/mt7915/mac.c | 26 +-
.../net/wireless/mediatek/mt76/mt7915/mmio.c | 507 +++++++++++++--
.../wireless/mediatek/mt76/mt7915/mt7915.h | 4 +-
.../net/wireless/mediatek/mt76/mt7915/regs.h | 607 ++++++++++++------
.../wireless/mediatek/mt76/mt7915/testmode.c | 58 +-
7 files changed, 907 insertions(+), 320 deletions(-)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c b/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c
index a15aa25..fa7553f 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c
@@ -302,14 +302,14 @@ mt7915_tx_stats_show(struct seq_file *file, void *data)
DEFINE_SHOW_ATTRIBUTE(mt7915_tx_stats);
static void
-mt7915_hw_queue_read(struct seq_file *s, u32 base, u32 size,
+mt7915_hw_queue_read(struct seq_file *s, u32 size,
const struct hw_queue_map *map)
{
struct mt7915_phy *phy = s->private;
struct mt7915_dev *dev = phy->dev;
u32 i, val;
- val = mt76_rr(dev, base + MT_FL_Q_EMPTY);
+ val = mt76_rr(dev, MT_FL_Q_EMPTY);
for (i = 0; i < size; i++) {
u32 ctrl, head, tail, queued;
@@ -317,13 +317,13 @@ mt7915_hw_queue_read(struct seq_file *s, u32 base, u32 size,
continue;
ctrl = BIT(31) | (map[i].pid << 10) | (map[i].qid << 24);
- mt76_wr(dev, base + MT_FL_Q0_CTRL, ctrl);
+ mt76_wr(dev, MT_FL_Q0_CTRL, ctrl);
- head = mt76_get_field(dev, base + MT_FL_Q2_CTRL,
+ head = mt76_get_field(dev, MT_FL_Q2_CTRL,
GENMASK(11, 0));
- tail = mt76_get_field(dev, base + MT_FL_Q2_CTRL,
+ tail = mt76_get_field(dev, MT_FL_Q2_CTRL,
GENMASK(27, 16));
- queued = mt76_get_field(dev, base + MT_FL_Q3_CTRL,
+ queued = mt76_get_field(dev, MT_FL_Q3_CTRL,
GENMASK(11, 0));
seq_printf(s, "\t%s: ", map[i].name);
@@ -351,8 +351,8 @@ mt7915_sta_hw_queue_read(void *data, struct ieee80211_sta *sta)
if (val & BIT(offs))
continue;
- mt76_wr(dev, MT_PLE_BASE + MT_FL_Q0_CTRL, ctrl | msta->wcid.idx);
- qlen = mt76_get_field(dev, MT_PLE_BASE + MT_FL_Q3_CTRL,
+ mt76_wr(dev, MT_FL_Q0_CTRL, ctrl | msta->wcid.idx);
+ qlen = mt76_get_field(dev, MT_FL_Q3_CTRL,
GENMASK(11, 0));
seq_printf(s, "\tSTA %pM wcid %d: AC%d%d queued:%d\n",
sta->addr, msta->wcid.idx, msta->vif->wmm_idx,
@@ -414,7 +414,7 @@ mt7915_hw_queues_show(struct seq_file *file, void *data)
val, head, tail);
seq_puts(file, "PLE non-empty queue info:\n");
- mt7915_hw_queue_read(file, MT_PLE_BASE, ARRAY_SIZE(ple_queue_map),
+ mt7915_hw_queue_read(file, ARRAY_SIZE(ple_queue_map),
&ple_queue_map[0]);
/* iterate per-sta ple queue */
@@ -422,7 +422,7 @@ mt7915_hw_queues_show(struct seq_file *file, void *data)
mt7915_sta_hw_queue_read, file);
/* pse queue */
seq_puts(file, "PSE non-empty queue info:\n");
- mt7915_hw_queue_read(file, MT_PSE_BASE, ARRAY_SIZE(pse_queue_map),
+ mt7915_hw_queue_read(file, ARRAY_SIZE(pse_queue_map),
&pse_queue_map[0]);
return 0;
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/dma.c b/drivers/net/wireless/mediatek/mt76/mt7915/dma.c
index 9182568..ad9678b 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/dma.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/dma.c
@@ -7,6 +7,7 @@
int mt7915_init_tx_queues(struct mt7915_phy *phy, int idx, int n_desc)
{
+ struct mt7915_dev *dev = phy->dev;
int i, err;
err = mt76_init_tx_queue(phy->mt76, 0, idx, n_desc, MT_TX_RING_BASE);
@@ -74,7 +75,7 @@ void mt7915_dma_prefetch(struct mt7915_dev *dev)
{
__mt7915_dma_prefetch(dev, 0);
if (dev->hif2)
- __mt7915_dma_prefetch(dev, MT_WFDMA1_PCIE1_BASE - MT_WFDMA1_BASE);
+ __mt7915_dma_prefetch(dev, MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0));
}
int mt7915_dma_init(struct mt7915_dev *dev)
@@ -85,7 +86,7 @@ int mt7915_dma_init(struct mt7915_dev *dev)
mt76_dma_attach(&dev->mt76);
if (dev->hif2)
- hif1_ofs = MT_WFDMA1_PCIE1_BASE - MT_WFDMA1_BASE;
+ hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
/* configure global setting */
mt76_set(dev, MT_WFDMA1_GLO_CFG,
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
index 60e8340..d808437 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
@@ -1847,7 +1847,7 @@ static void
mt7915_dma_reset(struct mt7915_dev *dev)
{
struct mt76_phy *mphy_ext = dev->mt76.phy2;
- u32 hif1_ofs = MT_WFDMA1_PCIE1_BASE - MT_WFDMA1_BASE;
+ u32 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
int i;
mt76_clear(dev, MT_WFDMA0_GLO_CFG,
@@ -2009,8 +2009,8 @@ void mt7915_mac_update_stats(struct mt7915_phy *phy)
bool ext_phy = phy != &dev->phy;
int i, aggr0, aggr1, cnt;
- mib->fcs_err_cnt += mt76_get_field(dev, MT_MIB_SDR3(ext_phy),
- MT_MIB_SDR3_FCS_ERR_MASK);
+ cnt = mt76_rr(dev, MT_MIB_SDR3(ext_phy));
+ mib->fcs_err_cnt += __FIELD_GET(MIB_SDR3_FCS_ERR, cnt);
cnt = mt76_rr(dev, MT_MIB_SDR4(ext_phy));
mib->rx_fifo_full_cnt += FIELD_GET(MT_MIB_SDR4_RX_FIFO_FULL_MASK, cnt);
@@ -2037,10 +2037,10 @@ void mt7915_mac_update_stats(struct mt7915_phy *phy)
mib->tx_stop_q_empty_cnt += FIELD_GET(MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK, cnt);
cnt = mt76_rr(dev, MT_MIB_SDR14(ext_phy));
- mib->tx_mpdu_attempts_cnt += FIELD_GET(MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK, cnt);
+ mib->tx_mpdu_attempts_cnt += __FIELD_GET(MIB_MPDU_ATTEMPTS_CNT, cnt);
cnt = mt76_rr(dev, MT_MIB_SDR15(ext_phy));
- mib->tx_mpdu_success_cnt += FIELD_GET(MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK, cnt);
+ mib->tx_mpdu_success_cnt += __FIELD_GET(MIB_MPDU_SUCCESS_CNT, cnt);
cnt = mt76_rr(dev, MT_MIB_SDR22(ext_phy));
mib->rx_ampdu_cnt += cnt;
@@ -2049,7 +2049,7 @@ void mt7915_mac_update_stats(struct mt7915_phy *phy)
mib->rx_ampdu_bytes_cnt += cnt;
cnt = mt76_rr(dev, MT_MIB_SDR24(ext_phy));
- mib->rx_ampdu_valid_subframe_cnt += FIELD_GET(MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK, cnt);
+ mib->rx_ampdu_valid_subframe_cnt += __FIELD_GET(MIB_AMPDU_SF_CNT, cnt);
cnt = mt76_rr(dev, MT_MIB_SDR25(ext_phy));
mib->rx_ampdu_valid_subframe_bytes_cnt += cnt;
@@ -2061,11 +2061,10 @@ void mt7915_mac_update_stats(struct mt7915_phy *phy)
mib->tx_rwp_need_cnt += FIELD_GET(MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK, cnt);
cnt = mt76_rr(dev, MT_MIB_SDR29(ext_phy));
- mib->rx_pfdrop_cnt += FIELD_GET(MT_MIB_SDR29_RX_PFDROP_CNT_MASK, cnt);
+ mib->rx_pfdrop_cnt += __FIELD_GET(MIB_PF_DROP_CNT, cnt);
- cnt = mt76_rr(dev, MT_MIB_SDR30(ext_phy));
- mib->rx_vec_queue_overflow_drop_cnt +=
- FIELD_GET(MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK, cnt);
+ cnt = mt76_rr(dev, MT_MIB_SDRVEC(ext_phy));
+ mib->rx_vec_queue_overflow_drop_cnt += __FIELD_GET(MIB_VEC_DROP_CNT, cnt);
cnt = mt76_rr(dev, MT_MIB_SDR31(ext_phy));
mib->rx_ba_cnt += cnt;
@@ -2073,10 +2072,11 @@ void mt7915_mac_update_stats(struct mt7915_phy *phy)
cnt = mt76_rr(dev, MT_MIB_SDR32(ext_phy));
mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT_MASK, cnt);
- cnt = mt76_rr(dev, MT_MIB_SDR33(ext_phy));
- mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR33_TX_PKT_IBF_CNT_MASK, cnt);
+ if (is_mt7915(&dev->mt76))
+ cnt = mt76_rr(dev, MT_MIB_SDR33(ext_phy));
+ mib->tx_pkt_ibf_cnt += __FIELD_GET(MIB_BF_TX_CNT, cnt);
- cnt = mt76_rr(dev, MT_MIB_SDR34(ext_phy));
+ cnt = mt76_rr(dev, MT_MIB_SDRMUBF(ext_phy));
mib->tx_bf_cnt += FIELD_GET(MT_MIB_MU_BF_TX_CNT, cnt);
cnt = mt76_rr(dev, MT_MIB_DR8(ext_phy));
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mmio.c b/drivers/net/wireless/mediatek/mt76/mt7915/mmio.c
index 2f8b72b..0d67321 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mmio.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mmio.c
@@ -10,100 +10,449 @@
#include "mac.h"
#include "../trace.h"
+static const u32 mt7915_base[] = {
+ [MT_REMAP_L1_CFG_BASE] = 0xf1000,
+ [MT_REMAP_L1_BASE] = 0xe0000,
+ [MT_REMAP_L2_CFG_BASE] = 0xf1000,
+ [MT_REMAP_L2_BASE] = 0x00000,
+ [MT_INFRA_MCU_END_BASE] = 0x7c3fffff,
+ [MT_PCIE_MAC_BASE] = 0x74030000,
+ [MT_PCIE1_MAC_BASE] = 0x74020000,
+ [MT_WFDMA0_BASE] = 0xd4000,
+ [MT_WFDMA1_BASE] = 0xd5000,
+ [MT_WFDMA0_PCIE1_BASE] = 0xd8000,
+ [MT_WFDMA1_PCIE1_BASE] = 0xd9000,
+ [MT_WFDMA_EXT_CSR_BASE] = 0xd7000,
+ [MT_SWDEF_BASE] = 0x41f200,
+ [MT_MCU_WFDMA0_BASE] = 0x2000,
+ [MT_MCU_WFDMA1_BASE] = 0x3000,
+};
+
+static const u32 mt7916_base[] = {
+ [MT_REMAP_L1_CFG_BASE] = 0xfe000,
+ [MT_REMAP_L1_BASE] = 0xe0000,
+ [MT_REMAP_L2_CFG_BASE] = 0x00000,
+ [MT_REMAP_L2_BASE] = 0x40000,
+ [MT_INFRA_MCU_END_BASE] = 0x7c085fff,
+ [MT_PCIE_MAC_BASE] = 0x74030000,
+ [MT_PCIE1_MAC_BASE] = 0x74090000,
+ [MT_WFDMA0_BASE] = 0xd4000,
+ [MT_WFDMA1_BASE] = 0xd5000,
+ [MT_WFDMA0_PCIE1_BASE] = 0xd8000,
+ [MT_WFDMA1_PCIE1_BASE] = 0xd9000,
+ [MT_WFDMA_EXT_CSR_BASE] = 0xd7000,
+ [MT_SWDEF_BASE] = 0x411400,
+ [MT_MCU_WFDMA0_BASE] = 0x2000,
+ [MT_MCU_WFDMA1_BASE] = 0x3000,
+};
+
+static const struct __reg mt7915_reg[] = {
+ [L1_REMAP_CFG_OFFSET] = { MT_REMAP_L1_CFG_BASE, 0x1ac },
+ [L2_REMAP_CFG_OFFSET] = { MT_REMAP_L2_CFG_BASE, 0x1b0 },
+ [INT_SOURCE_CSR] = { MT_WFDMA_EXT_CSR_BASE, 0x10 },
+ [INT_MASK_CSR] = { MT_WFDMA_EXT_CSR_BASE, 0x14 },
+ [INT1_SOURCE_CSR] = { MT_WFDMA_EXT_CSR_BASE, 0x88 },
+ [INT1_MASK_CSR] = { MT_WFDMA_EXT_CSR_BASE, 0x8c },
+ [INT_MCU_CMD_SOURCE] = { MT_WFDMA1_BASE, 0x1f0 },
+ [INT_MCU_CMD_EVENT] = { MT_MCU_WFDMA1_BASE, 0x108 },
+ [TX_RING_BASE] = { MT_WFDMA1_BASE, 0x400 },
+ [RX_EVENT_RING_BASE] = { MT_WFDMA1_BASE, 0x500 },
+ [RX_DATA_RING_BASE] = { MT_WFDMA0_BASE, 0x500 },
+ [TMAC_CDTR] = { INVALID_BASE, 0x090 },
+ [TMAC_ODTR] = { INVALID_BASE, 0x094 },
+ [TMAC_ATCR] = { INVALID_BASE, 0x098 },
+ [TMAC_TRCR0] = { INVALID_BASE, 0x09c },
+ [TMAC_ICR0] = { INVALID_BASE, 0x0a4 },
+ [TMAC_ICR1] = { INVALID_BASE, 0x0b4 },
+ [TMAC_CTCR0] = { INVALID_BASE, 0x0f4 },
+ [TMAC_TFCR0] = { INVALID_BASE, 0x1e0 },
+ [MDP_BNRCFR0] = { INVALID_BASE, 0x070 },
+ [MDP_BNRCFR1] = { INVALID_BASE, 0x074 },
+ [ARB_DRNGR0] = { INVALID_BASE, 0x194 },
+ [ARB_SCR] = { INVALID_BASE, 0x080 },
+ [RMAC_MIB_AIRTIME14] = { INVALID_BASE, 0x3b8 },
+ [AGG_AWSCR0] = { INVALID_BASE, 0x05c },
+ [AGG_PCR0] = { INVALID_BASE, 0x06c },
+ [AGG_ACR0] = { INVALID_BASE, 0x084 },
+ [AGG_MRCR] = { INVALID_BASE, 0x098 },
+ [AGG_ATCR1] = { INVALID_BASE, 0x0f0 },
+ [AGG_ATCR3] = { INVALID_BASE, 0x0f4 },
+ [LPON_UTTR0] = { INVALID_BASE, 0x080 },
+ [LPON_UTTR1] = { INVALID_BASE, 0x084 },
+ [MIB_SDR3] = { INVALID_BASE, 0x014 },
+ [MIB_SDR4] = { INVALID_BASE, 0x018 },
+ [MIB_SDR5] = { INVALID_BASE, 0x01c },
+ [MIB_SDR7] = { INVALID_BASE, 0x024 },
+ [MIB_SDR8] = { INVALID_BASE, 0x028 },
+ [MIB_SDR9] = { INVALID_BASE, 0x02c },
+ [MIB_SDR10] = { INVALID_BASE, 0x030 },
+ [MIB_SDR11] = { INVALID_BASE, 0x034 },
+ [MIB_SDR12] = { INVALID_BASE, 0x038 },
+ [MIB_SDR13] = { INVALID_BASE, 0x03c },
+ [MIB_SDR14] = { INVALID_BASE, 0x040 },
+ [MIB_SDR15] = { INVALID_BASE, 0x044 },
+ [MIB_SDR16] = { INVALID_BASE, 0x048 },
+ [MIB_SDR17] = { INVALID_BASE, 0x04c },
+ [MIB_SDR18] = { INVALID_BASE, 0x050 },
+ [MIB_SDR19] = { INVALID_BASE, 0x054 },
+ [MIB_SDR20] = { INVALID_BASE, 0x058 },
+ [MIB_SDR21] = { INVALID_BASE, 0x05c },
+ [MIB_SDR22] = { INVALID_BASE, 0x060 },
+ [MIB_SDR23] = { INVALID_BASE, 0x064 },
+ [MIB_SDR24] = { INVALID_BASE, 0x068 },
+ [MIB_SDR25] = { INVALID_BASE, 0x06c },
+ [MIB_SDR27] = { INVALID_BASE, 0x074 },
+ [MIB_SDR28] = { INVALID_BASE, 0x078 },
+ [MIB_SDR29] = { INVALID_BASE, 0x07c },
+ [MIB_SDRVEC] = { INVALID_BASE, 0x080 },
+ [MIB_SDR31] = { INVALID_BASE, 0x084 },
+ [MIB_SDR32] = { INVALID_BASE, 0x088 },
+ [MIB_SDRMUBF] = { INVALID_BASE, 0x090 },
+ [MIB_DR8] = { INVALID_BASE, 0x0c0 },
+ [MIB_DR9] = { INVALID_BASE, 0x0c4 },
+ [MIB_DR11] = { INVALID_BASE, 0x0cc },
+ [MIB_MB_SDR0] = { INVALID_BASE, 0x100 },
+ [MIB_MB_SDR1] = { INVALID_BASE, 0x104 },
+ [TX_AGG_CNT] = { INVALID_BASE, 0x0a8 },
+ [TX_AGG_CNT2] = { INVALID_BASE, 0x164 },
+ [MIB_ARNG] = { INVALID_BASE, 0x4b8 },
+ [WTBLON_TOP_WDUCR] = { INVALID_BASE, 0x0},
+ [WTBL_UPDATE] = { INVALID_BASE, 0x030},
+ [PLE_FL_Q_EMPTY] = { INVALID_BASE, 0x0b0},
+ [PLE_FL_Q_CTRL] = { INVALID_BASE, 0x1b0},
+ [PLE_AC_QEMPTY] = { INVALID_BASE, 0x500},
+ [PLE_FREEPG_CNT] = { INVALID_BASE, 0x100},
+ [PLE_FREEPG_HEAD_TAIL] = { INVALID_BASE, 0x104},
+ [PLE_PG_HIF_GROUP] = { INVALID_BASE, 0x110},
+ [PLE_HIF_PG_INFO] = { INVALID_BASE, 0x114},
+ [AC_OFFSET] = { INVALID_BASE, 0x040},
+};
+
+static const struct __reg mt7916_reg[] = {
+ [L1_REMAP_CFG_OFFSET] = { MT_REMAP_L1_CFG_BASE, 0x260 },
+ [L2_REMAP_CFG_OFFSET] = { MT_REMAP_L2_CFG_BASE, 0x1b8 },
+ [INT_SOURCE_CSR] = { MT_WFDMA0_BASE, 0x200 },
+ [INT_MASK_CSR] = { MT_WFDMA0_BASE, 0x204 },
+ [INT1_SOURCE_CSR] = { MT_WFDMA0_PCIE1_BASE, 0x200 },
+ [INT1_MASK_CSR] = { MT_WFDMA0_PCIE1_BASE, 0x204 },
+ [INT_MCU_CMD_SOURCE] = { MT_WFDMA0_BASE, 0x1f0 },
+ [INT_MCU_CMD_EVENT] = { MT_MCU_WFDMA0_BASE, 0x108 },
+ [TX_RING_BASE] = { MT_WFDMA0_BASE, 0x400 },
+ [RX_EVENT_RING_BASE] = { MT_WFDMA0_BASE, 0x500 },
+ [RX_DATA_RING_BASE] = { MT_WFDMA0_BASE, 0x540 },
+ [TMAC_CDTR] = { INVALID_BASE, 0x0c8 },
+ [TMAC_ODTR] = { INVALID_BASE, 0x0cc },
+ [TMAC_ATCR] = { INVALID_BASE, 0x00c },
+ [TMAC_TRCR0] = { INVALID_BASE, 0x010 },
+ [TMAC_ICR0] = { INVALID_BASE, 0x014 },
+ [TMAC_ICR1] = { INVALID_BASE, 0x018 },
+ [TMAC_CTCR0] = { INVALID_BASE, 0x114 },
+ [TMAC_TFCR0] = { INVALID_BASE, 0x0e4 },
+ [MDP_BNRCFR0] = { INVALID_BASE, 0x090 },
+ [MDP_BNRCFR1] = { INVALID_BASE, 0x094 },
+ [ARB_DRNGR0] = { INVALID_BASE, 0x1e0 },
+ [ARB_SCR] = { INVALID_BASE, 0x000 },
+ [RMAC_MIB_AIRTIME14] = { INVALID_BASE, 0x0398 },
+ [AGG_AWSCR0] = { INVALID_BASE, 0x030 },
+ [AGG_PCR0] = { INVALID_BASE, 0x040 },
+ [AGG_ACR0] = { INVALID_BASE, 0x054 },
+ [AGG_MRCR] = { INVALID_BASE, 0x068 },
+ [AGG_ATCR1] = { INVALID_BASE, 0x1a8 },
+ [AGG_ATCR3] = { INVALID_BASE, 0x080 },
+ [LPON_UTTR0] = { INVALID_BASE, 0x360 },
+ [LPON_UTTR1] = { INVALID_BASE, 0x364 },
+ [MIB_SDR3] = { INVALID_BASE, 0x698 },
+ [MIB_SDR4] = { INVALID_BASE, 0x788 },
+ [MIB_SDR5] = { INVALID_BASE, 0x780 },
+ [MIB_SDR7] = { INVALID_BASE, 0x5a8 },
+ [MIB_SDR8] = { INVALID_BASE, 0x78c },
+ [MIB_SDR9] = { INVALID_BASE, 0x024 },
+ [MIB_SDR10] = { INVALID_BASE, 0x76c },
+ [MIB_SDR11] = { INVALID_BASE, 0x790 },
+ [MIB_SDR12] = { INVALID_BASE, 0x558 },
+ [MIB_SDR13] = { INVALID_BASE, 0x560 },
+ [MIB_SDR14] = { INVALID_BASE, 0x564 },
+ [MIB_SDR15] = { INVALID_BASE, 0x568 },
+ [MIB_SDR16] = { INVALID_BASE, 0x7fc },
+ [MIB_SDR17] = { INVALID_BASE, 0x800 },
+ [MIB_SDR18] = { INVALID_BASE, 0x030 },
+ [MIB_SDR19] = { INVALID_BASE, 0x5ac },
+ [MIB_SDR20] = { INVALID_BASE, 0x5b0 },
+ [MIB_SDR21] = { INVALID_BASE, 0x5b4 },
+ [MIB_SDR22] = { INVALID_BASE, 0x770 },
+ [MIB_SDR23] = { INVALID_BASE, 0x774 },
+ [MIB_SDR24] = { INVALID_BASE, 0x778 },
+ [MIB_SDR25] = { INVALID_BASE, 0x77c },
+ [MIB_SDR27] = { INVALID_BASE, 0x080 },
+ [MIB_SDR28] = { INVALID_BASE, 0x084 },
+ [MIB_SDR29] = { INVALID_BASE, 0x650 },
+ [MIB_SDRVEC] = { INVALID_BASE, 0x5a8 },
+ [MIB_SDR31] = { INVALID_BASE, 0x55c },
+ [MIB_SDR32] = { INVALID_BASE, 0x7a8 },
+ [MIB_SDRMUBF] = { INVALID_BASE, 0x7ac },
+ [MIB_DR8] = { INVALID_BASE, 0x56c },
+ [MIB_DR9] = { INVALID_BASE, 0x570 },
+ [MIB_DR11] = { INVALID_BASE, 0x574 },
+ [MIB_MB_SDR0] = { INVALID_BASE, 0x688 },
+ [MIB_MB_SDR1] = { INVALID_BASE, 0x690 },
+ [TX_AGG_CNT] = { INVALID_BASE, 0x7dc },
+ [TX_AGG_CNT2] = { INVALID_BASE, 0x7ec },
+ [MIB_ARNG] = { INVALID_BASE, 0x0b0 },
+ [WTBLON_TOP_WDUCR] = { INVALID_BASE, 0x200},
+ [WTBL_UPDATE] = { INVALID_BASE, 0x230},
+ [PLE_FL_Q_EMPTY] = { INVALID_BASE, 0x360},
+ [PLE_FL_Q_CTRL] = { INVALID_BASE, 0x3e0},
+ [PLE_AC_QEMPTY] = { INVALID_BASE, 0x600},
+ [PLE_FREEPG_CNT] = { INVALID_BASE, 0x380},
+ [PLE_FREEPG_HEAD_TAIL] = { INVALID_BASE, 0x384},
+ [PLE_PG_HIF_GROUP] = { INVALID_BASE, 0x00c},
+ [PLE_HIF_PG_INFO] = { INVALID_BASE, 0x388},
+ [AC_OFFSET] = { INVALID_BASE, 0x080},
+};
+
+static const struct __mask mt7915_mask[] = {
+ [L2_REMAP_MASK] = {19, 0},
+ [L2_REMAP_OFFSET] = {11, 0},
+ [L2_REMAP_BASE] = {31, 12},
+ [MIB_SDR3_FCS_ERR] = {15, 0},
+ [MIB_MRDY_CNT] = {25, 0},
+ [MIB_MPDU_ATTEMPTS_CNT] = {23, 0},
+ [MIB_MPDU_SUCCESS_CNT] = {23, 0},
+ [MIB_AMPDU_SF_CNT] = {23, 0},
+ [MIB_PF_DROP_CNT] = {7, 0},
+ [MIB_VEC_DROP_CNT] = {15, 0},
+ [MIB_BF_TX_CNT] = {15, 0},
+};
+
+static const struct __mask mt7916_mask[] = {
+ [L2_REMAP_MASK] = {31, 16},
+ [L2_REMAP_OFFSET] = {15, 0},
+ [L2_REMAP_BASE] = {31, 16},
+ [MIB_SDR3_FCS_ERR] = {31, 16},
+ [MIB_MRDY_CNT] = {31, 0},
+ [MIB_MPDU_ATTEMPTS_CNT] = {31, 0},
+ [MIB_MPDU_SUCCESS_CNT] = {31, 0},
+ [MIB_AMPDU_SF_CNT] = {31, 0},
+ [MIB_PF_DROP_CNT] = {15, 0},
+ [MIB_VEC_DROP_CNT] = {31, 16},
+ [MIB_BF_TX_CNT] = {31, 16},
+};
+
+static const u32 mt7915_bit[] = {
+ [RX_DONE_DAND0] = 16,
+ [RX_DONE_DAND1] = 17,
+ [RX_DONE_MCU_WM] = 0,
+ [RX_DONE_MCU_WA] = 1,
+ [RX_DONE_WA_BAND0] = 1,
+ [RX_DONE_WA_BAND1] = 2,
+ [TX_DONE_FWDL] = 26,
+ [TX_DONE_MCU_WM] = 27,
+ [TX_DONE_MCU_WA] = 15,
+ [TX_DONE_BAND0] = 30,
+ [TX_DONE_BAND1] = 31,
+ [RX_MCU_TO_HOST] = 29,
+ [MIB_MB_SDR] = 2,
+ [LPON_TCR] = 0,
+};
+
+static const u32 mt7916_bit[] = {
+ [RX_DONE_DAND0] = 22,
+ [RX_DONE_DAND1] = 23,
+ [RX_DONE_MCU_WM] = 0,
+ [RX_DONE_MCU_WA] = 1,
+ [RX_DONE_WA_BAND0] = 2,
+ [RX_DONE_WA_BAND1] = 3,
+ [TX_DONE_FWDL] = 26,
+ [TX_DONE_MCU_WM] = 27,
+ [TX_DONE_MCU_WA] = 25,
+ [TX_DONE_BAND0] = 30,
+ [TX_DONE_BAND1] = 31,
+ [RX_MCU_TO_HOST] = 29,
+ [MIB_MB_SDR] = 1,
+ [LPON_TCR] = 2,
+};
+
+static const struct __map mt7915_reg_map[] = {
+ { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
+ { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure regs) */
+ { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
+ { 0x54000000, 0x02000, 0x1000 }, /* WFDMA PCIE0 MCU DMA0 */
+ { 0x55000000, 0x03000, 0x1000 }, /* WFDMA PCIE0 MCU DMA1 */
+ { 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
+ { 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */
+ { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
+ { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
+ { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
+ { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
+ { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */
+ { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */
+ { 0x820cc000, 0x0e000, 0x2000 }, /* WF_UMAC_TOP (PP) */
+ { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */
+ { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */
+ { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
+ { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
+ { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
+ { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
+ { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
+ { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
+ { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
+ { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
+ { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
+ { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
+ { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
+ { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
+ { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
+ { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
+ { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
+ { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
+ { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
+ { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
+ { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
+ { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
+ { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
+ { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
+ { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
+ { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
+ { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
+ { 0x0, 0x0, 0x0 }, /* imply end of search */
+};
+
+static const struct __map mt7916_reg_map[] = {
+ { 0x54000000, 0x02000, 0x1000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */
+ { 0x55000000, 0x03000, 0x1000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */
+ { 0x56000000, 0x04000, 0x1000 }, /* WFDMA_2 (Reserved) */
+ { 0x57000000, 0x05000, 0x1000 }, /* WFDMA_3 (MCU wrap CR) */
+ { 0x58000000, 0x06000, 0x1000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */
+ { 0x59000000, 0x07000, 0x1000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */
+ { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */
+ { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */
+ { 0x820cc000, 0x0e000, 0x2000 }, /* WF_UMAC_TOP (PP) */
+ { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
+ { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
+ { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
+ { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
+ { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
+ { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
+ { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */
+ { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
+ { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */
+ { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
+ { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
+ { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
+ { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
+ { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
+ { 0x820ca000, 0x26000, 0x2000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
+ { 0x820d0000, 0x30000, 0x10000}, /* WF_LMAC_TOP (WF_WTBLON) */
+ { 0x00400000, 0x80000, 0x10000}, /* WF_MCU_SYSRAM */
+ { 0x00410000, 0x90000, 0x10000}, /* WF_MCU_SYSRAM (configure cr) */
+ { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
+ { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
+ { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
+ { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
+ { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
+ { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
+ { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
+ { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
+ { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
+ { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
+ { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
+ { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
+ { 0x820c4000, 0xa8000, 0x1000 }, /* WF_LMAC_TOP (WF_UWTBL ) */
+ { 0x820b0000, 0xae000, 0x1000 }, /* [APB2] WFSYS_ON */
+ { 0x80020000, 0xb0000, 0x10000}, /* WF_TOP_MISC_OFF */
+ { 0x81020000, 0xc0000, 0x10000}, /* WF_TOP_MISC_ON */
+ { 0x0, 0x0, 0x100000 }, /* fixed remap range */
+ { 0x0, 0x0, 0x0 }, /* imply end of search */
+};
+
+static const struct mt7915_reg_desc reg_desc[] = {
+ { 0x7915,
+ mt7915_base,
+ mt7915_reg,
+ mt7915_mask,
+ mt7915_bit,
+ mt7915_reg_map,
+ ARRAY_SIZE(mt7915_reg_map)
+ },
+ { 0x7906,
+ mt7916_base,
+ mt7916_reg,
+ mt7916_mask,
+ mt7916_bit,
+ mt7916_reg_map,
+ ARRAY_SIZE(mt7916_reg_map)
+ },
+};
+
static u32 mt7915_reg_map_l1(struct mt7915_dev *dev, u32 addr)
{
u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr);
u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr);
- mt76_rmw_field(dev, MT_HIF_REMAP_L1, MT_HIF_REMAP_L1_MASK, base);
+ dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L1,
+ MT_HIF_REMAP_L1_MASK,
+ FIELD_PREP(MT_HIF_REMAP_L1_MASK, base));
/* use read to push write */
- mt76_rr(dev, MT_HIF_REMAP_L1);
+ dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1);
return MT_HIF_REMAP_BASE_L1 + offset;
}
static u32 mt7915_reg_map_l2(struct mt7915_dev *dev, u32 addr)
{
- u32 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET, addr);
- u32 base = FIELD_GET(MT_HIF_REMAP_L2_BASE, addr);
+ u32 offset = __FIELD_GET(L2_REMAP_OFFSET, addr);
+ u32 base = __FIELD_GET(L2_REMAP_BASE, addr);
+
+ dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2,
+ MT_HIF_REMAP_L2_MASK,
+ __FIELD_PREP(L2_REMAP_MASK, base));
- mt76_rmw_field(dev, MT_HIF_REMAP_L2, MT_HIF_REMAP_L2_MASK, base);
/* use read to push write */
- mt76_rr(dev, MT_HIF_REMAP_L2);
+ dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2);
return MT_HIF_REMAP_BASE_L2 + offset;
}
static u32 __mt7915_reg_addr(struct mt7915_dev *dev, u32 addr)
{
- static const struct {
- u32 phys;
- u32 mapped;
- u32 size;
- } fixed_map[] = {
- { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
- { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure regs) */
- { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
- { 0x54000000, 0x02000, 0x1000 }, /* WFDMA PCIE0 MCU DMA0 */
- { 0x55000000, 0x03000, 0x1000 }, /* WFDMA PCIE0 MCU DMA1 */
- { 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
- { 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */
- { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
- { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
- { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
- { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
- { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */
- { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */
- { 0x820cc000, 0x0e000, 0x2000 }, /* WF_UMAC_TOP (PP) */
- { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */
- { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */
- { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
- { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
- { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
- { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
- { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
- { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
- { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
- { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
- { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
- { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
- { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
- { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
- { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
- { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
- { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
- { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
- { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
- { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
- { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
- { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
- { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
- { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
- { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
- { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
- { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
- };
int i;
if (addr < 0x100000)
return addr;
- for (i = 0; i < ARRAY_SIZE(fixed_map); i++) {
+ if (!dev->reg->map) {
+ dev_err(dev->mt76.dev, "err: reg_map is null\n");
+ return addr;
+ }
+
+ for (i = 0; i < dev->reg->map_size; i++) {
u32 ofs;
- if (addr < fixed_map[i].phys)
+ if (addr < dev->reg->map[i].phys)
continue;
- ofs = addr - fixed_map[i].phys;
- if (ofs > fixed_map[i].size)
+ ofs = addr - dev->reg->map[i].phys;
+ if (ofs > dev->reg->map[i].size)
continue;
- return fixed_map[i].mapped + ofs;
+ return dev->reg->map[i].maps + ofs;
}
- if ((addr >= 0x18000000 && addr < 0x18c00000) ||
- (addr >= 0x70000000 && addr < 0x78000000))
+ if ((addr >= MT_INFRA_BASE && addr < MT_WFSYS0_PHY_START) ||
+ (addr >= MT_WFSYS0_PHY_START && addr < MT_WFSYS1_PHY_START) ||
+ (addr >= MT_WFSYS1_PHY_START && addr <= MT_WFSYS1_PHY_END))
+ return mt7915_reg_map_l1(dev, addr);
+
+ if (dev_is_pci(dev->mt76.dev) &&
+ ((addr >= MT_CBTOP1_PHY_START && addr <= MT_CBTOP1_PHY_END) ||
+ (addr >= MT_CBTOP2_PHY_START && addr <= MT_CBTOP2_PHY_END))) {
+ /* CONN_INFRA: covert to phyiscal addr and use layer 1 remap */
+ if (addr >= MT_CONN_INFRA_MCU_START &&
+ addr <= MT_CONN_INFRA_MCU_END)
+ addr = addr - MT_CONN_INFRA_MCU_START + MT_INFRA_BASE;
+
return mt7915_reg_map_l1(dev, addr);
+ }
return mt7915_reg_map_l2(dev, addr);
}
@@ -138,10 +487,18 @@ static int mt7915_mmio_init(struct mt76_dev *mdev,
{
struct mt76_bus_ops *bus_ops;
struct mt7915_dev *dev;
+ int i;
dev = container_of(mdev, struct mt7915_dev, mt76);
mt76_mmio_init(&dev->mt76, mem_base);
+ for (i = 0; i < ARRAY_SIZE(reg_desc); i++) {
+ if (device_id == reg_desc[i].id) {
+ dev->reg = ®_desc[i];
+ break;
+ }
+ }
+
dev->bus_ops = dev->mt76.bus;
bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
GFP_KERNEL);
@@ -184,15 +541,29 @@ static void mt7915_rx_poll_complete(struct mt76_dev *mdev,
enum mt76_rxq_id q)
{
struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
- static const u32 rx_irq_mask[] = {
- [MT_RXQ_MAIN] = MT_INT_RX_DONE_DATA0,
- [MT_RXQ_EXT] = MT_INT_RX_DONE_DATA1,
- [MT_RXQ_MCU] = MT_INT_RX_DONE_WM,
- [MT_RXQ_MCU_WA] = MT_INT_RX_DONE_WA,
- [MT_RXQ_EXT_WA] = MT_INT_RX_DONE_WA_EXT,
- };
+ u32 rx_irq_mask = 0;
+
+ switch (q) {
+ case MT_RXQ_MAIN:
+ rx_irq_mask = MT_INT_RX_DONE_DATA0;
+ break;
+ case MT_RXQ_EXT:
+ rx_irq_mask = MT_INT_RX_DONE_DATA1;
+ break;
+ case MT_RXQ_MCU:
+ rx_irq_mask = MT_INT_RX_DONE_WM;
+ break;
+ case MT_RXQ_MCU_WA:
+ rx_irq_mask = MT_INT_RX_DONE_WA;
+ break;
+ case MT_RXQ_EXT_WA:
+ rx_irq_mask = MT_INT_RX_DONE_WA_EXT;
+ break;
+ default:
+ break;
+ }
- mt7915_irq_enable(dev, rx_irq_mask[q]);
+ mt7915_irq_enable(dev, rx_irq_mask);
}
/* TODO: support 2/4/6/8 MSI-X vectors */
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
index 05a28c2..b69e00d 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
@@ -53,7 +53,7 @@ struct mt7915_dfs_pulse;
struct mt7915_dfs_pattern;
enum mt7915_txq_id {
- MT7915_TXQ_FWDL = 16,
+ MT7915_TXQ_FWDL = 0,
MT7915_TXQ_MCU_WM,
MT7915_TXQ_BAND0,
MT7915_TXQ_BAND1,
@@ -250,6 +250,7 @@ struct mt7915_dev {
};
struct mt7915_hif *hif2;
+ const struct mt7915_reg_desc *reg;
const struct mt76_bus_ops *bus_ops;
struct tasklet_struct irq_tasklet;
@@ -376,7 +377,6 @@ int mt7915_mmio_probe(struct device *pdev,
void __iomem *mem_base,
u32 device_id,
int irq, struct mt7915_hif *hif2);
-u32 mt7915_reg_map(struct mt7915_dev *dev, u32 addr);
u64 __mt7915_get_tsf(struct ieee80211_hw *hw, struct mt7915_vif *mvif);
int mt7915_register_device(struct mt7915_dev *dev);
void mt7915_unregister_device(struct mt7915_dev *dev);
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/regs.h b/drivers/net/wireless/mediatek/mt76/mt7915/regs.h
index 5969353..c80d16a 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/regs.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/regs.h
@@ -4,41 +4,221 @@
#ifndef __MT7915_REGS_H
#define __MT7915_REGS_H
+#define INVALID_BASE 0x0
+#define INVALID_OFFSET 0x0
+
+struct __map {
+ u32 phys;
+ u32 maps;
+ u32 size;
+};
+
+struct __reg {
+ u32 base;
+ u32 offs;
+};
+
+struct __mask {
+ u32 end;
+ u32 start;
+};
+
+/* used to differentiate between generations */
+struct mt7915_reg_desc {
+ const u32 id;
+ const u32 *base_rev;
+ const struct __reg *reg_rev;
+ const struct __mask *mask_rev;
+ const u32 *bit_rev;
+ const struct __map *map;
+ const u32 map_size;
+};
+
+enum base_rev {
+ MT_REMAP_L1_CFG_BASE,
+ MT_REMAP_L1_BASE,
+ MT_REMAP_L2_CFG_BASE,
+ MT_REMAP_L2_BASE,
+ MT_INFRA_MCU_END_BASE,
+ MT_PCIE_MAC_BASE,
+ MT_PCIE1_MAC_BASE,
+ MT_WFDMA0_BASE,
+ MT_WFDMA1_BASE,
+ MT_WFDMA0_PCIE1_BASE,
+ MT_WFDMA1_PCIE1_BASE,
+ MT_WFDMA_EXT_CSR_BASE,
+ MT_SWDEF_BASE,
+ MT_MCU_WFDMA0_BASE,
+ MT_MCU_WFDMA1_BASE,
+ __MT_REG_BASE_MAX,
+};
+
+enum reg_rev {
+ L1_REMAP_CFG_OFFSET,
+ L2_REMAP_CFG_OFFSET,
+ INT_SOURCE_CSR,
+ INT_MASK_CSR,
+ INT1_SOURCE_CSR,
+ INT1_MASK_CSR,
+ INT_MCU_CMD_SOURCE,
+ INT_MCU_CMD_EVENT,
+ TX_RING_BASE,
+ RX_EVENT_RING_BASE,
+ RX_DATA_RING_BASE,
+ TMAC_CDTR,
+ TMAC_ODTR,
+ TMAC_ATCR,
+ TMAC_TRCR0,
+ TMAC_ICR0,
+ TMAC_ICR1,
+ TMAC_CTCR0,
+ TMAC_TFCR0,
+ MDP_BNRCFR0,
+ MDP_BNRCFR1,
+ ARB_DRNGR0,
+ ARB_SCR,
+ RMAC_MIB_AIRTIME14,
+ AGG_AWSCR0,
+ AGG_PCR0,
+ AGG_ACR0,
+ AGG_MRCR,
+ AGG_ATCR1,
+ AGG_ATCR3,
+ LPON_UTTR0,
+ LPON_UTTR1,
+ MIB_SDR3,
+ MIB_SDR4,
+ MIB_SDR5,
+ MIB_SDR7,
+ MIB_SDR8,
+ MIB_SDR9,
+ MIB_SDR10,
+ MIB_SDR11,
+ MIB_SDR12,
+ MIB_SDR13,
+ MIB_SDR14,
+ MIB_SDR15,
+ MIB_SDR16,
+ MIB_SDR17,
+ MIB_SDR18,
+ MIB_SDR19,
+ MIB_SDR20,
+ MIB_SDR21,
+ MIB_SDR22,
+ MIB_SDR23,
+ MIB_SDR24,
+ MIB_SDR25,
+ MIB_SDR27,
+ MIB_SDR28,
+ MIB_SDR29,
+ MIB_SDRVEC,
+ MIB_SDR31,
+ MIB_SDR32,
+ MIB_SDRMUBF,
+ MIB_DR8,
+ MIB_DR9,
+ MIB_DR11,
+ MIB_MB_SDR0,
+ MIB_MB_SDR1,
+ TX_AGG_CNT,
+ TX_AGG_CNT2,
+ MIB_ARNG,
+ WTBLON_TOP_WDUCR,
+ WTBL_UPDATE,
+ PLE_FL_Q_EMPTY,
+ PLE_FL_Q_CTRL,
+ PLE_AC_QEMPTY,
+ PLE_FREEPG_CNT,
+ PLE_FREEPG_HEAD_TAIL,
+ PLE_PG_HIF_GROUP,
+ PLE_HIF_PG_INFO,
+ AC_OFFSET,
+ __MT_REG_MAX,
+};
+
+enum mask_rev {
+ L2_REMAP_MASK,
+ L2_REMAP_OFFSET,
+ L2_REMAP_BASE,
+ MIB_SDR3_FCS_ERR,
+ MIB_MRDY_CNT,
+ MIB_MPDU_ATTEMPTS_CNT,
+ MIB_MPDU_SUCCESS_CNT,
+ MIB_AMPDU_SF_CNT,
+ MIB_PF_DROP_CNT,
+ MIB_VEC_DROP_CNT,
+ MIB_BF_TX_CNT,
+ __MT_MASK_MAX,
+};
+
+enum bit_rev {
+ RX_DONE_DAND0,
+ RX_DONE_DAND1,
+ RX_DONE_MCU_WM,
+ RX_DONE_MCU_WA,
+ RX_DONE_WA_BAND0,
+ RX_DONE_WA_BAND1,
+ TX_DONE_FWDL,
+ TX_DONE_MCU_WM,
+ TX_DONE_MCU_WA,
+ TX_DONE_BAND0,
+ TX_DONE_BAND1,
+ RX_MCU_TO_HOST,
+ MIB_MB_SDR,
+ LPON_TCR,
+ __MT_BIT_MAX,
+};
+
+#define __REG_MAP(_dev, id, ofs) ((_dev)->reg->base_rev[(id)] + (ofs))
+#define __REG_BASE(_dev, id) ((_dev)->reg->reg_rev[(id)].base)
+#define __REG_OFFS(_dev, id) ((_dev)->reg->reg_rev[(id)].offs)
+
+#define __BIT(_dev, id) BIT((_dev)->reg->bit_rev[(id)])
+#define __MASK(_dev, id) GENMASK((_dev)->reg->mask_rev[(id)].end, \
+ (_dev)->reg->mask_rev[(id)].start)
+#define __REG(_dev, id) __REG_MAP((_dev), __REG_BASE((_dev), (id)), \
+ __REG_OFFS((_dev), (id)))
+
+#define __FIELD_GET(id, _reg) (((_reg) & __MASK(dev, (id))) >> \
+ dev->reg->mask_rev[(id)].start)
+#define __FIELD_PREP(id, _reg) (((_reg) << dev->reg->mask_rev[(id)].start) & \
+ __MASK(dev, (id)))
+
/* MCU WFDMA0 */
-#define MT_MCU_WFDMA0_BASE 0x2000
-#define MT_MCU_WFDMA0(ofs) (MT_MCU_WFDMA0_BASE + (ofs))
+#define MT_MCU_WFDMA0(ofs) __REG_MAP(dev, MT_MCU_WFDMA0_BASE, (ofs))
#define MT_MCU_WFDMA0_DUMMY_CR MT_MCU_WFDMA0(0x120)
/* MCU WFDMA1 */
-#define MT_MCU_WFDMA1_BASE 0x3000
-#define MT_MCU_WFDMA1(ofs) (MT_MCU_WFDMA1_BASE + (ofs))
-
-#define MT_MCU_INT_EVENT MT_MCU_WFDMA1(0x108)
+#define MT_MCU_INT_EVENT __REG(dev, INT_MCU_CMD_EVENT)
#define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
#define MT_MCU_INT_EVENT_DMA_INIT BIT(1)
#define MT_MCU_INT_EVENT_SER_TRIGGER BIT(2)
#define MT_MCU_INT_EVENT_RESET_DONE BIT(3)
-#define MT_PLE_BASE 0x8000
+/* PLE */
+#define MT_PLE_BASE 0x820c0000
#define MT_PLE(ofs) (MT_PLE_BASE + (ofs))
-#define MT_FL_Q_EMPTY 0x0b0
-#define MT_FL_Q0_CTRL 0x1b0
-#define MT_FL_Q2_CTRL 0x1b8
-#define MT_FL_Q3_CTRL 0x1bc
-
-#define MT_PLE_FREEPG_CNT MT_PLE(0x100)
-#define MT_PLE_FREEPG_HEAD_TAIL MT_PLE(0x104)
-#define MT_PLE_PG_HIF_GROUP MT_PLE(0x110)
-#define MT_PLE_HIF_PG_INFO MT_PLE(0x114)
-#define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(0x500 + 0x40 * (ac) + \
- ((n) << 2))
+#define MT_FL_Q_EMPTY MT_PLE(__REG_OFFS(dev, PLE_FL_Q_EMPTY))
+#define MT_FL_Q0_CTRL MT_PLE(__REG_OFFS(dev, PLE_FL_Q_CTRL))
+#define MT_FL_Q2_CTRL MT_PLE(__REG_OFFS(dev, PLE_FL_Q_CTRL) + 0x8)
+#define MT_FL_Q3_CTRL MT_PLE(__REG_OFFS(dev, PLE_FL_Q_CTRL) + 0xc)
+
+#define MT_PLE_FREEPG_CNT MT_PLE(__REG_OFFS(dev, PLE_FREEPG_CNT))
+#define MT_PLE_FREEPG_HEAD_TAIL MT_PLE(__REG_OFFS(dev, PLE_FREEPG_HEAD_TAIL))
+#define MT_PLE_PG_HIF_GROUP MT_PLE(__REG_OFFS(dev, PLE_PG_HIF_GROUP))
+#define MT_PLE_HIF_PG_INFO MT_PLE(__REG_OFFS(dev, PLE_HIF_PG_INFO))
+
+#define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(__REG_OFFS(dev, PLE_AC_QEMPTY) + \
+ __REG_OFFS(dev, AC_OFFSET) * \
+ (ac) + ((n) << 2))
#define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
-#define MT_PSE_BASE 0xc000
+#define MT_PSE_BASE 0x820c8000
#define MT_PSE(ofs) (MT_PSE_BASE + (ofs))
-#define MT_MDP_BASE 0xf000
+/* WF MDP TOP */
+#define MT_MDP_BASE 0x820cd000
#define MT_MDP(ofs) (MT_MDP_BASE + (ofs))
#define MT_MDP_DCR0 MT_MDP(0x000)
@@ -47,63 +227,66 @@
#define MT_MDP_DCR1 MT_MDP(0x004)
#define MT_MDP_DCR1_MAX_RX_LEN GENMASK(15, 3)
-#define MT_MDP_BNRCFR0(_band) MT_MDP(0x070 + ((_band) << 8))
+#define MT_MDP_BNRCFR0(_band) MT_MDP(__REG_OFFS(dev, MDP_BNRCFR0) + \
+ ((_band) << 8))
#define MT_MDP_RCFR0_MCU_RX_MGMT GENMASK(5, 4)
#define MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR GENMASK(7, 6)
#define MT_MDP_RCFR0_MCU_RX_CTL_BAR GENMASK(9, 8)
-#define MT_MDP_BNRCFR1(_band) MT_MDP(0x074 + ((_band) << 8))
+#define MT_MDP_BNRCFR1(_band) MT_MDP(__REG_OFFS(dev, MDP_BNRCFR1) + \
+ ((_band) << 8))
#define MT_MDP_RCFR1_MCU_RX_BYPASS GENMASK(23, 22)
#define MT_MDP_RCFR1_RX_DROPPED_UCAST GENMASK(28, 27)
#define MT_MDP_RCFR1_RX_DROPPED_MCAST GENMASK(30, 29)
#define MT_MDP_TO_HIF 0
#define MT_MDP_TO_WM 1
-/* TMAC: band 0(0x21000), band 1(0xa1000) */
-#define MT_WF_TMAC_BASE(_band) ((_band) ? 0xa1000 : 0x21000)
+/* TMAC: band 0(0x820e4000), band 1(0x820f4000) */
+#define MT_WF_TMAC_BASE(_band) ((_band) ? 0x820f4000 : 0x820e4000)
#define MT_WF_TMAC(_band, ofs) (MT_WF_TMAC_BASE(_band) + (ofs))
#define MT_TMAC_TCR0(_band) MT_WF_TMAC(_band, 0)
#define MT_TMAC_TCR0_TX_BLINK GENMASK(7, 6)
#define MT_TMAC_TCR0_TBTT_STOP_CTRL BIT(25)
-#define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, 0x090)
-#define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, 0x094)
+#define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, __REG_OFFS(dev, TMAC_CDTR))
+ #define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, __REG_OFFS(dev, TMAC_ODTR))
#define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)
#define MT_TIMEOUT_VAL_CCA GENMASK(31, 16)
-#define MT_TMAC_ATCR(_band) MT_WF_TMAC(_band, 0x098)
+#define MT_TMAC_ATCR(_band) MT_WF_TMAC(_band, __REG_OFFS(dev, TMAC_ATCR))
#define MT_TMAC_ATCR_TXV_TOUT GENMASK(7, 0)
-#define MT_TMAC_TRCR0(_band) MT_WF_TMAC(_band, 0x09c)
+#define MT_TMAC_TRCR0(_band) MT_WF_TMAC(_band, __REG_OFFS(dev, TMAC_TRCR0))
#define MT_TMAC_TRCR0_TR2T_CHK GENMASK(8, 0)
#define MT_TMAC_TRCR0_I2T_CHK GENMASK(24, 16)
-#define MT_TMAC_ICR0(_band) MT_WF_TMAC(_band, 0x0a4)
-#define MT_IFS_EIFS_OFDM GENMASK(8, 0)
+#define MT_TMAC_ICR0(_band) MT_WF_TMAC(_band, __REG_OFFS(dev, TMAC_ICR0))
+#define MT_IFS_EIFS_OFDM GENMASK(8, 0)
#define MT_IFS_RIFS GENMASK(14, 10)
#define MT_IFS_SIFS GENMASK(22, 16)
#define MT_IFS_SLOT GENMASK(30, 24)
-#define MT_TMAC_ICR1(_band) MT_WF_TMAC(_band, 0x0b4)
+#define MT_TMAC_ICR1(_band) MT_WF_TMAC(_band, __REG_OFFS(dev, TMAC_ICR1))
#define MT_IFS_EIFS_CCK GENMASK(8, 0)
-#define MT_TMAC_CTCR0(_band) MT_WF_TMAC(_band, 0x0f4)
+#define MT_TMAC_CTCR0(_band) MT_WF_TMAC(_band, __REG_OFFS(dev, TMAC_CTCR0))
#define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0)
#define MT_TMAC_CTCR0_INS_DDLMT_EN BIT(17)
#define MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN BIT(18)
-#define MT_TMAC_TFCR0(_band) MT_WF_TMAC(_band, 0x1e0)
+#define MT_TMAC_TFCR0(_band) MT_WF_TMAC(_band, __REG_OFFS(dev, TMAC_TFCR0))
-#define MT_WF_DMA_BASE(_band) ((_band) ? 0xa1e00 : 0x21e00)
+/* WF DMA TOP: band 0(0x820e7000),band 1(0x820f7000) */
+#define MT_WF_DMA_BASE(_band) ((_band) ? 0x820f7000 : 0x820e7000)
#define MT_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs))
#define MT_DMA_DCR0(_band) MT_WF_DMA(_band, 0x000)
#define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 3)
#define MT_DMA_DCR0_RXD_G5_EN BIT(23)
-/* ETBF: band 0(0x24000), band 1(0xa4000) */
-#define MT_WF_ETBF_BASE(_band) ((_band) ? 0xa4000 : 0x24000)
+/* ETBF: band 0(0x820ea000), band 1(0x820fa000) */
+#define MT_WF_ETBF_BASE(_band) ((_band) ? 0x820fa000 : 0x820ea000)
#define MT_WF_ETBF(_band, ofs) (MT_WF_ETBF_BASE(_band) + (ofs))
#define MT_ETBF_TX_NDP_BFRP(_band) MT_WF_ETBF(_band, 0x040)
@@ -125,174 +308,184 @@
#define MT_ETBF_RX_FB_VHT GENMASK(15, 8)
#define MT_ETBF_RX_FB_HT GENMASK(7, 0)
-/* LPON: band 0(0x24200), band 1(0xa4200) */
-#define MT_WF_LPON_BASE(_band) ((_band) ? 0xa4200 : 0x24200)
+/* LPON: band 0(0x820eb000), band 1(0x820fb000) */
+#define MT_WF_LPON_BASE(_band) ((_band) ? 0x820fb000 : 0x820eb000)
#define MT_WF_LPON(_band, ofs) (MT_WF_LPON_BASE(_band) + (ofs))
-#define MT_LPON_UTTR0(_band) MT_WF_LPON(_band, 0x080)
-#define MT_LPON_UTTR1(_band) MT_WF_LPON(_band, 0x084)
+#define MT_LPON_UTTR0(_band) MT_WF_LPON(_band, __REG_OFFS(dev, LPON_UTTR0))
+#define MT_LPON_UTTR1(_band) MT_WF_LPON(_band, __REG_OFFS(dev, LPON_UTTR1))
-#define MT_LPON_TCR(_band, n) MT_WF_LPON(_band, 0x0a8 + (n) * 4)
+#define MT_LPON_TCR(_band, n) MT_WF_LPON(_band, 0x0a8 + \
+ (((n) * 4) << __BIT(dev, LPON_TCR)))
#define MT_LPON_TCR_SW_MODE GENMASK(1, 0)
#define MT_LPON_TCR_SW_WRITE BIT(0)
#define MT_LPON_TCR_SW_ADJUST BIT(1)
#define MT_LPON_TCR_SW_READ GENMASK(1, 0)
-/* MIB: band 0(0x24800), band 1(0xa4800) */
+/* MIB: band 0(0x820ed000), band 1(0x820fd000) */
/* These counters are (mostly?) clear-on-read. So, some should not
* be read at all in case firmware is already reading them. These
* are commented with 'DNR' below. The DNR stats will be read by querying
* the firmware API for the appropriate message. For counters the driver
* does read, the driver should accumulate the counters.
*/
-#define MT_WF_MIB_BASE(_band) ((_band) ? 0xa4800 : 0x24800)
+#define MT_WF_MIB_BASE(_band) ((_band) ? 0x820fd000 : 0x820ed000)
#define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE(_band) + (ofs))
#define MT_MIB_SDR0(_band) MT_WF_MIB(_band, 0x010)
#define MT_MIB_SDR0_BERACON_TX_CNT_MASK GENMASK(15, 0)
-#define MT_MIB_SDR3(_band) MT_WF_MIB(_band, 0x014)
-#define MT_MIB_SDR3_FCS_ERR_MASK GENMASK(15, 0)
+#define MT_MIB_SDR3(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_SDR3))
+#define MT_MIB_SDR3_FCS_ERR_MASK __MASK(dev, MIB_SDR3_FCS_ERR)
-#define MT_MIB_SDR4(_band) MT_WF_MIB(_band, 0x018)
+#define MT_MIB_SDR4(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_SDR4))
#define MT_MIB_SDR4_RX_FIFO_FULL_MASK GENMASK(15, 0)
/* rx mpdu counter, full 32 bits */
-#define MT_MIB_SDR5(_band) MT_WF_MIB(_band, 0x01c)
+#define MT_MIB_SDR5(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_SDR5))
#define MT_MIB_SDR6(_band) MT_WF_MIB(_band, 0x020)
#define MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK GENMASK(15, 0)
-#define MT_MIB_SDR7(_band) MT_WF_MIB(_band, 0x024)
+#define MT_MIB_SDR7(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_SDR7))
#define MT_MIB_SDR7_RX_VECTOR_MISMATCH_CNT_MASK GENMASK(15, 0)
-#define MT_MIB_SDR8(_band) MT_WF_MIB(_band, 0x028)
+#define MT_MIB_SDR8(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_SDR8))
#define MT_MIB_SDR8_RX_DELIMITER_FAIL_CNT_MASK GENMASK(15, 0)
/* aka CCA_NAV_TX_TIME */
-#define MT_MIB_SDR9_DNR(_band) MT_WF_MIB(_band, 0x02c)
-#define MT_MIB_SDR9_CCA_BUSY_TIME_MASK GENMASK(23, 0)
+#define MT_MIB_SDR9_DNR(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_SDR9))
+#define MT_MIB_SDR9_CCA_BUSY_TIME_MASK GENMASK(23, 0)
-#define MT_MIB_SDR10_DNR(_band) MT_WF_MIB(_band, 0x030)
-#define MT_MIB_SDR10_MRDY_COUNT_MASK GENMASK(25, 0)
+#define MT_MIB_SDR10_DNR(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_SDR10))
+#define MT_MIB_SDR10_MRDY_COUNT_MASK __MASK(dev, MIB_MRDY_CNT)
-#define MT_MIB_SDR11(_band) MT_WF_MIB(_band, 0x034)
+#define MT_MIB_SDR11(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_SDR11))
#define MT_MIB_SDR11_RX_LEN_MISMATCH_CNT_MASK GENMASK(15, 0)
/* tx ampdu cnt, full 32 bits */
-#define MT_MIB_SDR12(_band) MT_WF_MIB(_band, 0x038)
+#define MT_MIB_SDR12(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_SDR12))
-#define MT_MIB_SDR13(_band) MT_WF_MIB(_band, 0x03c)
+#define MT_MIB_SDR13(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_SDR13))
#define MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK GENMASK(15, 0)
/* counts all mpdus in ampdu, regardless of success */
-#define MT_MIB_SDR14(_band) MT_WF_MIB(_band, 0x040)
-#define MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK GENMASK(23, 0)
+#define MT_MIB_SDR14(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_SDR14))
+#define MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK __MASK(dev, MIB_MPDU_ATTEMPTS_CNT)
/* counts all successfully tx'd mpdus in ampdu */
-#define MT_MIB_SDR15(_band) MT_WF_MIB(_band, 0x044)
-#define MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK GENMASK(23, 0)
+#define MT_MIB_SDR15(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_SDR15))
+#define MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK __MASK(dev, MIB_MPDU_SUCCESS_CNT)
/* in units of 'us' */
-#define MT_MIB_SDR16_DNR(_band) MT_WF_MIB(_band, 0x048)
+#define MT_MIB_SDR16_DNR(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_SDR16))
#define MT_MIB_SDR16_PRIMARY_CCA_BUSY_TIME_MASK GENMASK(23, 0)
-#define MT_MIB_SDR17_DNR(_band) MT_WF_MIB(_band, 0x04c)
+#define MT_MIB_SDR17_DNR(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_SDR17))
#define MT_MIB_SDR17_SECONDARY_CCA_BUSY_TIME_MASK GENMASK(23, 0)
-#define MT_MIB_SDR18(_band) MT_WF_MIB(_band, 0x050)
+#define MT_MIB_SDR18(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_SDR18))
#define MT_MIB_SDR18_PRIMARY_ENERGY_DETECT_TIME_MASK GENMASK(23, 0)
/* units are us */
-#define MT_MIB_SDR19_DNR(_band) MT_WF_MIB(_band, 0x054)
+#define MT_MIB_SDR19_DNR(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_SDR19))
#define MT_MIB_SDR19_CCK_MDRDY_TIME_MASK GENMASK(23, 0)
-#define MT_MIB_SDR20_DNR(_band) MT_WF_MIB(_band, 0x058)
+#define MT_MIB_SDR20_DNR(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_SDR20))
#define MT_MIB_SDR20_OFDM_VHT_MDRDY_TIME_MASK GENMASK(23, 0)
-#define MT_MIB_SDR21_DNR(_band) MT_WF_MIB(_band, 0x05c)
+#define MT_MIB_SDR21_DNR(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_SDR21))
#define MT_MIB_SDR20_GREEN_MDRDY_TIME_MASK GENMASK(23, 0)
/* rx ampdu count, 32-bit */
-#define MT_MIB_SDR22(_band) MT_WF_MIB(_band, 0x060)
+#define MT_MIB_SDR22(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_SDR22))
/* rx ampdu bytes count, 32-bit */
-#define MT_MIB_SDR23(_band) MT_WF_MIB(_band, 0x064)
+#define MT_MIB_SDR23(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_SDR23))
/* rx ampdu valid subframe count */
-#define MT_MIB_SDR24(_band) MT_WF_MIB(_band, 0x068)
-#define MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK GENMASK(23, 0)
+#define MT_MIB_SDR24(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_SDR24))
+#define MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK __MASK(dev, MIB_AMPDU_SF_CNT)
/* rx ampdu valid subframe bytes count, 32bits */
-#define MT_MIB_SDR25(_band) MT_WF_MIB(_band, 0x06c)
+#define MT_MIB_SDR25(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_SDR25))
/* remaining windows protected stats */
-#define MT_MIB_SDR27(_band) MT_WF_MIB(_band, 0x074)
+#define MT_MIB_SDR27(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_SDR27))
#define MT_MIB_SDR27_TX_RWP_FAIL_CNT_MASK GENMASK(15, 0)
-#define MT_MIB_SDR28(_band) MT_WF_MIB(_band, 0x078)
+#define MT_MIB_SDR28(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_SDR28))
#define MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK GENMASK(15, 0)
-#define MT_MIB_SDR29(_band) MT_WF_MIB(_band, 0x07c)
-#define MT_MIB_SDR29_RX_PFDROP_CNT_MASK GENMASK(7, 0)
+#define MT_MIB_SDR29(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_SDR29))
+#define MT_MIB_SDR29_RX_PFDROP_CNT_MASK __MASK(dev, MIB_PF_DROP_CNT)
-#define MT_MIB_SDR30(_band) MT_WF_MIB(_band, 0x080)
-#define MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK GENMASK(15, 0)
+#define MT_MIB_SDRVEC(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_SDRVEC))
+#define MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK __MASK(dev, MIB_VEC_DROP_CNT)
/* rx blockack count, 32 bits */
-#define MT_MIB_SDR31(_band) MT_WF_MIB(_band, 0x084)
+#define MT_MIB_SDR31(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_SDR31))
-#define MT_MIB_SDR32(_band) MT_WF_MIB(_band, 0x088)
+#define MT_MIB_SDR32(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_SDR32))
#define MT_MIB_SDR32_TX_PKT_EBF_CNT_MASK GENMASK(15, 0)
-#define MT_MIB_SDR33(_band) MT_WF_MIB(_band, 0x08c)
-#define MT_MIB_SDR33_TX_PKT_IBF_CNT_MASK GENMASK(15, 0)
+#define MT_MIB_SDR33(_band) MT_WF_MIB(_band, 0x088)
+#define MT_MIB_SDR32_TX_PKT_IBF_CNT_MASK __MASK(dev, MIB_BF_TX_CNT)
-#define MT_MIB_SDR34(_band) MT_WF_MIB(_band, 0x090)
+#define MT_MIB_SDRMUBF(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_SDRMUBF))
#define MT_MIB_MU_BF_TX_CNT GENMASK(15, 0)
/* 36, 37 both DNR */
-#define MT_MIB_DR8(_band) MT_WF_MIB(_band, 0x0c0)
-#define MT_MIB_DR9(_band) MT_WF_MIB(_band, 0x0c4)
-#define MT_MIB_DR11(_band) MT_WF_MIB(_band, 0x0cc)
+#define MT_MIB_DR8(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_DR8))
+#define MT_MIB_DR9(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_DR9))
+#define MT_MIB_DR11(_band) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_DR11))
-#define MT_MIB_MB_SDR0(_band, n) MT_WF_MIB(_band, 0x100 + ((n) << 4))
+#define MT_MIB_MB_SDR0(_band, n) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_MB_SDR0) + \
+ ((n) << __BIT(dev, MIB_MB_SDR)))
#define MT_MIB_RTS_RETRIES_COUNT_MASK GENMASK(31, 16)
#define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0)
-#define MT_MIB_MB_SDR1(_band, n) MT_WF_MIB(_band, 0x104 + ((n) << 4))
+#define MT_MIB_MB_SDR1(_band, n) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_MB_SDR1) + \
+ ((n) << __BIT(dev, MIB_MB_SDR)))
#define MT_MIB_BA_MISS_COUNT_MASK GENMASK(15, 0)
#define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(31, 16)
-#define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, 0x0a8 + ((n) << 2))
-#define MT_TX_AGG_CNT2(_band, n) MT_WF_MIB(_band, 0x164 + ((n) << 2))
-#define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, 0x4b8 + ((n) << 2))
+#define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, __REG_OFFS(dev, TX_AGG_CNT) + \
+ ((n) << 2))
+#define MT_TX_AGG_CNT2(_band, n) MT_WF_MIB(_band, __REG_OFFS(dev, TX_AGG_CNT2) + \
+ ((n) << 2))
+#define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, __REG_OFFS(dev, MIB_ARNG) + \
+ ((n) << 2))
#define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(7, 0))
-#define MT_WTBLON_TOP_BASE 0x34000
+/* WTBLON TOP */
+#define MT_WTBLON_TOP_BASE 0x820d4000
#define MT_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs))
-#define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(0x0)
+#define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(__REG_OFFS(dev, WTBLON_TOP_WDUCR))
#define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0)
-#define MT_WTBL_UPDATE MT_WTBLON_TOP(0x030)
+#define MT_WTBL_UPDATE MT_WTBLON_TOP(__REG_OFFS(dev, WTBL_UPDATE))
#define MT_WTBL_UPDATE_WLAN_IDX GENMASK(9, 0)
#define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(12)
#define MT_WTBL_UPDATE_BUSY BIT(31)
-#define MT_WTBL_BASE 0x38000
+/* WTBL */
+#define MT_WTBL_BASE 0x820d8000
#define MT_WTBL_LMAC_ID GENMASK(14, 8)
#define MT_WTBL_LMAC_DW GENMASK(7, 2)
#define MT_WTBL_LMAC_OFFS(_id, _dw) (MT_WTBL_BASE | \
- FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \
- FIELD_PREP(MT_WTBL_LMAC_DW, _dw))
+ FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \
+ FIELD_PREP(MT_WTBL_LMAC_DW, _dw))
-/* AGG: band 0(0x20800), band 1(0xa0800) */
-#define MT_WF_AGG_BASE(_band) ((_band) ? 0xa0800 : 0x20800)
+/* AGG: band 0(0x820e2000), band 1(0x820f2000) */
+#define MT_WF_AGG_BASE(_band) ((_band) ? 0x820f2000 : 0x820e2000)
#define MT_WF_AGG(_band, ofs) (MT_WF_AGG_BASE(_band) + (ofs))
-#define MT_AGG_AWSCR0(_band, _n) MT_WF_AGG(_band, 0x05c + (_n) * 4)
-#define MT_AGG_PCR0(_band, _n) MT_WF_AGG(_band, 0x06c + (_n) * 4)
+#define MT_AGG_AWSCR0(_band, _n) MT_WF_AGG(_band, (__REG_OFFS(dev, AGG_AWSCR0) + \
+ (_n) * 4))
+#define MT_AGG_PCR0(_band, _n) MT_WF_AGG(_band, (__REG_OFFS(dev, AGG_PCR0) + \
+ (_n) * 4))
#define MT_AGG_PCR0_MM_PROT BIT(0)
#define MT_AGG_PCR0_GF_PROT BIT(1)
#define MT_AGG_PCR0_BW20_PROT BIT(2)
@@ -305,31 +498,32 @@
#define MT_AGG_PCR1_RTS0_NUM_THRES GENMASK(31, 23)
#define MT_AGG_PCR1_RTS0_LEN_THRES GENMASK(19, 0)
-#define MT_AGG_ACR0(_band) MT_WF_AGG(_band, 0x084)
+#define MT_AGG_ACR0(_band) MT_WF_AGG(_band, __REG_OFFS(dev, AGG_ACR0))
#define MT_AGG_ACR_CFEND_RATE GENMASK(13, 0)
#define MT_AGG_ACR_BAR_RATE GENMASK(29, 16)
-#define MT_AGG_MRCR(_band) MT_WF_AGG(_band, 0x098)
-#define MT_AGG_MRCR_BAR_CNT_LIMIT GENMASK(15, 12)
-#define MT_AGG_MRCR_LAST_RTS_CTS_RN BIT(6)
-#define MT_AGG_MRCR_RTS_FAIL_LIMIT GENMASK(11, 7)
+#define MT_AGG_MRCR(_band) MT_WF_AGG(_band, __REG_OFFS(dev, AGG_MRCR))
+#define MT_AGG_MRCR_BAR_CNT_LIMIT GENMASK(15, 12)
+#define MT_AGG_MRCR_LAST_RTS_CTS_RN BIT(6)
+#define MT_AGG_MRCR_RTS_FAIL_LIMIT GENMASK(11, 7)
#define MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT GENMASK(28, 24)
-#define MT_AGG_ATCR1(_band) MT_WF_AGG(_band, 0x0f0)
-#define MT_AGG_ATCR3(_band) MT_WF_AGG(_band, 0x0f4)
+#define MT_AGG_ATCR1(_band) MT_WF_AGG(_band, __REG_OFFS(dev, AGG_ATCR1))
+#define MT_AGG_ATCR3(_band) MT_WF_AGG(_band, __REG_OFFS(dev, AGG_ATCR3))
-/* ARB: band 0(0x20c00), band 1(0xa0c00) */
-#define MT_WF_ARB_BASE(_band) ((_band) ? 0xa0c00 : 0x20c00)
+/* ARB: band 0(0x820e3000), band 1(0x820f3000) */
+#define MT_WF_ARB_BASE(_band) ((_band) ? 0x820f3000 : 0x820e3000)
#define MT_WF_ARB(_band, ofs) (MT_WF_ARB_BASE(_band) + (ofs))
-#define MT_ARB_SCR(_band) MT_WF_ARB(_band, 0x080)
+#define MT_ARB_SCR(_band) MT_WF_ARB(_band, __REG_OFFS(dev, ARB_SCR))
#define MT_ARB_SCR_TX_DISABLE BIT(8)
#define MT_ARB_SCR_RX_DISABLE BIT(9)
-#define MT_ARB_DRNGR0(_band, _n) MT_WF_ARB(_band, 0x194 + (_n) * 4)
+#define MT_ARB_DRNGR0(_band, _n) MT_WF_ARB(_band, (__REG_OFFS(dev, ARB_DRNGR0) + \
+ (_n) * 4))
-/* RMAC: band 0(0x21400), band 1(0xa1400) */
-#define MT_WF_RMAC_BASE(_band) ((_band) ? 0xa1400 : 0x21400)
+/* RMAC: band 0(0x820e5000), band 1(0x820f5000) */
+#define MT_WF_RMAC_BASE(_band) ((_band) ? 0x820f5000 : 0x820e5000)
#define MT_WF_RMAC(_band, ofs) (MT_WF_RMAC_BASE(_band) + (ofs))
#define MT_WF_RFCR(_band) MT_WF_RMAC(_band, 0x000)
@@ -366,8 +560,7 @@
#define MT_WF_RMAC_MIB_RXTIME_CLR BIT(31)
/* WFDMA0 */
-#define MT_WFDMA0_BASE 0xd4000
-#define MT_WFDMA0(ofs) (MT_WFDMA0_BASE + (ofs))
+#define MT_WFDMA0(ofs) __REG_MAP(dev, MT_WFDMA0_BASE, ofs)
#define MT_WFDMA0_RST MT_WFDMA0(0x100)
#define MT_WFDMA0_RST_LOGIC_RST BIT(4)
@@ -385,15 +578,12 @@
#define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)
#define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0)
-#define MT_RX_DATA_RING_BASE MT_WFDMA0(0x500)
-
#define MT_WFDMA0_RX_RING0_EXT_CTRL MT_WFDMA0(0x680)
#define MT_WFDMA0_RX_RING1_EXT_CTRL MT_WFDMA0(0x684)
#define MT_WFDMA0_RX_RING2_EXT_CTRL MT_WFDMA0(0x688)
/* WFDMA1 */
-#define MT_WFDMA1_BASE 0xd5000
-#define MT_WFDMA1(ofs) (MT_WFDMA1_BASE + (ofs))
+#define MT_WFDMA1(ofs) __REG_MAP(dev, MT_WFDMA1_BASE, ofs)
#define MT_WFDMA1_RST MT_WFDMA1(0x100)
#define MT_WFDMA1_RST_LOGIC_RST BIT(4)
@@ -404,14 +594,6 @@
#define MT_WFDMA1_BUSY_ENA_TX_FIFO1 BIT(1)
#define MT_WFDMA1_BUSY_ENA_RX_FIFO BIT(2)
-#define MT_MCU_CMD MT_WFDMA1(0x1f0)
-#define MT_MCU_CMD_STOP_DMA_FW_RELOAD BIT(1)
-#define MT_MCU_CMD_STOP_DMA BIT(2)
-#define MT_MCU_CMD_RESET_DONE BIT(3)
-#define MT_MCU_CMD_RECOVERY_DONE BIT(4)
-#define MT_MCU_CMD_NORMAL_STATE BIT(5)
-#define MT_MCU_CMD_ERROR_MASK GENMASK(5, 1)
-
#define MT_WFDMA1_GLO_CFG MT_WFDMA1(0x208)
#define MT_WFDMA1_GLO_CFG_TX_DMA_EN BIT(0)
#define MT_WFDMA1_GLO_CFG_RX_DMA_EN BIT(2)
@@ -421,9 +603,6 @@
#define MT_WFDMA1_RST_DTX_PTR MT_WFDMA1(0x20c)
#define MT_WFDMA1_PRI_DLY_INT_CFG0 MT_WFDMA1(0x2f0)
-#define MT_TX_RING_BASE MT_WFDMA1(0x300)
-#define MT_RX_EVENT_RING_BASE MT_WFDMA1(0x500)
-
#define MT_WFDMA1_TX_RING0_EXT_CTRL MT_WFDMA1(0x600)
#define MT_WFDMA1_TX_RING1_EXT_CTRL MT_WFDMA1(0x604)
#define MT_WFDMA1_TX_RING2_EXT_CTRL MT_WFDMA1(0x608)
@@ -448,31 +627,7 @@
#define MT_WFDMA1_RX_RING3_EXT_CTRL MT_WFDMA1(0x68c)
/* WFDMA CSR */
-#define MT_WFDMA_EXT_CSR_BASE 0xd7000
-#define MT_WFDMA_EXT_CSR(ofs) (MT_WFDMA_EXT_CSR_BASE + (ofs))
-
-#define MT_INT_SOURCE_CSR MT_WFDMA_EXT_CSR(0x10)
-#define MT_INT_MASK_CSR MT_WFDMA_EXT_CSR(0x14)
-#define MT_INT_RX_DONE_DATA0 BIT(16)
-#define MT_INT_RX_DONE_DATA1 BIT(17)
-#define MT_INT_RX_DONE_WM BIT(0)
-#define MT_INT_RX_DONE_WA BIT(1)
-#define MT_INT_RX_DONE_WA_EXT BIT(2)
-#define MT_INT_RX_DONE_ALL (GENMASK(2, 0) | GENMASK(17, 16))
-#define MT_INT_TX_DONE_MCU_WA BIT(15)
-#define MT_INT_TX_DONE_FWDL BIT(26)
-#define MT_INT_TX_DONE_MCU_WM BIT(27)
-#define MT_INT_TX_DONE_BAND0 BIT(30)
-#define MT_INT_TX_DONE_BAND1 BIT(31)
-
-#define MT_INT_BAND1_MASK (MT_INT_RX_DONE_WA_EXT | \
- MT_INT_TX_DONE_BAND1)
-
-#define MT_INT_MCU_CMD BIT(29)
-
-#define MT_INT_TX_DONE_MCU (MT_INT_TX_DONE_MCU_WA | \
- MT_INT_TX_DONE_MCU_WM | \
- MT_INT_TX_DONE_FWDL)
+#define MT_WFDMA_EXT_CSR(ofs) __REG_MAP(dev, MT_WFDMA_EXT_CSR_BASE, (ofs))
#define MT_WFDMA_HOST_CONFIG MT_WFDMA_EXT_CSR(0x30)
#define MT_WFDMA_HOST_CONFIG_PDMA_BAND BIT(0)
@@ -480,53 +635,113 @@
#define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR(0x44)
#define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0)
-#define MT_INT1_SOURCE_CSR MT_WFDMA_EXT_CSR(0x88)
-#define MT_INT1_MASK_CSR MT_WFDMA_EXT_CSR(0x8c)
-
-#define MT_PCIE_RECOG_ID MT_WFDMA_EXT_CSR(0x90)
+#define MT_PCIE_RECOG_ID 0xd7090
#define MT_PCIE_RECOG_ID_MASK GENMASK(30, 0)
#define MT_PCIE_RECOG_ID_SEM BIT(31)
/* WFDMA0 PCIE1 */
-#define MT_WFDMA0_PCIE1_BASE 0xd8000
-#define MT_WFDMA0_PCIE1(ofs) (MT_WFDMA0_PCIE1_BASE + (ofs))
+#define MT_WFDMA0_PCIE1(ofs) __REG_MAP(dev, MT_WFDMA0_PCIE1_BASE, (ofs))
-#define MT_WFDMA0_PCIE1_BUSY_ENA MT_WFDMA0_PCIE1(0x13c)
+#define MT_WFDMA0_PCIE1_BUSY_ENA MT_WFDMA0_PCIE1(0x13c)
#define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0)
#define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1)
#define MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO BIT(2)
/* WFDMA1 PCIE1 */
-#define MT_WFDMA1_PCIE1_BASE 0xd9000
-#define MT_WFDMA1_PCIE1(ofs) (MT_WFDMA0_PCIE1_BASE + (ofs))
+#define MT_WFDMA1_PCIE1(ofs) __REG_MAP(dev, MT_WFDMA1_PCIE1_BASE, (ofs))
-#define MT_WFDMA1_PCIE1_BUSY_ENA MT_WFDMA1_PCIE1(0x13c)
+#define MT_WFDMA1_PCIE1_BUSY_ENA MT_WFDMA1_PCIE1(0x13c)
#define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0)
#define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1)
#define MT_WFDMA1_PCIE1_BUSY_ENA_RX_FIFO BIT(2)
-#define MT_TOP_RGU_BASE 0xf0000
-#define MT_TOP_PWR_CTRL (MT_TOP_RGU_BASE + (0x0))
-#define MT_TOP_PWR_KEY (0x5746 << 16)
-#define MT_TOP_PWR_SW_RST BIT(0)
-#define MT_TOP_PWR_SW_PWR_ON GENMASK(3, 2)
-#define MT_TOP_PWR_HW_CTRL BIT(4)
-#define MT_TOP_PWR_PWR_ON BIT(7)
+/* WFDMA COMMON */
+#define MT_INT_SOURCE_CSR __REG(dev, INT_SOURCE_CSR)
+#define MT_INT_MASK_CSR __REG(dev, INT_MASK_CSR)
+
+#define MT_INT1_SOURCE_CSR __REG(dev, INT1_SOURCE_CSR)
+#define MT_INT1_MASK_CSR __REG(dev, INT1_MASK_CSR)
+
+#define MT_TX_RING_BASE __REG(dev, TX_RING_BASE)
+#define MT_RX_EVENT_RING_BASE __REG(dev, RX_EVENT_RING_BASE)
+#define MT_RX_DATA_RING_BASE __REG(dev, RX_DATA_RING_BASE)
+
+#define MT_INT_RX_DONE_DATA0 __BIT(dev, RX_DONE_DAND0)
+#define MT_INT_RX_DONE_DATA1 __BIT(dev, RX_DONE_DAND1)
+#define MT_INT_RX_DONE_WM __BIT(dev, RX_DONE_MCU_WM)
+#define MT_INT_RX_DONE_WA __BIT(dev, RX_DONE_MCU_WA)
+#define MT_INT_RX_DONE_WA_MAIN __BIT(dev, RX_DONE_WA_BAND0)
+#define MT_INT_RX_DONE_WA_EXT __BIT(dev, RX_DONE_WA_BAND1)
+#define MT_INT_MCU_CMD __BIT(dev, RX_MCU_TO_HOST)
+
+#define MT_INT_RX_DONE_MCU (MT_INT_RX_DONE_WM | \
+ MT_INT_RX_DONE_WA)
+#define MT_INT_BAND0_RX_DONE (MT_INT_RX_DONE_WA_MAIN | \
+ MT_INT_RX_DONE_DATA0)
+#define MT_INT_BAND1_RX_DONE (MT_INT_RX_DONE_WA_MAIN | \
+ MT_INT_RX_DONE_WA_EXT | \
+ MT_INT_RX_DONE_DATA1)
+#define MT_INT_RX_DONE_ALL (MT_INT_RX_DONE_MCU | \
+ MT_INT_BAND0_RX_DONE | \
+ MT_INT_BAND1_RX_DONE)
+
+#define MT_INT_TX_DONE_FWDL __BIT(dev, TX_DONE_FWDL)
+#define MT_INT_TX_DONE_MCU_WM __BIT(dev, TX_DONE_MCU_WM)
+#define MT_INT_TX_DONE_MCU_WA __BIT(dev, TX_DONE_MCU_WA)
+#define MT_INT_TX_DONE_BAND0 __BIT(dev, TX_DONE_BAND0)
+#define MT_INT_TX_DONE_BAND1 __BIT(dev, TX_DONE_BAND1)
-#define MT_INFRA_CFG_BASE 0xf1000
-#define MT_INFRA(ofs) (MT_INFRA_CFG_BASE + (ofs))
+#define MT_INT_TX_DONE_MCU (MT_INT_TX_DONE_MCU_WA | \
+ MT_INT_TX_DONE_MCU_WM | \
+ MT_INT_TX_DONE_FWDL)
+#define MT_MCU_CMD __REG(dev, INT_MCU_CMD_SOURCE)
+#define MT_MCU_CMD_STOP_DMA_FW_RELOAD BIT(1)
+#define MT_MCU_CMD_STOP_DMA BIT(2)
+#define MT_MCU_CMD_RESET_DONE BIT(3)
+#define MT_MCU_CMD_RECOVERY_DONE BIT(4)
+#define MT_MCU_CMD_NORMAL_STATE BIT(5)
+#define MT_MCU_CMD_ERROR_MASK GENMASK(5, 1)
-#define MT_HIF_REMAP_L1 MT_INFRA(0x1ac)
+/* TOP RGU */
+#define MT_TOP_RGU_BASE 0x18000000
+#define MT_TOP_PWR_CTRL (MT_TOP_RGU_BASE + (0x0))
+#define MT_TOP_PWR_KEY (0x5746 << 16)
+#define MT_TOP_PWR_SW_RST BIT(0)
+#define MT_TOP_PWR_SW_PWR_ON GENMASK(3, 2)
+#define MT_TOP_PWR_HW_CTRL BIT(4)
+#define MT_TOP_PWR_PWR_ON BIT(7)
+
+/* l1/l2 remap */
+#define MT_HIF_REMAP_L1 __REG(dev, L1_REMAP_CFG_OFFSET)
#define MT_HIF_REMAP_L1_MASK GENMASK(15, 0)
#define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0)
#define MT_HIF_REMAP_L1_BASE GENMASK(31, 16)
-#define MT_HIF_REMAP_BASE_L1 0xe0000
+#define MT_HIF_REMAP_BASE_L1 __REG_MAP(dev, MT_REMAP_L1_BASE, 0)
+
+#define MT_HIF_REMAP_L2 __REG(dev, L2_REMAP_CFG_OFFSET)
+#define MT_HIF_REMAP_L2_MASK __MASK(dev, L2_REMAP_MASK)
+#define MT_HIF_REMAP_L2_OFFSET __MASK(dev, L2_REMAP_OFFSET)
+#define MT_HIF_REMAP_L2_BASE __MASK(dev, L2_REMAP_BASE)
+#define MT_HIF_REMAP_BASE_L2 __REG_MAP(dev, MT_REMAP_L2_BASE, 0)
+
+#define MT_INFRA_BASE 0x18000000
+#define MT_WFSYS0_PHY_START 0x18400000
+#define MT_WFSYS1_PHY_START 0x18800000
+#define MT_WFSYS1_PHY_END 0x18bfffff
+#define MT_CBTOP1_PHY_START 0x70000000
+#define MT_CBTOP1_PHY_END 0x7fffffff
+#define MT_CBTOP2_PHY_START 0xf0000000
+#define MT_CBTOP2_PHY_END 0xffffffff
+#define MT_CONN_INFRA_MCU_START 0x7c000000
+#define MT_CONN_INFRA_MCU_END __REG_MAP(dev, MT_INFRA_MCU_END_BASE, 0)
+
+/* FW MODE SYNC */
+#define MT_SWDEF(ofs) __REG_MAP(dev, MT_SWDEF_BASE, (ofs))
-#define MT_HIF_REMAP_L2 MT_INFRA(0x1b0)
-#define MT_HIF_REMAP_L2_MASK GENMASK(19, 0)
-#define MT_HIF_REMAP_L2_OFFSET GENMASK(11, 0)
-#define MT_HIF_REMAP_L2_BASE GENMASK(31, 12)
-#define MT_HIF_REMAP_BASE_L2 0x00000
+#define MT_SWDEF_MODE MT_SWDEF(0x3c)
+#define MT_SWDEF_NORMAL_MODE 0
+#define MT_SWDEF_ICAP_MODE 1
+#define MT_SWDEF_SPECTRUM_MODE 2
#define MT_DIC_CMD_REG_BASE 0x41f000
#define MT_DIC_CMD_REG(ofs) (MT_DIC_CMD_REG_BASE + (ofs))
@@ -540,13 +755,7 @@
#define MT_CPU_UTIL_PEAK_IDLE_CNT MT_CPU_UTIL(0x0c)
#define MT_CPU_UTIL_CTRL MT_CPU_UTIL(0x1c)
-#define MT_SWDEF_BASE 0x41f200
-#define MT_SWDEF(ofs) (MT_SWDEF_BASE + (ofs))
-#define MT_SWDEF_MODE MT_SWDEF(0x3c)
-#define MT_SWDEF_NORMAL_MODE 0
-#define MT_SWDEF_ICAP_MODE 1
-#define MT_SWDEF_SPECTRUM_MODE 2
-
+/* LED */
#define MT_LED_TOP_BASE 0x18013000
#define MT_LED_PHYS(_n) (MT_LED_TOP_BASE + (_n))
@@ -561,6 +770,11 @@
#define MT_LED_EN(_n) MT_LED_PHYS(0x40 + ((_n) * 4))
+#define MT_LED_GPIO_MUX2 0x70005058 /* GPIO 18 */
+#define MT_LED_GPIO_MUX3 0x7000505C /* GPIO 26 */
+#define MT_LED_GPIO_SEL_MASK GENMASK(11, 8)
+
+/* MT TOP */
#define MT_TOP_BASE 0x18060000
#define MT_TOP(ofs) (MT_TOP_BASE + (ofs))
@@ -571,22 +785,17 @@
#define MT_TOP_MISC MT_TOP(0xf0)
#define MT_TOP_MISC_FW_STATE GENMASK(2, 0)
-#define MT_LED_GPIO_MUX2 0x70005058 /* GPIO 18 */
-#define MT_LED_GPIO_MUX3 0x7000505C /* GPIO 26 */
-#define MT_LED_GPIO_SEL_MASK GENMASK(11, 8)
-
#define MT_HW_BOUND 0x70010020
#define MT_HW_CHIPID 0x70010200
#define MT_HW_REV 0x70010204
-#define MT_PCIE1_MAC_BASE 0x74020000
-#define MT_PCIE1_MAC(ofs) (MT_PCIE1_MAC_BASE + (ofs))
-#define MT_PCIE1_MAC_INT_ENABLE MT_PCIE1_MAC(0x188)
-
-#define MT_PCIE_MAC_BASE 0x74030000
-#define MT_PCIE_MAC(ofs) (MT_PCIE_MAC_BASE + (ofs))
+/* PCIE MAC */
+#define MT_PCIE_MAC(ofs) __REG_MAP(dev, MT_PCIE_MAC_BASE, (ofs))
#define MT_PCIE_MAC_INT_ENABLE MT_PCIE_MAC(0x188)
+#define MT_PCIE1_MAC(ofs) __REG_MAP(dev, MT_PCIE1_MAC_BASE, (ofs))
+#define MT_PCIE1_MAC_INT_ENABLE MT_PCIE1_MAC(0x188)
+
#define MT_WF_IRPI_BASE 0x83006000
#define MT_WF_IRPI(ofs) (MT_WF_IRPI_BASE + ((ofs) << 16))
@@ -600,7 +809,7 @@
#define MT_WF_PHY_RXTD12(_phy) MT_WF_PHY(0x8230 + ((_phy) << 16))
#define MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY BIT(18)
-#define MT_WF_PHY_RXTD12_IRPI_SW_CLR BIT(29)
+#define MT_WF_PHY_RXTD12_IRPI_SW_CLR BIT(29)
#define MT_MCU_WM_CIRQ_BASE 0x89010000
#define MT_MCU_WM_CIRQ(ofs) (MT_MCU_WM_CIRQ_BASE + (ofs))
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/testmode.c b/drivers/net/wireless/mediatek/mt76/mt7915/testmode.c
index af80c2c..0ff14bd 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/testmode.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/testmode.c
@@ -23,30 +23,16 @@ struct reg_band {
u32 band[2];
};
-#define REG_BAND(_reg) \
- { .band[0] = MT_##_reg(0), .band[1] = MT_##_reg(1) }
-#define REG_BAND_IDX(_reg, _idx) \
- { .band[0] = MT_##_reg(0, _idx), .band[1] = MT_##_reg(1, _idx) }
-
-static const struct reg_band reg_backup_list[] = {
- REG_BAND_IDX(AGG_PCR0, 0),
- REG_BAND_IDX(AGG_PCR0, 1),
- REG_BAND_IDX(AGG_AWSCR0, 0),
- REG_BAND_IDX(AGG_AWSCR0, 1),
- REG_BAND_IDX(AGG_AWSCR0, 2),
- REG_BAND_IDX(AGG_AWSCR0, 3),
- REG_BAND(AGG_MRCR),
- REG_BAND(TMAC_TFCR0),
- REG_BAND(TMAC_TCR0),
- REG_BAND(AGG_ATCR1),
- REG_BAND(AGG_ATCR3),
- REG_BAND(TMAC_TRCR0),
- REG_BAND(TMAC_ICR0),
- REG_BAND_IDX(ARB_DRNGR0, 0),
- REG_BAND_IDX(ARB_DRNGR0, 1),
- REG_BAND(WF_RFCR),
- REG_BAND(WF_RFCR1),
-};
+#define REG_BAND(_list, _reg) \
+ { _list.band[0] = MT_##_reg(0); \
+ _list.band[1] = MT_##_reg(1); }
+#define REG_BAND_IDX(_list, _reg, _idx) \
+ { _list.band[0] = MT_##_reg(0, _idx); \
+ _list.band[1] = MT_##_reg(1, _idx); }
+
+#define TM_REG_MAX_ID 17
+static struct reg_band reg_backup_list[TM_REG_MAX_ID];
+
static int
mt7915_tm_set_tx_power(struct mt7915_phy *phy)
@@ -355,6 +341,24 @@ mt7915_tm_reg_backup_restore(struct mt7915_phy *phy)
u32 *b = phy->test.reg_backup;
int i;
+ REG_BAND_IDX(reg_backup_list[0], AGG_PCR0, 0);
+ REG_BAND_IDX(reg_backup_list[1], AGG_PCR0, 1);
+ REG_BAND_IDX(reg_backup_list[2], AGG_AWSCR0, 0);
+ REG_BAND_IDX(reg_backup_list[3], AGG_AWSCR0, 1);
+ REG_BAND_IDX(reg_backup_list[4], AGG_AWSCR0, 2);
+ REG_BAND_IDX(reg_backup_list[5], AGG_AWSCR0, 3);
+ REG_BAND(reg_backup_list[6], AGG_MRCR);
+ REG_BAND(reg_backup_list[7], TMAC_TFCR0);
+ REG_BAND(reg_backup_list[8], TMAC_TCR0);
+ REG_BAND(reg_backup_list[9], AGG_ATCR1);
+ REG_BAND(reg_backup_list[10], AGG_ATCR3);
+ REG_BAND(reg_backup_list[11], TMAC_TRCR0);
+ REG_BAND(reg_backup_list[12], TMAC_ICR0);
+ REG_BAND_IDX(reg_backup_list[13], ARB_DRNGR0, 0);
+ REG_BAND_IDX(reg_backup_list[14], ARB_DRNGR0, 1);
+ REG_BAND(reg_backup_list[15], WF_RFCR);
+ REG_BAND(reg_backup_list[16], WF_RFCR1);
+
if (phy->mt76->test.state == MT76_TM_STATE_OFF) {
for (i = 0; i < n_regs; i++)
mt76_wr(dev, reg_backup_list[i].band[ext_phy], b[i]);
@@ -725,6 +729,7 @@ mt7915_tm_dump_stats(struct mt76_phy *mphy, struct sk_buff *msg)
void *rx, *rssi;
u16 fcs_err;
int i;
+ u32 cnt;
rx = nla_nest_start(msg, MT76_TM_STATS_ATTR_LAST_RX);
if (!rx)
@@ -768,8 +773,9 @@ mt7915_tm_dump_stats(struct mt76_phy *mphy, struct sk_buff *msg)
nla_nest_end(msg, rx);
- fcs_err = mt76_get_field(dev, MT_MIB_SDR3(ext_phy),
- MT_MIB_SDR3_FCS_ERR_MASK);
+ cnt = mt76_rr(dev, MT_MIB_SDR3(ext_phy));
+ fcs_err = __FIELD_GET(MIB_SDR3_FCS_ERR, cnt);
+
q = ext_phy ? MT_RXQ_EXT : MT_RXQ_MAIN;
mphy->test.rx_stats.packets[q] += fcs_err;
mphy->test.rx_stats.fcs_error[q] += fcs_err;
--
2.18.0
From: Bo Jiao <[email protected]>
Adjust proper eeprom size and add default calibrated data support
for mt7916.
Co-developed-by: Shayne Chen <[email protected]>
Signed-off-by: Shayne Chen <[email protected]>
Co-developed-by: Sujuan Chen <[email protected]>
Signed-off-by: Sujuan Chen <[email protected]>
Signed-off-by: Bo Jiao <[email protected]>
Reviewed-by: Ryder Lee <[email protected]>
---
drivers/net/wireless/mediatek/mt76/mt7915/eeprom.c | 11 ++++++++---
drivers/net/wireless/mediatek/mt76/mt7915/mcu.c | 7 ++++---
drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h | 8 ++++++++
3 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/eeprom.c b/drivers/net/wireless/mediatek/mt76/mt7915/eeprom.c
index 40dcbeb..6aa749b 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/eeprom.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/eeprom.c
@@ -35,6 +35,7 @@ static int mt7915_check_eeprom(struct mt7915_dev *dev)
switch (val) {
case 0x7915:
+ case 0x7916:
return 0;
default:
return -EINVAL;
@@ -52,6 +53,9 @@ mt7915_eeprom_load_default(struct mt7915_dev *dev)
if (dev->dbdc_support)
default_bin = MT7915_EEPROM_DEFAULT_DBDC;
+ if (!is_mt7915(&dev->mt76))
+ default_bin = MT7916_EEPROM_DEFAULT;
+
ret = request_firmware(&fw, default_bin, dev->mt76.dev);
if (ret)
return ret;
@@ -62,7 +66,7 @@ mt7915_eeprom_load_default(struct mt7915_dev *dev)
goto out;
}
- memcpy(eeprom, fw->data, MT7915_EEPROM_SIZE);
+ memcpy(eeprom, fw->data, mt7915_eeprom_size(dev));
dev->flash_mode = true;
out:
@@ -74,8 +78,9 @@ out:
static int mt7915_eeprom_load(struct mt7915_dev *dev)
{
int ret;
+ u16 eeprom_size = mt7915_eeprom_size(dev);
- ret = mt76_eeprom_init(&dev->mt76, MT7915_EEPROM_SIZE);
+ ret = mt76_eeprom_init(&dev->mt76, eeprom_size);
if (ret < 0)
return ret;
@@ -91,7 +96,7 @@ static int mt7915_eeprom_load(struct mt7915_dev *dev)
return -EINVAL;
/* read eeprom data from efuse */
- block_num = DIV_ROUND_UP(MT7915_EEPROM_SIZE,
+ block_num = DIV_ROUND_UP(eeprom_size,
MT7915_EEPROM_BLOCK_SIZE);
for (i = 0; i < block_num; i++)
mt7915_mcu_get_eeprom(dev,
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mcu.c b/drivers/net/wireless/mediatek/mt76/mt7915/mcu.c
index 42a9135..668c617 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mcu.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mcu.c
@@ -3514,7 +3514,8 @@ static int mt7915_mcu_set_eeprom_flash(struct mt7915_dev *dev)
#define PAGE_IDX_MASK GENMASK(4, 2)
#define PER_PAGE_SIZE 0x400
struct mt7915_mcu_eeprom req = { .buffer_mode = EE_MODE_BUFFER };
- u8 total = DIV_ROUND_UP(MT7915_EEPROM_SIZE, PER_PAGE_SIZE);
+ u16 eeprom_size = mt7915_eeprom_size(dev);
+ u8 total = DIV_ROUND_UP(eeprom_size, PER_PAGE_SIZE);
u8 *eep = (u8 *)dev->mt76.eeprom.data;
int eep_len;
int i;
@@ -3523,8 +3524,8 @@ static int mt7915_mcu_set_eeprom_flash(struct mt7915_dev *dev)
struct sk_buff *skb;
int ret;
- if (i == total - 1 && !!(MT7915_EEPROM_SIZE % PER_PAGE_SIZE))
- eep_len = MT7915_EEPROM_SIZE % PER_PAGE_SIZE;
+ if (i == total - 1 && !!(eeprom_size % PER_PAGE_SIZE))
+ eep_len = eeprom_size % PER_PAGE_SIZE;
else
eep_len = PER_PAGE_SIZE;
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
index e8fbe69..4cc2666 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
@@ -37,8 +37,11 @@
#define MT7915_EEPROM_DEFAULT "mediatek/mt7915_eeprom.bin"
#define MT7915_EEPROM_DEFAULT_DBDC "mediatek/mt7915_eeprom_dbdc.bin"
+#define MT7916_EEPROM_DEFAULT "mediatek/mt7916_eeprom.bin"
#define MT7915_EEPROM_SIZE 3584
+#define MT7916_EEPROM_SIZE 4096
+
#define MT7915_EEPROM_BLOCK_SIZE 16
#define MT7915_TOKEN_SIZE 8192
@@ -483,6 +486,11 @@ static inline u16 mt7915_wtbl_size(struct mt7915_dev *dev)
return is_mt7915(&dev->mt76) ? MT7915_WTBL_SIZE : MT7916_WTBL_SIZE;
}
+static inline u16 mt7915_eeprom_size(struct mt7915_dev *dev)
+{
+ return is_mt7915(&dev->mt76) ? MT7915_EEPROM_SIZE : MT7916_EEPROM_SIZE;
+}
+
void mt7915_dual_hif_set_irq_mask(struct mt7915_dev *dev, bool write_reg,
u32 clear, u32 set);
--
2.18.0
From: Bo Jiao <[email protected]>
Update v2 offset. This is an intermediate patch to add mt7916 support.
Co-developed-by: Sujuan Chen <[email protected]>
Signed-off-by: Sujuan Chen <[email protected]>
Co-developed-by: Ryder Lee <[email protected]>
Signed-off-by: Ryder Lee <[email protected]>
Signed-off-by: Bo Jiao <[email protected]>
---
drivers/net/wireless/mediatek/mt76/mt7915/mcu.c | 13 +++++++++----
drivers/net/wireless/mediatek/mt76/mt7915/mcu.h | 8 +++++++-
2 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mcu.c b/drivers/net/wireless/mediatek/mt76/mt7915/mcu.c
index fd1df7e..42a9135 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mcu.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mcu.c
@@ -3757,19 +3757,24 @@ int mt7915_mcu_apply_tx_dpd(struct mt7915_phy *phy)
int mt7915_mcu_get_chan_mib_info(struct mt7915_phy *phy, bool chan_switch)
{
/* strict order */
- static const enum mt7915_chan_mib_offs offs[] = {
- MIB_BUSY_TIME, MIB_TX_TIME, MIB_RX_TIME, MIB_OBSS_AIRTIME
+ static const u32 offs[] = {
+ MIB_BUSY_TIME, MIB_TX_TIME, MIB_RX_TIME, MIB_OBSS_AIRTIME,
+ MIB_BUSY_TIME_V2, MIB_TX_TIME_V2, MIB_RX_TIME_V2,
+ MIB_OBSS_AIRTIME_V2
};
struct mt76_channel_state *state = phy->mt76->chan_state;
struct mt76_channel_state *state_ts = &phy->state_ts;
struct mt7915_dev *dev = phy->dev;
struct mt7915_mcu_mib *res, req[4];
struct sk_buff *skb;
- int i, ret;
+ int i, ret, start = 0;
+
+ if (!is_mt7915(&dev->mt76))
+ start = 4;
for (i = 0; i < 4; i++) {
req[i].band = cpu_to_le32(phy != &dev->phy);
- req[i].offs = cpu_to_le32(offs[i]);
+ req[i].offs = cpu_to_le32(offs[i + start]);
}
ret = mt76_mcu_send_and_get_msg(&dev->mt76, MCU_EXT_CMD(GET_MIB_INFO),
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mcu.h b/drivers/net/wireless/mediatek/mt76/mt7915/mcu.h
index c917243..d7b9dd0 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mcu.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mcu.h
@@ -182,10 +182,16 @@ struct mt7915_mcu_mib {
} __packed;
enum mt7915_chan_mib_offs {
+ /* mt7915 */
MIB_BUSY_TIME = 14,
MIB_TX_TIME = 81,
MIB_RX_TIME,
- MIB_OBSS_AIRTIME = 86
+ MIB_OBSS_AIRTIME = 86,
+ /* mt7916 */
+ MIB_BUSY_TIME_V2 = 0,
+ MIB_TX_TIME_V2 = 6,
+ MIB_RX_TIME_V2 = 8,
+ MIB_OBSS_AIRTIME_V2 = 490
};
struct edca {
--
2.18.0
From: Bo Jiao <[email protected]>
This is an intermediate patch to add mt7916 support.
Co-developed-by: Sujuan Chen <[email protected]>
Signed-off-by: Sujuan Chen <[email protected]>
Co-developed-by: Ryder Lee <[email protected]>
Signed-off-by: Ryder Lee <[email protected]>
Signed-off-by: Bo Jiao <[email protected]>
---
v2:
- extend mac address from main phy mac address for ext phy
when ext phy mac address is invalid.
---
.../wireless/mediatek/mt76/mt7915/eeprom.c | 76 ++++++++++++++-----
.../wireless/mediatek/mt76/mt7915/eeprom.h | 9 ++-
.../net/wireless/mediatek/mt76/mt7915/init.c | 56 ++++++++++----
.../wireless/mediatek/mt76/mt7915/mt7915.h | 3 +-
4 files changed, 107 insertions(+), 37 deletions(-)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/eeprom.c b/drivers/net/wireless/mediatek/mt76/mt7915/eeprom.c
index edd74d0..40dcbeb 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/eeprom.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/eeprom.c
@@ -10,6 +10,7 @@ static int mt7915_eeprom_load_precal(struct mt7915_dev *dev)
struct mt76_dev *mdev = &dev->mt76;
u8 *eeprom = mdev->eeprom.data;
u32 val = eeprom[MT_EE_DO_PRE_CAL];
+ u32 offs;
if (!dev->flash_mode)
return 0;
@@ -22,7 +23,9 @@ static int mt7915_eeprom_load_precal(struct mt7915_dev *dev)
if (!dev->cal)
return -ENOMEM;
- return mt76_get_of_eeprom(mdev, dev->cal, MT_EE_PRECAL, val);
+ offs = is_mt7915(&dev->mt76) ? MT_EE_PRECAL : MT_EE_PRECAL_V2;
+
+ return mt76_get_of_eeprom(mdev, dev->cal, offs, val);
}
static int mt7915_check_eeprom(struct mt7915_dev *dev)
@@ -98,7 +101,7 @@ static int mt7915_eeprom_load(struct mt7915_dev *dev)
return mt7915_check_eeprom(dev);
}
-void mt7915_eeprom_parse_band_config(struct mt7915_phy *phy)
+static void mt7915_eeprom_parse_band_config(struct mt7915_phy *phy)
{
struct mt7915_dev *dev = phy->dev;
bool ext_phy = phy != &dev->phy;
@@ -124,32 +127,55 @@ void mt7915_eeprom_parse_band_config(struct mt7915_phy *phy)
}
}
-static void mt7915_eeprom_parse_hw_cap(struct mt7915_dev *dev)
+void mt7915_eeprom_parse_hw_cap(struct mt7915_dev *dev,
+ struct mt7915_phy *phy)
{
u8 nss, nss_band, *eeprom = dev->mt76.eeprom.data;
+ struct mt76_phy *mphy = phy->mt76;
+ bool ext_phy = phy != &dev->phy;
+
+ mt7915_eeprom_parse_band_config(phy);
- mt7915_eeprom_parse_band_config(&dev->phy);
+ /* read tx/rx mask from eeprom */
+ if (is_mt7915(&dev->mt76)) {
+ nss = FIELD_GET(MT_EE_WIFI_CONF0_TX_PATH,
+ eeprom[MT_EE_WIFI_CONF]);
+ } else {
+ nss = FIELD_GET(MT_EE_WIFI_CONF0_TX_PATH,
+ eeprom[MT_EE_WIFI_CONF + ext_phy]);
+ }
- /* read tx mask from eeprom */
- nss = FIELD_GET(MT_EE_WIFI_CONF0_TX_PATH, eeprom[MT_EE_WIFI_CONF]);
if (!nss || nss > 4)
nss = 4;
+ /* read tx/rx stream */
nss_band = nss;
-
if (dev->dbdc_support) {
- nss_band = FIELD_GET(MT_EE_WIFI_CONF3_TX_PATH_B0,
- eeprom[MT_EE_WIFI_CONF + 3]);
+ if (is_mt7915(&dev->mt76)) {
+ nss_band = FIELD_GET(MT_EE_WIFI_CONF3_TX_PATH_B0,
+ eeprom[MT_EE_WIFI_CONF + 3]);
+ if (ext_phy)
+ nss_band = FIELD_GET(MT_EE_WIFI_CONF3_TX_PATH_B1,
+ eeprom[MT_EE_WIFI_CONF + 3]);
+ } else {
+ nss_band = FIELD_GET(MT_EE_WIFI_CONF_STREAM_NUM,
+ eeprom[MT_EE_WIFI_CONF + 2 + ext_phy]);
+ }
+
if (!nss_band || nss_band > 2)
nss_band = 2;
+ }
- if (nss_band >= nss)
- nss = 4;
+ if (nss_band > nss) {
+ dev_err(dev->mt76.dev,
+ "nss mismatch, nss(%d) nss_band(%d) ext_phy(%d)\n",
+ nss, nss_band, ext_phy);
+ nss = nss_band;
}
- dev->chainmask = BIT(nss) - 1;
- dev->mphy.antenna_mask = BIT(nss_band) - 1;
- dev->mphy.chainmask = dev->mphy.antenna_mask;
+ mphy->chainmask = ext_phy ? (BIT(nss_band) - 1) << 2 : (BIT(nss_band) - 1);
+ mphy->antenna_mask = BIT(hweight8(mphy->chainmask)) - 1;
+ dev->chainmask |= mphy->chainmask;
}
int mt7915_eeprom_init(struct mt7915_dev *dev)
@@ -171,7 +197,7 @@ int mt7915_eeprom_init(struct mt7915_dev *dev)
if (ret)
return ret;
- mt7915_eeprom_parse_hw_cap(dev);
+ mt7915_eeprom_parse_hw_cap(dev, &dev->phy);
memcpy(dev->mphy.macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR,
ETH_ALEN);
@@ -194,15 +220,20 @@ int mt7915_eeprom_get_target_power(struct mt7915_dev *dev,
tssi_on = mt7915_tssi_enabled(dev, chan->band);
if (chan->band == NL80211_BAND_2GHZ) {
- index = MT_EE_TX0_POWER_2G + chain_idx * 3;
+ u32 power = is_mt7915(&dev->mt76) ?
+ MT_EE_TX0_POWER_2G : MT_EE_TX0_POWER_2G_V2;
+
+ index = power + chain_idx * 3;
target_power = eeprom[index];
if (!tssi_on)
target_power += eeprom[index + 1];
} else {
int group = mt7915_get_channel_group(chan->hw_value);
+ u32 power = is_mt7915(&dev->mt76) ?
+ MT_EE_TX0_POWER_5G : MT_EE_TX0_POWER_5G_V2;
- index = MT_EE_TX0_POWER_5G + chain_idx * 12;
+ index = power + chain_idx * 12;
target_power = eeprom[index + group];
if (!tssi_on)
@@ -217,11 +248,18 @@ s8 mt7915_eeprom_get_power_delta(struct mt7915_dev *dev, int band)
u8 *eeprom = dev->mt76.eeprom.data;
u32 val;
s8 delta;
+ u32 rate_2g, rate_5g;
+
+ rate_2g = is_mt7915(&dev->mt76) ?
+ MT_EE_RATE_DELTA_2G : MT_EE_RATE_DELTA_2G_V2;
+
+ rate_5g = is_mt7915(&dev->mt76) ?
+ MT_EE_RATE_DELTA_5G : MT_EE_RATE_DELTA_5G_V2;
if (band == NL80211_BAND_2GHZ)
- val = eeprom[MT_EE_RATE_DELTA_2G];
+ val = eeprom[rate_2g];
else
- val = eeprom[MT_EE_RATE_DELTA_5G];
+ val = eeprom[rate_5g];
if (!(val & MT_EE_RATE_DELTA_EN))
return 0;
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/eeprom.h b/drivers/net/wireless/mediatek/mt76/mt7915/eeprom.h
index a43389a..92d1a94 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/eeprom.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/eeprom.h
@@ -23,11 +23,17 @@ enum mt7915_eeprom_field {
MT_EE_RATE_DELTA_5G = 0x29d,
MT_EE_TX0_POWER_2G = 0x2fc,
MT_EE_TX0_POWER_5G = 0x34b,
+ MT_EE_RATE_DELTA_2G_V2 = 0x7d3,
+ MT_EE_RATE_DELTA_5G_V2 = 0x81e,
+ MT_EE_TX0_POWER_2G_V2 = 0x441,
+ MT_EE_TX0_POWER_5G_V2 = 0x445,
MT_EE_ADIE_FT_VERSION = 0x9a0,
__MT_EE_MAX = 0xe00,
+ __MT_EE_MAX_V2 = 0x1000,
/* 0xe10 ~ 0x5780 used to save group cal data */
- MT_EE_PRECAL = 0xe10
+ MT_EE_PRECAL = 0xe10,
+ MT_EE_PRECAL_V2 = 0x1010
};
#define MT_EE_WIFI_CAL_GROUP BIT(0)
@@ -39,6 +45,7 @@ enum mt7915_eeprom_field {
#define MT_EE_WIFI_CONF0_TX_PATH GENMASK(2, 0)
#define MT_EE_WIFI_CONF0_BAND_SEL GENMASK(7, 6)
#define MT_EE_WIFI_CONF1_BAND_SEL GENMASK(7, 6)
+#define MT_EE_WIFI_CONF_STREAM_NUM GENMASK(7, 5)
#define MT_EE_WIFI_CONF3_TX_PATH_B0 GENMASK(1, 0)
#define MT_EE_WIFI_CONF3_TX_PATH_B1 GENMASK(5, 4)
#define MT_EE_WIFI_CONF7_TSSI0_2G BIT(0)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/init.c b/drivers/net/wireless/mediatek/mt76/mt7915/init.c
index 324263e..c2eae36 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/init.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/init.c
@@ -307,6 +307,7 @@ mt7915_init_wiphy(struct ieee80211_hw *hw)
{
struct mt7915_phy *phy = mt7915_hw_phy(hw);
struct wiphy *wiphy = hw->wiphy;
+ struct mt7915_dev *dev = phy->dev;
hw->queues = 4;
hw->max_rx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF;
@@ -349,14 +350,34 @@ mt7915_init_wiphy(struct ieee80211_hw *hw)
phy->mt76->sband_5g.sband.ht_cap.cap |=
IEEE80211_HT_CAP_LDPC_CODING |
IEEE80211_HT_CAP_MAX_AMSDU;
- phy->mt76->sband_5g.sband.vht_cap.cap |=
- IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991 |
- IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK;
+
+ if (is_mt7915(&dev->mt76)) {
+ phy->mt76->sband_5g.sband.vht_cap.cap |=
+ IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991 |
+ IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK;
+
+ if (!dev->dbdc_support)
+ phy->mt76->sband_5g.sband.vht_cap.cap |=
+ IEEE80211_VHT_CAP_SHORT_GI_160 |
+ IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ;
+ } else {
+ phy->mt76->sband_5g.sband.vht_cap.cap |=
+ IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
+ IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK;
+
+ /* mt7916 dbdc with 2g 2x2 bw40 and 5g 2x2 bw160c */
+ phy->mt76->sband_5g.sband.vht_cap.cap |=
+ IEEE80211_VHT_CAP_SHORT_GI_160 |
+ IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ;
+ }
}
mt76_set_stream_caps(phy->mt76, true);
mt7915_set_stream_vht_txbf_caps(phy);
mt7915_set_stream_he_caps(phy);
+
+ wiphy->available_antennas_rx = phy->mt76->antenna_mask;
+ wiphy->available_antennas_tx = phy->mt76->antenna_mask;
}
static void
@@ -456,18 +477,27 @@ static int mt7915_register_ext_phy(struct mt7915_dev *dev)
phy = mphy->priv;
phy->dev = dev;
phy->mt76 = mphy;
- mphy->chainmask = dev->chainmask & ~dev->mphy.chainmask;
- mphy->antenna_mask = BIT(hweight8(mphy->chainmask)) - 1;
INIT_DELAYED_WORK(&mphy->mac_work, mt7915_mac_work);
- mt7915_eeprom_parse_band_config(phy);
- mt7915_init_wiphy(mphy->hw);
+ mt7915_eeprom_parse_hw_cap(dev, phy);
memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR2,
ETH_ALEN);
+ /*
+ * Make the secondary PHY MAC address local without overlapping with
+ * the usual MAC address allocation scheme on multiple virtual interfaces
+ */
+ if (!is_valid_ether_addr(mphy->macaddr)) {
+ memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR,
+ ETH_ALEN);
+ mphy->macaddr[0] |= 2;
+ mphy->macaddr[0] ^= BIT(7);
+ }
mt76_eeprom_override(mphy);
+ /* init wiphy according to mphy and phy */
+ mt7915_init_wiphy(mphy->hw);
ret = mt7915_init_tx_queues(phy, MT7915_TXQ_BAND1,
MT7915_TX_RING_SIZE);
if (ret)
@@ -562,7 +592,9 @@ static int mt7915_init_hardware(struct mt7915_dev *dev)
mt76_wr(dev, MT_INT_SOURCE_CSR, ~0);
INIT_WORK(&dev->init_work, mt7915_init_work);
- dev->dbdc_support = !!(mt76_rr(dev, MT_HW_BOUND) & BIT(5));
+
+ dev->dbdc_support = is_mt7915(&dev->mt76) ?
+ !!(mt76_rr(dev, MT_HW_BOUND) & BIT(5)) : true;
/* If MCU was already running, it is likely in a bad state */
if (mt76_get_field(dev, MT_TOP_MISC, MT_TOP_MISC_FW_STATE) >
@@ -589,7 +621,6 @@ static int mt7915_init_hardware(struct mt7915_dev *dev)
if (ret < 0)
return ret;
-
if (dev->flash_mode) {
ret = mt7915_mcu_apply_group_cal(dev);
if (ret)
@@ -935,13 +966,6 @@ int mt7915_register_device(struct mt7915_dev *dev)
mt7915_init_wiphy(hw);
- if (!dev->dbdc_support)
- dev->mphy.sband_5g.sband.vht_cap.cap |=
- IEEE80211_VHT_CAP_SHORT_GI_160 |
- IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ;
-
- dev->mphy.hw->wiphy->available_antennas_rx = dev->mphy.chainmask;
- dev->mphy.hw->wiphy->available_antennas_tx = dev->mphy.chainmask;
dev->phy.dfs_state = -1;
#ifdef CONFIG_NL80211_TESTMODE
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
index cee719f..3e2e900 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
@@ -386,7 +386,8 @@ u64 __mt7915_get_tsf(struct ieee80211_hw *hw, struct mt7915_vif *mvif);
int mt7915_register_device(struct mt7915_dev *dev);
void mt7915_unregister_device(struct mt7915_dev *dev);
int mt7915_eeprom_init(struct mt7915_dev *dev);
-void mt7915_eeprom_parse_band_config(struct mt7915_phy *phy);
+void mt7915_eeprom_parse_hw_cap(struct mt7915_dev *dev,
+ struct mt7915_phy *phy);
int mt7915_eeprom_get_target_power(struct mt7915_dev *dev,
struct ieee80211_channel *chan,
u8 chain_idx);
--
2.18.0
From: Bo Jiao <[email protected]>
Add pci_device_id to enable mt7916. Note that MT_HW_CHIPID is no
longer used for further chips, so drop it accordingly.
Co-developed-by: Sujuan Chen <[email protected]>
Signed-off-by: Sujuan Chen <[email protected]>
Co-developed-by: Ryder Lee <[email protected]>
Signed-off-by: Ryder Lee <[email protected]>
Signed-off-by: Bo Jiao <[email protected]>
---
drivers/net/wireless/mediatek/mt76/mt7915/mmio.c | 2 +-
drivers/net/wireless/mediatek/mt76/mt7915/pci.c | 7 +++++--
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mmio.c b/drivers/net/wireless/mediatek/mt76/mt7915/mmio.c
index 7ba5b1f..d463b3c 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mmio.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mmio.c
@@ -534,7 +534,7 @@ static int mt7915_mmio_init(struct mt76_dev *mdev,
bus_ops->rmw = mt7915_rmw;
dev->mt76.bus = bus_ops;
- mdev->rev = (mt76_rr(dev, MT_HW_CHIPID) << 16) |
+ mdev->rev = (device_id << 16) |
(mt76_rr(dev, MT_HW_REV) & 0xff);
dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/pci.c b/drivers/net/wireless/mediatek/mt76/mt7915/pci.c
index 3134b46..8d1a811 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/pci.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/pci.c
@@ -18,11 +18,13 @@ static u32 hif_idx;
static const struct pci_device_id mt7915_pci_device_table[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7915) },
+ { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7906) },
{ },
};
static const struct pci_device_id mt7915_hif_device_table[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7916) },
+ { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x790a) },
{ },
};
@@ -61,7 +63,8 @@ static void mt7915_put_hif2(struct mt7915_hif *hif)
static struct mt7915_hif *mt7915_pci_init_hif2(struct pci_dev *pdev)
{
hif_idx++;
- if (!pci_get_device(PCI_VENDOR_ID_MEDIATEK, 0x7916, NULL))
+ if (!pci_get_device(PCI_VENDOR_ID_MEDIATEK, 0x7916, NULL) &&
+ !pci_get_device(PCI_VENDOR_ID_MEDIATEK, 0x790a, NULL))
return NULL;
writel(hif_idx | MT_PCIE_RECOG_ID_SEM,
@@ -112,7 +115,7 @@ static int mt7915_pci_probe(struct pci_dev *pdev,
mt76_pci_disable_aspm(pdev);
- if (id->device == 0x7916)
+ if (id->device == 0x7916 || id->device == 0x790a)
return mt7915_pci_hif2_probe(pdev);
ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
--
2.18.0
From: Bo Jiao <[email protected]>
mt7916 reports rx rate from rxd group3 directly.
Co-developed-by: Sujuan Chen <[email protected]>
Signed-off-by: Sujuan Chen <[email protected]>
Co-developed-by: Ryder Lee <[email protected]>
Signed-off-by: Ryder Lee <[email protected]>
Signed-off-by: Bo Jiao <[email protected]>
---
.../net/wireless/mediatek/mt76/mt7915/init.c | 3 +-
.../net/wireless/mediatek/mt76/mt7915/mac.c | 199 +++++++++++-------
.../net/wireless/mediatek/mt76/mt7915/mac.h | 6 +
.../net/wireless/mediatek/mt76/mt7915/main.c | 11 +-
4 files changed, 137 insertions(+), 82 deletions(-)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/init.c b/drivers/net/wireless/mediatek/mt76/mt7915/init.c
index 1b8a47c..6dae11a 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/init.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/init.c
@@ -408,7 +408,8 @@ mt7915_mac_init_band(struct mt7915_dev *dev, u8 band)
mt76_rmw(dev, MT_MDP_BNRCFR1(band), mask, set);
mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_MAX_RX_LEN, 0x680);
- /* disable rx rate report by default due to hw issues */
+
+ /* mt7915: disable rx rate report by default due to hw issues */
mt76_clear(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_RXD_G5_EN);
}
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
index 8e3901b..84879a3 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
@@ -460,6 +460,119 @@ static int mt7915_reverse_frag0_hdr_trans(struct sk_buff *skb, u16 hdr_gap)
return 0;
}
+static int
+mt7915_mac_fill_rx_rate(struct mt7915_dev *dev,
+ struct mt76_rx_status *status,
+ struct ieee80211_supported_band *sband,
+ __le32 *rxv)
+{
+ u32 v0, v1, v2;
+ u16 legacy;
+ u8 flags, stbc, gi, bw, dcm, mode, nss;
+ int i, idx;
+ bool cck = false;
+
+ v0 = le32_to_cpu(rxv[0]);
+ v1 = le32_to_cpu(rxv[1]);
+ v2 = le32_to_cpu(rxv[2]);
+
+ idx = i = FIELD_GET(MT_PRXV_TX_RATE, v0);
+ nss = FIELD_GET(MT_PRXV_NSTS, v0) + 1;
+
+ if (!is_mt7915(&dev->mt76)) {
+ stbc = FIELD_GET(MT_PRXV_HT_STBC, v0);
+ gi = FIELD_GET(MT_PRXV_HT_SHORT_GI, v0);
+ mode = FIELD_GET(MT_PRXV_TX_MODE, v0);
+ dcm = FIELD_GET(MT_PRXV_DCM, v0);
+ bw = FIELD_GET(MT_PRXV_FRAME_MODE, v0);
+ } else {
+ stbc = FIELD_GET(MT_CRXV_HT_STBC, v2);
+ gi = FIELD_GET(MT_CRXV_HT_SHORT_GI, v2);
+ mode = FIELD_GET(MT_CRXV_TX_MODE, v2);
+ dcm = !!(idx & GENMASK(3, 0) & MT_PRXV_TX_DCM);
+ bw = FIELD_GET(MT_CRXV_FRAME_MODE, v2);
+ }
+
+ switch (mode) {
+ case MT_PHY_TYPE_CCK:
+ cck = true;
+ fallthrough;
+ case MT_PHY_TYPE_OFDM:
+ i = mt76_get_rate(&dev->mt76, sband, i, cck);
+ legacy = sband->bitrates[i].bitrate;
+ break;
+ case MT_PHY_TYPE_HT_GF:
+ case MT_PHY_TYPE_HT:
+ status->encoding = RX_ENC_HT;
+ if (i > 31)
+ return -EINVAL;
+
+ flags = RATE_INFO_FLAGS_MCS;
+ if (gi)
+ flags |= RATE_INFO_FLAGS_SHORT_GI;
+ break;
+ case MT_PHY_TYPE_VHT:
+ status->nss = nss;
+ status->encoding = RX_ENC_VHT;
+ if (i > 9)
+ return -EINVAL;
+
+ flags = RATE_INFO_FLAGS_VHT_MCS;
+ if (gi)
+ flags |= RATE_INFO_FLAGS_SHORT_GI;
+ break;
+ case MT_PHY_TYPE_HE_MU:
+ status->flag |= RX_FLAG_RADIOTAP_HE_MU;
+ fallthrough;
+ case MT_PHY_TYPE_HE_SU:
+ case MT_PHY_TYPE_HE_EXT_SU:
+ case MT_PHY_TYPE_HE_TB:
+ status->nss = nss;
+ status->encoding = RX_ENC_HE;
+ status->flag |= RX_FLAG_RADIOTAP_HE;
+ i &= GENMASK(3, 0);
+
+ if (gi <= NL80211_RATE_INFO_HE_GI_3_2)
+ status->he_gi = gi;
+
+ status->he_dcm = dcm;
+ flags |= RATE_INFO_FLAGS_HE_MCS;
+ break;
+ default:
+ return -EINVAL;
+ }
+ status->rate_idx = i;
+
+ switch (bw) {
+ case IEEE80211_STA_RX_BW_20:
+ break;
+ case IEEE80211_STA_RX_BW_40:
+ if (mode & MT_PHY_TYPE_HE_EXT_SU &&
+ (idx & MT_PRXV_TX_ER_SU_106T)) {
+ status->bw = RATE_INFO_BW_HE_RU;
+ status->he_ru =
+ NL80211_RATE_INFO_HE_RU_ALLOC_106;
+ } else {
+ status->bw = RATE_INFO_BW_40;
+ }
+ break;
+ case IEEE80211_STA_RX_BW_80:
+ status->bw = RATE_INFO_BW_80;
+ break;
+ case IEEE80211_STA_RX_BW_160:
+ status->bw = RATE_INFO_BW_160;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc;
+ if (mode < MT_PHY_TYPE_HE_SU && gi)
+ status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
+
+ return 0;
+}
+
static int
mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
{
@@ -618,7 +731,8 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
/* RXD Group 3 - P-RXV */
if (rxd1 & MT_RXD1_NORMAL_GROUP_3) {
- u32 v0, v1, v2;
+ u32 v0, v1;
+ int ret;
rxv = rxd;
rxd += 2;
@@ -627,7 +741,6 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
v0 = le32_to_cpu(rxv[0]);
v1 = le32_to_cpu(rxv[1]);
- v2 = le32_to_cpu(rxv[2]);
if (v0 & MT_PRXV_HT_AD_CODE)
status->enc_flags |= RX_ENC_FLAG_LDPC;
@@ -649,85 +762,17 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
/* RXD Group 5 - C-RXV */
if (rxd1 & MT_RXD1_NORMAL_GROUP_5) {
- u8 stbc = FIELD_GET(MT_CRXV_HT_STBC, v2);
- u8 gi = FIELD_GET(MT_CRXV_HT_SHORT_GI, v2);
- bool cck = false;
-
rxd += 18;
if ((u8 *)rxd - skb->data >= skb->len)
return -EINVAL;
+ }
- idx = i = FIELD_GET(MT_PRXV_TX_RATE, v0);
- mode = FIELD_GET(MT_CRXV_TX_MODE, v2);
-
- switch (mode) {
- case MT_PHY_TYPE_CCK:
- cck = true;
- fallthrough;
- case MT_PHY_TYPE_OFDM:
- i = mt76_get_rate(&dev->mt76, sband, i, cck);
- break;
- case MT_PHY_TYPE_HT_GF:
- case MT_PHY_TYPE_HT:
- status->encoding = RX_ENC_HT;
- if (i > 31)
- return -EINVAL;
- break;
- case MT_PHY_TYPE_VHT:
- status->nss =
- FIELD_GET(MT_PRXV_NSTS, v0) + 1;
- status->encoding = RX_ENC_VHT;
- if (i > 9)
- return -EINVAL;
- break;
- case MT_PHY_TYPE_HE_MU:
- status->flag |= RX_FLAG_RADIOTAP_HE_MU;
- fallthrough;
- case MT_PHY_TYPE_HE_SU:
- case MT_PHY_TYPE_HE_EXT_SU:
- case MT_PHY_TYPE_HE_TB:
- status->nss =
- FIELD_GET(MT_PRXV_NSTS, v0) + 1;
- status->encoding = RX_ENC_HE;
- status->flag |= RX_FLAG_RADIOTAP_HE;
- i &= GENMASK(3, 0);
-
- if (gi <= NL80211_RATE_INFO_HE_GI_3_2)
- status->he_gi = gi;
-
- status->he_dcm = !!(idx & MT_PRXV_TX_DCM);
- break;
- default:
- return -EINVAL;
- }
- status->rate_idx = i;
-
- switch (FIELD_GET(MT_CRXV_FRAME_MODE, v2)) {
- case IEEE80211_STA_RX_BW_20:
- break;
- case IEEE80211_STA_RX_BW_40:
- if (mode & MT_PHY_TYPE_HE_EXT_SU &&
- (idx & MT_PRXV_TX_ER_SU_106T)) {
- status->bw = RATE_INFO_BW_HE_RU;
- status->he_ru =
- NL80211_RATE_INFO_HE_RU_ALLOC_106;
- } else {
- status->bw = RATE_INFO_BW_40;
- }
- break;
- case IEEE80211_STA_RX_BW_80:
- status->bw = RATE_INFO_BW_80;
- break;
- case IEEE80211_STA_RX_BW_160:
- status->bw = RATE_INFO_BW_160;
- break;
- default:
- return -EINVAL;
- }
-
- status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc;
- if (mode < MT_PHY_TYPE_HE_SU && gi)
- status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
+ if (!is_mt7915(&dev->mt76) ||
+ (is_mt7915(&dev->mt76) &&
+ (rxd1 & MT_RXD1_NORMAL_GROUP_5))) {
+ ret = mt7915_mac_fill_rx_rate(dev, status, sband, rxv);
+ if (ret < 0)
+ return ret;
}
}
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mac.h b/drivers/net/wireless/mediatek/mt76/mt7915/mac.h
index 4504ebc..d79f0a5 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mac.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mac.h
@@ -125,6 +125,12 @@ enum rx_pkt_type {
#define MT_PRXV_RCPI2 GENMASK(23, 16)
#define MT_PRXV_RCPI1 GENMASK(15, 8)
#define MT_PRXV_RCPI0 GENMASK(7, 0)
+#define MT_PRXV_HT_SHORT_GI GENMASK(16, 15)
+#define MT_PRXV_HT_STBC GENMASK(23, 22)
+#define MT_PRXV_TX_MODE GENMASK(27, 24)
+#define MT_PRXV_FRAME_MODE GENMASK(14, 12)
+#define MT_PRXV_DCM BIT(17)
+#define MT_PRXV_NUM_RX BIT(20, 18)
/* C-RXV */
#define MT_CRXV_HT_STBC GENMASK(1, 0)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/main.c b/drivers/net/wireless/mediatek/mt76/mt7915/main.c
index 057ab27..0650140 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/main.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/main.c
@@ -969,11 +969,14 @@ static void mt7915_sta_statistics(struct ieee80211_hw *hw,
struct mt7915_phy *phy = mt7915_hw_phy(hw);
struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
struct rate_info *txrate = &msta->wcid.rate;
- struct rate_info rxrate = {};
- if (!mt7915_mcu_get_rx_rate(phy, vif, sta, &rxrate)) {
- sinfo->rxrate = rxrate;
- sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_BITRATE);
+ if (is_mt7915(&phy->dev->mt76)) {
+ struct rate_info rxrate = {};
+
+ if (!mt7915_mcu_get_rx_rate(phy, vif, sta, &rxrate)) {
+ sinfo->rxrate = rxrate;
+ sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_BITRATE);
+ }
}
if (!txrate->legacy && !txrate->flags)
--
2.18.0
Hi,
Thank you for the patch. Some comments and change requests below.
On 2021-11-23 08:49, Bo Jiao wrote:
> From: Bo Jiao <[email protected]>
>
> Add mt7915_reg_desc to differentiate chip generations.
> This is an intermediate patch to introduce mt7916 support.
>
> Co-developed-by: Sujuan Chen <[email protected]>
> Signed-off-by: Sujuan Chen <[email protected]>
> Co-developed-by: Ryder Lee <[email protected]>
> Signed-off-by: Ryder Lee <[email protected]>
> Signed-off-by: Bo Jiao <[email protected]>
> ---
> .../wireless/mediatek/mt76/mt7915/debugfs.c | 20 +-
> .../net/wireless/mediatek/mt76/mt7915/dma.c | 5 +-
> .../net/wireless/mediatek/mt76/mt7915/mac.c | 26 +-
> .../net/wireless/mediatek/mt76/mt7915/mmio.c | 507 +++++++++++++--
> .../wireless/mediatek/mt76/mt7915/mt7915.h | 4 +-
> .../net/wireless/mediatek/mt76/mt7915/regs.h | 607 ++++++++++++------
> .../wireless/mediatek/mt76/mt7915/testmode.c | 58 +-
> 7 files changed, 907 insertions(+), 320 deletions(-)
>
> diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mmio.c b/drivers/net/wireless/mediatek/mt76/mt7915/mmio.c
> index 2f8b72b..0d67321 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt7915/mmio.c
> +++ b/drivers/net/wireless/mediatek/mt76/mt7915/mmio.c
> @@ -10,100 +10,449 @@
> #include "mac.h"
> #include "../trace.h"
>
I think the patch and the code can be much simpler if we get rid of the
base address abstraction that you introduced. Some more comments below:
> +static const u32 mt7915_base[] = {
> + [MT_REMAP_L1_CFG_BASE] = 0xf1000,
> + [MT_REMAP_L1_BASE] = 0xe0000,
> + [MT_REMAP_L2_CFG_BASE] = 0xf1000,
> + [MT_REMAP_L2_BASE] = 0x00000,
The use of these is limited to the mt7915_reg_map_l* functions. You can
simply add separate #defines and separate register map functions for
7915 and 7916.
> + [MT_INFRA_MCU_END_BASE] = 0x7c3fffff,
This one is unused if you also get rid of MT_CONN_INFRA_MCU_START and
MT_CONN_INFRA_MCU_END.
> + [MT_PCIE_MAC_BASE] = 0x74030000,
Same as 7916
> + [MT_PCIE1_MAC_BASE] = 0x74020000,
This is used in one place only. Separate register definitions would make
this easier to follow.
> + [MT_WFDMA0_BASE] = 0xd4000,
> + [MT_WFDMA1_BASE] = 0xd5000,
> + [MT_WFDMA0_PCIE1_BASE] = 0xd8000,
> + [MT_WFDMA1_PCIE1_BASE] = 0xd9000,
> + [MT_WFDMA_EXT_CSR_BASE] = 0xd7000,
Same as 7916
> + [MT_SWDEF_BASE] = 0x41f200,
Again used in one place only, so separate definitions makes sense here
as well.
> + [MT_MCU_WFDMA0_BASE] = 0x2000,
> + [MT_MCU_WFDMA1_BASE] = 0x3000,
Same as 7916.
> [...]
> +static const struct __reg mt7915_reg[] = {
> + [L1_REMAP_CFG_OFFSET] = { MT_REMAP_L1_CFG_BASE, 0x1ac },
> + [L2_REMAP_CFG_OFFSET] = { MT_REMAP_L2_CFG_BASE, 0x1b0 },
Same as for MT_REMAP_L1_CFG_BASE, ...
> + [INT_SOURCE_CSR] = { MT_WFDMA_EXT_CSR_BASE, 0x10 },
> + [INT_MASK_CSR] = { MT_WFDMA_EXT_CSR_BASE, 0x14 },
> + [INT1_SOURCE_CSR] = { MT_WFDMA_EXT_CSR_BASE, 0x88 },
> + [INT1_MASK_CSR] = { MT_WFDMA_EXT_CSR_BASE, 0x8c },
> + [INT_MCU_CMD_SOURCE] = { MT_WFDMA1_BASE, 0x1f0 },
> + [INT_MCU_CMD_EVENT] = { MT_MCU_WFDMA1_BASE, 0x108 },
> + [TX_RING_BASE] = { MT_WFDMA1_BASE, 0x400 },
> + [RX_EVENT_RING_BASE] = { MT_WFDMA1_BASE, 0x500 },
> + [RX_DATA_RING_BASE] = { MT_WFDMA0_BASE, 0x500 },
> + [TMAC_CDTR] = { INVALID_BASE, 0x090 },
> + [TMAC_ODTR] = { INVALID_BASE, 0x094 },
> + [TMAC_ATCR] = { INVALID_BASE, 0x098 },
> + [TMAC_TRCR0] = { INVALID_BASE, 0x09c },
> + [TMAC_ICR0] = { INVALID_BASE, 0x0a4 },
> + [TMAC_ICR1] = { INVALID_BASE, 0x0b4 },
> + [TMAC_CTCR0] = { INVALID_BASE, 0x0f4 },
> + [TMAC_TFCR0] = { INVALID_BASE, 0x1e0 },
> + [MDP_BNRCFR0] = { INVALID_BASE, 0x070 },
> + [MDP_BNRCFR1] = { INVALID_BASE, 0x074 },
> + [ARB_DRNGR0] = { INVALID_BASE, 0x194 },
> + [ARB_SCR] = { INVALID_BASE, 0x080 },
> + [RMAC_MIB_AIRTIME14] = { INVALID_BASE, 0x3b8 },
> + [AGG_AWSCR0] = { INVALID_BASE, 0x05c },
> + [AGG_PCR0] = { INVALID_BASE, 0x06c },
> + [AGG_ACR0] = { INVALID_BASE, 0x084 },
> + [AGG_MRCR] = { INVALID_BASE, 0x098 },
> + [AGG_ATCR1] = { INVALID_BASE, 0x0f0 },
> + [AGG_ATCR3] = { INVALID_BASE, 0x0f4 },
> + [LPON_UTTR0] = { INVALID_BASE, 0x080 },
> + [LPON_UTTR1] = { INVALID_BASE, 0x084 },
> + [MIB_SDR3] = { INVALID_BASE, 0x014 },
> + [MIB_SDR4] = { INVALID_BASE, 0x018 },
> + [MIB_SDR5] = { INVALID_BASE, 0x01c },
> + [MIB_SDR7] = { INVALID_BASE, 0x024 },
> + [MIB_SDR8] = { INVALID_BASE, 0x028 },
> + [MIB_SDR9] = { INVALID_BASE, 0x02c },
> + [MIB_SDR10] = { INVALID_BASE, 0x030 },
> + [MIB_SDR11] = { INVALID_BASE, 0x034 },
> + [MIB_SDR12] = { INVALID_BASE, 0x038 },
> + [MIB_SDR13] = { INVALID_BASE, 0x03c },
> + [MIB_SDR14] = { INVALID_BASE, 0x040 },
> + [MIB_SDR15] = { INVALID_BASE, 0x044 },
> + [MIB_SDR16] = { INVALID_BASE, 0x048 },
> + [MIB_SDR17] = { INVALID_BASE, 0x04c },
> + [MIB_SDR18] = { INVALID_BASE, 0x050 },
> + [MIB_SDR19] = { INVALID_BASE, 0x054 },
> + [MIB_SDR20] = { INVALID_BASE, 0x058 },
> + [MIB_SDR21] = { INVALID_BASE, 0x05c },
> + [MIB_SDR22] = { INVALID_BASE, 0x060 },
> + [MIB_SDR23] = { INVALID_BASE, 0x064 },
> + [MIB_SDR24] = { INVALID_BASE, 0x068 },
> + [MIB_SDR25] = { INVALID_BASE, 0x06c },
> + [MIB_SDR27] = { INVALID_BASE, 0x074 },
> + [MIB_SDR28] = { INVALID_BASE, 0x078 },
> + [MIB_SDR29] = { INVALID_BASE, 0x07c },
> + [MIB_SDRVEC] = { INVALID_BASE, 0x080 },
> + [MIB_SDR31] = { INVALID_BASE, 0x084 },
> + [MIB_SDR32] = { INVALID_BASE, 0x088 },
> + [MIB_SDRMUBF] = { INVALID_BASE, 0x090 },
> + [MIB_DR8] = { INVALID_BASE, 0x0c0 },
> + [MIB_DR9] = { INVALID_BASE, 0x0c4 },
> + [MIB_DR11] = { INVALID_BASE, 0x0cc },
> + [MIB_MB_SDR0] = { INVALID_BASE, 0x100 },
> + [MIB_MB_SDR1] = { INVALID_BASE, 0x104 },
> + [TX_AGG_CNT] = { INVALID_BASE, 0x0a8 },
> + [TX_AGG_CNT2] = { INVALID_BASE, 0x164 },
> + [MIB_ARNG] = { INVALID_BASE, 0x4b8 },
> + [WTBLON_TOP_WDUCR] = { INVALID_BASE, 0x0},
> + [WTBL_UPDATE] = { INVALID_BASE, 0x030},
> + [PLE_FL_Q_EMPTY] = { INVALID_BASE, 0x0b0},
> + [PLE_FL_Q_CTRL] = { INVALID_BASE, 0x1b0},
> + [PLE_AC_QEMPTY] = { INVALID_BASE, 0x500},
> + [PLE_FREEPG_CNT] = { INVALID_BASE, 0x100},
> + [PLE_FREEPG_HEAD_TAIL] = { INVALID_BASE, 0x104},
> + [PLE_PG_HIF_GROUP] = { INVALID_BASE, 0x110},
> + [PLE_HIF_PG_INFO] = { INVALID_BASE, 0x114},
> + [AC_OFFSET] = { INVALID_BASE, 0x040},
> +};
I think you can replace the { base, reg } tuple with just a register
address (or offset). For the PLE register definitions, it probably also
makes sense to get rid of the array indirection and just add separate
definitions and functions.
> [...]
> +
> +static const struct __mask mt7915_mask[] = {
> + [L2_REMAP_MASK] = {19, 0},
> + [L2_REMAP_OFFSET] = {11, 0},
> + [L2_REMAP_BASE] = {31, 12},
> + [MIB_SDR3_FCS_ERR] = {15, 0},
> + [MIB_MRDY_CNT] = {25, 0},
> + [MIB_MPDU_ATTEMPTS_CNT] = {23, 0},
> + [MIB_MPDU_SUCCESS_CNT] = {23, 0},
> + [MIB_AMPDU_SF_CNT] = {23, 0},
> + [MIB_PF_DROP_CNT] = {7, 0},
> + [MIB_VEC_DROP_CNT] = {15, 0},
> + [MIB_BF_TX_CNT] = {15, 0},
> +};
> +
> +static const struct __mask mt7916_mask[] = {
> + [L2_REMAP_MASK] = {31, 16},
> + [L2_REMAP_OFFSET] = {15, 0},
> + [L2_REMAP_BASE] = {31, 16},
> + [MIB_SDR3_FCS_ERR] = {31, 16},
> + [MIB_MRDY_CNT] = {31, 0},
> + [MIB_MPDU_ATTEMPTS_CNT] = {31, 0},
> + [MIB_MPDU_SUCCESS_CNT] = {31, 0},
> + [MIB_AMPDU_SF_CNT] = {31, 0},
> + [MIB_PF_DROP_CNT] = {15, 0},
> + [MIB_VEC_DROP_CNT] = {31, 16},
> + [MIB_BF_TX_CNT] = {31, 16},
> +};
I think this array should also be removed and the mask differences
open-coded in the relevant functions.
> +
> +static const u32 mt7915_bit[] = {
> + [RX_DONE_DAND0] = 16,
> + [RX_DONE_DAND1] = 17,
> + [RX_DONE_MCU_WM] = 0,
> + [RX_DONE_MCU_WA] = 1,
> + [RX_DONE_WA_BAND0] = 1,
> + [RX_DONE_WA_BAND1] = 2,
> + [TX_DONE_FWDL] = 26,
> + [TX_DONE_MCU_WM] = 27,
> + [TX_DONE_MCU_WA] = 15,
> + [TX_DONE_BAND0] = 30,
> + [TX_DONE_BAND1] = 31,
> + [RX_MCU_TO_HOST] = 29,
> + [MIB_MB_SDR] = 2,
> + [LPON_TCR] = 0,
> +};
> +
> +static const u32 mt7916_bit[] = {
> + [RX_DONE_DAND0] = 22,
> + [RX_DONE_DAND1] = 23,
> + [RX_DONE_MCU_WM] = 0,
> + [RX_DONE_MCU_WA] = 1,
> + [RX_DONE_WA_BAND0] = 2,
> + [RX_DONE_WA_BAND1] = 3,
> + [TX_DONE_FWDL] = 26,
> + [TX_DONE_MCU_WM] = 27,
> + [TX_DONE_MCU_WA] = 25,
> + [TX_DONE_BAND0] = 30,
> + [TX_DONE_BAND1] = 31,
> + [RX_MCU_TO_HOST] = 29,
> + [MIB_MB_SDR] = 1,
> + [LPON_TCR] = 2,
> +};
I think for the interrupt masks we should have a separate mask
definitions for 7915 vs 7916 and check for the chip type in
mt7915_irq_tasklet.
The other two bits also don't seem worth keeping a separate array for,
so better just open-code the differences.
> +
> +static const struct __map mt7915_reg_map[] = {
> + { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
> + { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure regs) */
> + { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
> + { 0x54000000, 0x02000, 0x1000 }, /* WFDMA PCIE0 MCU DMA0 */
> + { 0x55000000, 0x03000, 0x1000 }, /* WFDMA PCIE0 MCU DMA1 */
> + { 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
> + { 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */
> + { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
> + { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
> + { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
> + { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
> + { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */
> + { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */
> + { 0x820cc000, 0x0e000, 0x2000 }, /* WF_UMAC_TOP (PP) */
> + { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */
> + { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */
> + { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
> + { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
> + { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
> + { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
> + { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
> + { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
> + { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
> + { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
> + { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
> + { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
> + { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
> + { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
> + { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
> + { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
> + { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
> + { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
> + { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
> + { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
> + { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
> + { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
> + { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
> + { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
> + { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
> + { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
> + { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
> + { 0x0, 0x0, 0x0 }, /* imply end of search */
> +};
> +
> +static const struct __map mt7916_reg_map[] = {
> + { 0x54000000, 0x02000, 0x1000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */
> + { 0x55000000, 0x03000, 0x1000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */
> + { 0x56000000, 0x04000, 0x1000 }, /* WFDMA_2 (Reserved) */
> + { 0x57000000, 0x05000, 0x1000 }, /* WFDMA_3 (MCU wrap CR) */
> + { 0x58000000, 0x06000, 0x1000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */
> + { 0x59000000, 0x07000, 0x1000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */
> + { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */
> + { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */
> + { 0x820cc000, 0x0e000, 0x2000 }, /* WF_UMAC_TOP (PP) */
> + { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
> + { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
> + { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
> + { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
> + { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
> + { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
> + { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */
> + { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
> + { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */
> + { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
> + { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
> + { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
> + { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
> + { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
> + { 0x820ca000, 0x26000, 0x2000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
> + { 0x820d0000, 0x30000, 0x10000}, /* WF_LMAC_TOP (WF_WTBLON) */
> + { 0x00400000, 0x80000, 0x10000}, /* WF_MCU_SYSRAM */
> + { 0x00410000, 0x90000, 0x10000}, /* WF_MCU_SYSRAM (configure cr) */
> + { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
> + { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
> + { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
> + { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
> + { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
> + { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
> + { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
> + { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
> + { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
> + { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
> + { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
> + { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
> + { 0x820c4000, 0xa8000, 0x1000 }, /* WF_LMAC_TOP (WF_UWTBL ) */
> + { 0x820b0000, 0xae000, 0x1000 }, /* [APB2] WFSYS_ON */
> + { 0x80020000, 0xb0000, 0x10000}, /* WF_TOP_MISC_OFF */
> + { 0x81020000, 0xc0000, 0x10000}, /* WF_TOP_MISC_ON */
> + { 0x0, 0x0, 0x100000 }, /* fixed remap range */
This "fixed remap range" entry isn't needed, this is already handled in
__mt7915_reg_addr.
> + { 0x0, 0x0, 0x0 }, /* imply end of search */
> +};
> + [...]
>
> static u32 __mt7915_reg_addr(struct mt7915_dev *dev, u32 addr)
> {
> - static const struct {
> - u32 phys;
> - u32 mapped;
> - u32 size;
> - } fixed_map[] = {
> - { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
> - { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure regs) */
> - { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
> - { 0x54000000, 0x02000, 0x1000 }, /* WFDMA PCIE0 MCU DMA0 */
> - { 0x55000000, 0x03000, 0x1000 }, /* WFDMA PCIE0 MCU DMA1 */
> - { 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
> - { 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */
> - { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
> - { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
> - { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
> - { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
> - { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */
> - { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */
> - { 0x820cc000, 0x0e000, 0x2000 }, /* WF_UMAC_TOP (PP) */
> - { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */
> - { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */
> - { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
> - { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
> - { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
> - { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
> - { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
> - { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
> - { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
> - { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
> - { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
> - { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
> - { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
> - { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
> - { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
> - { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
> - { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
> - { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
> - { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
> - { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
> - { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
> - { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
> - { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
> - { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
> - { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
> - { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
> - { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
> - };
> int i;
>
> if (addr < 0x100000)
> return addr;
>
> - for (i = 0; i < ARRAY_SIZE(fixed_map); i++) {
> + if (!dev->reg->map) {
> + dev_err(dev->mt76.dev, "err: reg_map is null\n");
> + return addr;
> + }
> +
> + for (i = 0; i < dev->reg->map_size; i++) {
> u32 ofs;
>
> - if (addr < fixed_map[i].phys)
> + if (addr < dev->reg->map[i].phys)
> continue;
>
> - ofs = addr - fixed_map[i].phys;
> - if (ofs > fixed_map[i].size)
> + ofs = addr - dev->reg->map[i].phys;
> + if (ofs > dev->reg->map[i].size)
> continue;
>
> - return fixed_map[i].mapped + ofs;
> + return dev->reg->map[i].maps + ofs;
> }
>
> - if ((addr >= 0x18000000 && addr < 0x18c00000) ||
> - (addr >= 0x70000000 && addr < 0x78000000))
> + if ((addr >= MT_INFRA_BASE && addr < MT_WFSYS0_PHY_START) ||
> + (addr >= MT_WFSYS0_PHY_START && addr < MT_WFSYS1_PHY_START) ||
> + (addr >= MT_WFSYS1_PHY_START && addr <= MT_WFSYS1_PHY_END))
> + return mt7915_reg_map_l1(dev, addr);
> +
> + if (dev_is_pci(dev->mt76.dev) &&
> + ((addr >= MT_CBTOP1_PHY_START && addr <= MT_CBTOP1_PHY_END) ||
> + (addr >= MT_CBTOP2_PHY_START && addr <= MT_CBTOP2_PHY_END))) {
> + /* CONN_INFRA: covert to phyiscal addr and use layer 1 remap */
> + if (addr >= MT_CONN_INFRA_MCU_START &&
> + addr <= MT_CONN_INFRA_MCU_END)
> + addr = addr - MT_CONN_INFRA_MCU_START + MT_INFRA_BASE;
As far as I can tell, the MT_CONN_INFRA_MCU_START remapping is useless
and unused.
> +
> return mt7915_reg_map_l1(dev, addr);
> + }
>
> return mt7915_reg_map_l2(dev, addr);
> }
> @@ -138,10 +487,18 @@ static int mt7915_mmio_init(struct mt76_dev *mdev,
> {
> struct mt76_bus_ops *bus_ops;
> struct mt7915_dev *dev;
> + int i;
>
> dev = container_of(mdev, struct mt7915_dev, mt76);
> mt76_mmio_init(&dev->mt76, mem_base);
>
> + for (i = 0; i < ARRAY_SIZE(reg_desc); i++) {
> + if (device_id == reg_desc[i].id) {
> + dev->reg = ®_desc[i];
> + break;
> + }
> + }
I'd prefer removing the reg_desc array and just checking the chip types
here directly.
> +
> dev->bus_ops = dev->mt76.bus;
> bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
> GFP_KERNEL);
> @@ -184,15 +541,29 @@ static void mt7915_rx_poll_complete(struct mt76_dev *mdev,
> enum mt76_rxq_id q)
> {
> struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
> - static const u32 rx_irq_mask[] = {
> - [MT_RXQ_MAIN] = MT_INT_RX_DONE_DATA0,
> - [MT_RXQ_EXT] = MT_INT_RX_DONE_DATA1,
> - [MT_RXQ_MCU] = MT_INT_RX_DONE_WM,
> - [MT_RXQ_MCU_WA] = MT_INT_RX_DONE_WA,
> - [MT_RXQ_EXT_WA] = MT_INT_RX_DONE_WA_EXT,
> - };
> + u32 rx_irq_mask = 0;
> +
> + switch (q) {
> + case MT_RXQ_MAIN:
> + rx_irq_mask = MT_INT_RX_DONE_DATA0;
> + break;
> + case MT_RXQ_EXT:
> + rx_irq_mask = MT_INT_RX_DONE_DATA1;
> + break;
> + case MT_RXQ_MCU:
> + rx_irq_mask = MT_INT_RX_DONE_WM;
> + break;
> + case MT_RXQ_MCU_WA:
> + rx_irq_mask = MT_INT_RX_DONE_WA;
> + break;
> + case MT_RXQ_EXT_WA:
> + rx_irq_mask = MT_INT_RX_DONE_WA_EXT;
> + break;
> + default:
> + break;
> + }
If we have separate mask definitions, we could simply have two arrays
here, one for 7915 and one for 7916.
- Felix
On 2021-11-23 08:49, Bo Jiao wrote:
> From: Bo Jiao <[email protected]>
>
> The RXQ of mt7916 are separated to MT_RXQ_MAIN_WA and MT_RXQ_MCU_WA,
> which causes a hole for queue iteration so modify it accordingly.
>
> This is an intermediate patch to add mt7916 support.
>
> Co-developed-by: Sujuan Chen <[email protected]>
> Signed-off-by: Sujuan Chen <[email protected]>
> Co-developed-by: Ryder Lee <[email protected]>
> Signed-off-by: Ryder Lee <[email protected]>
> Signed-off-by: Bo Jiao <[email protected]>
> ---
> v2:
> - revert the modify to mt76_for_each_q_rx() which may cause
> not work for sdo/usb chip.
> ---
> drivers/net/wireless/mediatek/mt76/dma.c | 13 +-
> drivers/net/wireless/mediatek/mt76/mt76.h | 1 +
> .../net/wireless/mediatek/mt76/mt7915/dma.c | 375 ++++++++++++------
> .../net/wireless/mediatek/mt76/mt7915/init.c | 9 +-
> .../net/wireless/mediatek/mt76/mt7915/mac.c | 4 +
> .../net/wireless/mediatek/mt76/mt7915/mmio.c | 38 +-
> .../wireless/mediatek/mt76/mt7915/mt7915.h | 3 +-
> .../net/wireless/mediatek/mt76/mt7915/regs.h | 60 ++-
> 8 files changed, 358 insertions(+), 145 deletions(-)
>
> diff --git a/drivers/net/wireless/mediatek/mt76/dma.c b/drivers/net/wireless/mediatek/mt76/dma.c
> index 5e1c150..3cc1acf 100644
> --- a/drivers/net/wireless/mediatek/mt76/dma.c
> +++ b/drivers/net/wireless/mediatek/mt76/dma.c
> @@ -93,7 +93,7 @@ mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q)
> {
> int i;
>
> - if (!q)
> + if (!q || !q->ndesc)
> return;
>
> /* clear descriptors */
> @@ -233,7 +233,7 @@ mt76_dma_tx_cleanup(struct mt76_dev *dev, struct mt76_queue *q, bool flush)
> struct mt76_queue_entry entry;
> int last;
>
> - if (!q)
> + if (!q || !q->ndesc)
> return;
>
> spin_lock_bh(&q->cleanup_lock);
> @@ -448,6 +448,9 @@ mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
> int len = SKB_WITH_OVERHEAD(q->buf_size);
> int offset = q->buf_offset;
>
> + if (!q->ndesc)
> + return 0;
> +
> spin_lock_bh(&q->lock);
>
> while (q->queued < q->ndesc - 1) {
> @@ -484,6 +487,9 @@ mt76_dma_rx_cleanup(struct mt76_dev *dev, struct mt76_queue *q)
> void *buf;
> bool more;
>
> + if (!q->ndesc)
> + return;
> +
> spin_lock_bh(&q->lock);
> do {
> buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more);
> @@ -508,6 +514,9 @@ mt76_dma_rx_reset(struct mt76_dev *dev, enum mt76_rxq_id qid)
> struct mt76_queue *q = &dev->q_rx[qid];
> int i;
>
> + if (!q->ndesc)
> + return;
> +
> for (i = 0; i < q->ndesc; i++)
> q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE);
>
> diff --git a/drivers/net/wireless/mediatek/mt76/mt76.h b/drivers/net/wireless/mediatek/mt76/mt76.h
> index e2da720..8fd6890 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt76.h
> +++ b/drivers/net/wireless/mediatek/mt76/mt76.h
> @@ -85,6 +85,7 @@ enum mt76_rxq_id {
> MT_RXQ_MCU_WA,
> MT_RXQ_EXT,
> MT_RXQ_EXT_WA,
> + MT_RXQ_MAIN_WA,
> __MT_RXQ_MAX
> };
>
The mt76 core changes should be in a separate patch.
> diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/dma.c b/drivers/net/wireless/mediatek/mt76/mt7915/dma.c
> index ad9678b..05104b1 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt7915/dma.c
> +++ b/drivers/net/wireless/mediatek/mt76/mt7915/dma.c
> @@ -44,31 +44,52 @@ static int mt7915_poll_tx(struct napi_struct *napi, int budget)
> static void __mt7915_dma_prefetch(struct mt7915_dev *dev, u32 ofs)
> {
> #define PREFETCH(base, depth) ((base) << 16 | (depth))
> -
> - mt76_wr(dev, MT_WFDMA0_RX_RING0_EXT_CTRL + ofs, PREFETCH(0x0, 0x4));
> - mt76_wr(dev, MT_WFDMA0_RX_RING1_EXT_CTRL + ofs, PREFETCH(0x40, 0x4));
> - mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL + ofs, PREFETCH(0x80, 0x0));
> -
> - mt76_wr(dev, MT_WFDMA1_TX_RING0_EXT_CTRL + ofs, PREFETCH(0x80, 0x4));
> - mt76_wr(dev, MT_WFDMA1_TX_RING1_EXT_CTRL + ofs, PREFETCH(0xc0, 0x4));
> - mt76_wr(dev, MT_WFDMA1_TX_RING2_EXT_CTRL + ofs, PREFETCH(0x100, 0x4));
> - mt76_wr(dev, MT_WFDMA1_TX_RING3_EXT_CTRL + ofs, PREFETCH(0x140, 0x4));
> - mt76_wr(dev, MT_WFDMA1_TX_RING4_EXT_CTRL + ofs, PREFETCH(0x180, 0x4));
> - mt76_wr(dev, MT_WFDMA1_TX_RING5_EXT_CTRL + ofs, PREFETCH(0x1c0, 0x4));
> - mt76_wr(dev, MT_WFDMA1_TX_RING6_EXT_CTRL + ofs, PREFETCH(0x200, 0x4));
> - mt76_wr(dev, MT_WFDMA1_TX_RING7_EXT_CTRL + ofs, PREFETCH(0x240, 0x4));
> -
> - mt76_wr(dev, MT_WFDMA1_TX_RING16_EXT_CTRL + ofs, PREFETCH(0x280, 0x4));
> - mt76_wr(dev, MT_WFDMA1_TX_RING17_EXT_CTRL + ofs, PREFETCH(0x2c0, 0x4));
> - mt76_wr(dev, MT_WFDMA1_TX_RING18_EXT_CTRL + ofs, PREFETCH(0x300, 0x4));
> - mt76_wr(dev, MT_WFDMA1_TX_RING19_EXT_CTRL + ofs, PREFETCH(0x340, 0x4));
> - mt76_wr(dev, MT_WFDMA1_TX_RING20_EXT_CTRL + ofs, PREFETCH(0x380, 0x4));
> - mt76_wr(dev, MT_WFDMA1_TX_RING21_EXT_CTRL + ofs, PREFETCH(0x3c0, 0x0));
> -
> - mt76_wr(dev, MT_WFDMA1_RX_RING0_EXT_CTRL + ofs, PREFETCH(0x3c0, 0x4));
> - mt76_wr(dev, MT_WFDMA1_RX_RING1_EXT_CTRL + ofs, PREFETCH(0x400, 0x4));
> - mt76_wr(dev, MT_WFDMA1_RX_RING2_EXT_CTRL + ofs, PREFETCH(0x440, 0x4));
> - mt76_wr(dev, MT_WFDMA1_RX_RING3_EXT_CTRL + ofs, PREFETCH(0x480, 0x0));
> + struct mt76_dev *mdev = &dev->mt76;
> + u32 base_ofs = 0;
> +
> + /* prefetch SRAM wrapping boundary for tx/rx ring. */
> + mt76_wr(dev, MT_WFDMA_TX_RING_EXT_CTRL_FWDL + ofs,
> + PREFETCH(0x0, 0x4));
> + mt76_wr(dev, MT_WFDMA_TX_RING_EXT_CTRL_WM + ofs,
> + PREFETCH(0x40, 0x4));
> + mt76_wr(dev, MT_WFDMA_TX_RING_EXT_CTRL_BAND0 + ofs,
> + PREFETCH(0x80, 0x4));
> + mt76_wr(dev, MT_WFDMA_TX_RING_EXT_CTRL_BAND1 + ofs,
> + PREFETCH(0xc0, 0x4));
> + mt76_wr(dev, MT_WFDMA_TX_RING_EXT_CTRL_WA + ofs,
> + PREFETCH(0x100, 0x4));
> + mt76_wr(dev, MT_WFDMA1_TX_RING21_EXT_CTRL + ofs,
> + PREFETCH(0x140, 0x0));
> +
> + mt76_wr(dev, MT_WFDMA_RX_RING_EXT_CTRL_WM + ofs,
> + PREFETCH(0x140, 0x4));
> + if (!is_mt7915(mdev)) {
> + mt76_wr(dev, MT_WFDMA_RX_RING_EXT_CTRL_WA + ofs,
> + PREFETCH(0x180, 0x4));
> + base_ofs = 0x40;
> + }
> + mt76_wr(dev, MT_WFDMA_RX_RING_EXT_CTRL_STS0 + ofs,
> + PREFETCH(0x180 + base_ofs, 0x4));
> + mt76_wr(dev, MT_WFDMA_RX_RING_EXT_CTRL_STS1 + ofs,
> + PREFETCH(0x1c0 + base_ofs, 0x4));
> + mt76_wr(dev, MT_WFDMA_RX_RING_EXT_CTRL_BAND0 + ofs,
> + PREFETCH(0x200 + base_ofs, 0x4));
> + mt76_wr(dev, MT_WFDMA_RX_RING_EXT_CTRL_BAND1 + ofs,
> + PREFETCH(0x240 + base_ofs, 0x4));
> +
> + /* for mt7915, the ring which is next the last
> + * used ring must be initialized.
> + */
> + if (is_mt7915(mdev)) {
> + mt76_wr(dev, MT_WFDMA1_TX_RING21_EXT_CTRL + ofs,
> + PREFETCH(0x140, 0x0));
> +
> + mt76_wr(dev, MT_WFDMA1_RX_RING3_EXT_CTRL + ofs,
> + PREFETCH(0x200 + base_ofs, 0x0));
> +
> + mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL + ofs,
> + PREFETCH(0x280 + base_ofs, 0x0));
> + }
It seems to me that a large part of the tx/rx ring related register
differences come from the fact that they're distributed differently over
WFDMA0 and WFDMA1 on 7915 vs 7916. Maybe this could be simplified a lot
by using a chip specific mask for rx/tx queues that indicates which ones
should be on WFDMA1.
This could be used in queue allocation, prefetch configuration and maybe
in a few other places too.
- Felix
On 2021-11-23 08:49, Bo Jiao wrote:
> diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/main.c b/drivers/net/wireless/mediatek/mt76/mt7915/main.c
> index 057ab27..0650140 100644
> --- a/drivers/net/wireless/mediatek/mt76/mt7915/main.c
> +++ b/drivers/net/wireless/mediatek/mt76/mt7915/main.c
> @@ -969,11 +969,14 @@ static void mt7915_sta_statistics(struct ieee80211_hw *hw,
> struct mt7915_phy *phy = mt7915_hw_phy(hw);
> struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
> struct rate_info *txrate = &msta->wcid.rate;
> - struct rate_info rxrate = {};
>
> - if (!mt7915_mcu_get_rx_rate(phy, vif, sta, &rxrate)) {
> - sinfo->rxrate = rxrate;
> - sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_BITRATE);
> + if (is_mt7915(&phy->dev->mt76)) {
> + struct rate_info rxrate = {};
> +
> + if (!mt7915_mcu_get_rx_rate(phy, vif, sta, &rxrate)) {
> + sinfo->rxrate = rxrate;
> + sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_BITRATE);
> + }
> }
>
> if (!txrate->legacy && !txrate->flags)
You can simplify this part by leaving the code as-is and only changing
the if condition like this:
if (is_mt7915(&phy->dev->mt76) &&
!mt7915_mcu_get_rx_rate(phy, vif, sta, &rxrate) {
...
}