Now MBIGENs have pins that used to generate SPIs,
with
5052875 ("irqchip/gic-v3: Add support for Message Based Interrupts as an MSI controller"),
we can support MBIGEN to generate message based SPIs by writing
GICD_SETSPIR. This patchset add support for MBIGEN generating
message based SPIs and a bugfix for MBI driver.
Patch #1 is a bugfix for MBI driver.
Pathc #2 ~ #4 is support for MBIGEN generating message based SPIs.
v2:
Move the doorbell address comments to the top.
Yang Yingliang (4):
irqchip/gic-v3-mbi: fix uninitialized mbi_lock
irqchip/mbigen: rename register marcros
irqchip/mbigen: add support for a MBIGEN generating SPIs
dt-bindings/irqchip/mbigen: add example of MBIGEN generate SPIs
.../interrupt-controller/hisilicon,mbigen-v2.txt | 17 +++++++-
drivers/irqchip/irq-gic-v3-mbi.c | 2 +-
drivers/irqchip/irq-mbigen.c | 47 +++++++++++++++-------
3 files changed, 50 insertions(+), 16 deletions(-)
--
1.8.3
mbi_lock is uninitialized, use marco DEFINE_MUTEX
to initialize it.
Signed-off-by: Yang Yingliang <[email protected]>
---
drivers/irqchip/irq-gic-v3-mbi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-gic-v3-mbi.c b/drivers/irqchip/irq-gic-v3-mbi.c
index ad70e7c..fbfa7ff 100644
--- a/drivers/irqchip/irq-gic-v3-mbi.c
+++ b/drivers/irqchip/irq-gic-v3-mbi.c
@@ -24,7 +24,7 @@ struct mbi_range {
unsigned long *bm;
};
-static struct mutex mbi_lock;
+static DEFINE_MUTEX(mbi_lock);
static phys_addr_t mbi_phys_base;
static struct mbi_range *mbi_ranges;
static unsigned int mbi_range_nr;
--
1.8.3
Now with
5052875 ("irqchip/gic-v3: Add support for Message Based Interrupts as an MSI controller"),
we can support MBIGEN to generate message based SPIs by writing GICD_SETSPIR.
The first 64-pins of each MBIGEN chip is used to generate SPIs, and each
MBIGEN chip has several MBIGEN nodes, every node has 128 pins for generating
LPIs. The total pins are: 64(SPIs) + 128 * node_nr(LPIs). So we can translate
the pin index in a unified way in mbigen_domain_translate().
Also Add TYPE and VEC registers that used by generating SPIs, the driver can
access them when MBIGEN is used to generate SPIs.
Signed-off-by: Yang Yingliang <[email protected]>
---
drivers/irqchip/irq-mbigen.c | 29 ++++++++++++++++++++++++-----
1 file changed, 24 insertions(+), 5 deletions(-)
diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c
index f05998f..72db969 100644
--- a/drivers/irqchip/irq-mbigen.c
+++ b/drivers/irqchip/irq-mbigen.c
@@ -48,6 +48,7 @@
#define MBIGEN_NODE_OFFSET 0x1000
/* offset of vector register in mbigen node */
+#define REG_MBIGEN_SPI_VEC_OFFSET 0x500
#define REG_MBIGEN_LPI_VEC_OFFSET 0x200
/**
@@ -62,6 +63,7 @@
* This register is used to configure interrupt
* trigger type
*/
+#define REG_MBIGEN_SPI_TYPE_OFFSET 0x400
#define REG_MBIGEN_LPI_TYPE_OFFSET 0x0
/**
@@ -79,6 +81,9 @@ static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq)
{
unsigned int nid, pin;
+ if (hwirq < SPI_NUM_PER_MBIGEN_CHIP)
+ return (hwirq * 4 + REG_MBIGEN_SPI_VEC_OFFSET);
+
hwirq -= SPI_NUM_PER_MBIGEN_CHIP;
nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
pin = hwirq % IRQS_PER_MBIGEN_NODE;
@@ -92,6 +97,13 @@ static inline void get_mbigen_type_reg(irq_hw_number_t hwirq,
{
unsigned int nid, irq_ofst, ofst;
+ if (hwirq < SPI_NUM_PER_MBIGEN_CHIP) {
+ *mask = 1 << (hwirq % 32);
+ ofst = hwirq / 32 * 4;
+ *addr = ofst + REG_MBIGEN_SPI_TYPE_OFFSET;
+ return;
+ }
+
hwirq -= SPI_NUM_PER_MBIGEN_CHIP;
nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
irq_ofst = hwirq % IRQS_PER_MBIGEN_NODE;
@@ -162,14 +174,22 @@ static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg)
u32 val;
base += get_mbigen_vec_reg(d->hwirq);
+
+ /*
+ * The address of GICD_SETSPI_NSR and GITS_TRANSLATER
+ * is encoded in mbigen register by default. So,we don't
+ * need to program the doorbell address at here.
+ */
+ if (d->hwirq < SPI_NUM_PER_MBIGEN_CHIP) {
+ writel_relaxed(msg->data, base);
+ return;
+ }
+
val = readl_relaxed(base);
val &= ~(IRQ_EVENT_ID_MASK << IRQ_EVENT_ID_SHIFT);
val |= (msg->data << IRQ_EVENT_ID_SHIFT);
- /* The address of doorbell is encoded in mbigen register by default
- * So,we don't need to program the doorbell address at here
- */
writel_relaxed(val, base);
}
@@ -182,8 +202,7 @@ static int mbigen_domain_translate(struct irq_domain *d,
if (fwspec->param_count != 2)
return -EINVAL;
- if ((fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) ||
- (fwspec->param[0] < SPI_NUM_PER_MBIGEN_CHIP))
+ if (fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM)
return -EINVAL;
else
*hwirq = fwspec->param[0];
--
1.8.3
Now MBIGEN can support to generate SPIs by writing
GICD_SETSPIR. Add dt example to help document.
Signed-off-by: Yang Yingliang <[email protected]>
---
.../interrupt-controller/hisilicon,mbigen-v2.txt | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt
index a6813a0..298c033 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt
@@ -10,7 +10,7 @@ Hisilicon designed mbigen to collect and generate interrupt.
Non-pci devices can connect to mbigen and generate the
-interrupt by writing ITS register.
+interrupt by writing GICD or ITS register.
The mbigen chip and devices connect to mbigen have the following properties:
@@ -64,6 +64,13 @@ Examples:
num-pins = <2>;
#interrupt-cells = <2>;
};
+
+ mbigen_spi_example:spi_example {
+ interrupt-controller;
+ msi-parent = <&gic>;
+ num-pins = <2>;
+ #interrupt-cells = <2>;
+ };
};
Devices connect to mbigen required properties:
@@ -82,3 +89,11 @@ Examples:
interrupts = <656 1>,
<657 1>;
};
+
+ spi_example: spi0@0 {
+ compatible = "spi,example";
+ reg = <0 0 0 0>;
+ interrupt-parent = <&mbigen_spi_example>;
+ interrupts = <13 4>,
+ <14 4>;
+ };
--
1.8.3
A MBIGEN can also be used for generating SPIs, so let's
rename register macros to make them more resonable.
The first 64-pins of MBIGEN is used by SPIs, so rename
RESERVED_IRQ_PER_MBIGEN_CHIP to SPI_NUM_PER_MBIGEN_CHIP
and change the comment for this marcro.
Signed-off-by: Yang Yingliang <[email protected]>
---
drivers/irqchip/irq-mbigen.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c
index 567b29c..f05998f 100644
--- a/drivers/irqchip/irq-mbigen.c
+++ b/drivers/irqchip/irq-mbigen.c
@@ -30,14 +30,14 @@
/* Interrupt numbers per mbigen node supported */
#define IRQS_PER_MBIGEN_NODE 128
-/* 64 irqs (Pin0-pin63) are reserved for each mbigen chip */
-#define RESERVED_IRQ_PER_MBIGEN_CHIP 64
+/* 64 irqs (Pin0-pin63) are used for SPIs on each mbigen chip */
+#define SPI_NUM_PER_MBIGEN_CHIP 64
/* The maximum IRQ pin number of mbigen chip(start from 0) */
#define MAXIMUM_IRQ_PIN_NUM 1407
/**
- * In mbigen vector register
+ * In mbigen lpi vector register
* bit[21:12]: event id value
* bit[11:0]: device id
*/
@@ -48,7 +48,7 @@
#define MBIGEN_NODE_OFFSET 0x1000
/* offset of vector register in mbigen node */
-#define REG_MBIGEN_VEC_OFFSET 0x200
+#define REG_MBIGEN_LPI_VEC_OFFSET 0x200
/**
* offset of clear register in mbigen node
@@ -62,7 +62,7 @@
* This register is used to configure interrupt
* trigger type
*/
-#define REG_MBIGEN_TYPE_OFFSET 0x0
+#define REG_MBIGEN_LPI_TYPE_OFFSET 0x0
/**
* struct mbigen_device - holds the information of mbigen device.
@@ -79,12 +79,12 @@ static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq)
{
unsigned int nid, pin;
- hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP;
+ hwirq -= SPI_NUM_PER_MBIGEN_CHIP;
nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
pin = hwirq % IRQS_PER_MBIGEN_NODE;
return pin * 4 + nid * MBIGEN_NODE_OFFSET
- + REG_MBIGEN_VEC_OFFSET;
+ + REG_MBIGEN_LPI_VEC_OFFSET;
}
static inline void get_mbigen_type_reg(irq_hw_number_t hwirq,
@@ -92,7 +92,7 @@ static inline void get_mbigen_type_reg(irq_hw_number_t hwirq,
{
unsigned int nid, irq_ofst, ofst;
- hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP;
+ hwirq -= SPI_NUM_PER_MBIGEN_CHIP;
nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
irq_ofst = hwirq % IRQS_PER_MBIGEN_NODE;
@@ -100,7 +100,7 @@ static inline void get_mbigen_type_reg(irq_hw_number_t hwirq,
ofst = irq_ofst / 32 * 4;
*addr = ofst + nid * MBIGEN_NODE_OFFSET
- + REG_MBIGEN_TYPE_OFFSET;
+ + REG_MBIGEN_LPI_TYPE_OFFSET;
}
static inline void get_mbigen_clear_reg(irq_hw_number_t hwirq,
@@ -183,7 +183,7 @@ static int mbigen_domain_translate(struct irq_domain *d,
return -EINVAL;
if ((fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) ||
- (fwspec->param[0] < RESERVED_IRQ_PER_MBIGEN_CHIP))
+ (fwspec->param[0] < SPI_NUM_PER_MBIGEN_CHIP))
return -EINVAL;
else
*hwirq = fwspec->param[0];
--
1.8.3
Hi Marc,
Sorry for ping you...
On 2018/10/26 15:51, Yang Yingliang wrote:
> Now MBIGENs have pins that used to generate SPIs,
> with
> 5052875 ("irqchip/gic-v3: Add support for Message Based Interrupts as an MSI controller"),
> we can support MBIGEN to generate message based SPIs by writing
> GICD_SETSPIR. This patchset add support for MBIGEN generating
> message based SPIs and a bugfix for MBI driver.
What's you suggestion for this patch set? We would like your input
for next steps.
>
>
> Patch #1 is a bugfix for MBI driver.
At least this patch can be merged first as it's an obvious bug,
without this patch, the MBI dirver can't work I think because
the mutex lock is not initialized.
Thanks
Hanjun
Hi Hanjun,
On 09/01/2019 10:18, Hanjun Guo wrote:
> Hi Marc,
>
> Sorry for ping you...
>
> On 2018/10/26 15:51, Yang Yingliang wrote:
>> Now MBIGENs have pins that used to generate SPIs,
>> with
>> 5052875 ("irqchip/gic-v3: Add support for Message Based Interrupts as an MSI controller"),
>> we can support MBIGEN to generate message based SPIs by writing
>> GICD_SETSPIR. This patchset add support for MBIGEN generating
>> message based SPIs and a bugfix for MBI driver.
>
> What's you suggestion for this patch set? We would like your input
> for next steps.
>
>>
>>
>> Patch #1 is a bugfix for MBI driver.
>
> At least this patch can be merged first as it's an obvious bug,
> without this patch, the MBI dirver can't work I think because
> the mutex lock is not initialized.
I dropped the ball on that one. Let me have a quick look.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
On 26/10/2018 08:51, Yang Yingliang wrote:
> Now MBIGEN can support to generate SPIs by writing
> GICD_SETSPIR. Add dt example to help document.
>
> Signed-off-by: Yang Yingliang <[email protected]>
> ---
> .../interrupt-controller/hisilicon,mbigen-v2.txt | 17 ++++++++++++++++-
> 1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt
> index a6813a0..298c033 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt
> +++ b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt
> @@ -10,7 +10,7 @@ Hisilicon designed mbigen to collect and generate interrupt.
>
>
> Non-pci devices can connect to mbigen and generate the
> -interrupt by writing ITS register.
> +interrupt by writing GICD or ITS register.
>
> The mbigen chip and devices connect to mbigen have the following properties:
>
> @@ -64,6 +64,13 @@ Examples:
> num-pins = <2>;
> #interrupt-cells = <2>;
> };
> +
> + mbigen_spi_example:spi_example {
> + interrupt-controller;
> + msi-parent = <&gic>;
> + num-pins = <2>;
> + #interrupt-cells = <2>;
> + };
> };
>
> Devices connect to mbigen required properties:
> @@ -82,3 +89,11 @@ Examples:
> interrupts = <656 1>,
> <657 1>;
> };
> +
> + spi_example: spi0@0 {
> + compatible = "spi,example";
> + reg = <0 0 0 0>;
> + interrupt-parent = <&mbigen_spi_example>;
> + interrupts = <13 4>,
> + <14 4>;
> + };
>
I'd like an Ack of some sort from one of the DT maintainer. Rob?
Thanks,
M.
--
Jazz is not dead. It just smells funny...