Crashdump collection is enabled based on the DLOAD bit in the TCSR register.
This bit is set during bootup and cleared during shutdown. During crash,
dload bit is not cleared, due to which uboot starts crashdump collection.
This patch series adds the support for crashdump collection.
This series depends on the below patch set.
https://lore.kernel.org/linux-arm-msm/[email protected]/
Poovendhan Selvaraj (5):
dt-bindings: scm: Add compatible for IPQ9574
arm64: dts: Add support for Crashdump collection on IPQ9574
firmware: scm: Modify only the DLOAD bit in TCSR register for download
mode
arm64: defconfig: Enable scm download mode config for IPQ9574 SoC.
dt-bindings: tcsr: Add compatible for IPQ9574
.../bindings/firmware/qcom,scm.yaml | 1 +
.../devicetree/bindings/mfd/qcom,tcsr.yaml | 1 +
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 25 +++++++++++++++++++
arch/arm64/configs/defconfig | 1 +
drivers/firmware/qcom_scm.c | 12 ++++++---
5 files changed, 36 insertions(+), 4 deletions(-)
base-commit: d9fc1511728c15df49ff18e49a494d00f78b7cd4
--
2.17.1
Add the tcsr compatible string for IPQ9574 SoC
Co-developed-by: Anusha Rao <[email protected]>
Signed-off-by: Anusha Rao <[email protected]>
Co-developed-by: Kathiravan Thirumoorthy <[email protected]>
Signed-off-by: Kathiravan Thirumoorthy <[email protected]>
Signed-off-by: Poovendhan Selvaraj <[email protected]>
---
Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
index adcae6c007d9..85d818bd3288 100644
--- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
+++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
@@ -30,6 +30,7 @@ properties:
- qcom,tcsr-apq8084
- qcom,tcsr-ipq6018
- qcom,tcsr-ipq8064
+ - qcom,tcsr-ipq9574
- qcom,tcsr-mdm9615
- qcom,tcsr-msm8660
- qcom,tcsr-msm8916
--
2.17.1
On 13/01/2023 17:00, Poovendhan Selvaraj wrote:
> Add the tcsr compatible string for IPQ9574 SoC
>
> Co-developed-by: Anusha Rao <[email protected]>
> Signed-off-by: Anusha Rao <[email protected]>
> Co-developed-by: Kathiravan Thirumoorthy <[email protected]>
> Signed-off-by: Kathiravan Thirumoorthy <[email protected]>
Same question...
> Signed-off-by: Poovendhan Selvaraj <[email protected]>
> ---
Best regards,
Krzysztof
Add support to read-modify-write TCSR register to modify only DLOAD bit.
Co-developed-by: Anusha Rao <[email protected]>
Signed-off-by: Anusha Rao <[email protected]>
Co-developed-by: Kathiravan Thirumoorthy <[email protected]>
Signed-off-by: Kathiravan Thirumoorthy <[email protected]>
Signed-off-by: Poovendhan Selvaraj <[email protected]>
---
drivers/firmware/qcom_scm.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index cdbfe54c8146..b56d8f465f71 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -400,7 +400,7 @@ int qcom_scm_set_remote_state(u32 state, u32 id)
}
EXPORT_SYMBOL(qcom_scm_set_remote_state);
-static int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
+static int __qcom_scm_set_dload_mode(struct device *dev, u32 val, bool enable)
{
struct qcom_scm_desc desc = {
.svc = QCOM_SCM_SVC_BOOT,
@@ -410,7 +410,7 @@ static int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
.owner = ARM_SMCCC_OWNER_SIP,
};
- desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0;
+ desc.args[1] = enable ? val | QCOM_SCM_BOOT_SET_DLOAD_MODE : 0;
return qcom_scm_call_atomic(__scm->dev, &desc, NULL);
}
@@ -419,15 +419,19 @@ static void qcom_scm_set_download_mode(bool enable)
{
bool avail;
int ret = 0;
+ u32 dload_addr_val;
avail = __qcom_scm_is_call_available(__scm->dev,
QCOM_SCM_SVC_BOOT,
QCOM_SCM_BOOT_SET_DLOAD_MODE);
+ ret = qcom_scm_io_readl(__scm->dload_mode_addr, &dload_addr_val);
+
if (avail) {
- ret = __qcom_scm_set_dload_mode(__scm->dev, enable);
+ ret = __qcom_scm_set_dload_mode(__scm->dev, dload_addr_val, enable);
} else if (__scm->dload_mode_addr) {
ret = qcom_scm_io_writel(__scm->dload_mode_addr,
- enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0);
+ enable ? dload_addr_val |
+ QCOM_SCM_BOOT_SET_DLOAD_MODE : 0);
} else {
dev_err(__scm->dev,
"No available mechanism for setting download mode\n");
--
2.17.1
Add the scm compatible string for IPQ9574 SoC
Co-developed-by: Anusha Rao <[email protected]>
Signed-off-by: Anusha Rao <[email protected]>
Co-developed-by: Kathiravan Thirumoorthy <[email protected]>
Signed-off-by: Kathiravan Thirumoorthy <[email protected]>
Signed-off-by: Poovendhan Selvaraj <[email protected]>
---
Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
index 25688571ee7c..ef5a1fe236f2 100644
--- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
@@ -27,6 +27,7 @@ properties:
- qcom,scm-ipq6018
- qcom,scm-ipq806x
- qcom,scm-ipq8074
+ - qcom,scm-ipq9574
- qcom,scm-mdm9607
- qcom,scm-msm8226
- qcom,scm-msm8660
--
2.17.1
On Jan 13 2023 21:30, Poovendhan Selvaraj wrote:
> Add support to read-modify-write TCSR register to modify only DLOAD bit.
Could you please add more details on what problem this patch is fixing, and why
this patch is needed?
Thank you.
Guru Das.
On 1/13/2023 10:10 PM, Krzysztof Kozlowski wrote:
> On 13/01/2023 17:00, Poovendhan Selvaraj wrote:
>> Add the tcsr compatible string for IPQ9574 SoC
>>
>> Co-developed-by: Anusha Rao <[email protected]>
>> Signed-off-by: Anusha Rao <[email protected]>
>> Co-developed-by: Kathiravan Thirumoorthy <[email protected]>
>> Signed-off-by: Kathiravan Thirumoorthy <[email protected]>
> Same question...
>
> okay Sure, will address.
>> Signed-off-by: Poovendhan Selvaraj <[email protected]>
>> ---
> Best regards,
> Krzysztof
Best Regards,
Poovendhan S
On 1/14/2023 6:46 AM, Guru Das Srinagesh wrote:
> On Jan 13 2023 21:30, Poovendhan Selvaraj wrote:
>> Add support to read-modify-write TCSR register to modify only DLOAD bit.
> Could you please add more details on what problem this patch is fixing, and why
> this patch is needed?
>
> CrashDump collection is based on the DLOAD bit of TCSR register. To retain other bits, we read the register and modify only the DLOAD bit as the other bits have their own significance.
>
> Thank you.
>
> Guru Das.
>
> Regards,
> Poovendhan S
On Fri, 27 Jan 2023, POOVENDHAN SELVARAJ wrote:
>
> On 1/14/2023 6:46 AM, Guru Das Srinagesh wrote:
> > On Jan 13 2023 21:30, Poovendhan Selvaraj wrote:
> > > Add support to read-modify-write TCSR register to modify only DLOAD bit.
> > Could you please add more details on what problem this patch is fixing, and why
> > this patch is needed?
> >
> > CrashDump collection is based on the DLOAD bit of TCSR register. To retain other bits, we read the register and modify only the DLOAD bit as the other bits have their own significance.
> >
> > Thank you.
> >
> > Guru Das.
> >
> > Regards,
> > Poovendhan S
Could you please fix your email client.
I have no idea which text is yours, in any of your mails.
--
Lee Jones [李琼斯]
On 1/27/2023 10:47 PM, Lee Jones wrote:
> On Fri, 27 Jan 2023, POOVENDHAN SELVARAJ wrote:
>
>> On 1/14/2023 6:46 AM, Guru Das Srinagesh wrote:
>>> On Jan 13 2023 21:30, Poovendhan Selvaraj wrote:
>>>> Add support to read-modify-write TCSR register to modify only DLOAD bit.
>>> Could you please add more details on what problem this patch is fixing, and why
>>> this patch is needed?
>>>
>>> CrashDump collection is based on the DLOAD bit of TCSR register. To retain other bits, we read the register and modify only the DLOAD bit as the other bits have their own significance.
>>>
>>> Thank you.
>>>
>>> Guru Das.
>>>
>>> Regards,
>>> Poovendhan S
> Could you please fix your email client.
>
> I have no idea which text is yours, in any of your mails.
Okay, will fix it.
Regards,
Poovendhan S