This series extends the previous https://lore.kernel.org/all/[email protected]
And adds support for Dual and Quad SPI modes for the listed SoCs.
Both modes have been tested on the T113s and should work on
other Allwinner's SoCs that have a similar SPI conttoller.
It may also work for previous SoCs that support Dual/Quad modes.
One of them are H6 and H616.
Maksim Kiselev (3):
spi: sun6i: add quirk for dual and quad SPI modes support
spi: sun6i: add dual and quad SPI modes support for R329/D1/R528/T113s
riscv: dts: allwinner: d1: Add QSPI pins node for pinmux PC port
.../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 7 +++++
drivers/spi/spi-sun6i.c | 30 ++++++++++++++++---
2 files changed, 33 insertions(+), 4 deletions(-)
--
2.39.2
Add pinmux node that describes pins on PC port which required for
QSPI mode.
Signed-off-by: Maksim Kiselev <[email protected]>
---
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
index 1bb1e5cae602..9f754dd03d85 100644
--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
@@ -131,6 +131,13 @@ uart3_pb_pins: uart3-pb-pins {
pins = "PB6", "PB7";
function = "uart3";
};
+
+ /omit-if-no-ref/
+ qspi0_pc_pins: qspi0-pc-pins {
+ pins = "PC2", "PC3", "PC4", "PC5", "PC6",
+ "PC7";
+ function = "spi0";
+ };
};
ccu: clock-controller@2001000 {
--
2.39.2
On Sat, 24 Jun 2023 16:16:21 +0300, Maksim Kiselev wrote:
> This series extends the previous https://lore.kernel.org/all/[email protected]
> And adds support for Dual and Quad SPI modes for the listed SoCs.
> Both modes have been tested on the T113s and should work on
> other Allwinner's SoCs that have a similar SPI conttoller.
> It may also work for previous SoCs that support Dual/Quad modes.
> One of them are H6 and H616.
>
> [...]
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
Thanks!
[1/3] spi: sun6i: add quirk for dual and quad SPI modes support
commit: 0605d9fb411f3337482976842a3901d6c125d298
[2/3] spi: sun6i: add dual and quad SPI modes support for R329/D1/R528/T113s
commit: 25453d797d7abe8801951c8290ea11ea8bba7b96
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
Dne sobota, 24. junij 2023 ob 15:16:24 CEST je Maksim Kiselev napisal(a):
> Add pinmux node that describes pins on PC port which required for
> QSPI mode.
>
> Signed-off-by: Maksim Kiselev <[email protected]>
> ---
> arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index
> 1bb1e5cae602..9f754dd03d85 100644
> --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> @@ -131,6 +131,13 @@ uart3_pb_pins: uart3-pb-pins {
> pins = "PB6", "PB7";
> function = "uart3";
> };
> +
> + /omit-if-no-ref/
> + qspi0_pc_pins: qspi0-pc-pins {
> + pins = "PC2", "PC3", "PC4", "PC5",
"PC6",
> + "PC7";
> + function = "spi0";
> + };
Sorry for late review, but it seems I'm missing something. D1 manual says
those are pins for ordinary SPI, with HOLD and WP signals. Can they be
repurposed for quad SPI?
Best regards,
Jernej
> };
>
> ccu: clock-controller@2001000 {
пн, 31 июл. 2023 г. в 01:30, Jernej Škrabec <[email protected]>:
>
> Dne sobota, 24. junij 2023 ob 15:16:24 CEST je Maksim Kiselev napisal(a):
> > Add pinmux node that describes pins on PC port which required for
> > QSPI mode.
> >
> > Signed-off-by: Maksim Kiselev <[email protected]>
> > ---
> > arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 7 +++++++
> > 1 file changed, 7 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> > b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index
> > 1bb1e5cae602..9f754dd03d85 100644
> > --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> > +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> > @@ -131,6 +131,13 @@ uart3_pb_pins: uart3-pb-pins {
> > pins = "PB6", "PB7";
> > function = "uart3";
> > };
> > +
> > + /omit-if-no-ref/
> > + qspi0_pc_pins: qspi0-pc-pins {
> > + pins = "PC2", "PC3", "PC4", "PC5",
> "PC6",
> > + "PC7";
> > + function = "spi0";
> > + };
>
> Sorry for late review, but it seems I'm missing something. D1 manual says
> those are pins for ordinary SPI, with HOLD and WP signals. Can they be
> repurposed for quad SPI?
>
Yes, they can. Here is a quote from D1 datasheet (9.3.3.8 SPI
Quad-Input/Quad-Output Mode):
"Using the quad mode allows data to be transferred to or from the
device at 4 times the rate of standard single mode, the data can be
read
at fast speed using four data bits (MOSI, MISO, IO2 (WP#) and IO3
(HOLD#)) at the same time."
Dne ponedeljek, 31. julij 2023 ob 17:22:11 CEST je Maxim Kiselev napisal(a):
> пн, 31 июл. 2023 г. в 01:30, Jernej Škrabec <[email protected]>:
> > Dne sobota, 24. junij 2023 ob 15:16:24 CEST je Maksim Kiselev napisal(a):
> > > Add pinmux node that describes pins on PC port which required for
> > > QSPI mode.
> > >
> > > Signed-off-by: Maksim Kiselev <[email protected]>
> > > ---
> > >
> > > arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 7 +++++++
> > > 1 file changed, 7 insertions(+)
> > >
> > > diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> > > b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index
> > > 1bb1e5cae602..9f754dd03d85 100644
> > > --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> > > +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> > > @@ -131,6 +131,13 @@ uart3_pb_pins: uart3-pb-pins {
> > >
> > > pins = "PB6", "PB7";
> > > function = "uart3";
> > >
> > > };
> > >
> > > +
> > > + /omit-if-no-ref/
> > > + qspi0_pc_pins: qspi0-pc-pins {
> > > + pins = "PC2", "PC3", "PC4", "PC5",
> >
> > "PC6",
> >
> > > + "PC7";
> > > + function = "spi0";
> > > + };
> >
> > Sorry for late review, but it seems I'm missing something. D1 manual says
> > those are pins for ordinary SPI, with HOLD and WP signals. Can they be
> > repurposed for quad SPI?
>
> Yes, they can. Here is a quote from D1 datasheet (9.3.3.8 SPI
> Quad-Input/Quad-Output Mode):
> "Using the quad mode allows data to be transferred to or from the
> device at 4 times the rate of standard single mode, the data can be
> read
> at fast speed using four data bits (MOSI, MISO, IO2 (WP#) and IO3
> (HOLD#)) at the same time."
Alright then.
Acked-by: Jernej Skrabec <[email protected]>
Best regards,
Jernej