Hi,
This series was part of a bigger one[1], which was split into smaller
ones as asked by Ezequiel[2].
The support is added into the existing pxa3xx nand controller. Some
additions were done in order to get this controller working:
- Support for a non mandatory ECC clock has been added.
- The Berlin nand controller needs to poll the status register.
- Sequences of commands are quite different in order to perform write
operation.
Based on [3].
[1] https://lkml.org/lkml/2015/5/11/495
[2] https://lkml.org/lkml/2015/5/16/309
[3] https://lkml.org/lkml/2015/6/2/471
Antoine Tenart (7):
mtd: pxa3xx_nand: add a non mandatory ECC clock
Documentation: bindings: document the clocks for pxa3xx-nand
mtd: pxa3xx_nand: add support for the Marvell Berlin nand controller
Documentation: bindings: add the Berlin nand controller compatible
mtd: nand: let Marvell Berlin SoCs select the pxa3xx driver
ARM: berlin: add BG2Q node for the nand
ARM: berlin: enable flash on the BG2Q DMP
.../devicetree/bindings/mtd/pxa3xx-nand.txt | 5 +
arch/arm/boot/dts/berlin2q-marvell-dmp.dts | 25 +++
arch/arm/boot/dts/berlin2q.dtsi | 13 ++
drivers/mtd/nand/Kconfig | 4 +-
drivers/mtd/nand/pxa3xx_nand.c | 214 +++++++++++++++++++--
5 files changed, 240 insertions(+), 21 deletions(-)
--
2.4.2
Some controllers (as the coming Berlin nand controller) need to enable
an ECC clock. Add support for this clock in the pxa3xx nand driver, and
leave it as non mandatory.
Signed-off-by: Antoine Tenart <[email protected]>
---
drivers/mtd/nand/pxa3xx_nand.c | 32 +++++++++++++++++++++++---------
1 file changed, 23 insertions(+), 9 deletions(-)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 42ad199ed63d..ae8a7b6b3e5c 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -180,7 +180,7 @@ struct pxa3xx_nand_info {
struct nand_hw_control controller;
struct platform_device *pdev;
- struct clk *clk;
+ struct clk *clk, *ecc_clk;
void __iomem *mmio_base;
unsigned long mmio_phys;
struct completion cmd_complete, dev_ready;
@@ -1685,15 +1685,26 @@ static int alloc_nand_resource(struct platform_device *pdev)
spin_lock_init(&chip->controller->lock);
init_waitqueue_head(&chip->controller->wq);
- info->clk = devm_clk_get(&pdev->dev, NULL);
+ info->clk = devm_clk_get(&pdev->dev, "nfc");
if (IS_ERR(info->clk)) {
- dev_err(&pdev->dev, "failed to get nand clock\n");
- return PTR_ERR(info->clk);
+ info->clk = devm_clk_get(&pdev->dev, NULL);
+
+ if (IS_ERR(info->clk)) {
+ dev_err(&pdev->dev, "failed to get nand clock\n");
+ return PTR_ERR(info->clk);
+ }
}
ret = clk_prepare_enable(info->clk);
if (ret < 0)
return ret;
+ info->ecc_clk = devm_clk_get(&pdev->dev, "ecc");
+ if (!IS_ERR(info->ecc_clk)) {
+ ret = clk_prepare_enable(info->ecc_clk);
+ if (ret < 0)
+ goto fail_disable_clk;
+ }
+
if (use_dma) {
/*
* This is a dirty hack to make this driver work from
@@ -1710,7 +1721,7 @@ static int alloc_nand_resource(struct platform_device *pdev)
dev_err(&pdev->dev,
"no resource defined for data DMA\n");
ret = -ENXIO;
- goto fail_disable_clk;
+ goto fail_disable_ecc_clk;
}
info->drcmr_dat = r->start;
@@ -1719,7 +1730,7 @@ static int alloc_nand_resource(struct platform_device *pdev)
dev_err(&pdev->dev,
"no resource defined for cmd DMA\n");
ret = -ENXIO;
- goto fail_disable_clk;
+ goto fail_disable_ecc_clk;
}
info->drcmr_cmd = r->start;
}
@@ -1729,14 +1740,14 @@ static int alloc_nand_resource(struct platform_device *pdev)
if (irq < 0) {
dev_err(&pdev->dev, "no IRQ resource defined\n");
ret = -ENXIO;
- goto fail_disable_clk;
+ goto fail_disable_ecc_clk;
}
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
info->mmio_base = devm_ioremap_resource(&pdev->dev, r);
if (IS_ERR(info->mmio_base)) {
ret = PTR_ERR(info->mmio_base);
- goto fail_disable_clk;
+ goto fail_disable_ecc_clk;
}
info->mmio_phys = r->start;
@@ -1745,7 +1756,7 @@ static int alloc_nand_resource(struct platform_device *pdev)
info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
if (info->data_buff == NULL) {
ret = -ENOMEM;
- goto fail_disable_clk;
+ goto fail_disable_ecc_clk;
}
/* initialize all interrupts to be disabled */
@@ -1766,6 +1777,8 @@ static int alloc_nand_resource(struct platform_device *pdev)
fail_free_buf:
free_irq(irq, info);
kfree(info->data_buff);
+fail_disable_ecc_clk:
+ clk_disable_unprepare(info->ecc_clk);
fail_disable_clk:
clk_disable_unprepare(info->clk);
return ret;
@@ -1788,6 +1801,7 @@ static int pxa3xx_nand_remove(struct platform_device *pdev)
pxa3xx_nand_free_buff(info);
clk_disable_unprepare(info->clk);
+ clk_disable_unprepare(info->ecc_clk);
for (cs = 0; cs < pdata->num_cs; cs++)
nand_release(info->host[cs]->mtd);
--
2.4.2
The pxa3xx nand driver requires at least one clock to probe correctly.
A second one, named 'ecc' can be specified if needed. Add the
corresponding documentation.
Signed-off-by: Antoine Tenart <[email protected]>
---
Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
index 4f833e3c4f51..ad30a02f1346 100644
--- a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
@@ -8,6 +8,8 @@ Required properties:
- reg: The register base for the controller
- interrupts: The interrupt to map
- #address-cells: Set to <1> if the node includes partitions
+ - clocks: A phandle to the clocks
+ - clock-names: 'nfc' and 'ecc'. The 'nfc' clock is mandatory.
Optional properties:
@@ -32,6 +34,8 @@ Example:
compatible = "marvell,pxa3xx-nand";
reg = <0x43100000 90>;
interrupts = <45>;
+ clocks = <&gateclk 11>;
+ clock-names = "nfc";
#address-cells = <1>;
marvell,nand-enable-arbiter;
--
2.4.2
The nand controller on Marvell Berlin SoC reuse the pxa3xx nand driver
as it quite close. The process of sending commands can be compared to
the one of the Marvell armada 370: read and write commands are done in
chunks.
But the Berlin nand controller has some other specificities which
require some modifications of the pxa3xx nand driver:
- there are no IRQ available so we need to poll the status register: we
have to use our own cmdfunc Berlin function, and early on the probing
function.
- PAGEPROG are very different from the one used in the pxa3xx driver,
so we're using a specific process for this one
- the SEQIN command is equivalent to a READ0 command
Signed-off-by: Antoine Tenart <[email protected]>
---
drivers/mtd/nand/pxa3xx_nand.c | 182 ++++++++++++++++++++++++++++++++++++++---
1 file changed, 172 insertions(+), 10 deletions(-)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index ae8a7b6b3e5c..1af8079164fd 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -109,6 +109,8 @@
#define NDCB0_EXT_CMD_TYPE(x) (((x) << 29) & NDCB0_EXT_CMD_TYPE_MASK)
#define NDCB0_CMD_TYPE_MASK (0x7 << 21)
#define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK)
+#define NDCB0_CMD_XTYPE_MASK (0x7 << 29)
+#define NDCB0_CMD_XTYPE(x) (((x) << 29) & NDCB0_CMD_XTYPE_MASK)
#define NDCB0_NC (0x1 << 20)
#define NDCB0_DBC (0x1 << 19)
#define NDCB0_ADDR_CYC_MASK (0x7 << 16)
@@ -117,13 +119,15 @@
#define NDCB0_CMD1_MASK (0xff)
#define NDCB0_ADDR_CYC_SHIFT (16)
-#define EXT_CMD_TYPE_DISPATCH 6 /* Command dispatch */
-#define EXT_CMD_TYPE_NAKED_RW 5 /* Naked read or Naked write */
-#define EXT_CMD_TYPE_READ 4 /* Read */
-#define EXT_CMD_TYPE_DISP_WR 4 /* Command dispatch with write */
-#define EXT_CMD_TYPE_FINAL 3 /* Final command */
-#define EXT_CMD_TYPE_LAST_RW 1 /* Last naked read/write */
-#define EXT_CMD_TYPE_MONO 0 /* Monolithic read/write */
+#define EXT_CMD_TYPE_LAST_PAGEPROG 8
+#define EXT_CMD_TYPE_CHUNK_PAGEPROG 7
+#define EXT_CMD_TYPE_DISPATCH 6 /* Command dispatch */
+#define EXT_CMD_TYPE_NAKED_RW 5 /* Naked read or Naked write */
+#define EXT_CMD_TYPE_READ 4 /* Read */
+#define EXT_CMD_TYPE_DISP_WR 4 /* Command dispatch with write */
+#define EXT_CMD_TYPE_FINAL 3 /* Final command */
+#define EXT_CMD_TYPE_LAST_RW 1 /* Last naked read/write */
+#define EXT_CMD_TYPE_MONO 0 /* Monolithic read/write */
/* macros for registers read/write */
#define nand_writel(info, off, val) \
@@ -158,6 +162,7 @@ enum {
enum pxa3xx_nand_variant {
PXA3XX_NAND_VARIANT_PXA,
PXA3XX_NAND_VARIANT_ARMADA370,
+ PXA3XX_NAND_VARIANT_BERLIN2,
};
struct pxa3xx_nand_host {
@@ -319,6 +324,18 @@ static struct nand_ecclayout ecc_layout_4KB_bch8bit = {
.oobfree = { }
};
+static struct nand_ecclayout ecc_layout_oob_128 = {
+ .eccbytes = 48,
+ .eccpos = {
+ 80, 81, 82, 83, 84, 85, 86, 87,
+ 88, 89, 90, 91, 92, 93, 94, 95,
+ 96, 97, 98, 99, 100, 101, 102, 103,
+ 104, 105, 106, 107, 108, 109, 110, 111,
+ 112, 113, 114, 115, 116, 117, 118, 119,
+ 120, 121, 122, 123, 124, 125, 126, 127},
+ .oobfree = { {.offset = 2, .length = 78} }
+};
+
#define NDTR0_tCH(c) (min((c), 7) << 19)
#define NDTR0_tCS(c) (min((c), 7) << 16)
#define NDTR0_tWH(c) (min((c), 7) << 11)
@@ -342,6 +359,10 @@ static const struct of_device_id pxa3xx_nand_dt_ids[] = {
.compatible = "marvell,armada370-nand",
.data = (void *)PXA3XX_NAND_VARIANT_ARMADA370,
},
+ {
+ .compatible = "marvell,berlin2-nand",
+ .data = (void *)PXA3XX_NAND_VARIANT_BERLIN2,
+ },
{}
};
MODULE_DEVICE_TABLE(of, pxa3xx_nand_dt_ids);
@@ -782,7 +803,8 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
nand_writel(info, NDCB0, info->ndcb2);
/* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */
- if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
+ if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
+ info->variant == PXA3XX_NAND_VARIANT_BERLIN2)
nand_writel(info, NDCB0, info->ndcb3);
}
@@ -892,6 +914,16 @@ static int prepare_set_command(struct pxa3xx_nand_info *info, int command,
if (command == NAND_CMD_SEQIN)
exec_cmd = 0;
+ /* Berlin specific */
+ if (info->variant == PXA3XX_NAND_VARIANT_BERLIN2) {
+ if ((command == NAND_CMD_READ0 && !ext_cmd_type) ||
+ command == NAND_CMD_READOOB)
+ exec_cmd = 0;
+
+ if (command == NAND_CMD_SEQIN)
+ command = NAND_CMD_READ0;
+ }
+
addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles
+ host->col_addr_cycles);
@@ -951,6 +983,37 @@ static int prepare_set_command(struct pxa3xx_nand_info *info, int command,
break;
}
+ if (info->variant == PXA3XX_NAND_VARIANT_BERLIN2) {
+ if (ext_cmd_type == EXT_CMD_TYPE_LAST_PAGEPROG) {
+ info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
+ | NDCB0_CMD_XTYPE(0x3)
+ | NDCB0_ST_ROW_EN
+ | NDCB0_DBC
+ | (NAND_CMD_PAGEPROG << 8);
+ } else if (ext_cmd_type == EXT_CMD_TYPE_CHUNK_PAGEPROG) {
+ info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
+ | NDCB0_CMD_XTYPE(0x5)
+ | NDCB0_NC
+ | NDCB0_AUTO_RS
+ | NDCB0_LEN_OVRD
+ | (NAND_CMD_PAGEPROG << 8)
+ | NAND_CMD_SEQIN;
+ info->ndcb3 = info->chunk_size;
+ } else {
+ info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
+ | NDCB0_CMD_XTYPE(0x4)
+ | NDCB0_NC
+ | NDCB0_AUTO_RS
+ | NDCB0_LEN_OVRD
+ | addr_cycle
+ | (NAND_CMD_PAGEPROG << 8)
+ | NAND_CMD_SEQIN;
+ info->ndcb3 = info->chunk_size;
+ }
+
+ break;
+ }
+
/* Second command setting for large pages */
if (mtd->writesize > PAGE_CHUNK_SIZE) {
/*
@@ -1007,6 +1070,7 @@ static int prepare_set_command(struct pxa3xx_nand_info *info, int command,
info->data_size = 8;
break;
+
case NAND_CMD_STATUS:
info->buf_count = 1;
info->ndcb0 |= NDCB0_CMD_TYPE(4)
@@ -1015,7 +1079,6 @@ static int prepare_set_command(struct pxa3xx_nand_info *info, int command,
info->data_size = 8;
break;
-
case NAND_CMD_ERASE1:
info->ndcb0 |= NDCB0_CMD_TYPE(2)
| NDCB0_AUTO_RS
@@ -1213,6 +1276,92 @@ static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
return 0;
}
+static void nand_cmdfunc_berlin(struct mtd_info *mtd, const unsigned command,
+ int column, int page_addr)
+{
+ struct pxa3xx_nand_host *host = mtd->priv;
+ struct pxa3xx_nand_info *info = host->info_data;
+ unsigned long timeout;
+ int exec_cmd, ext_cmd_type = 0;
+ unsigned cmd = command;
+ irqreturn_t irq_ret;
+
+ if (info->reg_ndcr & NDCR_DWIDTH_M)
+ column /= 2;
+
+ /*
+ * There may be different NAND chip hooked to
+ * different chip select, so check whether
+ * chip select has been changed, if yes, reset the timing
+ */
+ if (info->cs != host->cs) {
+ info->cs = host->cs;
+ nand_writel(info, NDTR0CS0, info->ndtr0cs0);
+ nand_writel(info, NDTR1CS0, info->ndtr1cs0);
+ }
+
+ prepare_start_command(info, cmd);
+
+ info->need_wait = 1;
+ init_completion(&info->dev_ready);
+
+ pxa3xx_nand_start(info);
+
+ do {
+ init_completion(&info->cmd_complete);
+ info->state = STATE_PREPARED;
+ exec_cmd = prepare_set_command(info, cmd, ext_cmd_type,
+ column, page_addr);
+
+ if (cmd == NAND_CMD_READ0 && !ext_cmd_type) {
+ ext_cmd_type = NDCB0_CMD_XTYPE(0x5);
+ continue;
+ }
+
+ if (!exec_cmd) {
+ info->need_wait = 0;
+ complete(&info->dev_ready);
+ break;
+ }
+
+ /* no IRQ, poll */
+ timeout = jiffies + CHIP_DELAY_TIMEOUT;
+ do {
+ irq_ret = pxa3xx_nand_irq(0, info);
+ if (irq_ret == IRQ_WAKE_THREAD)
+ handle_data_pio(info);
+
+ if (cmd == NAND_CMD_PAGEPROG &&
+ ext_cmd_type != EXT_CMD_TYPE_LAST_PAGEPROG)
+ break;
+
+ if (time_after(jiffies, timeout))
+ goto berlin_timeout;
+ } while (!completion_done(&info->cmd_complete));
+
+ /* sequence completed */
+ if (info->data_size == 0)
+ break;
+
+ if (cmd == NAND_CMD_PAGEPROG &&
+ ext_cmd_type == EXT_CMD_TYPE_LAST_PAGEPROG) {
+ complete(&info->dev_ready);
+ break;
+ }
+
+ if (cmd == NAND_CMD_PAGEPROG) {
+ /* last command */
+ if (info->data_size == info->chunk_size * 2)
+ ext_cmd_type = EXT_CMD_TYPE_LAST_PAGEPROG;
+ else
+ ext_cmd_type = EXT_CMD_TYPE_CHUNK_PAGEPROG;
+ }
+ } while (1);
+
+berlin_timeout:
+ info->state = STATE_IDLE;
+}
+
static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
struct nand_chip *chip, uint8_t *buf, int oob_required,
int page)
@@ -1513,6 +1662,16 @@ static int pxa_ecc_init(struct pxa3xx_nand_info *info,
ecc->size = info->chunk_size;
ecc->layout = &ecc_layout_4KB_bch8bit;
ecc->strength = 16;
+ } else if (strength == 48 && ecc_stepsize == 1024 &&
+ page_size == 8192) {
+ info->ecc_bch = 1;
+ info->chunk_size = 2048;
+ info->spare_size = 0;
+ info->ecc_size = 32;
+ ecc->mode = NAND_ECC_HW;
+ ecc->size = info->chunk_size;
+ ecc->layout = &ecc_layout_oob_128;
+ ecc->strength = 48;
} else {
dev_err(&info->pdev->dev,
"ECC strength %d at page size %d is not supported\n",
@@ -1541,6 +1700,9 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
/* Set a default chunk size */
info->chunk_size = 512;
+ if (info->variant == PXA3XX_NAND_VARIANT_BERLIN2)
+ chip->cmdfunc = nand_cmdfunc_berlin;
+
ret = pxa3xx_nand_sensing(host);
if (ret) {
dev_info(&info->pdev->dev, "There is no chip on cs %d!\n",
@@ -1588,7 +1750,7 @@ KEEP_CONFIG:
if (mtd->writesize > PAGE_CHUNK_SIZE) {
if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) {
chip->cmdfunc = nand_cmdfunc_extended;
- } else {
+ } else if (info->variant != PXA3XX_NAND_VARIANT_BERLIN2) {
dev_err(&info->pdev->dev,
"unsupported page size on this variant\n");
return -ENODEV;
--
2.4.2
The Berlin nand controller support was introduced using the existing
pxa3xx nand driver. Add the Berlin specific compatible into the
documentation.
Signed-off-by: Antoine Tenart <[email protected]>
---
Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
index ad30a02f1346..e0adc584fdce 100644
--- a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
@@ -5,6 +5,7 @@ Required properties:
- compatible: Should be set to one of the following:
marvell,pxa3xx-nand
marvell,armada370-nand
+ marvell,berlin2-nand
- reg: The register base for the controller
- interrupts: The interrupt to map
- #address-cells: Set to <1> if the node includes partitions
--
2.4.2
Marvell Berlin nand controller support has been added in the pxa3xx nand
driver. Let these SoCs select the driver.
Signed-off-by: Antoine Tenart <[email protected]>
---
drivers/mtd/nand/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 5897d8d8fa5a..0e41f2126e39 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -331,8 +331,8 @@ config MTD_NAND_ATMEL
on Atmel AT91 and AVR32 processors.
config MTD_NAND_PXA3xx
- tristate "NAND support on PXA3xx and Armada 370/XP"
- depends on PXA3xx || ARCH_MMP || PLAT_ORION
+ tristate "NAND support on PXA3xx, Armada 370/XP and Marvell Berlin"
+ depends on PXA3xx || ARCH_MMP || PLAT_ORION || ARCH_BERLIN
help
This enables the driver for the NAND flash device found on
PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
--
2.4.2
Add a node describing the nand controller of the Marvell Berlin BG2Q
SoC. It uses the pxa3xx nand driver, with a dedicated compatible.
Also add the corresponding pinmuxing configuration.
Signed-off-by: Antoine Tenart <[email protected]>
---
arch/arm/boot/dts/berlin2q.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index be5397288d24..aeb3a0ea0540 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -437,6 +437,19 @@
status = "disabled";
};
+ nand0: nand@f00000 {
+ compatible = "marvell,berlin2-nand";
+ reg = <0xf00000 0x10000>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&chip CLKID_NFC>,
+ <&chip CLKID_NFC_ECC>;
+ clock-names = "nfc", "ecc";
+
+ #address-cells = <1>;
+
+ status = "disabled";
+ };
+
apb@fc0000 {
compatible = "simple-bus";
#address-cells = <1>;
--
2.4.2
The BG2Q DMP has a nand controller. Add the corresponding node, but do
not enable it by default because the nand is only available on some BG2Q
DMP.
Signed-off-by: Antoine Tenart <[email protected]>
---
arch/arm/boot/dts/berlin2q-marvell-dmp.dts | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
index a98ac1bd8f65..4157258a6fb0 100644
--- a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
+++ b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
@@ -112,3 +112,28 @@
&sata_phy {
status = "okay";
};
+
+&chip {
+ nand_pmux: nand-pmux {
+ groups = "G0", "G1";
+ function = "nand";
+ };
+};
+
+&nand0 {
+ pinctrl-0 = <&nand_pmux>;
+ pinctrl-names = "default";
+
+ marvell,nand-enable-arbiter;
+ nand-ecc-strength = <48>;
+ nand-ecc-step-size = <1024>;
+
+ num-cs = <1>;
+
+ /*
+ * Two kinds of BG2Q DMP are available: one with emmc and
+ * one with a nand. The latter is not widespread. Because
+ * of this, disable the nand by default.
+ */
+ status = "disabled";
+};
--
2.4.2
Antoine Tenart <[email protected]> writes:
> The pxa3xx nand driver requires at least one clock to probe correctly.
> A second one, named 'ecc' can be specified if needed. Add the
> corresponding documentation.
Is it mandatory, really ?
The code does :
info->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(info->clk)) {
dev_err(&pdev->dev, "failed to get nand clock\n");
return PTR_ERR(info->clk);
}
info->clk can very well be NULL, can't it ?
Cheers.
--
Robert
Antoine Tenart <[email protected]> writes:
> Some controllers (as the coming Berlin nand controller) need to enable
> an ECC clock. Add support for this clock in the pxa3xx nand driver, and
> leave it as non mandatory.
> - info->clk = devm_clk_get(&pdev->dev, NULL);
> + info->clk = devm_clk_get(&pdev->dev, "nfc");
> if (IS_ERR(info->clk)) {
> - dev_err(&pdev->dev, "failed to get nand clock\n");
> - return PTR_ERR(info->clk);
> + info->clk = devm_clk_get(&pdev->dev, NULL);
> +
> + if (IS_ERR(info->clk)) {
> + dev_err(&pdev->dev, "failed to get nand clock\n");
> + return PTR_ERR(info->clk);
> + }
I suppose this is done to keep the compatibility with existing pxa3xx/berlin
clock code, which was defined without a con_id. More specifically I'm thinking
of the function clk_find().
Now maybe it would be cleaner to keep you "nfc" change, remove the failback plan
with NULL as an con_id, and change the clock providers. I cannot speak for
berlin/others, but for pxa3xx, this is one 3 hunks change in :
- drivers/clk/pxa/clk-pxa3xx.c
Cheers.
--
Robert