These patches enable Intel Xeon Phi x200 feature to use MONITOR/MWAIT
instruction in ring 3 (userspace) Patches set MSR 0x140 for all logical CPUs.
Then expose it as CPU feature and introduces elf HWCAP capability for x86.
Reference (the solution is temporary MSR definition will be in next SDM document):
https://software.intel.com/en-us/blogs/2016/10/06/intel-xeon-phi-product-family-x200-knl-user-mode-ring-3-monitor-and-mwait
v2:
Check MSR before wrmsrl
Shortened names
Used Word 3 for feature init_scattered_cpuid_features()
Fixed commit messages
v3:
Included Daves and Thomas comments
Grzegorz Andrejczuk (4):
Add R3MWAIT register and bit to msr-info.h
Add enabling of the R3 MWAIT during boot for KNL
Add hwcap2 for x86
Add R3MWAIT to CPU features
arch/x86/include/asm/cpufeatures.h | 2 ++
arch/x86/include/asm/elf.h | 9 +++++++++
arch/x86/include/asm/msr-index.h | 5 +++++
arch/x86/include/uapi/asm/hwcap.h | 7 +++++++
arch/x86/kernel/cpu/common.c | 6 ++++++
arch/x86/kernel/cpu/intel.c | 33 +++++++++++++++++++++++++++++++++
6 files changed, 62 insertions(+)
create mode 100644 arch/x86/include/uapi/asm/hwcap.h
--
2.5.1
Intel Xeon Phi x200 (codenamed Knights Landing) has MSR
MISC_THD_FEATURE_ENABLE 0x140.
Setting its 2nd bit make MONITOR and MWAIT instructions do not cause
invalid-opcode exception.
This commit adds this register prefixed by PHI and bit to msr-info.h
Reference:
https://software.intel.com/en-us/blogs/2016/10/06/intel-xeon-phi-product-family-x200-knl-user-mode-ring-3-monitor-and-mwait
Blog entry is a temporary solution, MSR will be present in the next SDM.
Signed-off-by: Grzegorz Andrejczuk <[email protected]>
---
arch/x86/include/asm/msr-index.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 56f4c66..df9d8d3 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -540,6 +540,11 @@
#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39
#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
+/* Intel Xeon Phi x200 ring 3 MONITOR/MWAIT */
+#define MSR_PHI_MISC_THD_FEATURE 0x00000140
+#define MSR_PHI_MISC_THD_FEATURE_R3MWAIT_BIT 1
+#define MSR_PHI_MISC_THD_FEATURE_R3MWAIT (1ULL << MSR_PHI_MISC_THD_FEATURE_R3MWAIT_BIT)
+
#define MSR_IA32_TSC_DEADLINE 0x000006E0
/* P4/Xeon+ specific */
--
2.5.1
Add cpu feature for ring 3 monitor/mwait.
Signed-off-by: Grzegorz Andrejczuk <[email protected]>
---
arch/x86/include/asm/cpufeatures.h | 2 ++
arch/x86/kernel/cpu/common.c | 3 +++
arch/x86/kernel/cpu/intel.c | 1 +
3 files changed, 6 insertions(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 92a8308..02bfcc6 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -71,6 +71,8 @@
#define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */
#define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */
#define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */
+/* non architectural Intel-defined CPU features not present in CPUID */
+#define X86_FEATURE_PHIR3MWAIT ( 2*32+ 4)
/* Other features, Linux-defined mapping, word 3 */
/* This range is used for feature bits which conflict or are synthesized */
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index ff26036..ce47687 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1108,6 +1108,9 @@ static void identify_cpu(struct cpuinfo_x86 *c)
#endif
/* The boot/hotplug time assigment got cleared, restore it */
c->logical_proc_id = topology_phys_to_logical_pkg(c->phys_proc_id);
+
+ if (cpu_has(c, X86_FEATURE_PHIR3MWAIT))
+ elf_hwcap2 |= HWCAP2_PHIR3MWAIT;
}
/*
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 464df22..d524a06 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -88,6 +88,7 @@ static void __init probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
rdmsrl(MSR_PHI_MISC_THD_FEATURE, msr);
msr |= MSR_PHI_MISC_THD_FEATURE_R3MWAIT;
wrmsrl(MSR_PHI_MISC_THD_FEATURE, msr);
+ set_cpu_cap(c, X86_FEATURE_PHIR3MWAIT);
}
}
--
2.5.1
Add hwcap2 attribute for x86.
Reserve 1st bit of HWCAP2 for exposing Xeon Phi ring 3 monitor/mwait.
With this userspace apps can detect Ring 3 MONITOR/MWAIT instructions.
Signed-off-by: Grzegorz Andrejczuk <[email protected]>
---
arch/x86/include/asm/elf.h | 9 +++++++++
arch/x86/include/uapi/asm/hwcap.h | 7 +++++++
arch/x86/kernel/cpu/common.c | 3 +++
3 files changed, 19 insertions(+)
create mode 100644 arch/x86/include/uapi/asm/hwcap.h
diff --git a/arch/x86/include/asm/elf.h b/arch/x86/include/asm/elf.h
index e7f155c..0c4336f 100644
--- a/arch/x86/include/asm/elf.h
+++ b/arch/x86/include/asm/elf.h
@@ -258,6 +258,15 @@ extern int force_personality32;
#define ELF_HWCAP (boot_cpu_data.x86_capability[CPUID_1_EDX])
+extern unsigned int elf_hwcap2;
+
+/*
+ * HWCAP2 supplies kernel enabled CPU feature, so that the application
+ * can know that it can safely use them. The bits are defined in
+ * uapi/asm/hwcap.h.
+ */
+#define ELF_HWCAP2 elf_hwcap2
+
/* This yields a string that ld.so will use to load implementation
specific libraries for optimization. This is more specific in
intent than poking at uname or /proc/cpuinfo.
diff --git a/arch/x86/include/uapi/asm/hwcap.h b/arch/x86/include/uapi/asm/hwcap.h
new file mode 100644
index 0000000..d1f4f98
--- /dev/null
+++ b/arch/x86/include/uapi/asm/hwcap.h
@@ -0,0 +1,7 @@
+#ifndef _ASM_HWCAP_H
+#define _ASM_HWCAP_H 1
+
+/* Kernel enabled Ring 3 MWAIT for Xeon Phi*/
+#define HWCAP2_PHIR3MWAIT (1 << 0)
+/* upto bit 31 free */
+#endif
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index bcc9ccc..ff26036 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -35,6 +35,7 @@
#include <asm/desc.h>
#include <asm/fpu/internal.h>
#include <asm/mtrr.h>
+#include <asm/hwcap.h>
#include <linux/numa.h>
#include <asm/asm.h>
#include <asm/bugs.h>
@@ -51,6 +52,8 @@
#include "cpu.h"
+unsigned int elf_hwcap2 __read_mostly;
+
/* all of these masks are initialized in setup_cpu_local_masks() */
cpumask_var_t cpu_initialized_mask;
cpumask_var_t cpu_callout_mask;
--
2.5.1
If processor is Intel Xeon Phi we enable user-level mwait feature.
Enabling this feature suppreses invalid-opcode error, when MONITOR/MWAIT
is called from ring 3.
Signed-off-by: Grzegorz Andrejczuk <[email protected]>
---
arch/x86/kernel/cpu/intel.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index fcd484d..464df22 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -26,6 +26,8 @@
#include <asm/apic.h>
#endif
+static int phi_r3mwait_disabled;
+
/*
* Just in case our CPU detection goes bad, or you have a weird system,
* allow a way to override the automatic disabling of MPX.
@@ -61,6 +63,34 @@ void check_mpx_erratum(struct cpuinfo_x86 *c)
}
}
+static int __init phir3mwait_disable(char *__unused)
+{
+ phi_r3mwait_disabled = 1;
+
+ return 1;
+}
+__setup("phir3mwait=disable", phir3mwait_disable);
+
+static void __init probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
+{
+ if (phi_r3mwait_disabled)
+ return;
+
+ /*
+ * Setting ring 3 MONITOR/MWAIT for all threads
+ * when CPU is Xeon Phi Family x200
+ * This can be disabled with phir3mwait=disable cmdline switch.
+ * We preserve the reserved values and set only 2nd bit.
+ */
+ if (c->x86 == 6 && c->x86_model == INTEL_FAM6_XEON_PHI_KNL) {
+ u64 msr;
+
+ rdmsrl(MSR_PHI_MISC_THD_FEATURE, msr);
+ msr |= MSR_PHI_MISC_THD_FEATURE_R3MWAIT;
+ wrmsrl(MSR_PHI_MISC_THD_FEATURE, msr);
+ }
+}
+
static void early_init_intel(struct cpuinfo_x86 *c)
{
u64 misc_enable;
@@ -211,6 +241,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
}
check_mpx_erratum(c);
+ probe_xeon_phi_r3mwait(c);
}
#ifdef CONFIG_X86_32
--
2.5.1
On Thu, 13 Oct 2016, Grzegorz Andrejczuk wrote:
>
> +static int phi_r3mwait_disabled;
__read_mostly please.
> +
> /*
> * Just in case our CPU detection goes bad, or you have a weird system,
> * allow a way to override the automatic disabling of MPX.
> @@ -61,6 +63,34 @@ void check_mpx_erratum(struct cpuinfo_x86 *c)
> }
> }
>
> +static int __init phir3mwait_disable(char *__unused)
> +{
> + phi_r3mwait_disabled = 1;
> +
> + return 1;
> +}
> +__setup("phir3mwait=disable", phir3mwait_disable);
This needs proper documentation in Documentation/kernel-parameters.txt
> +static void __init probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
> +{
> + if (phi_r3mwait_disabled)
> + return;
> +
> + /*
> + * Setting ring 3 MONITOR/MWAIT for all threads
> + * when CPU is Xeon Phi Family x200
> + * This can be disabled with phir3mwait=disable cmdline switch.
And why is this information useful in this comment?
> + * We preserve the reserved values and set only 2nd bit.
This last sentence does not make any sense at all.
Thanks,
tglx
On Thu, 13 Oct 2016, Grzegorz Andrejczuk wrote:
> --- a/arch/x86/kernel/cpu/common.c
> +++ b/arch/x86/kernel/cpu/common.c
> @@ -1108,6 +1108,9 @@ static void identify_cpu(struct cpuinfo_x86 *c)
> #endif
> /* The boot/hotplug time assigment got cleared, restore it */
> c->logical_proc_id = topology_phys_to_logical_pkg(c->phys_proc_id);
> +
> + if (cpu_has(c, X86_FEATURE_PHIR3MWAIT))
> + elf_hwcap2 |= HWCAP2_PHIR3MWAIT;
Why can't you just set that bit in probe_xeon_phi_r3mwait()?
Just because its so much fun to sprinkle code at random places, right?
Sigh.
tglx
On Thu, 13 Oct 2016, Grzegorz Andrejczuk wrote:
> Subject: [PATCH v3 1/4] Add R3MWAIT register and bit to msr-info.h
Did you ever notice that all patches have a subsystem related prefix before
the sentence decribing the change?
See Documentation/SubmittingPatches. Also git log some/file might give you an idea.
> This commit adds this register prefixed by PHI and bit to msr-info.h
> Reference:
> https://software.intel.com/en-us/blogs/2016/10/06/intel-xeon-phi-product-family-x200-knl-user-mode-ring-3-monitor-and-mwait
> Blog entry is a temporary solution, MSR will be present in the next SDM.
Why do you think that the blog entry link in the changelog does not have
the same issues as the link the code comment?
Just copy the relevant bits into the changelog and be done with it.
Thanks,
tglx
On Thu, 13 Oct 2016, Grzegorz Andrejczuk wrote:
> Add hwcap2 attribute for x86.
Great value in repeating the subject line. And the subject line is crap
because this patch does way more than adding hwcap2 ....
> Reserve 1st bit of HWCAP2 for exposing Xeon Phi ring 3 monitor/mwait.
> With this userspace apps can detect Ring 3 MONITOR/MWAIT instructions.
User space cannot detect the instructions. User space can check whether the
instructions are enabled.
> +/* Kernel enabled Ring 3 MWAIT for Xeon Phi*/
> +#define HWCAP2_PHIR3MWAIT (1 << 0)
> +/* upto bit 31 free */
Very useful comment, NOT! Stop documenting the obvious.
Thanks,
tglx