There are also ARM and ARM64 based SOCs with a QUICC Engine, and the
core QE code as well as net/wan/fsl_ucc_hdlc and tty/serial/ucc_uart
has now been modified to not rely on ppcisms.
So extend the architectures that can select QUICC_ENGINE, and add the
rather modest requirements of OF && HAS_IOMEM.
The core code as well as the ucc_uart driver has been tested on an
LS1021A (arm), and it has also been tested that the QE code still
works on an mpc8309 (ppc).
Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/soc/fsl/qe/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig
index cfa4b2939992..f1974f811572 100644
--- a/drivers/soc/fsl/qe/Kconfig
+++ b/drivers/soc/fsl/qe/Kconfig
@@ -5,7 +5,8 @@
config QUICC_ENGINE
bool "QUICC Engine (QE) framework support"
- depends on FSL_SOC && PPC32
+ depends on OF && HAS_IOMEM
+ depends on PPC32 || ARM || ARM64 || COMPILE_TEST
select GENERIC_ALLOCATOR
select CRC32
help
--
2.23.0
On Fri, Nov 8, 2019 at 7:05 AM Rasmus Villemoes
<[email protected]> wrote:
>
> There are also ARM and ARM64 based SOCs with a QUICC Engine, and the
> core QE code as well as net/wan/fsl_ucc_hdlc and tty/serial/ucc_uart
> has now been modified to not rely on ppcisms.
>
> So extend the architectures that can select QUICC_ENGINE, and add the
> rather modest requirements of OF && HAS_IOMEM.
>
> The core code as well as the ucc_uart driver has been tested on an
> LS1021A (arm), and it has also been tested that the QE code still
> works on an mpc8309 (ppc).
>
> Signed-off-by: Rasmus Villemoes <[email protected]>
> ---
> drivers/soc/fsl/qe/Kconfig | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig
> index cfa4b2939992..f1974f811572 100644
> --- a/drivers/soc/fsl/qe/Kconfig
> +++ b/drivers/soc/fsl/qe/Kconfig
> @@ -5,7 +5,8 @@
>
> config QUICC_ENGINE
> bool "QUICC Engine (QE) framework support"
> - depends on FSL_SOC && PPC32
> + depends on OF && HAS_IOMEM
> + depends on PPC32 || ARM || ARM64 || COMPILE_TEST
Can you also add PPC64? It is also used on some PPC64 platforms
(QorIQ T series).
> select GENERIC_ALLOCATOR
> select CRC32
> help
> --
> 2.23.0
>
On 09/11/2019 00.48, Li Yang wrote:
> On Fri, Nov 8, 2019 at 7:05 AM Rasmus Villemoes
> <[email protected]> wrote:
>>
>> There are also ARM and ARM64 based SOCs with a QUICC Engine, and the
>> core QE code as well as net/wan/fsl_ucc_hdlc and tty/serial/ucc_uart
>> has now been modified to not rely on ppcisms.
>>
>> So extend the architectures that can select QUICC_ENGINE, and add the
>> rather modest requirements of OF && HAS_IOMEM.
>>
>> The core code as well as the ucc_uart driver has been tested on an
>> LS1021A (arm), and it has also been tested that the QE code still
>> works on an mpc8309 (ppc).
>>
>> Signed-off-by: Rasmus Villemoes <[email protected]>
>> ---
>> drivers/soc/fsl/qe/Kconfig | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig
>> index cfa4b2939992..f1974f811572 100644
>> --- a/drivers/soc/fsl/qe/Kconfig
>> +++ b/drivers/soc/fsl/qe/Kconfig
>> @@ -5,7 +5,8 @@
>>
>> config QUICC_ENGINE
>> bool "QUICC Engine (QE) framework support"
>> - depends on FSL_SOC && PPC32
>> + depends on OF && HAS_IOMEM
>> + depends on PPC32 || ARM || ARM64 || COMPILE_TEST
>
> Can you also add PPC64? It is also used on some PPC64 platforms
> (QorIQ T series).
Sure, but if that's the only thing in the whole series, perhaps you
could amend it when applying instead of me sending all 47 patches again.
Should PPC32 || PPC64 be spelled PPC?
Rasmus
On Mon, Nov 11, 2019 at 1:36 AM Rasmus Villemoes
<[email protected]> wrote:
>
> On 09/11/2019 00.48, Li Yang wrote:
> > On Fri, Nov 8, 2019 at 7:05 AM Rasmus Villemoes
> > <[email protected]> wrote:
> >>
> >> There are also ARM and ARM64 based SOCs with a QUICC Engine, and the
> >> core QE code as well as net/wan/fsl_ucc_hdlc and tty/serial/ucc_uart
> >> has now been modified to not rely on ppcisms.
> >>
> >> So extend the architectures that can select QUICC_ENGINE, and add the
> >> rather modest requirements of OF && HAS_IOMEM.
> >>
> >> The core code as well as the ucc_uart driver has been tested on an
> >> LS1021A (arm), and it has also been tested that the QE code still
> >> works on an mpc8309 (ppc).
> >>
> >> Signed-off-by: Rasmus Villemoes <[email protected]>
> >> ---
> >> drivers/soc/fsl/qe/Kconfig | 3 ++-
> >> 1 file changed, 2 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig
> >> index cfa4b2939992..f1974f811572 100644
> >> --- a/drivers/soc/fsl/qe/Kconfig
> >> +++ b/drivers/soc/fsl/qe/Kconfig
> >> @@ -5,7 +5,8 @@
> >>
> >> config QUICC_ENGINE
> >> bool "QUICC Engine (QE) framework support"
> >> - depends on FSL_SOC && PPC32
> >> + depends on OF && HAS_IOMEM
> >> + depends on PPC32 || ARM || ARM64 || COMPILE_TEST
> >
> > Can you also add PPC64? It is also used on some PPC64 platforms
> > (QorIQ T series).
>
> Sure, but if that's the only thing in the whole series, perhaps you
> could amend it when applying instead of me sending all 47 patches again.
Sure. I can do that.
>
> Should PPC32 || PPC64 be spelled PPC?
Yes. That will be good.
Regards,
Leo
On Fri, Nov 8, 2019 at 21:01, Rasmus Villemoes <[email protected]> wrote:
> -----Original Message-----
> From: Rasmus Villemoes <[email protected]>
> Sent: 2019??11??8?? 21:01
> To: Qiang Zhao <[email protected]>; Leo Li <[email protected]>;
> Christophe Leroy <[email protected]>
> Cc: [email protected]; [email protected];
> [email protected]; Scott Wood <[email protected]>; Rasmus
> Villemoes <[email protected]>
> Subject: [PATCH v4 47/47] soc: fsl: qe: remove PPC32 dependency from
> CONFIG_QUICC_ENGINE
>
> There are also ARM and ARM64 based SOCs with a QUICC Engine, and the core
> QE code as well as net/wan/fsl_ucc_hdlc and tty/serial/ucc_uart has now been
> modified to not rely on ppcisms.
>
> So extend the architectures that can select QUICC_ENGINE, and add the rather
> modest requirements of OF && HAS_IOMEM.
>
> The core code as well as the ucc_uart driver has been tested on an LS1021A
> (arm), and it has also been tested that the QE code still works on an mpc8309
> (ppc).
>
> Signed-off-by: Rasmus Villemoes <[email protected]>
> ---
> drivers/soc/fsl/qe/Kconfig | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig index
> cfa4b2939992..f1974f811572 100644
> --- a/drivers/soc/fsl/qe/Kconfig
> +++ b/drivers/soc/fsl/qe/Kconfig
> @@ -5,7 +5,8 @@
>
> config QUICC_ENGINE
> bool "QUICC Engine (QE) framework support"
> - depends on FSL_SOC && PPC32
> + depends on OF && HAS_IOMEM
> + depends on PPC32 || ARM || ARM64 || COMPILE_TEST
> select GENERIC_ALLOCATOR
> select CRC32
> help
> --
Tested-by: Qiang Zhao <[email protected]>
Tested QE-HDLC on ARM64!
Best Regards
Qiang Zhao
Hi Rasmus,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on net-next/master]
[cannot apply to v5.4-rc8 next-20191120]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Rasmus-Villemoes/soc-fsl-qe-remove-space-before-tab/20191110-050001
base: https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git 92da362c07d413786ab59db1665376fb63805586
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (GCC) 7.4.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.4.0 make.cross ARCH=arm
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <[email protected]>
All errors (new ones prefixed by >>):
In file included from drivers/soc/fsl/qe/ucc.c:18:0:
>> arch/arm/include/asm/irq.h:34:50: error: unknown type name 'cpumask_t'
extern void arch_trigger_cpumask_backtrace(const cpumask_t *mask,
^~~~~~~~~
vim +/cpumask_t +34 arch/arm/include/asm/irq.h
446616dbb48c7d Russell King 2008-09-06 32
96f0e00378d4a1 Russell King 2014-09-03 33 #ifdef CONFIG_SMP
9a01c3ed5cdb35 Chris Metcalf 2016-10-07 @34 extern void arch_trigger_cpumask_backtrace(const cpumask_t *mask,
9a01c3ed5cdb35 Chris Metcalf 2016-10-07 35 bool exclude_self);
9a01c3ed5cdb35 Chris Metcalf 2016-10-07 36 #define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace
96f0e00378d4a1 Russell King 2014-09-03 37 #endif
96f0e00378d4a1 Russell King 2014-09-03 38
:::::: The code at line 34 was first introduced by commit
:::::: 9a01c3ed5cdb35d9004eb92510ee6ea11b4a5f16 nmi_backtrace: add more trigger_*_cpu_backtrace() methods
:::::: TO: Chris Metcalf <[email protected]>
:::::: CC: Linus Torvalds <[email protected]>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/hyperkitty/list/[email protected] Intel Corporation