The RK3128 pinctrl is similar as the RK2928.
David Wu (2):
pinctrl: rockchip: Use common interface for recalced iomux
pinctrl: rockchip: Add rk3128 pinctrl support
.../bindings/pinctrl/rockchip,pinctrl.txt | 1 +
drivers/pinctrl/pinctrl-rockchip.c | 218 +++++++++++++++++----
2 files changed, 180 insertions(+), 39 deletions(-)
--
1.9.1
The other Socs also need the feature of recalced iomux, so
make it as a common interface like iomux route feature.
Signed-off-by: David Wu <[email protected]>
---
drivers/pinctrl/pinctrl-rockchip.c | 89 +++++++++++++++++++++-----------------
1 file changed, 50 insertions(+), 39 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index e831647..fd4e491 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -76,7 +76,6 @@ enum rockchip_pinctrl_type {
#define IOMUX_SOURCE_PMU BIT(2)
#define IOMUX_UNROUTED BIT(3)
#define IOMUX_WIDTH_3BIT BIT(4)
-#define IOMUX_RECALCED BIT(5)
/**
* @type: iomux variant using IOMUX_* constants
@@ -166,6 +165,7 @@ struct rockchip_pin_bank {
struct pinctrl_gpio_range grange;
raw_spinlock_t slock;
u32 toggle_edge_mode;
+ u32 recalced_mask;
u32 route_mask;
};
@@ -291,6 +291,22 @@ struct rockchip_pin_bank {
/**
* struct rockchip_mux_recalced_data: represent a pin iomux data.
+ * @num: bank number.
+ * @pin: pin number.
+ * @bit: index at register.
+ * @reg: register offset.
+ * @mask: mask bit
+ */
+struct rockchip_mux_recalced_data {
+ u8 num;
+ u8 pin;
+ u8 reg;
+ u8 bit;
+ u8 mask;
+};
+
+/**
+ * struct rockchip_mux_recalced_data: represent a pin iomux data.
* @bank_num: bank number.
* @pin: index at register or used to calc index.
* @func: the min pin.
@@ -317,6 +333,8 @@ struct rockchip_pin_ctrl {
int pmu_mux_offset;
int grf_drv_offset;
int pmu_drv_offset;
+ struct rockchip_mux_recalced_data *iomux_recalced;
+ u32 niomux_recalced;
struct rockchip_mux_route_data *iomux_routes;
u32 niomux_routes;
@@ -326,8 +344,6 @@ struct rockchip_pin_ctrl {
void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit);
- void (*iomux_recalc)(u8 bank_num, int pin, int *reg,
- u8 *bit, int *mask);
int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit);
@@ -382,22 +398,6 @@ struct rockchip_pinctrl {
unsigned int nfunctions;
};
-/**
- * struct rockchip_mux_recalced_data: represent a pin iomux data.
- * @num: bank number.
- * @pin: pin number.
- * @bit: index at register.
- * @reg: register offset.
- * @mask: mask bit
- */
-struct rockchip_mux_recalced_data {
- u8 num;
- u8 pin;
- u8 reg;
- u8 bit;
- u8 mask;
-};
-
static struct regmap_config rockchip_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
@@ -557,7 +557,7 @@ static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
* Hardware access
*/
-static const struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
+static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
{
.num = 2,
.pin = 12,
@@ -579,20 +579,22 @@ static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
},
};
-static void rk3328_recalc_mux(u8 bank_num, int pin, int *reg,
- u8 *bit, int *mask)
+static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
+ int *reg, u8 *bit, int *mask)
{
- const struct rockchip_mux_recalced_data *data = NULL;
+ struct rockchip_pinctrl *info = bank->drvdata;
+ struct rockchip_pin_ctrl *ctrl = info->ctrl;
+ struct rockchip_mux_recalced_data *data;
int i;
- for (i = 0; i < ARRAY_SIZE(rk3328_mux_recalced_data); i++)
- if (rk3328_mux_recalced_data[i].num == bank_num &&
- rk3328_mux_recalced_data[i].pin == pin) {
- data = &rk3328_mux_recalced_data[i];
+ for (i = 0; i < ctrl->niomux_recalced; i++) {
+ data = &ctrl->iomux_recalced[i];
+ if (data->num == bank->bank_num &&
+ data->pin == pin)
break;
- }
+ }
- if (!data)
+ if (i >= ctrl->niomux_recalced)
return;
*reg = data->reg;
@@ -877,7 +879,6 @@ static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
{
struct rockchip_pinctrl *info = bank->drvdata;
- struct rockchip_pin_ctrl *ctrl = info->ctrl;
int iomux_num = (pin / 8);
struct regmap *regmap;
unsigned int val;
@@ -916,8 +917,8 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
mask = 0x3;
}
- if (ctrl->iomux_recalc && (mux_type & IOMUX_RECALCED))
- ctrl->iomux_recalc(bank->bank_num, pin, ®, &bit, &mask);
+ if (bank->recalced_mask & BIT(pin))
+ rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
ret = regmap_read(regmap, reg, &val);
if (ret)
@@ -967,7 +968,6 @@ static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
{
struct rockchip_pinctrl *info = bank->drvdata;
- struct rockchip_pin_ctrl *ctrl = info->ctrl;
int iomux_num = (pin / 8);
struct regmap *regmap;
int reg, ret, mask, mux_type;
@@ -1005,8 +1005,8 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
mask = 0x3;
}
- if (ctrl->iomux_recalc && (mux_type & IOMUX_RECALCED))
- ctrl->iomux_recalc(bank->bank_num, pin, ®, &bit, &mask);
+ if (bank->recalced_mask & BIT(pin))
+ rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
if (bank->route_mask & BIT(pin)) {
if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
@@ -2853,6 +2853,16 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
bank_pins += 8;
}
+ /* calculate the per-bank recalced_mask */
+ for (j = 0; j < ctrl->niomux_recalced; j++) {
+ int pin = 0;
+
+ if (ctrl->iomux_recalced[j].num == bank->bank_num) {
+ pin = ctrl->iomux_recalced[j].pin;
+ bank->recalced_mask |= BIT(pin);
+ }
+ }
+
/* calculate the per-bank route_mask */
for (j = 0; j < ctrl->niomux_routes; j++) {
int pin = 0;
@@ -3165,12 +3175,12 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
- IOMUX_WIDTH_3BIT | IOMUX_RECALCED,
- IOMUX_WIDTH_3BIT | IOMUX_RECALCED,
+ IOMUX_WIDTH_3BIT,
+ IOMUX_WIDTH_3BIT,
0),
PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
IOMUX_WIDTH_3BIT,
- IOMUX_WIDTH_3BIT | IOMUX_RECALCED,
+ IOMUX_WIDTH_3BIT,
0,
0),
};
@@ -3181,11 +3191,12 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
.label = "RK3328-GPIO",
.type = RK3288,
.grf_mux_offset = 0x0,
+ .iomux_recalced = rk3328_mux_recalced_data,
+ .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
.iomux_routes = rk3328_mux_route_data,
.niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
.pull_calc_reg = rk3228_calc_pull_reg_and_bit,
.drv_calc_reg = rk3228_calc_drv_reg_and_bit,
- .iomux_recalc = rk3328_recalc_mux,
.schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
};
--
1.9.1
There are 3 IP blocks pin routes need to be switched, that are
emmc-cmd, spi, i2s. And there are some pins need to be recalced,
which are gpio2c4~gpio2c7 and gpio2d0.
Signed-off-by: David Wu <[email protected]>
---
.../bindings/pinctrl/rockchip,pinctrl.txt | 1 +
drivers/pinctrl/pinctrl-rockchip.c | 129 +++++++++++++++++++++
2 files changed, 130 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
index ee01ab5..58b7921 100644
--- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
@@ -24,6 +24,7 @@ Required properties for iomux controller:
"rockchip,rk2928-pinctrl": for Rockchip RK2928
"rockchip,rk3066a-pinctrl": for Rockchip RK3066a
"rockchip,rk3066b-pinctrl": for Rockchip RK3066b
+ "rockchip,rk3128-pinctrl": for Rockchip RK3128
"rockchip,rk3188-pinctrl": for Rockchip RK3188
"rockchip,rk3228-pinctrl": for Rockchip RK3228
"rockchip,rk3288-pinctrl": for Rockchip RK3288
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index fd4e491..7ba0c40 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -62,6 +62,7 @@ enum rockchip_pinctrl_type {
RV1108,
RK2928,
RK3066B,
+ RK3128,
RK3188,
RK3288,
RK3368,
@@ -557,6 +558,40 @@ static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
* Hardware access
*/
+static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
+ {
+ .num = 2,
+ .pin = 20,
+ .reg = 0xe8,
+ .bit = 0,
+ .mask = 0x7
+ }, {
+ .num = 2,
+ .pin = 21,
+ .reg = 0xe8,
+ .bit = 4,
+ .mask = 0x7
+ }, {
+ .num = 2,
+ .pin = 22,
+ .reg = 0xe8,
+ .bit = 8,
+ .mask = 0x7
+ }, {
+ .num = 2,
+ .pin = 23,
+ .reg = 0xe8,
+ .bit = 12,
+ .mask = 0x7
+ }, {
+ .num = 2,
+ .pin = 24,
+ .reg = 0xd4,
+ .bit = 12,
+ .mask = 0x7
+ },
+};
+
static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
{
.num = 2,
@@ -602,6 +637,59 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
*bit = data->bit;
}
+static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
+ {
+ /* spi-0 */
+ .bank_num = 1,
+ .pin = 10,
+ .func = 1,
+ .route_offset = 0x144,
+ .route_val = BIT(16 + 3) | BIT(16 + 4),
+ }, {
+ /* spi-1 */
+ .bank_num = 1,
+ .pin = 27,
+ .func = 3,
+ .route_offset = 0x144,
+ .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
+ }, {
+ /* spi-2 */
+ .bank_num = 0,
+ .pin = 13,
+ .func = 2,
+ .route_offset = 0x144,
+ .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
+ }, {
+ /* i2s-0 */
+ .bank_num = 1,
+ .pin = 5,
+ .func = 1,
+ .route_offset = 0x144,
+ .route_val = BIT(16 + 5),
+ }, {
+ /* i2s-1 */
+ .bank_num = 0,
+ .pin = 14,
+ .func = 1,
+ .route_offset = 0x144,
+ .route_val = BIT(16 + 5) | BIT(5),
+ }, {
+ /* emmc-0 */
+ .bank_num = 1,
+ .pin = 22,
+ .func = 2,
+ .route_offset = 0x144,
+ .route_val = BIT(16 + 6),
+ }, {
+ /* emmc-1 */
+ .bank_num = 2,
+ .pin = 4,
+ .func = 2,
+ .route_offset = 0x144,
+ .route_val = BIT(16 + 6) | BIT(6),
+ },
+};
+
static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
{
/* pwm0-0 */
@@ -1102,6 +1190,22 @@ static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*bit = pin_num % RK2928_PULL_PINS_PER_REG;
};
+#define RK3128_PULL_OFFSET 0x118
+
+static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+
+ *regmap = info->regmap_base;
+ *reg = RK3128_PULL_OFFSET;
+ *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
+ *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
+
+ *bit = pin_num % RK2928_PULL_PINS_PER_REG;
+}
+
#define RK3188_PULL_OFFSET 0x164
#define RK3188_PULL_BITS_PER_PIN 2
#define RK3188_PULL_PINS_PER_REG 8
@@ -1571,6 +1675,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
switch (ctrl->type) {
case RK2928:
+ case RK3128:
return !(data & BIT(bit))
? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
: PIN_CONFIG_BIAS_DISABLE;
@@ -1611,6 +1716,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
switch (ctrl->type) {
case RK2928:
+ case RK3128:
data = BIT(bit + 16);
if (pull == PIN_CONFIG_BIAS_DISABLE)
data |= BIT(bit);
@@ -1865,6 +1971,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
{
switch (ctrl->type) {
case RK2928:
+ case RK3128:
return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
pull == PIN_CONFIG_BIAS_DISABLE);
case RK3066B:
@@ -3093,6 +3200,26 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
.grf_mux_offset = 0x60,
};
+static struct rockchip_pin_bank rk3128_pin_banks[] = {
+ PIN_BANK(0, 32, "gpio0"),
+ PIN_BANK(1, 32, "gpio1"),
+ PIN_BANK(2, 32, "gpio2"),
+ PIN_BANK(3, 32, "gpio3"),
+};
+
+static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
+ .pin_banks = rk3128_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
+ .label = "RK3128-GPIO",
+ .type = RK3128,
+ .grf_mux_offset = 0xa8,
+ .iomux_recalced = rk3128_mux_recalced_data,
+ .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
+ .iomux_routes = rk3128_mux_route_data,
+ .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
+ .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
+};
+
static struct rockchip_pin_bank rk3188_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
PIN_BANK(1, 32, "gpio1"),
@@ -3301,6 +3428,8 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
.data = &rk3066a_pin_ctrl },
{ .compatible = "rockchip,rk3066b-pinctrl",
.data = &rk3066b_pin_ctrl },
+ { .compatible = "rockchip,rk3128-pinctrl",
+ .data = (void *)&rk3128_pin_ctrl },
{ .compatible = "rockchip,rk3188-pinctrl",
.data = &rk3188_pin_ctrl },
{ .compatible = "rockchip,rk3228-pinctrl",
--
1.9.1
Am Freitag, 21. Juli 2017, 14:27:14 CEST schrieb David Wu:
> The other Socs also need the feature of recalced iomux, so
> make it as a common interface like iomux route feature.
>
> Signed-off-by: David Wu <[email protected]>
> ---
> drivers/pinctrl/pinctrl-rockchip.c | 89 +++++++++++++++++++++-----------------
> 1 file changed, 50 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
> index e831647..fd4e491 100644
> --- a/drivers/pinctrl/pinctrl-rockchip.c
> +++ b/drivers/pinctrl/pinctrl-rockchip.c
> @@ -76,7 +76,6 @@ enum rockchip_pinctrl_type {
> #define IOMUX_SOURCE_PMU BIT(2)
> #define IOMUX_UNROUTED BIT(3)
> #define IOMUX_WIDTH_3BIT BIT(4)
> -#define IOMUX_RECALCED BIT(5)
very cool to see this flag go away and simply calculating the affected
bits is obviously a way nicer solution.
Reviewed-by: Heiko Stuebner <[email protected]>
Thanks for that cleanup
Heiko
Am Freitag, 21. Juli 2017, 14:27:15 CEST schrieb David Wu:
> There are 3 IP blocks pin routes need to be switched, that are
> emmc-cmd, spi, i2s. And there are some pins need to be recalced,
> which are gpio2c4~gpio2c7 and gpio2d0.
>
> Signed-off-by: David Wu <[email protected]>
Reviewed-by: Heiko Stuebner <[email protected]>
On Fri, Jul 21, 2017 at 8:27 AM, David Wu <[email protected]> wrote:
> The other Socs also need the feature of recalced iomux, so
> make it as a common interface like iomux route feature.
>
> Signed-off-by: David Wu <[email protected]>
Patch applied with Heiko's review tag.
Yours,
Linus Walleij
On Fri, Jul 21, 2017 at 8:27 AM, David Wu <[email protected]> wrote:
> There are 3 IP blocks pin routes need to be switched, that are
> emmc-cmd, spi, i2s. And there are some pins need to be recalced,
> which are gpio2c4~gpio2c7 and gpio2d0.
>
> Signed-off-by: David Wu <[email protected]>
Patch applied with Heiko's review tag.
Yours,
Linus Walleij