* Set and print cpu frequency at boot time generic way.
* Get rid of platform specific cpu clock configuration for AXS103 in
arch/arc/plat-axs10x/axs10x.c
* Add core pll node to AXS103 device tree to manage cpu frequency
* Refactor clock managment in arch/arc/plat-axs10x/axs10x.c
Eugeniy Paltsev (5):
ARC: set and print cpu frequency at boot time
ARC: AXS103: Get rid of platform specific cpu clock configuration
ARC: AXS103: DTS: Add core pll node to manage cpu frequency
ARC: AXS103: DTS: Set cpu frequency explicitly via dts
ARC: AXS103: use cpu-freq param instead of /cpu_card/core_clk
arch/arc/boot/dts/axc003.dtsi | 24 +++++++++-
arch/arc/boot/dts/axc003_idu.dtsi | 42 +++++++++++++++++-
arch/arc/kernel/setup.c | 49 +++++++++++++++++++++
arch/arc/plat-axs10x/axs10x.c | 92 ++-------------------------------------
4 files changed, 115 insertions(+), 92 deletions(-)
--
2.9.3
Print cpu frequency at boot time. In case we have pre-defined
cpu frequency value in device tree try to set it.
Signed-off-by: Eugeniy Paltsev <[email protected]>
---
arch/arc/kernel/setup.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index 877cec8..b5fcc5d 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -464,12 +464,61 @@ void __init setup_arch(char **cmdline_p)
arc_unwind_init();
}
+static int __init set_cpu_freq(int cpu_id)
+{
+ struct device_node *cpunode;
+ u32 cpu_freq_required;
+ struct clk *clk;
+ int ret;
+
+ cpunode = of_get_cpu_node(cpu_id, NULL);
+ if (cpunode == NULL) {
+ pr_err("Can't find CPU %d node.\n", cpu_id);
+ return -ENOENT;
+ }
+
+ clk = of_clk_get(cpunode, 0);
+ if (IS_ERR(clk)) {
+ pr_err("CPU %d missing clk.\n", cpu_id);
+ return PTR_ERR(clk);
+ }
+
+ ret = clk_prepare_enable(clk);
+ if (ret) {
+ pr_err("Couldn't enable CPU %d clk.\n", cpu_id);
+ return ret;
+ }
+
+ /*
+ * In case we have pre-defined cpu frequency value in device tree
+ * try to set it. Otherwise just print current cpu frequency.
+ */
+ if (of_property_read_u32(cpunode, "cpu-freq", &cpu_freq_required)) {
+ pr_info("CPU %d has no cpu-freq param. Frequency is %lu Hz.\n",
+ cpu_id, clk_get_rate(clk));
+ return 0;
+ }
+
+ if (clk_set_rate(clk, cpu_freq_required))
+ pr_err("CPU %d frequency set failed. Probably fixed-clock is used for cpu.\n",
+ cpu_id);
+
+ pr_info("CPU %d frequency is %lu Hz.\n", cpu_id, clk_get_rate(clk));
+
+ return 0;
+}
+
/*
* Called from start_kernel() - boot CPU only
*/
void __init time_init(void)
{
of_clk_init(NULL);
+ /*
+ * As for now we have common clock for all cpu cores, so set
+ * frequency only for master cpu.
+ */
+ set_cpu_freq(0);
timer_probe();
}
--
2.9.3
We set AXS103 cpu frequency in arch/arc/plat-axs10x/axs10x.c
via direct writing to pll registers for historical reasons.
So get rid of AXS103 platform specific cpu clock configuration as
we have driver for AXS103 core pll (AXS103 pll driver is already
in linux-next. It is selected automatically when
CONFIG_ARC_PLAT_AXS10X is set)
Signed-off-by: Eugeniy Paltsev <[email protected]>
---
arch/arc/plat-axs10x/axs10x.c | 88 ++-----------------------------------------
1 file changed, 4 insertions(+), 84 deletions(-)
diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat-axs10x/axs10x.c
index 38ff349..98d07b7 100644
--- a/arch/arc/plat-axs10x/axs10x.c
+++ b/arch/arc/plat-axs10x/axs10x.c
@@ -335,61 +335,12 @@ union pll_reg {
unsigned int val;
};
-static unsigned int __init axs103_get_freq(void)
-{
- union pll_reg idiv, fbdiv, odiv;
- unsigned int f = 33333333;
-
- idiv.val = ioread32((void __iomem *)AXC003_CGU + 0x80 + 0);
- fbdiv.val = ioread32((void __iomem *)AXC003_CGU + 0x80 + 4);
- odiv.val = ioread32((void __iomem *)AXC003_CGU + 0x80 + 8);
-
- if (idiv.bypass != 1)
- f = f / (idiv.low + idiv.high);
-
- if (fbdiv.bypass != 1)
- f = f * (fbdiv.low + fbdiv.high);
-
- if (odiv.bypass != 1)
- f = f / (odiv.low + odiv.high);
-
- f = (f + 500000) / 1000000; /* Rounding */
- return f;
-}
-
-static inline unsigned int __init encode_div(unsigned int id, int upd)
-{
- union pll_reg div;
-
- div.val = 0;
-
- div.noupd = !upd;
- div.bypass = id == 1 ? 1 : 0;
- div.edge = (id%2 == 0) ? 0 : 1; /* 0 = rising */
- div.low = (id%2 == 0) ? id >> 1 : (id >> 1)+1;
- div.high = id >> 1;
-
- return div.val;
-}
-
-noinline static void __init
-axs103_set_freq(unsigned int id, unsigned int fd, unsigned int od)
-{
- write_cgu_reg(encode_div(id, 0),
- (void __iomem *)AXC003_CGU + 0x80 + 0,
- (void __iomem *)AXC003_CGU + 0x110);
-
- write_cgu_reg(encode_div(fd, 0),
- (void __iomem *)AXC003_CGU + 0x80 + 4,
- (void __iomem *)AXC003_CGU + 0x110);
-
- write_cgu_reg(encode_div(od, 1),
- (void __iomem *)AXC003_CGU + 0x80 + 8,
- (void __iomem *)AXC003_CGU + 0x110);
-}
-
static void __init axs103_early_init(void)
{
+ /*
+ * TODO: use cpu node "cpu-freq" param instead of platform-specific
+ * "/cpu_card/core_clk" as it works only if we use fixed-clock for cpu.
+ */
int offset = fdt_path_offset(initial_boot_params, "/cpu_card/core_clk");
const struct fdt_property *prop = fdt_get_property(initial_boot_params,
offset,
@@ -412,37 +363,6 @@ static void __init axs103_early_init(void)
freq = 50;
#endif
- switch (freq) {
- case 33:
- axs103_set_freq(1, 1, 1);
- break;
- case 50:
- axs103_set_freq(1, 30, 20);
- break;
- case 75:
- axs103_set_freq(2, 45, 10);
- break;
- case 90:
- axs103_set_freq(2, 54, 10);
- break;
- case 100:
- axs103_set_freq(1, 30, 10);
- break;
- case 125:
- axs103_set_freq(2, 45, 6);
- break;
- default:
- /*
- * In this case, core_frequency derived from
- * DT "clock-frequency" might not match with board value.
- * Hence update it to match the board value.
- */
- freq = axs103_get_freq();
- break;
- }
-
- pr_info("Freq is %dMHz\n", freq);
-
/* Patching .dtb in-place with new core clock value */
if (freq != orig ) {
freq = cpu_to_be32(freq * 1000000);
--
2.9.3
Set cpu frequency explicitly via "cpu-freq" param in cpu 0 node
in device tree.
We add "cpu-freq" only to cpu 0 as all cpus are clocking from same
clock source (same pll in our case).
We override cpus node in skeleton as we don't need this change for
nsim.
Signed-off-by: Eugeniy Paltsev <[email protected]>
---
arch/arc/boot/dts/axc003.dtsi | 13 +++++++++++++
arch/arc/boot/dts/axc003_idu.dtsi | 35 +++++++++++++++++++++++++++++++++++
2 files changed, 48 insertions(+)
diff --git a/arch/arc/boot/dts/axc003.dtsi b/arch/arc/boot/dts/axc003.dtsi
index dca7e39..7c7411c 100644
--- a/arch/arc/boot/dts/axc003.dtsi
+++ b/arch/arc/boot/dts/axc003.dtsi
@@ -17,6 +17,19 @@
#address-cells = <2>;
#size-cells = <2>;
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "snps,archs38";
+ reg = <0>;
+ cpu-freq = <100000000>;
+ clocks = <&core_clk>;
+ };
+ };
+
cpu_card {
compatible = "simple-bus";
#address-cells = <1>;
diff --git a/arch/arc/boot/dts/axc003_idu.dtsi b/arch/arc/boot/dts/axc003_idu.dtsi
index 5b56bef..44bc01e 100644
--- a/arch/arc/boot/dts/axc003_idu.dtsi
+++ b/arch/arc/boot/dts/axc003_idu.dtsi
@@ -17,6 +17,41 @@
#address-cells = <2>;
#size-cells = <2>;
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /*
+ * "cpu-freq" was added only to cpu 0 as all cpus are clocking
+ * from same clock source (same pll (core_clk) in our case).
+ */
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "snps,archs38";
+ reg = <0>;
+ cpu-freq = <100000000>;
+ clocks = <&core_clk>;
+ };
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "snps,archs38";
+ reg = <1>;
+ clocks = <&core_clk>;
+ };
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "snps,archs38";
+ reg = <2>;
+ clocks = <&core_clk>;
+ };
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "snps,archs38";
+ reg = <3>;
+ clocks = <&core_clk>;
+ };
+ };
+
cpu_card {
compatible = "simple-bus";
#address-cells = <1>;
--
2.9.3
Use cpu's node "cpu-freq" param instead of platform-specific
"/cpu_card/core_clk" as it works only if we use fixed-clock for cpu
clocking.
Signed-off-by: Eugeniy Paltsev <[email protected]>
---
arch/arc/plat-axs10x/axs10x.c | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat-axs10x/axs10x.c
index 98d07b7..75118fdc 100644
--- a/arch/arc/plat-axs10x/axs10x.c
+++ b/arch/arc/plat-axs10x/axs10x.c
@@ -337,20 +337,16 @@ union pll_reg {
static void __init axs103_early_init(void)
{
- /*
- * TODO: use cpu node "cpu-freq" param instead of platform-specific
- * "/cpu_card/core_clk" as it works only if we use fixed-clock for cpu.
- */
- int offset = fdt_path_offset(initial_boot_params, "/cpu_card/core_clk");
+ int offset = fdt_path_offset(initial_boot_params, "/cpus/cpu@0");
const struct fdt_property *prop = fdt_get_property(initial_boot_params,
offset,
- "clock-frequency",
+ "cpu-freq",
NULL);
u32 freq = be32_to_cpu(*(u32*)(prop->data)) / 1000000, orig = freq;
/*
* AXS103 configurations for SMP/QUAD configurations share device tree
- * which defaults to 90 MHz. However recent failures of Quad config
+ * which defaults to 100 MHz. However recent failures of Quad config
* revealed P&R timing violations so clamp it down to safe 50 MHz
* Instead of duplicating defconfig/DT for SMP/QUAD, add a small hack
*
@@ -367,7 +363,7 @@ static void __init axs103_early_init(void)
if (freq != orig ) {
freq = cpu_to_be32(freq * 1000000);
fdt_setprop_inplace(initial_boot_params, offset,
- "clock-frequency", &freq, sizeof(freq));
+ "cpu-freq", &freq, sizeof(freq));
}
/* Memory maps already config in pre-bootloader */
--
2.9.3
Add core pll node (core_clk) to manage cpu frequency.
core_clk represents pll itself.
input_clk represents clock signal source (basically xtal) which
comes to pll input.
Signed-off-by: Eugeniy Paltsev <[email protected]>
---
arch/arc/boot/dts/axc003.dtsi | 11 +++++++++--
arch/arc/boot/dts/axc003_idu.dtsi | 11 +++++++++--
2 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/arch/arc/boot/dts/axc003.dtsi b/arch/arc/boot/dts/axc003.dtsi
index cc9239e..dca7e39 100644
--- a/arch/arc/boot/dts/axc003.dtsi
+++ b/arch/arc/boot/dts/axc003.dtsi
@@ -24,10 +24,17 @@
ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
- core_clk: core_clk {
+ input_clk: input-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
- clock-frequency = <90000000>;
+ clock-frequency = <33333333>;
+ };
+
+ core_clk: core-clk@80 {
+ compatible = "snps,axs10x-arc-pll-clock";
+ reg = <0x80 0x10>, <0x100 0x10>;
+ #clock-cells = <0>;
+ clocks = <&input_clk>;
};
core_intc: archs-intc@cpu {
diff --git a/arch/arc/boot/dts/axc003_idu.dtsi b/arch/arc/boot/dts/axc003_idu.dtsi
index 4ebb2170..5b56bef 100644
--- a/arch/arc/boot/dts/axc003_idu.dtsi
+++ b/arch/arc/boot/dts/axc003_idu.dtsi
@@ -24,10 +24,17 @@
ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
- core_clk: core_clk {
+ input_clk: input-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
- clock-frequency = <100000000>;
+ clock-frequency = <33333333>;
+ };
+
+ core_clk: core-clk@80 {
+ compatible = "snps,axs10x-arc-pll-clock";
+ reg = <0x80 0x10>, <0x100 0x10>;
+ #clock-cells = <0>;
+ clocks = <&input_clk>;
};
core_intc: archs-intc@cpu {
--
2.9.3
On 08/14/2017 09:12 AM, Eugeniy Paltsev wrote:
> We set AXS103 cpu frequency in arch/arc/plat-axs10x/axs10x.c
> via direct writing to pll registers for historical reasons.
> So get rid of AXS103 platform specific cpu clock configuration as
> we have driver for AXS103 core pll (AXS103 pll driver is already
> in linux-next. It is selected automatically when
> CONFIG_ARC_PLAT_AXS10X is set)
>
> Signed-off-by: Eugeniy Paltsev <[email protected]>
> ---
> arch/arc/plat-axs10x/axs10x.c | 88 ++-----------------------------------------
> 1 file changed, 4 insertions(+), 84 deletions(-)
>
> diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat-axs10x/axs10x.c
> index 38ff349..98d07b7 100644
> --- a/arch/arc/plat-axs10x/axs10x.c
> +++ b/arch/arc/plat-axs10x/axs10x.c
> @@ -335,61 +335,12 @@ union pll_reg {
> unsigned int val;
> };
You forget to prune a bunch of code not needed anymore - pll_reg struct /
write_cgu_reg ....
I've fixed that up locally !
Nice cleanup !
Thx,
-Vineet
On 08/14/2017 09:12 AM, Eugeniy Paltsev wrote:
> Add core pll node (core_clk) to manage cpu frequency.
> core_clk represents pll itself.
> input_clk represents clock signal source (basically xtal) which
> comes to pll input.
>
> Signed-off-by: Eugeniy Paltsev <[email protected]>
> ---
> arch/arc/boot/dts/axc003.dtsi | 11 +++++++++--
> arch/arc/boot/dts/axc003_idu.dtsi | 11 +++++++++--
> 2 files changed, 18 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arc/boot/dts/axc003.dtsi b/arch/arc/boot/dts/axc003.dtsi
> index cc9239e..dca7e39 100644
> --- a/arch/arc/boot/dts/axc003.dtsi
> +++ b/arch/arc/boot/dts/axc003.dtsi
> @@ -24,10 +24,17 @@
>
> ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
>
> - core_clk: core_clk {
> + input_clk: input-clk {
> #clock-cells = <0>;
> compatible = "fixed-clock";
> - clock-frequency = <90000000>;
> + clock-frequency = <33333333>;
Note our custom built UP bitfiles for AXS generally can do 90 MHz only - you are
likely breaking linux on them now by forcing 100 MHz ?
> + };
> +
> + core_clk: core-clk@80 {
> + compatible = "snps,axs10x-arc-pll-clock";
> + reg = <0x80 0x10>, <0x100 0x10>;
> + #clock-cells = <0>;
> + clocks = <&input_clk>;
> };
>
> core_intc: archs-intc@cpu {
> diff --git a/arch/arc/boot/dts/axc003_idu.dtsi b/arch/arc/boot/dts/axc003_idu.dtsi
> index 4ebb2170..5b56bef 100644
> --- a/arch/arc/boot/dts/axc003_idu.dtsi
> +++ b/arch/arc/boot/dts/axc003_idu.dtsi
> @@ -24,10 +24,17 @@
>
> ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
>
> - core_clk: core_clk {
> + input_clk: input-clk {
> #clock-cells = <0>;
> compatible = "fixed-clock";
> - clock-frequency = <100000000>;
> + clock-frequency = <33333333>;
> + };
> +
> + core_clk: core-clk@80 {
> + compatible = "snps,axs10x-arc-pll-clock";
> + reg = <0x80 0x10>, <0x100 0x10>;
> + #clock-cells = <0>;
> + clocks = <&input_clk>;
> };
>
> core_intc: archs-intc@cpu {
On 08/14/2017 09:12 AM, Eugeniy Paltsev wrote:
> Add core pll node (core_clk) to manage cpu frequency.
> core_clk represents pll itself.
> input_clk represents clock signal source (basically xtal) which
> comes to pll input.
>
> Signed-off-by: Eugeniy Paltsev <[email protected]>
> ---
> arch/arc/boot/dts/axc003.dtsi | 11 +++++++++--
> arch/arc/boot/dts/axc003_idu.dtsi | 11 +++++++++--
> 2 files changed, 18 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arc/boot/dts/axc003.dtsi b/arch/arc/boot/dts/axc003.dtsi
> index cc9239e..dca7e39 100644
> --- a/arch/arc/boot/dts/axc003.dtsi
> +++ b/arch/arc/boot/dts/axc003.dtsi
> @@ -24,10 +24,17 @@
>
> ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
>
> - core_clk: core_clk {
> + input_clk: input-clk {
> #clock-cells = <0>;
> compatible = "fixed-clock";
> - clock-frequency = <90000000>;
> + clock-frequency = <33333333>;
> + };
> +
> + core_clk: core-clk@80 {
> + compatible = "snps,axs10x-arc-pll-clock";
> + reg = <0x80 0x10>, <0x100 0x10>;
> + #clock-cells = <0>;
> + clocks = <&input_clk>;
> };
>
> core_intc: archs-intc@cpu {
> diff --git a/arch/arc/boot/dts/axc003_idu.dtsi b/arch/arc/boot/dts/axc003_idu.dtsi
> index 4ebb2170..5b56bef 100644
> --- a/arch/arc/boot/dts/axc003_idu.dtsi
> +++ b/arch/arc/boot/dts/axc003_idu.dtsi
> @@ -24,10 +24,17 @@
>
> ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
>
> - core_clk: core_clk {
> + input_clk: input-clk {
> #clock-cells = <0>;
> compatible = "fixed-clock";
> - clock-frequency = <100000000>;
> + clock-frequency = <33333333>;
> + };
> +
> + core_clk: core-clk@80 {
> + compatible = "snps,axs10x-arc-pll-clock";
> + reg = <0x80 0x10>, <0x100 0x10>;
> + #clock-cells = <0>;
> + clocks = <&input_clk>;
> };
>
> core_intc: archs-intc@cpu {
Do we have a bisectability issue here - isn't system broken temporarily at 2/5 -
and only 3/5 makes it work again - if so we need to squash them together !
-Vineet
On 08/14/2017 09:12 AM, Eugeniy Paltsev wrote:
> Set cpu frequency explicitly via "cpu-freq" param in cpu 0 node
> in device tree.
>
> We add "cpu-freq" only to cpu 0 as all cpus are clocking from same
> clock source (same pll in our case).
>
> We override cpus node in skeleton as we don't need this change for
> nsim.
Given that you added a generic feature as part of 1/5 - do other platforms
abilis/nps need corresponding fixups as this one !
>
> Signed-off-by: Eugeniy Paltsev <[email protected]>
> ---
> arch/arc/boot/dts/axc003.dtsi | 13 +++++++++++++
> arch/arc/boot/dts/axc003_idu.dtsi | 35 +++++++++++++++++++++++++++++++++++
> 2 files changed, 48 insertions(+)
>
> diff --git a/arch/arc/boot/dts/axc003.dtsi b/arch/arc/boot/dts/axc003.dtsi
> index dca7e39..7c7411c 100644
> --- a/arch/arc/boot/dts/axc003.dtsi
> +++ b/arch/arc/boot/dts/axc003.dtsi
> @@ -17,6 +17,19 @@
> #address-cells = <2>;
> #size-cells = <2>;
>
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "snps,archs38";
> + reg = <0>;
> + cpu-freq = <100000000>;
> + clocks = <&core_clk>;
> + };
> + };
> +
> cpu_card {
> compatible = "simple-bus";
> #address-cells = <1>;
> diff --git a/arch/arc/boot/dts/axc003_idu.dtsi b/arch/arc/boot/dts/axc003_idu.dtsi
> index 5b56bef..44bc01e 100644
> --- a/arch/arc/boot/dts/axc003_idu.dtsi
> +++ b/arch/arc/boot/dts/axc003_idu.dtsi
> @@ -17,6 +17,41 @@
> #address-cells = <2>;
> #size-cells = <2>;
>
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /*
> + * "cpu-freq" was added only to cpu 0 as all cpus are clocking
> + * from same clock source (same pll (core_clk) in our case).
> + */
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "snps,archs38";
> + reg = <0>;
> + cpu-freq = <100000000>;
> + clocks = <&core_clk>;
> + };
> + cpu@1 {
> + device_type = "cpu";
> + compatible = "snps,archs38";
> + reg = <1>;
> + clocks = <&core_clk>;
> + };
> + cpu@2 {
> + device_type = "cpu";
> + compatible = "snps,archs38";
> + reg = <2>;
> + clocks = <&core_clk>;
> + };
> + cpu@3 {
> + device_type = "cpu";
> + compatible = "snps,archs38";
> + reg = <3>;
> + clocks = <&core_clk>;
> + };
> + };
> +
> cpu_card {
> compatible = "simple-bus";
> #address-cells = <1>;
On Tue, 2017-08-22 at 14:40 -0700, Vineet Gupta wrote:
> On 08/14/2017 09:12 AM, Eugeniy Paltsev wrote:
> > Set cpu frequency explicitly via "cpu-freq" param in cpu 0 node
> > in device tree.
> >
> > We add "cpu-freq" only to cpu 0 as all cpus are clocking from same
> > clock source (same pll in our case).
> >
> > We override cpus node in skeleton as we don't need this change for
> > nsim.
>
> Given that you added a generic feature as part of 1/5 - do other
> platforms
> abilis/nps need corresponding fixups as this one !
Actually no.
If cpu 0 node don't have "cpu-freq" property we simply print cpu
frequency and don't try to change it.
So we can left other dts untouched.
> >
> > Signed-off-by: Eugeniy Paltsev <[email protected]>
> > ---
> > arch/arc/boot/dts/axc003.dtsi | 13 +++++++++++++
> > arch/arc/boot/dts/axc003_idu.dtsi | 35
> > +++++++++++++++++++++++++++++++++++
> > 2 files changed, 48 insertions(+)
> >
> > diff --git a/arch/arc/boot/dts/axc003.dtsi
> > b/arch/arc/boot/dts/axc003.dtsi
> > index dca7e39..7c7411c 100644
> > --- a/arch/arc/boot/dts/axc003.dtsi
> > +++ b/arch/arc/boot/dts/axc003.dtsi
> > @@ -17,6 +17,19 @@
> > #address-cells = <2>;
> > #size-cells = <2>;
> >
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + cpu@0 {
> > + device_type = "cpu";
> > + compatible = "snps,archs38";
> > + reg = <0>;
> > + cpu-freq = <100000000>;
> > + clocks = <&core_clk>;
> > + };
> > + };
> > +
> > cpu_card {
> > compatible = "simple-bus";
> > #address-cells = <1>;
> > diff --git a/arch/arc/boot/dts/axc003_idu.dtsi
> > b/arch/arc/boot/dts/axc003_idu.dtsi
> > index 5b56bef..44bc01e 100644
> > --- a/arch/arc/boot/dts/axc003_idu.dtsi
> > +++ b/arch/arc/boot/dts/axc003_idu.dtsi
> > @@ -17,6 +17,41 @@
> > #address-cells = <2>;
> > #size-cells = <2>;
> >
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + /*
> > + * "cpu-freq" was added only to cpu 0 as all cpus
> > are clocking
> > + * from same clock source (same pll (core_clk) in
> > our case).
> > + */
> > + cpu@0 {
> > + device_type = "cpu";
> > + compatible = "snps,archs38";
> > + reg = <0>;
> > + cpu-freq = <100000000>;
> > + clocks = <&core_clk>;
> > + };
> > + cpu@1 {
> > + device_type = "cpu";
> > + compatible = "snps,archs38";
> > + reg = <1>;
> > + clocks = <&core_clk>;
> > + };
> > + cpu@2 {
> > + device_type = "cpu";
> > + compatible = "snps,archs38";
> > + reg = <2>;
> > + clocks = <&core_clk>;
> > + };
> > + cpu@3 {
> > + device_type = "cpu";
> > + compatible = "snps,archs38";
> > + reg = <3>;
> > + clocks = <&core_clk>;
> > + };
> > + };
> > +
> > cpu_card {
> > compatible = "simple-bus";
> > #address-cells = <1>;
>
>
--
Eugeniy Paltsev
On Tue, 2017-08-22 at 13:45 -0700, Vineet Gupta wrote:
> On 08/14/2017 09:12 AM, Eugeniy Paltsev wrote:
> > Add core pll node (core_clk) to manage cpu frequency.
> > core_clk represents pll itself.
> > input_clk represents clock signal source (basically xtal) which
> > comes to pll input.
> >
> > Signed-off-by: Eugeniy Paltsev <[email protected]>
> > ---
> > arch/arc/boot/dts/axc003.dtsi | 11 +++++++++--
> > arch/arc/boot/dts/axc003_idu.dtsi | 11 +++++++++--
> > 2 files changed, 18 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arc/boot/dts/axc003.dtsi
> > b/arch/arc/boot/dts/axc003.dtsi
> > index cc9239e..dca7e39 100644
> > --- a/arch/arc/boot/dts/axc003.dtsi
> > +++ b/arch/arc/boot/dts/axc003.dtsi
> > @@ -24,10 +24,17 @@
> >
> > ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
> >
> > - core_clk: core_clk {
> > + input_clk: input-clk {
> > #clock-cells = <0>;
> > compatible = "fixed-clock";
> > - clock-frequency = <90000000>;
> > + clock-frequency = <33333333>;
> > + };
> > +
> > + core_clk: core-clk@80 {
> > + compatible = "snps,axs10x-arc-pll-clock";
> > + reg = <0x80 0x10>, <0x100 0x10>;
> > + #clock-cells = <0>;
> > + clocks = <&input_clk>;
> > };
> >
> > core_intc: archs-intc@cpu {
> > diff --git a/arch/arc/boot/dts/axc003_idu.dtsi
> > b/arch/arc/boot/dts/axc003_idu.dtsi
> > index 4ebb2170..5b56bef 100644
> > --- a/arch/arc/boot/dts/axc003_idu.dtsi
> > +++ b/arch/arc/boot/dts/axc003_idu.dtsi
> > @@ -24,10 +24,17 @@
> >
> > ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
> >
> > - core_clk: core_clk {
> > + input_clk: input-clk {
> > #clock-cells = <0>;
> > compatible = "fixed-clock";
> > - clock-frequency = <100000000>;
> > + clock-frequency = <33333333>;
> > + };
> > +
> > + core_clk: core-clk@80 {
> > + compatible = "snps,axs10x-arc-pll-clock";
> > + reg = <0x80 0x10>, <0x100 0x10>;
> > + #clock-cells = <0>;
> > + clocks = <&input_clk>;
> > };
> >
> > core_intc: archs-intc@cpu {
>
>
> Do we have a bisectability issue here - isn't system broken
> temporarily at 2/5 -
> and only 3/5 makes it work again - if so we need to squash them
> together !
Could you please be more specific about this bisectability issue as I
can't see it here.
If we apply 2/5 and don't apply 3/5 we simply won't change frequency
after linux boot. We won't increase frequency so I can't see any
problem here here.
---
The only problem I can see is in 4/5:
I should use
cpu-freq = <90000000>;
instead of
cpu-freq = <100000000>;
in arch/arc/boot/dts/axc003.dtsi
So diff should be like
--------------->8-----------
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "snps,archs38";
+ reg = <0>;
+ cpu-freq = <90000000>;
+ clocks = <&core_clk>;
+ };
+ };
+
--------------->8-----------
Should I send you v2 respin or you'll fix that up locally?
> -Vineet
--
Eugeniy Paltsev
On 08/23/2017 04:24 AM, Eugeniy Paltsev wrote:
>> Given that you added a generic feature as part of 1/5 - do other
>> platforms
>> abilis/nps need corresponding fixups as this one !
> Actually no.
> If cpu 0 node don't have "cpu-freq" property we simply print cpu
> frequency and don't try to change it.
> So we can left other dts untouched.
OK good. But to keep things consistent lets fix the rest of DTs, as needed, as a
separate patch.