This patch updates the round_rate() logic here to return zero instead of a
negative number on error.
In conjunction with higher-level changes associated with acting on the
return value of clk_ops->round_rate() it is then possible to have
clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of
the current limitation of 1 Hz to LONG_MAX Hz.
Signed-off-by: Bryan O'Donoghue <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: Vladimir Barinov <[email protected]>
Cc: Alexey Firago <[email protected]>
---
drivers/clk/clk-versaclock5.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c
index 9432122..733b402 100644
--- a/drivers/clk/clk-versaclock5.c
+++ b/drivers/clk/clk-versaclock5.c
@@ -294,7 +294,7 @@ static unsigned long vc5_dbl_round_rate(struct clk_hw *hw, unsigned long rate,
if ((*parent_rate == rate) || ((*parent_rate * 2) == rate))
return rate;
else
- return -EINVAL;
+ return 0;
}
static int vc5_dbl_set_rate(struct clk_hw *hw, unsigned long rate,
--
2.7.4
vtwm_pll_round_rate() returns an unsigned long. This patch changes the
internal holder variable from signed to unsigned long for the sake of
completeness and neatness.
Signed-off-by: Bryan O'Donoghue <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: Tony Prisk <[email protected]>
---
drivers/clk/clk-vt8500.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c
index 750c087..a4aa0bf 100644
--- a/drivers/clk/clk-vt8500.c
+++ b/drivers/clk/clk-vt8500.c
@@ -609,7 +609,7 @@ static unsigned long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate,
{
struct clk_pll *pll = to_clk_pll(hw);
u32 filter, mul, div1, div2;
- long round_rate;
+ unsigned long round_rate;
int ret = 1;
switch (pll->type) {
--
2.7.4
This patch updates the round_rate() logic here to return zero instead of a
negative number on error.
In conjunction with higher-level changes associated with acting on the
return value of clk_ops->round_rate() it is then possible to have
clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of
the current limitation of 1 Hz to LONG_MAX Hz.
Signed-off-by: Bryan O'Donoghue <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Joachim Eastwood <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
drivers/clk/nxp/clk-lpc18xx-cgu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/nxp/clk-lpc18xx-cgu.c b/drivers/clk/nxp/clk-lpc18xx-cgu.c
index e08bad9..396d4f7 100644
--- a/drivers/clk/nxp/clk-lpc18xx-cgu.c
+++ b/drivers/clk/nxp/clk-lpc18xx-cgu.c
@@ -381,13 +381,13 @@ static unsigned long lpc18xx_pll0_round_rate(struct clk_hw *hw,
if (*prate < rate) {
pr_warn("%s: pll dividers not supported\n", __func__);
- return -EINVAL;
+ return 0;
}
m = DIV_ROUND_UP_ULL(*prate, rate * 2);
if (m <= 0 && m > LPC18XX_PLL0_MSEL_MAX) {
pr_warn("%s: unable to support rate %lu\n", __func__, rate);
- return -EINVAL;
+ return 0;
}
return 2 * *prate * m;
--
2.7.4
This patch updates the round_rate() logic here to return zero instead of a
negative number on error.
In conjunction with higher-level changes associated with acting on the
return value of clk_ops->round_rate() it is then possible to have
clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of
the current limitation of 1 Hz to LONG_MAX Hz.
Signed-off-by: Bryan O'Donoghue <[email protected]>
Cc: Peter De Schrijver <[email protected]>
Cc: Prashant Gaikwad <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Thierry Reding <[email protected]>
Cc: Jonathan Hunter <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
drivers/clk/tegra/clk-bpmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-bpmp.c b/drivers/clk/tegra/clk-bpmp.c
index 0c1197b..4297bb2 100644
--- a/drivers/clk/tegra/clk-bpmp.c
+++ b/drivers/clk/tegra/clk-bpmp.c
@@ -190,7 +190,7 @@ static unsigned long tegra_bpmp_clk_round_rate(struct clk_hw *hw,
err = tegra_bpmp_clk_transfer(clk->bpmp, &msg);
if (err < 0)
- return err;
+ return 0;
return response.rate;
}
--
2.7.4
This patch updates the round_rate() logic here to return zero instead of a
negative number on error.
In conjunction with higher-level changes associated with acting on the
return value of clk_ops->round_rate() it is then possible to have
clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of
the current limitation of 1 Hz to LONG_MAX Hz.
Signed-off-by: Bryan O'Donoghue <[email protected]>
Cc: Eugeniy Paltsev <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Cc: [email protected]
---
drivers/clk/clk-hsdk-pll.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c
index 62c8e18..7bff5e3 100644
--- a/drivers/clk/clk-hsdk-pll.c
+++ b/drivers/clk/clk-hsdk-pll.c
@@ -201,7 +201,7 @@ static unsigned long hsdk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
const struct hsdk_pll_cfg *pll_cfg = clk->pll_devdata->pll_cfg;
if (pll_cfg[0].rate == 0)
- return -EINVAL;
+ return 0;
best_rate = pll_cfg[0].rate;
--
2.7.4
This patch updates the round_rate() logic here to return zero instead of a
negative number on error.
In conjunction with higher-level changes associated with acting on the
return value of clk_ops->round_rate() it is then possible to have
clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of
the current limitation of 1 Hz to LONG_MAX Hz.
Signed-off-by: Bryan O'Donoghue <[email protected]>
Cc: Boris Brezillon <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Quentin Schulz <[email protected]>
Cc: [email protected]
Cc: [email protected]
---
drivers/clk/at91/clk-audio-pll.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/at91/clk-audio-pll.c b/drivers/clk/at91/clk-audio-pll.c
index 56227cb..48231e3 100644
--- a/drivers/clk/at91/clk-audio-pll.c
+++ b/drivers/clk/at91/clk-audio-pll.c
@@ -278,7 +278,7 @@ static unsigned long clk_audio_pll_pad_round_rate(struct clk_hw *hw,
unsigned long *parent_rate)
{
struct clk_hw *pclk = clk_hw_get_parent(hw);
- long best_rate = -EINVAL;
+ unsigned long best_rate = 0;
unsigned long best_parent_rate;
unsigned long tmp_qd;
u32 div;
@@ -330,7 +330,7 @@ static unsigned long clk_audio_pll_pmc_round_rate(struct clk_hw *hw,
unsigned long *parent_rate)
{
struct clk_hw *pclk = clk_hw_get_parent(hw);
- long best_rate = -EINVAL;
+ unsigned long best_rate = 0;
unsigned long best_parent_rate = 0;
u32 tmp_qd = 0, div;
long tmp_rate;
--
2.7.4
This patch updates the round_rate() logic here to return zero instead of a
negative number on error.
In conjunction with higher-level changes associated with acting on the
return value of clk_ops->round_rate() it is then possible to have
clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of
the current limitation of 1 Hz to LONG_MAX Hz.
Signed-off-by: Bryan O'Donoghue <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Vladimir Zapolskiy <[email protected]>
Cc: Sylvain Lemieux <[email protected]>
Cc: Gabriel Fernandez <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
drivers/clk/nxp/clk-lpc32xx.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/nxp/clk-lpc32xx.c b/drivers/clk/nxp/clk-lpc32xx.c
index 76c17f4..0e0d258 100644
--- a/drivers/clk/nxp/clk-lpc32xx.c
+++ b/drivers/clk/nxp/clk-lpc32xx.c
@@ -664,17 +664,17 @@ static unsigned long clk_usb_pll_round_rate(struct clk_hw *hw,
* USB divider, USB PLL N and M parameters.
*/
if (rate != 48000000)
- return -EINVAL;
+ return 0;
/* USB divider clock */
usb_div_hw = clk_hw_get_parent_by_index(hw, 0);
if (!usb_div_hw)
- return -EINVAL;
+ return 0;
/* Main oscillator clock */
osc_hw = clk_hw_get_parent_by_index(usb_div_hw, 0);
if (!osc_hw)
- return -EINVAL;
+ return 0;
o = clk_hw_get_rate(osc_hw); /* must be in range 1..20 MHz */
/* Check if valid USB divider and USB PLL parameters exists */
@@ -697,7 +697,7 @@ static unsigned long clk_usb_pll_round_rate(struct clk_hw *hw,
}
}
- return -EINVAL;
+ return 0;
}
#define LPC32XX_DEFINE_PLL_OPS(_name, _rc, _sr, _rr) \
--
2.7.4
Change the handling of clk_ops->round_rate() return values such that only
zero is treated as an error. All implementations of clk_ops->round_rate()
will have previously been updated to match this change.
Using zero as the determinant for an error means its possible to pass an
unsigned long as req->rate to a clk_ops->round_rate() function and return a
rounded clock which is as high as the original req->rate. This allows us on
32 bit systems to return rounded rates of (2^32)-1 Hz or ULONG_MAX Hz -
whereas without this change and the associated clk_ops->round_rate() change
the maximum value that can be returned via clk_ops->round_rate() is
LONG_MAX Hz - after which a higher-frequency clock looks like a negative
error code - due to sign extension.
Signed-off-by: Bryan O'Donoghue <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Cc: [email protected]
---
drivers/clk/clk.c | 15 +++------------
1 file changed, 3 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 8a1860a..6af2ece 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -909,7 +909,6 @@ static int clk_core_round_rate_nolock(struct clk_core *core,
struct clk_rate_request *req)
{
struct clk_core *parent;
- long rate;
lockdep_assert_held(&prepare_lock);
@@ -928,12 +927,8 @@ static int clk_core_round_rate_nolock(struct clk_core *core,
if (core->ops->determine_rate) {
return core->ops->determine_rate(core->hw, req);
} else if (core->ops->round_rate) {
- rate = core->ops->round_rate(core->hw, req->rate,
+ req->rate = core->ops->round_rate(core->hw, req->rate,
&req->best_parent_rate);
- if (rate < 0)
- return rate;
-
- req->rate = rate;
} else if (core->flags & CLK_SET_RATE_PARENT) {
return clk_core_round_rate_nolock(parent, req);
} else {
@@ -1454,12 +1449,8 @@ static struct clk_core *clk_calc_new_rates(struct clk_core *core,
new_rate = req.rate;
parent = req.best_parent_hw ? req.best_parent_hw->core : NULL;
} else if (core->ops->round_rate) {
- ret = core->ops->round_rate(core->hw, rate,
- &best_parent_rate);
- if (ret < 0)
- return NULL;
-
- new_rate = ret;
+ new_rate = core->ops->round_rate(core->hw, rate,
+ &best_parent_rate);
if (new_rate < min_rate || new_rate > max_rate)
return NULL;
} else if (!parent || !(core->flags & CLK_SET_RATE_PARENT)) {
--
2.7.4
This patch updates the round_rate() logic here to return zero instead of a
negative number on error.
In conjunction with higher-level changes associated with acting on the
return value of clk_ops->round_rate() it is then possible to have
clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of
the current limitation of 1 Hz to LONG_MAX Hz.
Signed-off-by: Bryan O'Donoghue <[email protected]>
Cc: Eugeniy Paltsev <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Cc: [email protected]
---
drivers/clk/axs10x/pll_clock.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/axs10x/pll_clock.c b/drivers/clk/axs10x/pll_clock.c
index 27498eb..e90ae9e 100644
--- a/drivers/clk/axs10x/pll_clock.c
+++ b/drivers/clk/axs10x/pll_clock.c
@@ -162,7 +162,7 @@ static unsigned long axs10x_pll_round_rate(struct clk_hw *hw,
const struct axs10x_pll_cfg *pll_cfg = clk->pll_cfg;
if (pll_cfg[0].rate == 0)
- return -EINVAL;
+ return 0;
best_rate = pll_cfg[0].rate;
--
2.7.4
This patch updates the round_rate() logic here to return zero instead of a
negative number on error.
In conjunction with higher-level changes associated with acting on the
return value of clk_ops->round_rate() it is then possible to have
clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of
the current limitation of 1 Hz to LONG_MAX Hz.
Signed-off-by: Bryan O'Donoghue <[email protected]>
Cc: Peter De Schrijver <[email protected]>
Cc: Prashant Gaikwad <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Thierry Reding <[email protected]>
Cc: Jonathan Hunter <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: Rhyland Klein <[email protected]>
Cc: Bill Huang <[email protected]>
---
drivers/clk/tegra/clk-pll.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index b4a7d30..0a3edb0 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -839,7 +839,7 @@ static unsigned long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
if (_get_table_rate(hw, &cfg, rate, *prate) &&
pll->params->calc_rate(hw, &cfg, rate, *prate))
- return -EINVAL;
+ return 0;
return cfg.output_rate;
}
--
2.7.4
This patch updates the round_rate() logic here to return zero instead of a
negative number on error.
In conjunction with higher-level changes associated with acting on the
return value of clk_ops->round_rate() it is then possible to have
clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of
the current limitation of 1 Hz to LONG_MAX Hz.
Signed-off-by: Bryan O'Donoghue <[email protected]>
Cc: Tero Kristo <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
drivers/clk/ti/composite.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c
index 2477cf1..0e82b61 100644
--- a/drivers/clk/ti/composite.c
+++ b/drivers/clk/ti/composite.c
@@ -38,7 +38,7 @@ static unsigned long ti_composite_round_rate(struct clk_hw *hw,
unsigned long rate,
unsigned long *prate)
{
- return -EINVAL;
+ return 0;
}
static int ti_composite_set_rate(struct clk_hw *hw, unsigned long rate,
--
2.7.4
This patch updates the round_rate() logic here to return zero instead of a
negative number on error.
In conjunction with higher-level changes associated with acting on the
return value of clk_ops->round_rate() it is then possible to have
clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of
the current limitation of 1 Hz to LONG_MAX Hz.
Signed-off-by: Bryan O'Donoghue <[email protected]>
Cc: Tero Kristo <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Tony Lindgren <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
drivers/clk/ti/fapll.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c
index 2e74437..f435a8c 100644
--- a/drivers/clk/ti/fapll.c
+++ b/drivers/clk/ti/fapll.c
@@ -227,12 +227,12 @@ static unsigned long ti_fapll_round_rate(struct clk_hw *hw, unsigned long rate,
int error;
if (!rate)
- return -EINVAL;
+ return 0;
error = ti_fapll_set_div_mult(rate, *parent_rate,
&pre_div_p, &mult_n);
if (error)
- return error;
+ return 0;
rate = *parent_rate / pre_div_p;
rate *= mult_n;
@@ -414,7 +414,7 @@ static unsigned long ti_fapll_synth_round_rate(struct clk_hw *hw,
unsigned long r;
if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate)
- return -EINVAL;
+ return 0;
/* Only post divider m available with no fractional divider? */
if (!synth->freq) {
--
2.7.4
This patch updates the round_rate() logic here to return zero instead of a
negative number on error.
In conjunction with higher-level changes associated with acting on the
return value of clk_ops->round_rate() it is then possible to have
clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of
the current limitation of 1 Hz to LONG_MAX Hz.
Signed-off-by: Bryan O'Donoghue <[email protected]>
Cc: Jun Nie <[email protected]>
Cc: Baoyou Xie <[email protected]>
Cc: Shawn Guo <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
drivers/clk/zte/clk.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/zte/clk.c b/drivers/clk/zte/clk.c
index df91842..6afdc4a 100644
--- a/drivers/clk/zte/clk.c
+++ b/drivers/clk/zte/clk.c
@@ -247,7 +247,7 @@ static unsigned long zx_audio_round_rate(struct clk_hw *hw, unsigned long rate,
u32 reg;
if (rate * 2 > *prate)
- return -EINVAL;
+ return 0;
reg = calc_reg(*prate, rate);
return calc_rate(reg, *prate);
--
2.7.4
This patch updates the round_rate() logic here to return zero instead of a
negative number on error.
In conjunction with higher-level changes associated with acting on the
return value of clk_ops->round_rate() it is then possible to have
clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of
the current limitation of 1 Hz to LONG_MAX Hz.
Signed-off-by: Bryan O'Donoghue <[email protected]>
Cc: Peter De Schrijver <[email protected]>
Cc: Prashant Gaikwad <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Thierry Reding <[email protected]>
Cc: Jonathan Hunter <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
drivers/clk/tegra/clk-audio-sync.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-audio-sync.c b/drivers/clk/tegra/clk-audio-sync.c
index 9784d58..5fd825b 100644
--- a/drivers/clk/tegra/clk-audio-sync.c
+++ b/drivers/clk/tegra/clk-audio-sync.c
@@ -35,7 +35,7 @@ static unsigned long clk_sync_source_round_rate(struct clk_hw *hw,
struct tegra_clk_sync_source *sync = to_clk_sync_source(hw);
if (rate > sync->max_rate)
- return -EINVAL;
+ return 0;
else
return rate;
}
--
2.7.4
Due to the old function signature of clk_ops->round_rate
pll_clk_round_rate does a cast of an internal unsigned long
to a long. After updating clk_ops->round_rate() to be an unsigned long
though the cast isn't necessary. Remove the cast now.
Signed-off-by: Bryan O'Donoghue <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Barry Song <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: Barry Song <[email protected]>
---
drivers/clk/sirf/clk-common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sirf/clk-common.c b/drivers/clk/sirf/clk-common.c
index 3ce6741..bfa3f4b 100644
--- a/drivers/clk/sirf/clk-common.c
+++ b/drivers/clk/sirf/clk-common.c
@@ -121,7 +121,7 @@ static unsigned long pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
dividend = (u64)fin * nf;
do_div(dividend, nr * od);
- return (long)dividend;
+ return dividend;
}
static int pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
--
2.7.4
This patch updates the round_rate() logic here to return zero instead of a
negative number on error.
In conjunction with higher-level changes associated with acting on the
return value of clk_ops->round_rate() it is then possible to have
clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of
the current limitation of 1 Hz to LONG_MAX Hz.
Signed-off-by: Bryan O'Donoghue <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Vladimir Zapolskiy <[email protected]>
Cc: Sylvain Lemieux <[email protected]>
Cc: Gabriel Fernandez <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
drivers/clk/nxp/clk-lpc32xx.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/nxp/clk-lpc32xx.c b/drivers/clk/nxp/clk-lpc32xx.c
index 81ab57d..76c17f4 100644
--- a/drivers/clk/nxp/clk-lpc32xx.c
+++ b/drivers/clk/nxp/clk-lpc32xx.c
@@ -595,7 +595,7 @@ static unsigned long clk_hclk_pll_round_rate(struct clk_hw *hw,
pr_debug("%s: %lu/%lu\n", clk_hw_get_name(hw), *parent_rate, rate);
if (rate > 266500000)
- return -EINVAL;
+ return 0;
/* Have to check all 20 possibilities to find the minimal M */
for (p_i = 4; p_i >= 0; p_i--) {
@@ -622,7 +622,7 @@ static unsigned long clk_hclk_pll_round_rate(struct clk_hw *hw,
if (d == (u64)rate << 6) {
pr_err("%s: %lu: no valid PLL parameters are found\n",
clk_hw_get_name(hw), rate);
- return -EINVAL;
+ return 0;
}
clk->m_div = m;
--
2.7.4
This patch updates the round_rate() logic here to return zero instead of a
negative number on error.
In conjunction with higher-level changes associated with acting on the
return value of clk_ops->round_rate() it is then possible to have
clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of
the current limitation of 1 Hz to LONG_MAX Hz.
Signed-off-by: Bryan O'Donoghue <[email protected]>
Cc: Andy Gross <[email protected]>
Cc: David Brown <[email protected]>
Cc: Abhishek Sahu <[email protected]>
Cc: Varadarajan Narayanan <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
drivers/clk/qcom/gcc-ipq4019.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index 804231b..943acbc 100644
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -1268,7 +1268,7 @@ static unsigned long clk_cpu_div_round_rate(struct clk_hw *hw,
f = qcom_find_freq(pll->freq_tbl, rate);
if (!f)
- return -EINVAL;
+ return 0;
p_hw = clk_hw_get_parent_by_index(hw, f->src);
*p_rate = clk_hw_get_rate(p_hw);
--
2.7.4
This patch updates the round_rate() logic here to return zero instead of a
negative number on error.
In conjunction with higher-level changes associated with acting on the
return value of clk_ops->round_rate() it is then possible to have
clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of
the current limitation of 1 Hz to LONG_MAX Hz.
Signed-off-by: Bryan O'Donoghue <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: Shawn Guo <[email protected]>
---
drivers/clk/mxs/clk-frac.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/mxs/clk-frac.c b/drivers/clk/mxs/clk-frac.c
index f57281f..9debf86 100644
--- a/drivers/clk/mxs/clk-frac.c
+++ b/drivers/clk/mxs/clk-frac.c
@@ -59,7 +59,7 @@ static unsigned long clk_frac_round_rate(struct clk_hw *hw, unsigned long rate,
u64 tmp, tmp_rate, result;
if (rate > parent_rate)
- return -EINVAL;
+ return 0;
tmp = rate;
tmp <<= frac->width;
@@ -67,7 +67,7 @@ static unsigned long clk_frac_round_rate(struct clk_hw *hw, unsigned long rate,
div = tmp;
if (!div)
- return -EINVAL;
+ return 0;
tmp_rate = (u64)parent_rate * div;
result = tmp_rate >> frac->width;
--
2.7.4
This patch updates the round_rate() logic here to return zero instead of a
negative number on error.
In conjunction with higher-level changes associated with acting on the
return value of clk_ops->round_rate() it is then possible to have
clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of
the current limitation of 1 Hz to LONG_MAX Hz.
Signed-off-by: Bryan O'Donoghue <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: Russell King <[email protected]>
---
drivers/clk/mvebu/dove-divider.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/mvebu/dove-divider.c b/drivers/clk/mvebu/dove-divider.c
index 234ba0a..7704b5e 100644
--- a/drivers/clk/mvebu/dove-divider.c
+++ b/drivers/clk/mvebu/dove-divider.c
@@ -117,7 +117,7 @@ static unsigned long dove_round_rate(struct clk_hw *hw, unsigned long rate,
divider = dove_calc_divider(dc, rate, parent_rate, false);
if (divider < 0)
- return divider;
+ return 0;
rate = DIV_ROUND_CLOSEST(parent_rate, divider);
--
2.7.4
This patch updates the round_rate() logic here to return zero instead of a
negative number on error.
In conjunction with higher-level changes associated with acting on the
return value of clk_ops->round_rate() it is then possible to have
clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of
the current limitation of 1 Hz to LONG_MAX Hz.
Signed-off-by: Bryan O'Donoghue <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: Tony Prisk <[email protected]>
---
drivers/clk/clk-vt8500.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c
index 43c88f6..750c087 100644
--- a/drivers/clk/clk-vt8500.c
+++ b/drivers/clk/clk-vt8500.c
@@ -610,7 +610,7 @@ static unsigned long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate,
struct clk_pll *pll = to_clk_pll(hw);
u32 filter, mul, div1, div2;
long round_rate;
- int ret;
+ int ret = 1;
switch (pll->type) {
case PLL_TYPE_VT8500:
@@ -634,11 +634,11 @@ static unsigned long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate,
round_rate = WM8850_BITS_TO_FREQ(*prate, mul, div1, div2);
break;
default:
- ret = -EINVAL;
+ break;
}
if (ret)
- return ret;
+ return 0;
return round_rate;
}
--
2.7.4