2019-04-22 09:24:03

by Andy Tang

Subject: [PATCH 1/2] dt-bindings: qoriq-clock: add more PLL divider clocks support

From: Yuantian Tang <[email protected]>

More PLL divider clocks are needed by clock consumer IP. So update
the PLL divider description to make it more general.

Signed-off-by: Yuantian Tang <[email protected]>
---
.../devicetree/bindings/clock/qoriq-clock.txt | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index c655f28..27aeed0 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -83,8 +83,8 @@ second cell is the clock index for the specified type.
1 cmux index (n in CLKCnCSR)
2 hwaccel index (n in CLKCGnHWACSR)
3 fman 0 for fm1, 1 for fm2
- 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
- 4=pll/5, 5=pll/6, 6=pll/7, 7=pll/8
+ 4 platform pll n=pll/(n+1). For example, when n=1,
+ that means output_freq=PLL_freq/2.
5 coreclk must be 0

3. Example
--
1.7.1

2019-04-22 09:49:49

by Andy Tang

Subject: [PATCH 2/2] clk: qoriq: add more PLL divider clocks support

From: Yuantian Tang <[email protected]>

More PLL divider clocks are needed by clock consumer IP. So enlarge
the PLL divider array to accommodate more divider clocks.

Signed-off-by: Yuantian Tang <[email protected]>
---
drivers/clk/clk-qoriq.c | 5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 1212a9b..5e2b3ac 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -34,6 +34,7 @@
#define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
#define CGB_PLL1 4
#define CGB_PLL2 5
+#define MAX_PLL_DIV 16

struct clockgen_pll_div {
struct clk *clk;
@@ -41,7 +42,7 @@ struct clockgen_pll_div {
};

struct clockgen_pll {
- struct clockgen_pll_div div[8];
+ struct clockgen_pll_div div[MAX_PLL_DIV];
};

#define CLKSEL_VALID 1
@@ -1128,7 +1129,7 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
int ret;

/*
- * For platform PLL, there are 8 divider clocks.
+ * For platform PLL, there are MAX_PLL_DIV divider clocks.
* For core PLL, there are 4 divider clocks at most.
*/
if (idx != PLATFORM_PLL && i >= 4)
--
1.7.1

2019-04-25 18:58:45

by Stephen Boyd

Subject: Re: [PATCH 1/2] dt-bindings: qoriq-clock: add more PLL divider clocks support

Quoting [email protected] (2019-04-22 02:15:08)
> From: Yuantian Tang <[email protected]>
>
> More PLL divider clocks are needed by clock consumer IP. So update
> the PLL divider description to make it more general.
>
> Signed-off-by: Yuantian Tang <[email protected]>
> ---

Applied to clk-next

2019-04-25 18:59:17

by Stephen Boyd

Subject: Re: [PATCH 2/2] clk: qoriq: add more PLL divider clocks support

Quoting [email protected] (2019-04-22 02:15:09)
> From: Yuantian Tang <[email protected]>
>
> More PLL divider clocks are needed by clock consumer IP. So enlarge
> the PLL divider array to accommodate more divider clocks.
>
> Signed-off-by: Yuantian Tang <[email protected]>
> ---

Applied to clk-next