ZynqMP clock driver can be used for Versal platform also. Add support
for Versal platform in ZynqMP clock driver.
Also this patch series fixes divider calculation, fractional clock
check and adds support for get maximum divider, clock with
CLK_DIVIDER_POWER_OF_TWO flag and warn user if clock users are more
than allowed.
Rajan Vaja (6):
dt-bindings: clock: Add bindings for versal clock driver
clk: zynqmp: Extend driver for versal
clk: zynqmp: Warn user if clock user are more than allowed
clk: zynqmp: Add support for get max divider
clk: zynqmp: Fix divider calculation
clk: zynqmp: Fix fractional clock check
Tejas Patel (1):
clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag
.../devicetree/bindings/clock/xlnx,versal-clk.yaml | 67 +++++++++++
drivers/clk/zynqmp/clk-zynqmp.h | 1 +
drivers/clk/zynqmp/clkc.c | 7 +-
drivers/clk/zynqmp/divider.c | 108 ++++++++++++++++--
drivers/clk/zynqmp/pll.c | 9 +-
drivers/firmware/xilinx/zynqmp.c | 2 +
include/dt-bindings/clock/xlnx-versal-clk.h | 123 +++++++++++++++++++++
include/linux/firmware/xlnx-zynqmp.h | 2 +
8 files changed, 306 insertions(+), 13 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
create mode 100644 include/dt-bindings/clock/xlnx-versal-clk.h
--
2.7.4
Add documentation to describe Xilinx Versal clock driver
bindings.
Signed-off-by: Rajan Vaja <[email protected]>
---
.../devicetree/bindings/clock/xlnx,versal-clk.yaml | 67 +++++++++++
include/dt-bindings/clock/xlnx-versal-clk.h | 123 +++++++++++++++++++++
2 files changed, 190 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
create mode 100644 include/dt-bindings/clock/xlnx-versal-clk.h
diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
new file mode 100644
index 0000000..da82f6a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/clock/xlnx,versal-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Versal clock controller
+
+maintainers:
+ - Michal Simek <[email protected]>
+ - Jolly Shah <[email protected]>
+ - Rajan Vaja <[email protected]>
+
+description: |
+ The clock controller is a h/w block of Xilinx versal clock tree. It reads
+ required input clock frequencies from the devicetree and acts as clock
+ provider for all clock consumers of PS clocks. See clock_bindings.txt
+ for more information on the generic clock bindings.
+
+properties:
+ compatible:
+ const: xlnx,versal-clk
+
+ "#clock-cells":
+ const: 1
+
+ clocks:
+ description: List of clock specifiers which are external input
+ clocks to the given clock controller.
+ minItems: 3
+ maxItems: 3
+ items:
+ - description: ref clk
+ - description: alternate ref clk
+ - description: pl alternate ref clk
+
+ clock-names:
+ minItems: 3
+ maxItems: 3
+ items:
+ - const: ref_clk
+ - const: alt_ref_clk
+ - const: pl_alt_ref_clk
+
+required:
+ - compatible
+ - "#clock-cells"
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ method = "smc";
+ versal_clk: clock-controller {
+ #clock-cells = <1>;
+ compatible = "xlnx,versal-clk";
+ clocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>;
+ clock-names = "ref_clk", "alt_ref_clk", "pl_alt_ref_clk";
+ };
+ };
+ };
+...
diff --git a/include/dt-bindings/clock/xlnx-versal-clk.h b/include/dt-bindings/clock/xlnx-versal-clk.h
new file mode 100644
index 0000000..264d634
--- /dev/null
+++ b/include/dt-bindings/clock/xlnx-versal-clk.h
@@ -0,0 +1,123 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 Xilinx Inc.
+ *
+ */
+
+#ifndef _DT_BINDINGS_CLK_VERSAL_H
+#define _DT_BINDINGS_CLK_VERSAL_H
+
+#define PMC_PLL 1
+#define APU_PLL 2
+#define RPU_PLL 3
+#define CPM_PLL 4
+#define NOC_PLL 5
+#define PLL_MAX 6
+#define PMC_PRESRC 7
+#define PMC_POSTCLK 8
+#define PMC_PLL_OUT 9
+#define PPLL 10
+#define NOC_PRESRC 11
+#define NOC_POSTCLK 12
+#define NOC_PLL_OUT 13
+#define NPLL 14
+#define APU_PRESRC 15
+#define APU_POSTCLK 16
+#define APU_PLL_OUT 17
+#define APLL 18
+#define RPU_PRESRC 19
+#define RPU_POSTCLK 20
+#define RPU_PLL_OUT 21
+#define RPLL 22
+#define CPM_PRESRC 23
+#define CPM_POSTCLK 24
+#define CPM_PLL_OUT 25
+#define CPLL 26
+#define PPLL_TO_XPD 27
+#define NPLL_TO_XPD 28
+#define APLL_TO_XPD 29
+#define RPLL_TO_XPD 30
+#define EFUSE_REF 31
+#define SYSMON_REF 32
+#define IRO_SUSPEND_REF 33
+#define USB_SUSPEND 34
+#define SWITCH_TIMEOUT 35
+#define RCLK_PMC 36
+#define RCLK_LPD 37
+#define WDT 38
+#define TTC0 39
+#define TTC1 40
+#define TTC2 41
+#define TTC3 42
+#define GEM_TSU 43
+#define GEM_TSU_LB 44
+#define MUXED_IRO_DIV2 45
+#define MUXED_IRO_DIV4 46
+#define PSM_REF 47
+#define GEM0_RX 48
+#define GEM0_TX 49
+#define GEM1_RX 50
+#define GEM1_TX 51
+#define CPM_CORE_REF 52
+#define CPM_LSBUS_REF 53
+#define CPM_DBG_REF 54
+#define CPM_AUX0_REF 55
+#define CPM_AUX1_REF 56
+#define QSPI_REF 57
+#define OSPI_REF 58
+#define SDIO0_REF 59
+#define SDIO1_REF 60
+#define PMC_LSBUS_REF 61
+#define I2C_REF 62
+#define TEST_PATTERN_REF 63
+#define DFT_OSC_REF 64
+#define PMC_PL0_REF 65
+#define PMC_PL1_REF 66
+#define PMC_PL2_REF 67
+#define PMC_PL3_REF 68
+#define CFU_REF 69
+#define SPARE_REF 70
+#define NPI_REF 71
+#define HSM0_REF 72
+#define HSM1_REF 73
+#define SD_DLL_REF 74
+#define FPD_TOP_SWITCH 75
+#define FPD_LSBUS 76
+#define ACPU 77
+#define DBG_TRACE 78
+#define DBG_FPD 79
+#define LPD_TOP_SWITCH 80
+#define ADMA 81
+#define LPD_LSBUS 82
+#define CPU_R5 83
+#define CPU_R5_CORE 84
+#define CPU_R5_OCM 85
+#define CPU_R5_OCM2 86
+#define IOU_SWITCH 87
+#define GEM0_REF 88
+#define GEM1_REF 89
+#define GEM_TSU_REF 90
+#define USB0_BUS_REF 91
+#define UART0_REF 92
+#define UART1_REF 93
+#define SPI0_REF 94
+#define SPI1_REF 95
+#define CAN0_REF 96
+#define CAN1_REF 97
+#define I2C0_REF 98
+#define I2C1_REF 99
+#define DBG_LPD 100
+#define TIMESTAMP_REF 101
+#define DBG_TSTMP 102
+#define CPM_TOPSW_REF 103
+#define USB3_DUAL_REF 104
+#define OUTCLK_MAX 105
+#define REF_CLK 106
+#define PL_ALT_REF_CLK 107
+#define MUXED_IRO 108
+#define PL_EXT 109
+#define PL_LB 110
+#define MIO_50_OR_51 111
+#define MIO_24_OR_25 112
+
+#endif
--
2.7.4
From: Tejas Patel <[email protected]>
Existing clock divider functions is not checking for
base of divider. So, if any clock divider is power of 2
then clock rate calculation will be wrong.
Add support to calculate divider value for the clocks
with CLK_DIVIDER_POWER_OF_TWO flag.
Signed-off-by: Tejas Patel <[email protected]>
Signed-off-by: Radhey Shyam Pandey <[email protected]>
Signed-off-by: Rajan Vaja <[email protected]>
---
drivers/clk/zynqmp/divider.c | 36 +++++++++++++++++++++++++++++++-----
1 file changed, 31 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
index b564696..67aa88c 100644
--- a/drivers/clk/zynqmp/divider.c
+++ b/drivers/clk/zynqmp/divider.c
@@ -2,7 +2,7 @@
/*
* Zynq UltraScale+ MPSoC Divider support
*
- * Copyright (C) 2016-2018 Xilinx
+ * Copyright (C) 2016-2019 Xilinx
*
* Adjustable divider clock implementation
*/
@@ -45,9 +45,26 @@ struct zynqmp_clk_divider {
};
static inline int zynqmp_divider_get_val(unsigned long parent_rate,
- unsigned long rate)
+ unsigned long rate, u16 flags)
{
- return DIV_ROUND_CLOSEST(parent_rate, rate);
+ int up, down;
+ unsigned long up_rate, down_rate;
+
+ if (flags & CLK_DIVIDER_POWER_OF_TWO) {
+ up = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+ down = DIV_ROUND_DOWN_ULL((u64)parent_rate, rate);
+
+ up = __roundup_pow_of_two(up);
+ down = __rounddown_pow_of_two(down);
+
+ up_rate = DIV_ROUND_UP_ULL((u64)parent_rate, up);
+ down_rate = DIV_ROUND_UP_ULL((u64)parent_rate, down);
+
+ return (rate - up_rate) <= (down_rate - rate) ? up : down;
+
+ } else {
+ return DIV_ROUND_CLOSEST(parent_rate, rate);
+ }
}
/**
@@ -79,6 +96,9 @@ static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw,
else
value = div >> 16;
+ if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
+ value = 1 << value;
+
if (!value) {
WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
@@ -157,10 +177,13 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw,
else
bestdiv = bestdiv >> 16;
+ if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
+ bestdiv = 1 << bestdiv;
+
return DIV_ROUND_UP_ULL((u64)*prate, bestdiv);
}
- bestdiv = zynqmp_divider_get_val(*prate, rate);
+ bestdiv = zynqmp_divider_get_val(*prate, rate, divider->flags);
/*
* In case of two divisors, compute best divider values and return
@@ -198,7 +221,7 @@ static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
int ret;
const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
- value = zynqmp_divider_get_val(parent_rate, rate);
+ value = zynqmp_divider_get_val(parent_rate, rate, divider->flags);
if (div_type == TYPE_DIV1) {
div = value & 0xFFFF;
div |= 0xffff << 16;
@@ -207,6 +230,9 @@ static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
div |= value << 16;
}
+ if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
+ div = __ffs(div);
+
ret = eemi_ops->clock_setdivider(clk_id, div);
if (ret)
--
2.7.4
Warn user if clock is used by more than allowed devices.
This check is done by firmware and returns respective
error code. Upon receiving error code for excessive user,
warn user for the same.
This change is done to restrict VPLL use count. It is
assumed that VPLL is used by one user only.
Signed-off-by: Michal Simek <[email protected]>
Signed-off-by: Rajan Vaja <[email protected]>
---
drivers/clk/zynqmp/pll.c | 9 ++++++---
drivers/firmware/xilinx/zynqmp.c | 2 ++
include/linux/firmware/xlnx-zynqmp.h | 1 +
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c
index a541397..2f4ccaa 100644
--- a/drivers/clk/zynqmp/pll.c
+++ b/drivers/clk/zynqmp/pll.c
@@ -188,9 +188,12 @@ static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate,
frac = (parent_rate * f) / FRAC_DIV;
ret = eemi_ops->clock_setdivider(clk_id, m);
- if (ret)
- pr_warn_once("%s() set divider failed for %s, ret = %d\n",
- __func__, clk_name, ret);
+ if (ret) {
+ if (ret == -EUSERS)
+ WARN(1, "More than allowed devices are using the %s, which is forbidden\n", clk_name);
+ pr_err("%s() set divider failed for %s, ret = %d\n",
+ __func__, clk_name, ret);
+ }
eemi_ops->ioctl(0, IOCTL_SET_PLL_FRAC_DATA, clk_id, f, NULL);
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 0137bf3..ecc339d 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -53,6 +53,8 @@ static int zynqmp_pm_ret_code(u32 ret_status)
return -EACCES;
case XST_PM_ABORT_SUSPEND:
return -ECANCELED;
+ case XST_PM_MULT_USER:
+ return -EUSERS;
case XST_PM_INTERNAL:
case XST_PM_CONFLICT:
case XST_PM_INVALID_NODE:
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 25bedd2..f019d1c 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -96,6 +96,7 @@ enum pm_ret_status {
XST_PM_INVALID_NODE,
XST_PM_DOUBLE_REQ,
XST_PM_ABORT_SUSPEND,
+ XST_PM_MULT_USER = 2008,
};
enum pm_ioctl_id {
--
2.7.4
Firmware driver sets BIT(4) to BIT(7) as custom type flags. To make
divider as fractional divider firmware sets BIT(4). So add support
for custom type flag and use BIT(4) of custom type flag as CLOCK_FRAC
bit.
Add a new field to the clock_topology to store custom type flags.
Signed-off-by: Rajan Vaja <[email protected]>
---
drivers/clk/zynqmp/clk-zynqmp.h | 1 +
drivers/clk/zynqmp/clkc.c | 4 ++++
drivers/clk/zynqmp/divider.c | 7 +++----
3 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqmp.h
index fec9a15..5beeb41 100644
--- a/drivers/clk/zynqmp/clk-zynqmp.h
+++ b/drivers/clk/zynqmp/clk-zynqmp.h
@@ -30,6 +30,7 @@ struct clock_topology {
u32 type;
u32 flag;
u32 type_flag;
+ u8 custom_type_flag;
};
struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c
index 10e89f2..4dd8413 100644
--- a/drivers/clk/zynqmp/clkc.c
+++ b/drivers/clk/zynqmp/clkc.c
@@ -84,6 +84,7 @@ struct name_resp {
struct topology_resp {
#define CLK_TOPOLOGY_TYPE GENMASK(3, 0)
+#define CLK_TOPOLOGY_CUSTOM_TYPE_FLAGS GENMASK(7, 4)
#define CLK_TOPOLOGY_FLAGS GENMASK(23, 8)
#define CLK_TOPOLOGY_TYPE_FLAGS GENMASK(31, 24)
u32 topology[CLK_GET_TOPOLOGY_RESP_WORDS];
@@ -396,6 +397,9 @@ static int __zynqmp_clock_get_topology(struct clock_topology *topology,
topology[*nnodes].type_flag =
FIELD_GET(CLK_TOPOLOGY_TYPE_FLAGS,
response->topology[i]);
+ topology[*nnodes].custom_type_flag =
+ FIELD_GET(CLK_TOPOLOGY_CUSTOM_TYPE_FLAGS,
+ response->topology[i]);
(*nnodes)++;
}
diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
index 67aa88c..e700504 100644
--- a/drivers/clk/zynqmp/divider.c
+++ b/drivers/clk/zynqmp/divider.c
@@ -25,7 +25,7 @@
#define to_zynqmp_clk_divider(_hw) \
container_of(_hw, struct zynqmp_clk_divider, hw)
-#define CLK_FRAC BIT(13) /* has a fractional parent */
+#define CLK_FRAC BIT(4) /* has a fractional parent */
/**
* struct zynqmp_clk_divider - adjustable divider clock
@@ -279,13 +279,12 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name,
init.name = name;
init.ops = &zynqmp_clk_divider_ops;
- /* CLK_FRAC is not defined in the common clk framework */
- init.flags = nodes->flag & ~CLK_FRAC;
+ init.flags = nodes->flag;
init.parent_names = parents;
init.num_parents = 1;
/* struct clk_divider assignments */
- div->is_frac = !!(nodes->flag & CLK_FRAC);
+ div->is_frac = !!(nodes->custom_type_flag & CLK_FRAC);
div->flags = nodes->type_flag;
div->hw.init = &init;
div->clk_id = clk_id;
--
2.7.4
zynqmp_clk_divider_round_rate() returns actual divider value
after calculating from parent rate and desired rate, even though
that rate is not supported by single divider of hardware. It is
also possible that such divisor value can be achieved through 2
different dividers. As, Linux tries to set such divisor value(out
of range) in single divider set divider is getting failed.
Fix the same by computing best possible combination of two
divisors which provides more accurate clock rate.
Signed-off-by: Michal Simek <[email protected]>
Signed-off-by: Tejas Patel <[email protected]>
Signed-off-by: Rajan Vaja <[email protected]>
---
drivers/clk/zynqmp/divider.c | 46 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
index b79cd45..b564696 100644
--- a/drivers/clk/zynqmp/divider.c
+++ b/drivers/clk/zynqmp/divider.c
@@ -89,6 +89,42 @@ static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw,
return DIV_ROUND_UP_ULL(parent_rate, value);
}
+static void zynqmp_get_divider2_val(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long parent_rate,
+ struct zynqmp_clk_divider *divider,
+ int *bestdiv)
+{
+ int div1;
+ int div2;
+ long error = LONG_MAX;
+ struct clk_hw *parent_hw = clk_hw_get_parent(hw);
+ struct zynqmp_clk_divider *pdivider = to_zynqmp_clk_divider(parent_hw);
+
+ if (!pdivider)
+ return;
+
+ *bestdiv = 1;
+ for (div1 = 1; div1 <= pdivider->max_div;) {
+ for (div2 = 1; div2 <= divider->max_div;) {
+ long new_error = ((parent_rate / div1) / div2) - rate;
+
+ if (abs(new_error) < abs(error)) {
+ *bestdiv = div2;
+ error = new_error;
+ }
+ if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
+ div2 = div2 << 1;
+ else
+ div2++;
+ }
+ if (pdivider->flags & CLK_DIVIDER_POWER_OF_TWO)
+ div1 = div1 << 1;
+ else
+ div1++;
+ }
+}
+
/**
* zynqmp_clk_divider_round_rate() - Round rate of divider clock
* @hw: handle between common and hardware-specific interfaces
@@ -126,6 +162,16 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw,
bestdiv = zynqmp_divider_get_val(*prate, rate);
+ /*
+ * In case of two divisors, compute best divider values and return
+ * divider2 value based on compute value. div1 will be automatically
+ * set to optimum based on required total divider value.
+ */
+ if (div_type == TYPE_DIV2 &&
+ (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
+ zynqmp_get_divider2_val(hw, rate, *prate, divider, &bestdiv);
+ }
+
if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac)
bestdiv = rate % *prate ? 1 : bestdiv;
*prate = rate * bestdiv;
--
2.7.4
To achieve best possible rate, maximum limit of divider is required
while computation. Get maximum supported divisor from firmware. To
maintain backward compatibility assign maximum possible value(0xFFFF)
if query for max divisor is not successful.
Signed-off-by: Rajan Vaja <[email protected]>
---
drivers/clk/zynqmp/divider.c | 19 +++++++++++++++++++
include/linux/firmware/xlnx-zynqmp.h | 1 +
2 files changed, 20 insertions(+)
diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
index d8f5b70d..b79cd45 100644
--- a/drivers/clk/zynqmp/divider.c
+++ b/drivers/clk/zynqmp/divider.c
@@ -41,6 +41,7 @@ struct zynqmp_clk_divider {
bool is_frac;
u32 clk_id;
u32 div_type;
+ u16 max_div;
};
static inline int zynqmp_divider_get_val(unsigned long parent_rate,
@@ -195,6 +196,9 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name,
struct clk_hw *hw;
struct clk_init_data init;
int ret;
+ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
+ struct zynqmp_pm_query_data qdata = {0};
+ u32 ret_payload[PAYLOAD_ARG_CNT];
/* allocate the divider */
div = kzalloc(sizeof(*div), GFP_KERNEL);
@@ -215,6 +219,21 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name,
div->clk_id = clk_id;
div->div_type = nodes->type;
+ /*
+ * To achieve best possible rate, maximum limit of divider is required
+ * while computation. Get maximum supported divisor from firmware. To
+ * maintain backward compatibility assign maximum possible value(0xFFFF)
+ * if query for max divisor is not successful.
+ */
+ qdata.qid = PM_QID_CLOCK_GET_MAX_DIVISOR;
+ qdata.arg1 = clk_id;
+ qdata.arg2 = nodes->type;
+ ret = eemi_ops->query_data(qdata, ret_payload);
+ if (ret)
+ div->max_div = U16_MAX;
+ else
+ div->max_div = ret_payload[1];
+
hw = &div->hw;
ret = clk_hw_register(NULL, hw);
if (ret) {
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index f019d1c..f0d4558 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -114,6 +114,7 @@ enum pm_query_id {
PM_QID_CLOCK_GET_PARENTS,
PM_QID_CLOCK_GET_ATTRIBUTES,
PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
+ PM_QID_CLOCK_GET_MAX_DIVISOR,
};
enum zynqmp_pm_reset_action {
--
2.7.4
Quoting Rajan Vaja (2019-11-12 05:16:14)
> diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
> new file mode 100644
> index 0000000..da82f6a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
> @@ -0,0 +1,67 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/bindings/clock/xlnx,versal-clk.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx Versal clock controller
> +
> +maintainers:
> + - Michal Simek <[email protected]>
> + - Jolly Shah <[email protected]>
> + - Rajan Vaja <[email protected]>
> +
> +description: |
> + The clock controller is a h/w block of Xilinx versal clock tree. It reads
hardware instead of h/w
> + required input clock frequencies from the devicetree and acts as clock
> + provider for all clock consumers of PS clocks. See clock_bindings.txt
> + for more information on the generic clock bindings.
Please drop this last sentence about clock_bindings.txt
> +
> +properties:
> + compatible:
> + const: xlnx,versal-clk
> +
> + "#clock-cells":
> + const: 1
> +
> + clocks:
> + description: List of clock specifiers which are external input
> + clocks to the given clock controller.
> + minItems: 3
> + maxItems: 3
> + items:
> + - description: ref clk
> + - description: alternate ref clk
> + - description: pl alternate ref clk
What is "pl"? Can you clarify?
> +
> + clock-names:
> + minItems: 3
> + maxItems: 3
> + items:
> + - const: ref_clk
> + - const: alt_ref_clk
> + - const: pl_alt_ref_clk
> +
> +required:
> + - compatible
> + - "#clock-cells"
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + firmware {
> + zynqmp_firmware: zynqmp-firmware {
> + compatible = "xlnx,zynqmp-firmware";
> + method = "smc";
Is there a way to say in the binding that this must be a child of a
xlnx,zynqmp-firmware node? That would be ideal so we can constrain this
to that location somehow.
> + versal_clk: clock-controller {
> + #clock-cells = <1>;
> + compatible = "xlnx,versal-clk";
> + clocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>;
> + clock-names = "ref_clk", "alt_ref_clk", "pl_alt_ref_clk";
> + };
> + };
> + };
> +...
On Tue, Nov 12, 2019 at 02:51:46PM -0800, Stephen Boyd wrote:
> Quoting Rajan Vaja (2019-11-12 05:16:14)
> > diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
> > new file mode 100644
> > index 0000000..da82f6a
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
> > @@ -0,0 +1,67 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/bindings/clock/xlnx,versal-clk.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Xilinx Versal clock controller
> > +
> > +maintainers:
> > + - Michal Simek <[email protected]>
> > + - Jolly Shah <[email protected]>
> > + - Rajan Vaja <[email protected]>
> > +
> > +description: |
> > + The clock controller is a h/w block of Xilinx versal clock tree. It reads
>
> hardware instead of h/w
>
> > + required input clock frequencies from the devicetree and acts as clock
> > + provider for all clock consumers of PS clocks. See clock_bindings.txt
> > + for more information on the generic clock bindings.
>
> Please drop this last sentence about clock_bindings.txt
>
> > +
> > +properties:
> > + compatible:
> > + const: xlnx,versal-clk
> > +
> > + "#clock-cells":
> > + const: 1
> > +
> > + clocks:
> > + description: List of clock specifiers which are external input
> > + clocks to the given clock controller.
> > + minItems: 3
> > + maxItems: 3
Can drop these. Implied by by 'items' list.
> > + items:
> > + - description: ref clk
> > + - description: alternate ref clk
> > + - description: pl alternate ref clk
>
> What is "pl"? Can you clarify?
>
> > +
> > + clock-names:
> > + minItems: 3
> > + maxItems: 3
Same here.
> > + items:
> > + - const: ref_clk
> > + - const: alt_ref_clk
> > + - const: pl_alt_ref_clk
'_clk' is redundant.
> > +
> > +required:
> > + - compatible
> > + - "#clock-cells"
> > + - clocks
> > + - clock-names
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + firmware {
> > + zynqmp_firmware: zynqmp-firmware {
> > + compatible = "xlnx,zynqmp-firmware";
> > + method = "smc";
>
> Is there a way to say in the binding that this must be a child of a
> xlnx,zynqmp-firmware node? That would be ideal so we can constrain this
> to that location somehow.
Yes. Add the node name as a property to the f/w schema and reference
($ref) this file and add 'select: false' to this one. The problem is the
firmware binding is probably not yet a schema. Once it is a schema, this
example will start failing because it's incomplete. For that reason, I
prefer the examples in these cases (inc MFDs) in the base schema and not
in the child node schemas.
> > + versal_clk: clock-controller {
> > + #clock-cells = <1>;
> > + compatible = "xlnx,versal-clk";
> > + clocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>;
> > + clock-names = "ref_clk", "alt_ref_clk", "pl_alt_ref_clk";
> > + };
> > + };
> > + };
> > +...
>
On Tue, 12 Nov 2019 05:16:16 -0800, Rajan Vaja wrote:
> Warn user if clock is used by more than allowed devices.
> This check is done by firmware and returns respective
> error code. Upon receiving error code for excessive user,
> warn user for the same.
>
> This change is done to restrict VPLL use count. It is
> assumed that VPLL is used by one user only.
>
> Signed-off-by: Michal Simek <[email protected]>
> Signed-off-by: Rajan Vaja <[email protected]>
> ---
> drivers/clk/zynqmp/pll.c | 9 ++++++---
> drivers/firmware/xilinx/zynqmp.c | 2 ++
> include/linux/firmware/xlnx-zynqmp.h | 1 +
> 3 files changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c
> index a541397..2f4ccaa 100644
> --- a/drivers/clk/zynqmp/pll.c
> +++ b/drivers/clk/zynqmp/pll.c
> @@ -188,9 +188,12 @@ static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> frac = (parent_rate * f) / FRAC_DIV;
>
> ret = eemi_ops->clock_setdivider(clk_id, m);
> - if (ret)
> - pr_warn_once("%s() set divider failed for %s, ret = %d\n",
> - __func__, clk_name, ret);
> + if (ret) {
> + if (ret == -EUSERS)
> + WARN(1, "More than allowed devices are using the %s, which is forbidden\n", clk_name);
> + pr_err("%s() set divider failed for %s, ret = %d\n",
> + __func__, clk_name, ret);
> + }
In case of -EUSERS this prints the warning and the error. This seems a
bit excessive to me. Isn't it enough to leave the existing
pr_warn_once() for the new error code? If not, then add a new warning
for the -EUSERS error, but leave the existing warning as it is.
Michael
>
> eemi_ops->ioctl(0, IOCTL_SET_PLL_FRAC_DATA, clk_id, f, NULL);
>
> diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
> index 0137bf3..ecc339d 100644
> --- a/drivers/firmware/xilinx/zynqmp.c
> +++ b/drivers/firmware/xilinx/zynqmp.c
> @@ -53,6 +53,8 @@ static int zynqmp_pm_ret_code(u32 ret_status)
> return -EACCES;
> case XST_PM_ABORT_SUSPEND:
> return -ECANCELED;
> + case XST_PM_MULT_USER:
> + return -EUSERS;
> case XST_PM_INTERNAL:
> case XST_PM_CONFLICT:
> case XST_PM_INVALID_NODE:
> diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
> index 25bedd2..f019d1c 100644
> --- a/include/linux/firmware/xlnx-zynqmp.h
> +++ b/include/linux/firmware/xlnx-zynqmp.h
> @@ -96,6 +96,7 @@ enum pm_ret_status {
> XST_PM_INVALID_NODE,
> XST_PM_DOUBLE_REQ,
> XST_PM_ABORT_SUSPEND,
> + XST_PM_MULT_USER = 2008,
> };
>
> enum pm_ioctl_id {
On Tue, 12 Nov 2019 05:16:17 -0800, Rajan Vaja wrote:
> To achieve best possible rate, maximum limit of divider is required
> while computation. Get maximum supported divisor from firmware. To
> maintain backward compatibility assign maximum possible value(0xFFFF)
> if query for max divisor is not successful.
>
> Signed-off-by: Rajan Vaja <[email protected]>
> ---
> drivers/clk/zynqmp/divider.c | 19 +++++++++++++++++++
> include/linux/firmware/xlnx-zynqmp.h | 1 +
> 2 files changed, 20 insertions(+)
>
> diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
> index d8f5b70d..b79cd45 100644
> --- a/drivers/clk/zynqmp/divider.c
> +++ b/drivers/clk/zynqmp/divider.c
> @@ -41,6 +41,7 @@ struct zynqmp_clk_divider {
> bool is_frac;
> u32 clk_id;
> u32 div_type;
> + u16 max_div;
> };
>
> static inline int zynqmp_divider_get_val(unsigned long parent_rate,
> @@ -195,6 +196,9 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name,
> struct clk_hw *hw;
> struct clk_init_data init;
> int ret;
> + const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
> + struct zynqmp_pm_query_data qdata = {0};
> + u32 ret_payload[PAYLOAD_ARG_CNT];
>
> /* allocate the divider */
> div = kzalloc(sizeof(*div), GFP_KERNEL);
> @@ -215,6 +219,21 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name,
> div->clk_id = clk_id;
> div->div_type = nodes->type;
>
> + /*
> + * To achieve best possible rate, maximum limit of divider is required
> + * while computation. Get maximum supported divisor from firmware. To
> + * maintain backward compatibility assign maximum possible value(0xFFFF)
> + * if query for max divisor is not successful.
> + */
> + qdata.qid = PM_QID_CLOCK_GET_MAX_DIVISOR;
> + qdata.arg1 = clk_id;
> + qdata.arg2 = nodes->type;
> + ret = eemi_ops->query_data(qdata, ret_payload);
> + if (ret)
> + div->max_div = U16_MAX;
> + else
> + div->max_div = ret_payload[1];
Add a helper function for retrieving the max divisor. The clk_register
function should really not be mixed with code to access the firmware.
Michael
> +
> hw = &div->hw;
> ret = clk_hw_register(NULL, hw);
> if (ret) {
> diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
> index f019d1c..f0d4558 100644
> --- a/include/linux/firmware/xlnx-zynqmp.h
> +++ b/include/linux/firmware/xlnx-zynqmp.h
> @@ -114,6 +114,7 @@ enum pm_query_id {
> PM_QID_CLOCK_GET_PARENTS,
> PM_QID_CLOCK_GET_ATTRIBUTES,
> PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
> + PM_QID_CLOCK_GET_MAX_DIVISOR,
> };
>
> enum zynqmp_pm_reset_action {
On Tue, 12 Nov 2019 05:16:20 -0800, Rajan Vaja wrote:
> Firmware driver sets BIT(4) to BIT(7) as custom type flags. To make
> divider as fractional divider firmware sets BIT(4). So add support
> for custom type flag and use BIT(4) of custom type flag as CLOCK_FRAC
> bit.
>
> Add a new field to the clock_topology to store custom type flags.
>
> Signed-off-by: Rajan Vaja <[email protected]>
> ---
> drivers/clk/zynqmp/clk-zynqmp.h | 1 +
> drivers/clk/zynqmp/clkc.c | 4 ++++
> drivers/clk/zynqmp/divider.c | 7 +++----
> 3 files changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqmp.h
> index fec9a15..5beeb41 100644
> --- a/drivers/clk/zynqmp/clk-zynqmp.h
> +++ b/drivers/clk/zynqmp/clk-zynqmp.h
> @@ -30,6 +30,7 @@ struct clock_topology {
> u32 type;
> u32 flag;
> u32 type_flag;
> + u8 custom_type_flag;
> };
>
> struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
> diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c
> index 10e89f2..4dd8413 100644
> --- a/drivers/clk/zynqmp/clkc.c
> +++ b/drivers/clk/zynqmp/clkc.c
> @@ -84,6 +84,7 @@ struct name_resp {
>
> struct topology_resp {
> #define CLK_TOPOLOGY_TYPE GENMASK(3, 0)
> +#define CLK_TOPOLOGY_CUSTOM_TYPE_FLAGS GENMASK(7, 4)
> #define CLK_TOPOLOGY_FLAGS GENMASK(23, 8)
> #define CLK_TOPOLOGY_TYPE_FLAGS GENMASK(31, 24)
> u32 topology[CLK_GET_TOPOLOGY_RESP_WORDS];
> @@ -396,6 +397,9 @@ static int __zynqmp_clock_get_topology(struct clock_topology *topology,
> topology[*nnodes].type_flag =
> FIELD_GET(CLK_TOPOLOGY_TYPE_FLAGS,
> response->topology[i]);
> + topology[*nnodes].custom_type_flag =
> + FIELD_GET(CLK_TOPOLOGY_CUSTOM_TYPE_FLAGS,
> + response->topology[i]);
> (*nnodes)++;
> }
>
> diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
> index 67aa88c..e700504 100644
> --- a/drivers/clk/zynqmp/divider.c
> +++ b/drivers/clk/zynqmp/divider.c
> @@ -25,7 +25,7 @@
> #define to_zynqmp_clk_divider(_hw) \
> container_of(_hw, struct zynqmp_clk_divider, hw)
>
> -#define CLK_FRAC BIT(13) /* has a fractional parent */
> +#define CLK_FRAC BIT(4) /* has a fractional parent */
Still NACK. This breaks the compatibility with the mainline TF-A. The
bit is now a different from the bit than in the previous version of
that patch. Moving the flag to custom_type_flags is fine, but please
make sure that you stay backwards compatible to existing versions of the
TF-A.
Michael
>
> /**
> * struct zynqmp_clk_divider - adjustable divider clock
> @@ -279,13 +279,12 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name,
>
> init.name = name;
> init.ops = &zynqmp_clk_divider_ops;
> - /* CLK_FRAC is not defined in the common clk framework */
> - init.flags = nodes->flag & ~CLK_FRAC;
> + init.flags = nodes->flag;
> init.parent_names = parents;
> init.num_parents = 1;
>
> /* struct clk_divider assignments */
> - div->is_frac = !!(nodes->flag & CLK_FRAC);
> + div->is_frac = !!(nodes->custom_type_flag & CLK_FRAC);
> div->flags = nodes->type_flag;
> div->hw.init = &init;
> div->clk_id = clk_id;
ZynqMP clock driver can be used for Versal platform also. Add support
for Versal platform in ZynqMP clock driver.
Also this patch series fixes divider calculation and adds support for get
maximum divider, clock with CLK_DIVIDER_POWER_OF_TWO flag and warn user if
clock users are more than allowed.
Rajan Vaja (5):
dt-bindings: clock: Add bindings for versal clock driver
clk: zynqmp: Extend driver for versal
clk: zynqmp: Warn user if clock user are more than allowed
clk: zynqmp: Add support for get max divider
clk: zynqmp: Fix divider calculation
Tejas Patel (1):
clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag
.../devicetree/bindings/clock/xlnx,versal-clk.yaml | 64 +++++++++++
drivers/clk/zynqmp/clkc.c | 3 +-
drivers/clk/zynqmp/divider.c | 118 +++++++++++++++++++-
drivers/clk/zynqmp/pll.c | 6 +-
drivers/firmware/xilinx/zynqmp.c | 2 +
include/dt-bindings/clock/xlnx-versal-clk.h | 123 +++++++++++++++++++++
include/linux/firmware/xlnx-zynqmp.h | 2 +
7 files changed, 310 insertions(+), 8 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
create mode 100644 include/dt-bindings/clock/xlnx-versal-clk.h
--
Changes in v2:
- [PATCH 7/7]: Removed patch #7 to fix clock frac to handle backward
compatibility. Will send this patch separately with
proper backward compatibility handling.
- Rest of the changes are mentioned in individual patches.
--
2.7.4
Add documentation to describe Xilinx Versal clock driver
bindings.
Signed-off-by: Rajan Vaja <[email protected]>
---
Changes in v2:
- Correct description.
- Add "select: false" field to avoid failing when firmware schema is
available.
- Remove "_clk" from clock names.
- Remove minItems and maxItems fields.
NOTE: firmware dt-bindings in yaml format will be added in a separate
change and $ref of this yaml to firmware will be added.
---
.../devicetree/bindings/clock/xlnx,versal-clk.yaml | 64 +++++++++++
include/dt-bindings/clock/xlnx-versal-clk.h | 123 +++++++++++++++++++++
2 files changed, 187 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
create mode 100644 include/dt-bindings/clock/xlnx-versal-clk.h
diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
new file mode 100644
index 0000000..a1f47cf
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/clock/xlnx,versal-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Versal clock controller
+
+maintainers:
+ - Michal Simek <[email protected]>
+ - Jolly Shah <[email protected]>
+ - Rajan Vaja <[email protected]>
+
+description: |
+ The clock controller is a hardware block of Xilinx versal clock tree. It
+ reads required input clock frequencies from the devicetree and acts as clock
+ provider for all clock consumers of PS clocks.
+
+select: false
+
+properties:
+ compatible:
+ const: xlnx,versal-clk
+
+ "#clock-cells":
+ const: 1
+
+ clocks:
+ description: List of clock specifiers which are external input
+ clocks to the given clock controller.
+ items:
+ - description: reference clock
+ - description: alternate reference clock
+ - description: alternate reference clock for programmable logic
+
+ clock-names:
+ items:
+ - const: ref
+ - const: alt_ref
+ - const: pl_alt_ref
+
+required:
+ - compatible
+ - "#clock-cells"
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ method = "smc";
+ versal_clk: clock-controller {
+ #clock-cells = <1>;
+ compatible = "xlnx,versal-clk";
+ clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>;
+ clock-names = "ref", "alt_ref", "pl_alt_ref";
+ };
+ };
+ };
+...
diff --git a/include/dt-bindings/clock/xlnx-versal-clk.h b/include/dt-bindings/clock/xlnx-versal-clk.h
new file mode 100644
index 0000000..264d634
--- /dev/null
+++ b/include/dt-bindings/clock/xlnx-versal-clk.h
@@ -0,0 +1,123 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 Xilinx Inc.
+ *
+ */
+
+#ifndef _DT_BINDINGS_CLK_VERSAL_H
+#define _DT_BINDINGS_CLK_VERSAL_H
+
+#define PMC_PLL 1
+#define APU_PLL 2
+#define RPU_PLL 3
+#define CPM_PLL 4
+#define NOC_PLL 5
+#define PLL_MAX 6
+#define PMC_PRESRC 7
+#define PMC_POSTCLK 8
+#define PMC_PLL_OUT 9
+#define PPLL 10
+#define NOC_PRESRC 11
+#define NOC_POSTCLK 12
+#define NOC_PLL_OUT 13
+#define NPLL 14
+#define APU_PRESRC 15
+#define APU_POSTCLK 16
+#define APU_PLL_OUT 17
+#define APLL 18
+#define RPU_PRESRC 19
+#define RPU_POSTCLK 20
+#define RPU_PLL_OUT 21
+#define RPLL 22
+#define CPM_PRESRC 23
+#define CPM_POSTCLK 24
+#define CPM_PLL_OUT 25
+#define CPLL 26
+#define PPLL_TO_XPD 27
+#define NPLL_TO_XPD 28
+#define APLL_TO_XPD 29
+#define RPLL_TO_XPD 30
+#define EFUSE_REF 31
+#define SYSMON_REF 32
+#define IRO_SUSPEND_REF 33
+#define USB_SUSPEND 34
+#define SWITCH_TIMEOUT 35
+#define RCLK_PMC 36
+#define RCLK_LPD 37
+#define WDT 38
+#define TTC0 39
+#define TTC1 40
+#define TTC2 41
+#define TTC3 42
+#define GEM_TSU 43
+#define GEM_TSU_LB 44
+#define MUXED_IRO_DIV2 45
+#define MUXED_IRO_DIV4 46
+#define PSM_REF 47
+#define GEM0_RX 48
+#define GEM0_TX 49
+#define GEM1_RX 50
+#define GEM1_TX 51
+#define CPM_CORE_REF 52
+#define CPM_LSBUS_REF 53
+#define CPM_DBG_REF 54
+#define CPM_AUX0_REF 55
+#define CPM_AUX1_REF 56
+#define QSPI_REF 57
+#define OSPI_REF 58
+#define SDIO0_REF 59
+#define SDIO1_REF 60
+#define PMC_LSBUS_REF 61
+#define I2C_REF 62
+#define TEST_PATTERN_REF 63
+#define DFT_OSC_REF 64
+#define PMC_PL0_REF 65
+#define PMC_PL1_REF 66
+#define PMC_PL2_REF 67
+#define PMC_PL3_REF 68
+#define CFU_REF 69
+#define SPARE_REF 70
+#define NPI_REF 71
+#define HSM0_REF 72
+#define HSM1_REF 73
+#define SD_DLL_REF 74
+#define FPD_TOP_SWITCH 75
+#define FPD_LSBUS 76
+#define ACPU 77
+#define DBG_TRACE 78
+#define DBG_FPD 79
+#define LPD_TOP_SWITCH 80
+#define ADMA 81
+#define LPD_LSBUS 82
+#define CPU_R5 83
+#define CPU_R5_CORE 84
+#define CPU_R5_OCM 85
+#define CPU_R5_OCM2 86
+#define IOU_SWITCH 87
+#define GEM0_REF 88
+#define GEM1_REF 89
+#define GEM_TSU_REF 90
+#define USB0_BUS_REF 91
+#define UART0_REF 92
+#define UART1_REF 93
+#define SPI0_REF 94
+#define SPI1_REF 95
+#define CAN0_REF 96
+#define CAN1_REF 97
+#define I2C0_REF 98
+#define I2C1_REF 99
+#define DBG_LPD 100
+#define TIMESTAMP_REF 101
+#define DBG_TSTMP 102
+#define CPM_TOPSW_REF 103
+#define USB3_DUAL_REF 104
+#define OUTCLK_MAX 105
+#define REF_CLK 106
+#define PL_ALT_REF_CLK 107
+#define MUXED_IRO 108
+#define PL_EXT 109
+#define PL_LB 110
+#define MIO_50_OR_51 111
+#define MIO_24_OR_25 112
+
+#endif
--
2.7.4
From: Tejas Patel <[email protected]>
Existing clock divider functions is not checking for
base of divider. So, if any clock divider is power of 2
then clock rate calculation will be wrong.
Add support to calculate divider value for the clocks
with CLK_DIVIDER_POWER_OF_TWO flag.
Signed-off-by: Tejas Patel <[email protected]>
Signed-off-by: Radhey Shyam Pandey <[email protected]>
Signed-off-by: Rajan Vaja <[email protected]>
---
drivers/clk/zynqmp/divider.c | 36 +++++++++++++++++++++++++++++++-----
1 file changed, 31 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
index e0d49cc..1d5a416 100644
--- a/drivers/clk/zynqmp/divider.c
+++ b/drivers/clk/zynqmp/divider.c
@@ -2,7 +2,7 @@
/*
* Zynq UltraScale+ MPSoC Divider support
*
- * Copyright (C) 2016-2018 Xilinx
+ * Copyright (C) 2016-2019 Xilinx
*
* Adjustable divider clock implementation
*/
@@ -45,9 +45,26 @@ struct zynqmp_clk_divider {
};
static inline int zynqmp_divider_get_val(unsigned long parent_rate,
- unsigned long rate)
+ unsigned long rate, u16 flags)
{
- return DIV_ROUND_CLOSEST(parent_rate, rate);
+ int up, down;
+ unsigned long up_rate, down_rate;
+
+ if (flags & CLK_DIVIDER_POWER_OF_TWO) {
+ up = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+ down = DIV_ROUND_DOWN_ULL((u64)parent_rate, rate);
+
+ up = __roundup_pow_of_two(up);
+ down = __rounddown_pow_of_two(down);
+
+ up_rate = DIV_ROUND_UP_ULL((u64)parent_rate, up);
+ down_rate = DIV_ROUND_UP_ULL((u64)parent_rate, down);
+
+ return (rate - up_rate) <= (down_rate - rate) ? up : down;
+
+ } else {
+ return DIV_ROUND_CLOSEST(parent_rate, rate);
+ }
}
/**
@@ -79,6 +96,9 @@ static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw,
else
value = div >> 16;
+ if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
+ value = 1 << value;
+
if (!value) {
WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
@@ -157,10 +177,13 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw,
else
bestdiv = bestdiv >> 16;
+ if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
+ bestdiv = 1 << bestdiv;
+
return DIV_ROUND_UP_ULL((u64)*prate, bestdiv);
}
- bestdiv = zynqmp_divider_get_val(*prate, rate);
+ bestdiv = zynqmp_divider_get_val(*prate, rate, divider->flags);
/*
* In case of two divisors, compute best divider values and return
@@ -198,7 +221,7 @@ static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
int ret;
const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
- value = zynqmp_divider_get_val(parent_rate, rate);
+ value = zynqmp_divider_get_val(parent_rate, rate, divider->flags);
if (div_type == TYPE_DIV1) {
div = value & 0xFFFF;
div |= 0xffff << 16;
@@ -207,6 +230,9 @@ static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
div |= value << 16;
}
+ if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
+ div = __ffs(div);
+
ret = eemi_ops->clock_setdivider(clk_id, div);
if (ret)
--
2.7.4
Warn user if clock is used by more than allowed devices.
This check is done by firmware and returns respective
error code. Upon receiving error code for excessive user,
warn user for the same.
This change is done to restrict VPLL use count. It is
assumed that VPLL is used by one user only.
Signed-off-by: Michal Simek <[email protected]>
Signed-off-by: Rajan Vaja <[email protected]>
---
Changes in v2:
- Leave the existing warning as it is and print new warning in case of
-EUSERS instead of printing error and warning both.
---
drivers/clk/zynqmp/pll.c | 6 ++++--
drivers/firmware/xilinx/zynqmp.c | 2 ++
include/linux/firmware/xlnx-zynqmp.h | 1 +
3 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c
index a541397..89b5995 100644
--- a/drivers/clk/zynqmp/pll.c
+++ b/drivers/clk/zynqmp/pll.c
@@ -188,10 +188,12 @@ static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate,
frac = (parent_rate * f) / FRAC_DIV;
ret = eemi_ops->clock_setdivider(clk_id, m);
- if (ret)
+ if (ret == -EUSERS)
+ WARN(1, "More than allowed devices are using the %s, which is forbidden\n",
+ clk_name);
+ else if (ret)
pr_warn_once("%s() set divider failed for %s, ret = %d\n",
__func__, clk_name, ret);
-
eemi_ops->ioctl(0, IOCTL_SET_PLL_FRAC_DATA, clk_id, f, NULL);
return rate + frac;
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 75bdfaa..74d9f13 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -48,6 +48,8 @@ static int zynqmp_pm_ret_code(u32 ret_status)
return -EACCES;
case XST_PM_ABORT_SUSPEND:
return -ECANCELED;
+ case XST_PM_MULT_USER:
+ return -EUSERS;
case XST_PM_INTERNAL:
case XST_PM_CONFLICT:
case XST_PM_INVALID_NODE:
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index adb14bc..a3b0a39 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -89,6 +89,7 @@ enum pm_ret_status {
XST_PM_INVALID_NODE,
XST_PM_DOUBLE_REQ,
XST_PM_ABORT_SUSPEND,
+ XST_PM_MULT_USER = 2008,
};
enum pm_ioctl_id {
--
2.7.4
To achieve best possible rate, maximum limit of divider is required
while computation. Get maximum supported divisor from firmware. To
maintain backward compatibility assign maximum possible value(0xFFFF)
if query for max divisor is not successful.
Signed-off-by: Rajan Vaja <[email protected]>
---
Changes in v2:
- Add helper function to get maximum divisor of a clock from firmware.
---
drivers/clk/zynqmp/divider.c | 36 ++++++++++++++++++++++++++++++++++++
include/linux/firmware/xlnx-zynqmp.h | 1 +
2 files changed, 37 insertions(+)
diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
index d8f5b70d..aea52cd 100644
--- a/drivers/clk/zynqmp/divider.c
+++ b/drivers/clk/zynqmp/divider.c
@@ -41,6 +41,7 @@ struct zynqmp_clk_divider {
bool is_frac;
u32 clk_id;
u32 div_type;
+ u16 max_div;
};
static inline int zynqmp_divider_get_val(unsigned long parent_rate,
@@ -176,6 +177,35 @@ static const struct clk_ops zynqmp_clk_divider_ops = {
};
/**
+ * zynqmp_clk_get_max_divisor() - Get maximum supported divisor from firmware.
+ * @clk_id: Id of clock
+ * @type: Divider type
+ *
+ * Return: Maximum divisor of a clock if query data is successful
+ * U16_MAX in case of query data is not success
+ */
+u32 zynqmp_clk_get_max_divisor(u32 clk_id, u32 type)
+{
+ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
+ struct zynqmp_pm_query_data qdata = {0};
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ int ret;
+
+ qdata.qid = PM_QID_CLOCK_GET_MAX_DIVISOR;
+ qdata.arg1 = clk_id;
+ qdata.arg2 = type;
+ ret = eemi_ops->query_data(qdata, ret_payload);
+ /*
+ * To maintain backward compatibility return maximum possible value
+ * (0xFFFF) if query for max divisor is not successful.
+ */
+ if (ret)
+ return U16_MAX;
+ else
+ return ret_payload[1];
+}
+
+/**
* zynqmp_clk_register_divider() - Register a divider clock
* @name: Name of this clock
* @clk_id: Id of clock
@@ -215,6 +245,12 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name,
div->clk_id = clk_id;
div->div_type = nodes->type;
+ /*
+ * To achieve best possible rate, maximum limit of divider is required
+ * while computation.
+ */
+ div->max_div = zynqmp_clk_get_max_divisor(clk_id, nodes->type);
+
hw = &div->hw;
ret = clk_hw_register(NULL, hw);
if (ret) {
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index a3b0a39..74d710d 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -107,6 +107,7 @@ enum pm_query_id {
PM_QID_CLOCK_GET_PARENTS,
PM_QID_CLOCK_GET_ATTRIBUTES,
PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
+ PM_QID_CLOCK_GET_MAX_DIVISOR,
};
enum zynqmp_pm_reset_action {
--
2.7.4
On Fri, Nov 22, 2019 at 01:43:29AM -0800, Rajan Vaja wrote:
> Add documentation to describe Xilinx Versal clock driver
> bindings.
>
> Signed-off-by: Rajan Vaja <[email protected]>
> ---
> Changes in v2:
> - Correct description.
> - Add "select: false" field to avoid failing when firmware schema is
> available.
> - Remove "_clk" from clock names.
> - Remove minItems and maxItems fields.
>
> NOTE: firmware dt-bindings in yaml format will be added in a separate
> change and $ref of this yaml to firmware will be added.
> ---
> .../devicetree/bindings/clock/xlnx,versal-clk.yaml | 64 +++++++++++
> include/dt-bindings/clock/xlnx-versal-clk.h | 123 +++++++++++++++++++++
> 2 files changed, 187 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
> create mode 100644 include/dt-bindings/clock/xlnx-versal-clk.h
>
> diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
> new file mode 100644
> index 0000000..a1f47cf
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
> @@ -0,0 +1,64 @@
> +# SPDX-License-Identifier: GPL-2.0
For new bindings: (GPL-2.0-only OR BSD-2-Clause)
With that,
Reviewed-by: Rob Herring <[email protected]>
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/bindings/clock/xlnx,versal-clk.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx Versal clock controller
> +
> +maintainers:
> + - Michal Simek <[email protected]>
> + - Jolly Shah <[email protected]>
> + - Rajan Vaja <[email protected]>
> +
> +description: |
> + The clock controller is a hardware block of Xilinx versal clock tree. It
> + reads required input clock frequencies from the devicetree and acts as clock
> + provider for all clock consumers of PS clocks.
> +
> +select: false
> +
> +properties:
> + compatible:
> + const: xlnx,versal-clk
> +
> + "#clock-cells":
> + const: 1
> +
> + clocks:
> + description: List of clock specifiers which are external input
> + clocks to the given clock controller.
> + items:
> + - description: reference clock
> + - description: alternate reference clock
> + - description: alternate reference clock for programmable logic
> +
> + clock-names:
> + items:
> + - const: ref
> + - const: alt_ref
> + - const: pl_alt_ref
> +
> +required:
> + - compatible
> + - "#clock-cells"
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + firmware {
> + zynqmp_firmware: zynqmp-firmware {
> + compatible = "xlnx,zynqmp-firmware";
> + method = "smc";
> + versal_clk: clock-controller {
> + #clock-cells = <1>;
> + compatible = "xlnx,versal-clk";
> + clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>;
> + clock-names = "ref", "alt_ref", "pl_alt_ref";
> + };
> + };
> + };
> +...
> diff --git a/include/dt-bindings/clock/xlnx-versal-clk.h b/include/dt-bindings/clock/xlnx-versal-clk.h
> new file mode 100644
> index 0000000..264d634
> --- /dev/null
> +++ b/include/dt-bindings/clock/xlnx-versal-clk.h
> @@ -0,0 +1,123 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2019 Xilinx Inc.
> + *
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_VERSAL_H
> +#define _DT_BINDINGS_CLK_VERSAL_H
> +
> +#define PMC_PLL 1
> +#define APU_PLL 2
> +#define RPU_PLL 3
> +#define CPM_PLL 4
> +#define NOC_PLL 5
> +#define PLL_MAX 6
> +#define PMC_PRESRC 7
> +#define PMC_POSTCLK 8
> +#define PMC_PLL_OUT 9
> +#define PPLL 10
> +#define NOC_PRESRC 11
> +#define NOC_POSTCLK 12
> +#define NOC_PLL_OUT 13
> +#define NPLL 14
> +#define APU_PRESRC 15
> +#define APU_POSTCLK 16
> +#define APU_PLL_OUT 17
> +#define APLL 18
> +#define RPU_PRESRC 19
> +#define RPU_POSTCLK 20
> +#define RPU_PLL_OUT 21
> +#define RPLL 22
> +#define CPM_PRESRC 23
> +#define CPM_POSTCLK 24
> +#define CPM_PLL_OUT 25
> +#define CPLL 26
> +#define PPLL_TO_XPD 27
> +#define NPLL_TO_XPD 28
> +#define APLL_TO_XPD 29
> +#define RPLL_TO_XPD 30
> +#define EFUSE_REF 31
> +#define SYSMON_REF 32
> +#define IRO_SUSPEND_REF 33
> +#define USB_SUSPEND 34
> +#define SWITCH_TIMEOUT 35
> +#define RCLK_PMC 36
> +#define RCLK_LPD 37
> +#define WDT 38
> +#define TTC0 39
> +#define TTC1 40
> +#define TTC2 41
> +#define TTC3 42
> +#define GEM_TSU 43
> +#define GEM_TSU_LB 44
> +#define MUXED_IRO_DIV2 45
> +#define MUXED_IRO_DIV4 46
> +#define PSM_REF 47
> +#define GEM0_RX 48
> +#define GEM0_TX 49
> +#define GEM1_RX 50
> +#define GEM1_TX 51
> +#define CPM_CORE_REF 52
> +#define CPM_LSBUS_REF 53
> +#define CPM_DBG_REF 54
> +#define CPM_AUX0_REF 55
> +#define CPM_AUX1_REF 56
> +#define QSPI_REF 57
> +#define OSPI_REF 58
> +#define SDIO0_REF 59
> +#define SDIO1_REF 60
> +#define PMC_LSBUS_REF 61
> +#define I2C_REF 62
> +#define TEST_PATTERN_REF 63
> +#define DFT_OSC_REF 64
> +#define PMC_PL0_REF 65
> +#define PMC_PL1_REF 66
> +#define PMC_PL2_REF 67
> +#define PMC_PL3_REF 68
> +#define CFU_REF 69
> +#define SPARE_REF 70
> +#define NPI_REF 71
> +#define HSM0_REF 72
> +#define HSM1_REF 73
> +#define SD_DLL_REF 74
> +#define FPD_TOP_SWITCH 75
> +#define FPD_LSBUS 76
> +#define ACPU 77
> +#define DBG_TRACE 78
> +#define DBG_FPD 79
> +#define LPD_TOP_SWITCH 80
> +#define ADMA 81
> +#define LPD_LSBUS 82
> +#define CPU_R5 83
> +#define CPU_R5_CORE 84
> +#define CPU_R5_OCM 85
> +#define CPU_R5_OCM2 86
> +#define IOU_SWITCH 87
> +#define GEM0_REF 88
> +#define GEM1_REF 89
> +#define GEM_TSU_REF 90
> +#define USB0_BUS_REF 91
> +#define UART0_REF 92
> +#define UART1_REF 93
> +#define SPI0_REF 94
> +#define SPI1_REF 95
> +#define CAN0_REF 96
> +#define CAN1_REF 97
> +#define I2C0_REF 98
> +#define I2C1_REF 99
> +#define DBG_LPD 100
> +#define TIMESTAMP_REF 101
> +#define DBG_TSTMP 102
> +#define CPM_TOPSW_REF 103
> +#define USB3_DUAL_REF 104
> +#define OUTCLK_MAX 105
> +#define REF_CLK 106
> +#define PL_ALT_REF_CLK 107
> +#define MUXED_IRO 108
> +#define PL_EXT 109
> +#define PL_LB 110
> +#define MIO_50_OR_51 111
> +#define MIO_24_OR_25 112
> +
> +#endif
> --
> 2.7.4
>
ZynqMP clock driver can be used for Versal platform also. Add support
for Versal platform in ZynqMP clock driver.
Also this patch series fixes divider calculation and adds support for get
maximum divider, clock with CLK_DIVIDER_POWER_OF_TWO flag and warn user if
clock users are more than allowed.
Rajan Vaja (5):
dt-bindings: clock: Add bindings for versal clock driver
clk: zynqmp: Extend driver for versal
clk: zynqmp: Warn user if clock user are more than allowed
clk: zynqmp: Add support for get max divider
clk: zynqmp: Fix divider calculation
Tejas Patel (1):
clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag
.../devicetree/bindings/clock/xlnx,versal-clk.yaml | 64 +++++++++++
drivers/clk/zynqmp/clkc.c | 3 +-
drivers/clk/zynqmp/divider.c | 118 +++++++++++++++++++-
drivers/clk/zynqmp/pll.c | 6 +-
drivers/firmware/xilinx/zynqmp.c | 2 +
include/dt-bindings/clock/xlnx-versal-clk.h | 123 +++++++++++++++++++++
include/linux/firmware/xlnx-zynqmp.h | 2 +
7 files changed, 310 insertions(+), 8 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
create mode 100644 include/dt-bindings/clock/xlnx-versal-clk.h
--
Changes in v3:
- [PATCH 1/7]: Update SPDX-License-Identifier.
Changes in v2:
- [PATCH 7/7]: Removed patch #7 to fix clock frac to handle backward
compatibility. Will send this patch separately with
proper backward compatibility handling.
- Rest of the changes are mentioned in individual patches.
--
2.7.4
Add Versal compatible string to support Versal
binding.
Signed-off-by: Jolly Shah <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Signed-off-by: Rajan Vaja <[email protected]>
---
drivers/clk/zynqmp/clkc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c
index a11f93e..10e89f2 100644
--- a/drivers/clk/zynqmp/clkc.c
+++ b/drivers/clk/zynqmp/clkc.c
@@ -2,7 +2,7 @@
/*
* Zynq UltraScale+ MPSoC clock controller
*
- * Copyright (C) 2016-2018 Xilinx
+ * Copyright (C) 2016-2019 Xilinx
*
* Based on drivers/clk/zynq/clkc.c
*/
@@ -749,6 +749,7 @@ static int zynqmp_clock_probe(struct platform_device *pdev)
static const struct of_device_id zynqmp_clock_of_match[] = {
{.compatible = "xlnx,zynqmp-clk"},
+ {.compatible = "xlnx,versal-clk"},
{},
};
MODULE_DEVICE_TABLE(of, zynqmp_clock_of_match);
--
2.7.4
From: Tejas Patel <[email protected]>
Existing clock divider functions is not checking for
base of divider. So, if any clock divider is power of 2
then clock rate calculation will be wrong.
Add support to calculate divider value for the clocks
with CLK_DIVIDER_POWER_OF_TWO flag.
Signed-off-by: Tejas Patel <[email protected]>
Signed-off-by: Radhey Shyam Pandey <[email protected]>
Signed-off-by: Rajan Vaja <[email protected]>
---
drivers/clk/zynqmp/divider.c | 36 +++++++++++++++++++++++++++++++-----
1 file changed, 31 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
index e0d49cc..1d5a416 100644
--- a/drivers/clk/zynqmp/divider.c
+++ b/drivers/clk/zynqmp/divider.c
@@ -2,7 +2,7 @@
/*
* Zynq UltraScale+ MPSoC Divider support
*
- * Copyright (C) 2016-2018 Xilinx
+ * Copyright (C) 2016-2019 Xilinx
*
* Adjustable divider clock implementation
*/
@@ -45,9 +45,26 @@ struct zynqmp_clk_divider {
};
static inline int zynqmp_divider_get_val(unsigned long parent_rate,
- unsigned long rate)
+ unsigned long rate, u16 flags)
{
- return DIV_ROUND_CLOSEST(parent_rate, rate);
+ int up, down;
+ unsigned long up_rate, down_rate;
+
+ if (flags & CLK_DIVIDER_POWER_OF_TWO) {
+ up = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+ down = DIV_ROUND_DOWN_ULL((u64)parent_rate, rate);
+
+ up = __roundup_pow_of_two(up);
+ down = __rounddown_pow_of_two(down);
+
+ up_rate = DIV_ROUND_UP_ULL((u64)parent_rate, up);
+ down_rate = DIV_ROUND_UP_ULL((u64)parent_rate, down);
+
+ return (rate - up_rate) <= (down_rate - rate) ? up : down;
+
+ } else {
+ return DIV_ROUND_CLOSEST(parent_rate, rate);
+ }
}
/**
@@ -79,6 +96,9 @@ static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw,
else
value = div >> 16;
+ if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
+ value = 1 << value;
+
if (!value) {
WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
@@ -157,10 +177,13 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw,
else
bestdiv = bestdiv >> 16;
+ if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
+ bestdiv = 1 << bestdiv;
+
return DIV_ROUND_UP_ULL((u64)*prate, bestdiv);
}
- bestdiv = zynqmp_divider_get_val(*prate, rate);
+ bestdiv = zynqmp_divider_get_val(*prate, rate, divider->flags);
/*
* In case of two divisors, compute best divider values and return
@@ -198,7 +221,7 @@ static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
int ret;
const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
- value = zynqmp_divider_get_val(parent_rate, rate);
+ value = zynqmp_divider_get_val(parent_rate, rate, divider->flags);
if (div_type == TYPE_DIV1) {
div = value & 0xFFFF;
div |= 0xffff << 16;
@@ -207,6 +230,9 @@ static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
div |= value << 16;
}
+ if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
+ div = __ffs(div);
+
ret = eemi_ops->clock_setdivider(clk_id, div);
if (ret)
--
2.7.4
On 05. 12. 19 7:35, Rajan Vaja wrote:
> ZynqMP clock driver can be used for Versal platform also. Add support
> for Versal platform in ZynqMP clock driver.
>
> Also this patch series fixes divider calculation and adds support for get
> maximum divider, clock with CLK_DIVIDER_POWER_OF_TWO flag and warn user if
> clock users are more than allowed.
>
> Rajan Vaja (5):
> dt-bindings: clock: Add bindings for versal clock driver
> clk: zynqmp: Extend driver for versal
> clk: zynqmp: Warn user if clock user are more than allowed
> clk: zynqmp: Add support for get max divider
> clk: zynqmp: Fix divider calculation
>
> Tejas Patel (1):
> clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag
>
> .../devicetree/bindings/clock/xlnx,versal-clk.yaml | 64 +++++++++++
> drivers/clk/zynqmp/clkc.c | 3 +-
> drivers/clk/zynqmp/divider.c | 118 +++++++++++++++++++-
> drivers/clk/zynqmp/pll.c | 6 +-
> drivers/firmware/xilinx/zynqmp.c | 2 +
> include/dt-bindings/clock/xlnx-versal-clk.h | 123 +++++++++++++++++++++
> include/linux/firmware/xlnx-zynqmp.h | 2 +
> 7 files changed, 310 insertions(+), 8 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
> create mode 100644 include/dt-bindings/clock/xlnx-versal-clk.h
>
That firmware changes looks good. That's why feel free to add my
Acked-by: Michal Simek <[email protected]>
to that patches.
If you want me to take it via my tree please let me know.
Thanks,
Michal
Hi Stephen,
Could please let us know if you have comment on this patch series?
Thanks,
Rajan
> -----Original Message-----
> From: Michal Simek <[email protected]>
> Sent: 12 December 2019 08:50 PM
> To: Rajan Vaja <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected]; Michal Simek
> <[email protected]>; Jolly Shah <[email protected]>;
> [email protected]; [email protected]; Tejas Patel
> <[email protected]>; Nava kishore Manne <[email protected]>; [email protected]
> Cc: [email protected]; [email protected]; linux-
> [email protected]; [email protected]
> Subject: Re: [PATCH v3 0/6] clk: zynqmp: Extend and fix zynqmp clock driver
>
> On 05. 12. 19 7:35, Rajan Vaja wrote:
> > ZynqMP clock driver can be used for Versal platform also. Add support
> > for Versal platform in ZynqMP clock driver.
> >
> > Also this patch series fixes divider calculation and adds support for get
> > maximum divider, clock with CLK_DIVIDER_POWER_OF_TWO flag and warn user
> if
> > clock users are more than allowed.
> >
> > Rajan Vaja (5):
> > dt-bindings: clock: Add bindings for versal clock driver
> > clk: zynqmp: Extend driver for versal
> > clk: zynqmp: Warn user if clock user are more than allowed
> > clk: zynqmp: Add support for get max divider
> > clk: zynqmp: Fix divider calculation
> >
> > Tejas Patel (1):
> > clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag
> >
> > .../devicetree/bindings/clock/xlnx,versal-clk.yaml | 64 +++++++++++
> > drivers/clk/zynqmp/clkc.c | 3 +-
> > drivers/clk/zynqmp/divider.c | 118 +++++++++++++++++++-
> > drivers/clk/zynqmp/pll.c | 6 +-
> > drivers/firmware/xilinx/zynqmp.c | 2 +
> > include/dt-bindings/clock/xlnx-versal-clk.h | 123 +++++++++++++++++++++
> > include/linux/firmware/xlnx-zynqmp.h | 2 +
> > 7 files changed, 310 insertions(+), 8 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/clock/xlnx,versal-
> clk.yaml
> > create mode 100644 include/dt-bindings/clock/xlnx-versal-clk.h
> >
>
> That firmware changes looks good. That's why feel free to add my
> Acked-by: Michal Simek <[email protected]>
> to that patches.
> If you want me to take it via my tree please let me know.
>
> Thanks,
> Michal
Quoting Rajan Vaja (2019-12-04 22:35:59)
> From: Tejas Patel <[email protected]>
>
> Existing clock divider functions is not checking for
> base of divider. So, if any clock divider is power of 2
> then clock rate calculation will be wrong.
>
> Add support to calculate divider value for the clocks
> with CLK_DIVIDER_POWER_OF_TWO flag.
>
> Signed-off-by: Tejas Patel <[email protected]>
> Signed-off-by: Radhey Shyam Pandey <[email protected]>
> Signed-off-by: Rajan Vaja <[email protected]>
> ---
Applied to clk-next
Quoting Rajan Vaja (2019-12-04 22:35:55)
> Add Versal compatible string to support Versal
> binding.
>
> Signed-off-by: Jolly Shah <[email protected]>
> Signed-off-by: Michal Simek <[email protected]>
> Signed-off-by: Rajan Vaja <[email protected]>
> ---
Applied to clk-next