change log:
v3:
- Address Marc's comments.
- Reform arch_timer_configure_evtstream.
v2:
- Do not revert commit 0ea415390cd3, fix it instead.
- Correct the tags of second patch.
Keqian Zhu (2):
clocksource: arm_arch_timer: Use stable count reader in erratum sne
clocksource: arm_arch_timer: Correct fault programming of
CNTKCTL_EL1.EVNTI
drivers/clocksource/arm_arch_timer.c | 27 ++++++++++++++++++---------
1 file changed, 18 insertions(+), 9 deletions(-)
--
2.23.0
ARM virtual counter supports event stream, it can only trigger an event
when the trigger bit (the value of CNTKCTL_EL1.EVNTI) of CNTVCT_EL0 changes,
so the actual period of event stream is 2^(cntkctl_evnti + 1). For example,
when the trigger bit is 0, then virtual counter trigger an event for every
two cycles.
Fixes: 037f637767a8 ("drivers: clocksource: add support for ARM architected timer event stream")
Suggested-by: Marc Zyngier <[email protected]>
Signed-off-by: Keqian Zhu <[email protected]>
---
drivers/clocksource/arm_arch_timer.c | 23 ++++++++++++++++-------
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 777d38cb39b0..d0177824c518 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -822,15 +822,24 @@ static void arch_timer_evtstrm_enable(int divider)
static void arch_timer_configure_evtstream(void)
{
- int evt_stream_div, pos;
+ int evt_stream_div, lsb;
+
+ /*
+ * As the event stream can at most be generated at half the frequency
+ * of the counter, use half the frequency when computing the divider.
+ */
+ evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ / 2;
+
+ /*
+ * Find the closest power of two to the divisor. If the adjacent bit
+ * of lsb (last set bit, starts from 0) is set, then we use (lsb + 1).
+ */
+ lsb = fls(evt_stream_div) - 1;
+ if (lsb > 0 && (evt_stream_div & BIT(lsb - 1)))
+ lsb++;
- /* Find the closest power of two to the divisor */
- evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ;
- pos = fls(evt_stream_div);
- if (pos > 1 && !(evt_stream_div & (1 << (pos - 2))))
- pos--;
/* enable event stream */
- arch_timer_evtstrm_enable(min(pos, 15));
+ arch_timer_evtstrm_enable(max(0, min(lsb, 15)));
}
static void arch_counter_set_user_access(void)
--
2.23.0
In commit 0ea415390cd3 ("clocksource/arm_arch_timer: Use arch_timer_read_counter
to access stable counters"), we separate stable and normal count reader to omit
unnecessary overhead on systems that have no timer erratum.
However, in erratum_set_next_event_tval_generic(), count reader becomes normal
reader. This converts it to stable reader.
Fixes: 0ea415390cd3 ("clocksource/arm_arch_timer: Use arch_timer_read_counter to access stable counters")
Acked-by: Marc Zyngier <[email protected]>
Signed-off-by: Keqian Zhu <[email protected]>
---
drivers/clocksource/arm_arch_timer.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 6c3e84180146..777d38cb39b0 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -396,10 +396,10 @@ static void erratum_set_next_event_tval_generic(const int access, unsigned long
ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
if (access == ARCH_TIMER_PHYS_ACCESS) {
- cval = evt + arch_counter_get_cntpct();
+ cval = evt + arch_counter_get_cntpct_stable();
write_sysreg(cval, cntp_cval_el0);
} else {
- cval = evt + arch_counter_get_cntvct();
+ cval = evt + arch_counter_get_cntvct_stable();
write_sysreg(cval, cntv_cval_el0);
}
--
2.23.0
Hi Marc,
are you fine with this patch ?
On 04/12/2020 08:31, Keqian Zhu wrote:
> ARM virtual counter supports event stream, it can only trigger an event
> when the trigger bit (the value of CNTKCTL_EL1.EVNTI) of CNTVCT_EL0 changes,
> so the actual period of event stream is 2^(cntkctl_evnti + 1). For example,
> when the trigger bit is 0, then virtual counter trigger an event for every
> two cycles.
>
> Fixes: 037f637767a8 ("drivers: clocksource: add support for ARM architected timer event stream")
> Suggested-by: Marc Zyngier <[email protected]>
> Signed-off-by: Keqian Zhu <[email protected]>
> ---
> drivers/clocksource/arm_arch_timer.c | 23 ++++++++++++++++-------
> 1 file changed, 16 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
> index 777d38cb39b0..d0177824c518 100644
> --- a/drivers/clocksource/arm_arch_timer.c
> +++ b/drivers/clocksource/arm_arch_timer.c
> @@ -822,15 +822,24 @@ static void arch_timer_evtstrm_enable(int divider)
>
> static void arch_timer_configure_evtstream(void)
> {
> - int evt_stream_div, pos;
> + int evt_stream_div, lsb;
> +
> + /*
> + * As the event stream can at most be generated at half the frequency
> + * of the counter, use half the frequency when computing the divider.
> + */
> + evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ / 2;
> +
> + /*
> + * Find the closest power of two to the divisor. If the adjacent bit
> + * of lsb (last set bit, starts from 0) is set, then we use (lsb + 1).
> + */
> + lsb = fls(evt_stream_div) - 1;
> + if (lsb > 0 && (evt_stream_div & BIT(lsb - 1)))
> + lsb++;
>
> - /* Find the closest power of two to the divisor */
> - evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ;
> - pos = fls(evt_stream_div);
> - if (pos > 1 && !(evt_stream_div & (1 << (pos - 2))))
> - pos--;
> /* enable event stream */
> - arch_timer_evtstrm_enable(min(pos, 15));
> + arch_timer_evtstrm_enable(max(0, min(lsb, 15)));
> }
>
> static void arch_counter_set_user_access(void)
>
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
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Hi Marc,
On 05/12/2020 19:22, Marc Zyngier wrote:
> Hi Daniel,
>
> On 2020-12-05 11:15, Daniel Lezcano wrote:
>> Hi Marc,
>>
>> are you fine with this patch ?
>
> I am, although there still isn't any justification for the pos/lsb
> rework in the commit message (and calling that variable lsb is somewhat
> confusing). If you are going to apply it, please consider adding
> the additional comment below.
Ok, I will do that.
Thanks for the additional comment
-- Daniel
>> On 04/12/2020 08:31, Keqian Zhu wrote:
>>> ARM virtual counter supports event stream, it can only trigger an event
>>> when the trigger bit (the value of CNTKCTL_EL1.EVNTI) of CNTVCT_EL0
>>> changes,
>>> so the actual period of event stream is 2^(cntkctl_evnti + 1). For
>>> example,
>>> when the trigger bit is 0, then virtual counter trigger an event for
>>> every
>>> two cycles.
>
> "While we're at it, rework the way we compute the trigger bit position by
> making it more obvious that when bits [n:n-1] are both set (with n being
> the most significant bit), we pick bit (n + 1)."
>
> With that:
>
> Acked-by: Marc Zyngier <[email protected]>
>
> Thanks,
>
> M.
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
Hi Daniel,
On 2020-12-05 11:15, Daniel Lezcano wrote:
> Hi Marc,
>
> are you fine with this patch ?
I am, although there still isn't any justification for the pos/lsb
rework in the commit message (and calling that variable lsb is somewhat
confusing). If you are going to apply it, please consider adding
the additional comment below.
>
>
> On 04/12/2020 08:31, Keqian Zhu wrote:
>> ARM virtual counter supports event stream, it can only trigger an
>> event
>> when the trigger bit (the value of CNTKCTL_EL1.EVNTI) of CNTVCT_EL0
>> changes,
>> so the actual period of event stream is 2^(cntkctl_evnti + 1). For
>> example,
>> when the trigger bit is 0, then virtual counter trigger an event for
>> every
>> two cycles.
"While we're at it, rework the way we compute the trigger bit position
by
making it more obvious that when bits [n:n-1] are both set (with n
being
the most significant bit), we pick bit (n + 1)."
With that:
Acked-by: Marc Zyngier <[email protected]>
Thanks,
M.
--
Jazz is not dead. It just smells funny...
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 8b7770b877d187bfdae1eaf587bd2b792479a31c
Gitweb: https://git.kernel.org/tip/8b7770b877d187bfdae1eaf587bd2b792479a31c
Author: Keqian Zhu <[email protected]>
AuthorDate: Fri, 04 Dec 2020 15:31:26 +08:00
Committer: Daniel Lezcano <[email protected]>
CommitterDate: Sat, 05 Dec 2020 19:34:04 +01:00
clocksource/drivers/arm_arch_timer: Correct fault programming of CNTKCTL_EL1.EVNTI
ARM virtual counter supports event stream, it can only trigger an event
when the trigger bit (the value of CNTKCTL_EL1.EVNTI) of CNTVCT_EL0 changes,
so the actual period of event stream is 2^(cntkctl_evnti + 1). For example,
when the trigger bit is 0, then virtual counter trigger an event for every
two cycles.
While we're at it, rework the way we compute the trigger bit position
by making it more obvious that when bits [n:n-1] are both set (with n
being the most significant bit), we pick bit (n + 1).
Fixes: 037f637767a8 ("drivers: clocksource: add support for ARM architected timer event stream")
Suggested-by: Marc Zyngier <[email protected]>
Signed-off-by: Keqian Zhu <[email protected]>
Acked-by: Marc Zyngier <[email protected]>
Signed-off-by: Daniel Lezcano <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
---
drivers/clocksource/arm_arch_timer.c | 23 ++++++++++++++++-------
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 777d38c..d017782 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -822,15 +822,24 @@ static void arch_timer_evtstrm_enable(int divider)
static void arch_timer_configure_evtstream(void)
{
- int evt_stream_div, pos;
+ int evt_stream_div, lsb;
+
+ /*
+ * As the event stream can at most be generated at half the frequency
+ * of the counter, use half the frequency when computing the divider.
+ */
+ evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ / 2;
+
+ /*
+ * Find the closest power of two to the divisor. If the adjacent bit
+ * of lsb (last set bit, starts from 0) is set, then we use (lsb + 1).
+ */
+ lsb = fls(evt_stream_div) - 1;
+ if (lsb > 0 && (evt_stream_div & BIT(lsb - 1)))
+ lsb++;
- /* Find the closest power of two to the divisor */
- evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ;
- pos = fls(evt_stream_div);
- if (pos > 1 && !(evt_stream_div & (1 << (pos - 2))))
- pos--;
/* enable event stream */
- arch_timer_evtstrm_enable(min(pos, 15));
+ arch_timer_evtstrm_enable(max(0, min(lsb, 15)));
}
static void arch_counter_set_user_access(void)
The following commit has been merged into the timers/core branch of tip:
Commit-ID: d8cc3905b8073c7cfbff94af889fa8dc71f21dd5
Gitweb: https://git.kernel.org/tip/d8cc3905b8073c7cfbff94af889fa8dc71f21dd5
Author: Keqian Zhu <[email protected]>
AuthorDate: Fri, 04 Dec 2020 15:31:25 +08:00
Committer: Daniel Lezcano <[email protected]>
CommitterDate: Sat, 05 Dec 2020 19:33:55 +01:00
clocksource/drivers/arm_arch_timer: Use stable count reader in erratum sne
In commit 0ea415390cd3 ("clocksource/arm_arch_timer: Use arch_timer_read_counter
to access stable counters"), we separate stable and normal count reader to omit
unnecessary overhead on systems that have no timer erratum.
However, in erratum_set_next_event_tval_generic(), count reader becomes normal
reader. This converts it to stable reader.
Fixes: 0ea415390cd3 ("clocksource/arm_arch_timer: Use arch_timer_read_counter to access stable counters")
Acked-by: Marc Zyngier <[email protected]>
Signed-off-by: Keqian Zhu <[email protected]>
Signed-off-by: Daniel Lezcano <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
---
drivers/clocksource/arm_arch_timer.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 6c3e841..777d38c 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -396,10 +396,10 @@ static void erratum_set_next_event_tval_generic(const int access, unsigned long
ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
if (access == ARCH_TIMER_PHYS_ACCESS) {
- cval = evt + arch_counter_get_cntpct();
+ cval = evt + arch_counter_get_cntpct_stable();
write_sysreg(cval, cntp_cval_el0);
} else {
- cval = evt + arch_counter_get_cntvct();
+ cval = evt + arch_counter_get_cntvct_stable();
write_sysreg(cval, cntv_cval_el0);
}