From: Stefan Chulski <[email protected]>
Armada hardware has a pause generation mechanism in GOP (MAC).
The GOP generate flow control frames based on an indication programmed in Ports Control 0 Register. There is a bit per port.
However assertion of the PortX Pause bits in the ports control 0 register only sends a one time pause.
To complement the function the GOP has a mechanism to periodically send pause control messages based on periodic counters.
This mechanism ensures that the pause is effective as long as the Appropriate PortX Pause is asserted.
Problem is that Packet Processor that actually can drop packets due to lack of resources not connected to the GOP flow control generation mechanism.
To solve this issue Armada has firmware running on CM3 CPU dedicated for Flow Control support.
Firmware monitors Packet Processor resources and asserts XON/XOFF by writing to Ports Control 0 Register.
MSS shared SRAM memory used to communicate between CM3 firmware and PP2 driver.
During init PP2 driver informs firmware about used BM pools, RXQs, congestion and depletion thresholds.
The pause frames are generated whenever congestion or depletion in resources is detected.
The back pressure is stopped when the resource reaches a sufficient level.
So the congestion/depletion and sufficient level implement a hysteresis that reduces the XON/XOFF toggle frequency.
Packet Processor v23 hardware introduces support for RX FIFO fill level monitor.
Patch "add PPv23 version definition" to differ between v23 and v22 hardware.
Patch "add TX FC firmware check" verifies that CM3 firmware supports Flow Control monitoring.
v6 --> v7
- Reduce patch set from 18 to 15 patches
- Documentation change combined into a single patch
- RXQ and BM size change combined into a single patch
- Ring size change check moved into "add RXQ flow control configurations" commit
v5 --> v6
- No change
v4 --> v5
- Add missed Signed-off
- Fix warnings in patches 3 and 12
- Add revision requirement to warning message
- Move mss_spinlock into RXQ flow control configurations patch
- Improve FCA RXQ non occupied descriptor threshold commit message
v3 --> v4
- Remove RFC tag
v2 --> v3
- Remove inline functions
- Add PPv2.3 description into marvell-pp2.txt
- Improve mvpp2_interrupts_mask/unmask procedure
- Improve FC enable/disable procedure
- Add priv->sram_pool check
- Remove gen_pool_destroy call
- Reduce Flow Control timer to x100 faster
v1 --> v2
- Add memory requirements information
- Add EPROBE_DEFER if of_gen_pool_get return NULL
- Move Flow control configuration to mvpp2_mac_link_up callback
- Add firmware version info with Flow control support
Konstantin Porotchkin (1):
dts: marvell: add CM3 SRAM memory to cp115 ethernet device tree
Stefan Chulski (14):
doc: marvell: add cm3-mem and PPv2.3 description
net: mvpp2: add CM3 SRAM memory map
net: mvpp2: add PPv23 version definition
net: mvpp2: always compare hw-version vs MVPP21
net: mvpp2: increase BM pool and RXQ size
net: mvpp2: add FCA periodic timer configurations
net: mvpp2: add FCA RXQ non occupied descriptor threshold
net: mvpp2: enable global flow control
net: mvpp2: add RXQ flow control configurations
net: mvpp2: add ethtool flow control configuration support
net: mvpp2: add BM protection underrun feature support
net: mvpp2: add PPv23 RX FIFO flow control
net: mvpp2: set 802.3x GoP Flow Control mode
net: mvpp2: add TX FC firmware check
Documentation/devicetree/bindings/net/marvell-pp2.txt | 4 +-
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 10 +
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 128 ++++-
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 563 ++++++++++++++++++--
4 files changed, 655 insertions(+), 50 deletions(-)
--
1.9.1
From: Stefan Chulski <[email protected]>
Flow Control periodic timer would be used if port in
XOFF to transmit periodic XOFF frames.
Signed-off-by: Stefan Chulski <[email protected]>
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 13 +++++-
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 45 ++++++++++++++++++++
2 files changed, 57 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
index cac9885..73f087c 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
@@ -596,6 +596,15 @@
#define MVPP22_MPCS_CLK_RESET_DIV_RATIO(n) ((n) << 4)
#define MVPP22_MPCS_CLK_RESET_DIV_SET BIT(11)
+/* FCA registers. PPv2.2 and PPv2.3 */
+#define MVPP22_FCA_BASE(port) (0x7600 + (port) * 0x1000)
+#define MVPP22_FCA_REG_SIZE 16
+#define MVPP22_FCA_REG_MASK 0xFFFF
+#define MVPP22_FCA_CONTROL_REG 0x0
+#define MVPP22_FCA_ENABLE_PERIODIC BIT(11)
+#define MVPP22_PERIODIC_COUNTER_LSB_REG (0x110)
+#define MVPP22_PERIODIC_COUNTER_MSB_REG (0x114)
+
/* XPCS registers. PPv2.2 and PPv2.3 */
#define MVPP22_XPCS_BASE(port) (0x7400 + (port) * 0x1000)
#define MVPP22_XPCS_CFG0 0x0
@@ -752,7 +761,9 @@
((kb) * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN)
/* MSS Flow control */
-#define MSS_SRAM_SIZE 0x800
+#define MSS_SRAM_SIZE 0x800
+#define FC_QUANTA 0xFFFF
+#define FC_CLK_DIVIDER 100
/* RX buffer constants */
#define MVPP2_SKB_SHINFO_SIZE \
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index d80947a..6e59d07 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -1281,6 +1281,49 @@ static void mvpp22_gop_init_10gkr(struct mvpp2_port *port)
writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
}
+static void mvpp22_gop_fca_enable_periodic(struct mvpp2_port *port, bool en)
+{
+ struct mvpp2 *priv = port->priv;
+ void __iomem *fca = priv->iface_base + MVPP22_FCA_BASE(port->gop_id);
+ u32 val;
+
+ val = readl(fca + MVPP22_FCA_CONTROL_REG);
+ val &= ~MVPP22_FCA_ENABLE_PERIODIC;
+ if (en)
+ val |= MVPP22_FCA_ENABLE_PERIODIC;
+ writel(val, fca + MVPP22_FCA_CONTROL_REG);
+}
+
+static void mvpp22_gop_fca_set_timer(struct mvpp2_port *port, u32 timer)
+{
+ struct mvpp2 *priv = port->priv;
+ void __iomem *fca = priv->iface_base + MVPP22_FCA_BASE(port->gop_id);
+ u32 lsb, msb;
+
+ lsb = timer & MVPP22_FCA_REG_MASK;
+ msb = timer >> MVPP22_FCA_REG_SIZE;
+
+ writel(lsb, fca + MVPP22_PERIODIC_COUNTER_LSB_REG);
+ writel(msb, fca + MVPP22_PERIODIC_COUNTER_MSB_REG);
+}
+
+/* Set Flow Control timer x100 faster than pause quanta to ensure that link
+ * partner won't send traffic if port is in XOFF mode.
+ */
+static void mvpp22_gop_fca_set_periodic_timer(struct mvpp2_port *port)
+{
+ u32 timer;
+
+ timer = (port->priv->tclk / (USEC_PER_SEC * FC_CLK_DIVIDER))
+ * FC_QUANTA;
+
+ mvpp22_gop_fca_enable_periodic(port, false);
+
+ mvpp22_gop_fca_set_timer(port, timer);
+
+ mvpp22_gop_fca_enable_periodic(port, true);
+}
+
static int mvpp22_gop_init(struct mvpp2_port *port)
{
struct mvpp2 *priv = port->priv;
@@ -1325,6 +1368,8 @@ static int mvpp22_gop_init(struct mvpp2_port *port)
val |= GENCONF_SOFT_RESET1_GOP;
regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val);
+ mvpp22_gop_fca_set_periodic_timer(port);
+
unsupported_conf:
return 0;
--
1.9.1
From: Stefan Chulski <[email protected]>
This patch add ethtool flow control configuration support.
Tx flow control retrieved correctly by ethtool get function.
FW per port ethtool configuration capability added.
Patch also takes care about mtu change procedure, if PPv2 switch
BM pools during mtu change.
Signed-off-by: Stefan Chulski <[email protected]>
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 13 +++
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 98 ++++++++++++++++++++
2 files changed, 111 insertions(+)
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
index 0f27be0..9071ab6 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
@@ -775,6 +775,19 @@
#define MSS_RXQ_TRESH_REG(q, fq) (MSS_RXQ_TRESH_BASE + (((q) + (fq)) \
* MSS_RXQ_TRESH_OFFS))
+#define MSS_BUF_POOL_BASE 0x40
+#define MSS_BUF_POOL_OFFS 4
+#define MSS_BUF_POOL_REG(id) (MSS_BUF_POOL_BASE \
+ + (id) * MSS_BUF_POOL_OFFS)
+
+#define MSS_BUF_POOL_STOP_MASK 0xFFF
+#define MSS_BUF_POOL_START_MASK (0xFFF << MSS_BUF_POOL_START_OFFS)
+#define MSS_BUF_POOL_START_OFFS 12
+#define MSS_BUF_POOL_PORTS_MASK (0xF << MSS_BUF_POOL_PORTS_OFFS)
+#define MSS_BUF_POOL_PORTS_OFFS 24
+#define MSS_BUF_POOL_PORT_OFFS(id) (0x1 << \
+ ((id) + MSS_BUF_POOL_PORTS_OFFS))
+
#define MSS_RXQ_TRESH_START_MASK 0xFFFF
#define MSS_RXQ_TRESH_STOP_MASK (0xFFFF << MSS_RXQ_TRESH_STOP_OFFS)
#define MSS_RXQ_TRESH_STOP_OFFS 16
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index d778ae1..bbefc7e 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -846,6 +846,59 @@ static void mvpp2_rxq_disable_fc(struct mvpp2_port *port)
spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
}
+/* Routine disable/enable flow control for BM pool condition */
+static void mvpp2_bm_pool_update_fc(struct mvpp2_port *port,
+ struct mvpp2_bm_pool *pool,
+ bool en)
+{
+ int val, cm3_state;
+ unsigned long flags;
+
+ spin_lock_irqsave(&port->priv->mss_spinlock, flags);
+
+ /* Remove Flow control enable bit to prevent race between FW and Kernel
+ * If Flow control were enabled, it would be re-enabled.
+ */
+ val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
+ cm3_state = (val & FLOW_CONTROL_ENABLE_BIT);
+ val &= ~FLOW_CONTROL_ENABLE_BIT;
+ mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
+
+ /* Check if BM pool should be enabled/disable */
+ if (en) {
+ /* Set BM pool start and stop thresholds per port */
+ val = mvpp2_cm3_read(port->priv, MSS_BUF_POOL_REG(pool->id));
+ val |= MSS_BUF_POOL_PORT_OFFS(port->id);
+ val &= ~MSS_BUF_POOL_START_MASK;
+ val |= (MSS_THRESHOLD_START << MSS_BUF_POOL_START_OFFS);
+ val &= ~MSS_BUF_POOL_STOP_MASK;
+ val |= MSS_THRESHOLD_STOP;
+ mvpp2_cm3_write(port->priv, MSS_BUF_POOL_REG(pool->id), val);
+ } else {
+ /* Remove BM pool from the port */
+ val = mvpp2_cm3_read(port->priv, MSS_BUF_POOL_REG(pool->id));
+ val &= ~MSS_BUF_POOL_PORT_OFFS(port->id);
+
+ /* Zero BM pool start and stop thresholds to disable pool
+ * flow control if pool empty (not used by any port)
+ */
+ if (!pool->buf_num) {
+ val &= ~MSS_BUF_POOL_START_MASK;
+ val &= ~MSS_BUF_POOL_STOP_MASK;
+ }
+
+ mvpp2_cm3_write(port->priv, MSS_BUF_POOL_REG(pool->id), val);
+ }
+
+ /* Notify Firmware that Flow control config space ready for update */
+ val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
+ val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
+ val |= cm3_state;
+ mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
+
+ spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
+}
+
/* Release buffer to BM */
static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
dma_addr_t buf_dma_addr,
@@ -1176,6 +1229,16 @@ static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu)
new_long_pool = MVPP2_BM_LONG;
if (new_long_pool != port->pool_long->id) {
+ if (port->tx_fc) {
+ if (pkt_size > MVPP2_BM_LONG_PKT_SIZE)
+ mvpp2_bm_pool_update_fc(port,
+ port->pool_short,
+ false);
+ else
+ mvpp2_bm_pool_update_fc(port, port->pool_long,
+ false);
+ }
+
/* Remove port from old short & long pool */
port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id,
port->pool_long->pkt_size);
@@ -1193,6 +1256,25 @@ static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu)
mvpp2_swf_bm_pool_init(port);
mvpp2_set_hw_csum(port, new_long_pool);
+
+ if (port->tx_fc) {
+ if (pkt_size > MVPP2_BM_LONG_PKT_SIZE)
+ mvpp2_bm_pool_update_fc(port, port->pool_long,
+ true);
+ else
+ mvpp2_bm_pool_update_fc(port, port->pool_short,
+ true);
+ }
+
+ /* Update L4 checksum when jumbo enable/disable on port */
+ if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) {
+ dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
+ dev->hw_features &= ~(NETIF_F_IP_CSUM |
+ NETIF_F_IPV6_CSUM);
+ } else {
+ dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
+ dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
+ }
}
out_set:
@@ -6358,6 +6440,7 @@ static void mvpp2_mac_link_up(struct phylink_config *config,
{
struct mvpp2_port *port = mvpp2_phylink_to_port(config);
u32 val;
+ int i;
if (mvpp2_is_xlg(interface)) {
if (!phylink_autoneg_inband(mode)) {
@@ -6408,6 +6491,21 @@ static void mvpp2_mac_link_up(struct phylink_config *config,
val);
}
+ if (port->priv->global_tx_fc) {
+ port->tx_fc = tx_pause;
+ if (tx_pause)
+ mvpp2_rxq_enable_fc(port);
+ else
+ mvpp2_rxq_disable_fc(port);
+ if (port->priv->percpu_pools) {
+ for (i = 0; i < port->nrxqs; i++)
+ mvpp2_bm_pool_update_fc(port, &port->priv->bm_pools[i], tx_pause);
+ } else {
+ mvpp2_bm_pool_update_fc(port, port->pool_long, tx_pause);
+ mvpp2_bm_pool_update_fc(port, port->pool_short, tx_pause);
+ }
+ }
+
mvpp2_port_enable(port);
mvpp2_egress_enable(port);
--
1.9.1
From: Stefan Chulski <[email protected]>
This patch enables global flow control in FW and in the phylink validate mask.
Signed-off-by: Stefan Chulski <[email protected]>
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 13 ++++++---
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 30 +++++++++++++++++++-
2 files changed, 38 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
index ca84995..e010410 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
@@ -763,10 +763,12 @@
((kb) * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN)
/* MSS Flow control */
-#define MSS_SRAM_SIZE 0x800
-#define FC_QUANTA 0xFFFF
-#define FC_CLK_DIVIDER 100
-#define MSS_THRESHOLD_STOP 768
+#define MSS_SRAM_SIZE 0x800
+#define MSS_FC_COM_REG 0
+#define FLOW_CONTROL_ENABLE_BIT BIT(0)
+#define FC_QUANTA 0xFFFF
+#define FC_CLK_DIVIDER 100
+#define MSS_THRESHOLD_STOP 768
/* RX buffer constants */
#define MVPP2_SKB_SHINFO_SIZE \
@@ -1021,6 +1023,9 @@ struct mvpp2 {
/* CM3 SRAM pool */
struct gen_pool *sram_pool;
+
+ /* Global TX Flow Control config */
+ bool global_tx_fc;
};
struct mvpp2_pcpu_stats {
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index 19a3f38..770f45a 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -92,6 +92,16 @@ static inline u32 mvpp2_cpu_to_thread(struct mvpp2 *priv, int cpu)
return cpu % priv->nthreads;
}
+static void mvpp2_cm3_write(struct mvpp2 *priv, u32 offset, u32 data)
+{
+ writel(data, priv->cm3_base + offset);
+}
+
+static u32 mvpp2_cm3_read(struct mvpp2 *priv, u32 offset)
+{
+ return readl(priv->cm3_base + offset);
+}
+
static struct page_pool *
mvpp2_create_page_pool(struct device *dev, int num, int len,
enum dma_data_direction dma_dir)
@@ -5951,6 +5961,11 @@ static void mvpp2_phylink_validate(struct phylink_config *config,
phylink_set(mask, Autoneg);
phylink_set_port_modes(mask);
+ if (port->priv->global_tx_fc) {
+ phylink_set(mask, Pause);
+ phylink_set(mask, Asym_Pause);
+ }
+
switch (state->interface) {
case PHY_INTERFACE_MODE_10GBASER:
case PHY_INTERFACE_MODE_XAUI:
@@ -6969,7 +6984,7 @@ static int mvpp2_probe(struct platform_device *pdev)
struct resource *res;
void __iomem *base;
int i, shared;
- int err;
+ int err, val;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
@@ -7023,6 +7038,10 @@ static int mvpp2_probe(struct platform_device *pdev)
return err;
else if (err)
dev_warn(&pdev->dev, "Fail to alloc CM3 SRAM\n");
+
+ /* Enable global Flow Control only if handler to SRAM not NULL */
+ if (priv->cm3_base)
+ priv->global_tx_fc = true;
}
if (priv->hw_version != MVPP21 && dev_of_node(&pdev->dev)) {
@@ -7190,6 +7209,15 @@ static int mvpp2_probe(struct platform_device *pdev)
goto err_port_probe;
}
+ /* Enable global flow control. In this stage global
+ * flow control enabled, but still disabled per port.
+ */
+ if (priv->global_tx_fc && priv->hw_version != MVPP21) {
+ val = mvpp2_cm3_read(priv, MSS_FC_COM_REG);
+ val |= FLOW_CONTROL_ENABLE_BIT;
+ mvpp2_cm3_write(priv, MSS_FC_COM_REG, val);
+ }
+
mvpp2_dbgfs_init(priv, pdev->name);
platform_set_drvdata(pdev, priv);
--
1.9.1
From: Stefan Chulski <[email protected]>
This patch add PPv23 version definition.
PPv23 is new packet processor in CP115.
Everything that supported by PPv22, also supported by PPv23.
No functional changes in this stage.
Signed-off-by: Stefan Chulski <[email protected]>
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 24 ++++++++++++--------
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 17 +++++++++-----
2 files changed, 25 insertions(+), 16 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
index aec9179..89b3ede 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
@@ -60,6 +60,9 @@
/* Top Registers */
#define MVPP2_MH_REG(port) (0x5040 + 4 * (port))
#define MVPP2_DSA_EXTENDED BIT(5)
+#define MVPP2_VER_ID_REG 0x50b0
+#define MVPP2_VER_PP22 0x10
+#define MVPP2_VER_PP23 0x11
/* Parser Registers */
#define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
@@ -469,7 +472,7 @@
#define MVPP22_GMAC_INT_SUM_MASK_LINK_STAT BIT(1)
#define MVPP22_GMAC_INT_SUM_MASK_PTP BIT(2)
-/* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
+/* Per-port XGMAC registers. PPv2.2 and PPv2.3, only for GOP port 0,
* relative to port->base.
*/
#define MVPP22_XLG_CTRL0_REG 0x100
@@ -506,7 +509,7 @@
#define MVPP22_XLG_CTRL4_MACMODSELECT_GMAC BIT(12)
#define MVPP22_XLG_CTRL4_EN_IDLE_CHECK BIT(14)
-/* SMI registers. PPv2.2 only, relative to priv->iface_base. */
+/* SMI registers. PPv2.2 and PPv2.3, relative to priv->iface_base. */
#define MVPP22_SMI_MISC_CFG_REG 0x1204
#define MVPP22_SMI_POLLING_EN BIT(10)
@@ -582,7 +585,7 @@
#define MVPP2_QUEUE_NEXT_DESC(q, index) \
(((index) < (q)->last_desc) ? ((index) + 1) : 0)
-/* XPCS registers. PPv2.2 only */
+/* XPCS registers.PPv2.2 and PPv2.3 */
#define MVPP22_MPCS_BASE(port) (0x7000 + (port) * 0x1000)
#define MVPP22_MPCS_CTRL 0x14
#define MVPP22_MPCS_CTRL_FWD_ERR_CONN BIT(10)
@@ -593,7 +596,7 @@
#define MVPP22_MPCS_CLK_RESET_DIV_RATIO(n) ((n) << 4)
#define MVPP22_MPCS_CLK_RESET_DIV_SET BIT(11)
-/* XPCS registers. PPv2.2 only */
+/* XPCS registers. PPv2.2 and PPv2.3 */
#define MVPP22_XPCS_BASE(port) (0x7400 + (port) * 0x1000)
#define MVPP22_XPCS_CFG0 0x0
#define MVPP22_XPCS_CFG0_RESET_DIS BIT(0)
@@ -930,15 +933,16 @@ struct mvpp2 {
void __iomem *iface_base;
void __iomem *cm3_base;
- /* On PPv2.2, each "software thread" can access the base
+ /* On PPv2.2 and PPv2.3, each "software thread" can access the base
* register through a separate address space, each 64 KB apart
* from each other. Typically, such address spaces will be
* used per CPU.
*/
void __iomem *swth_base[MVPP2_MAX_THREADS];
- /* On PPv2.2, some port control registers are located into the system
- * controller space. These registers are accessible through a regmap.
+ /* On PPv2.2 and PPv2.3, some port control registers are located into
+ * the system controller space. These registers are accessible
+ * through a regmap.
*/
struct regmap *sysctrl_base;
@@ -980,7 +984,7 @@ struct mvpp2 {
u32 tclk;
/* HW version */
- enum { MVPP21, MVPP22 } hw_version;
+ enum { MVPP21, MVPP22, MVPP23 } hw_version;
/* Maximum number of RXQs per port */
unsigned int max_port_rxqs;
@@ -1227,7 +1231,7 @@ struct mvpp21_rx_desc {
__le32 reserved8;
};
-/* HW TX descriptor for PPv2.2 */
+/* HW TX descriptor for PPv2.2 and PPv2.3 */
struct mvpp22_tx_desc {
__le32 command;
u8 packet_offset;
@@ -1239,7 +1243,7 @@ struct mvpp22_tx_desc {
__le64 buf_cookie_misc;
};
-/* HW RX descriptor for PPv2.2 */
+/* HW RX descriptor for PPv2.2 and PPv2.3 */
struct mvpp22_rx_desc {
__le32 status;
__le16 reserved1;
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index 307f9fd..11c56d2 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -385,7 +385,7 @@ static int mvpp2_bm_pool_create(struct device *dev, struct mvpp2 *priv,
if (!IS_ALIGNED(size, 16))
return -EINVAL;
- /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16
+ /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 and PPv2.3 needs 16
* bytes per buffer pointer
*/
if (priv->hw_version == MVPP21)
@@ -1173,7 +1173,7 @@ static void mvpp2_interrupts_unmask(void *arg)
u32 val;
int i;
- if (port->priv->hw_version != MVPP22)
+ if (port->priv->hw_version == MVPP21)
return;
if (mask)
@@ -5457,7 +5457,7 @@ static void mvpp2_rx_irqs_setup(struct mvpp2_port *port)
return;
}
- /* Handle the more complicated PPv2.2 case */
+ /* Handle the more complicated PPv2.2 and PPv2.3 case */
for (i = 0; i < port->nqvecs; i++) {
struct mvpp2_queue_vector *qv = port->qvecs + i;
@@ -5634,7 +5634,7 @@ static bool mvpp22_port_has_legacy_tx_irqs(struct device_node *port_node,
/* Checks if the port dt description has the required Tx interrupts:
* - PPv2.1: there are no such interrupts.
- * - PPv2.2:
+ * - PPv2.2 and PPv2.3:
* - The old DTs have: "rx-shared", "tx-cpuX" with X in [0...3]
* - The new ones have: "hifX" with X in [0..8]
*
@@ -6622,7 +6622,7 @@ static void mvpp22_rx_fifo_set_hw(struct mvpp2 *priv, int port, int data_size)
mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), attr_size);
}
-/* Initialize TX FIFO's: the total FIFO size is 48kB on PPv2.2.
+/* Initialize TX FIFO's: the total FIFO size is 48kB on PPv2.2 and PPv2.3.
* 4kB fixed space must be assigned for the loopback port.
* Redistribute remaining avialable 44kB space among all active ports.
* Guarantee minimum 32kB for 10G port and 8kB for port 1, capable of 2.5G
@@ -6679,7 +6679,7 @@ static void mvpp22_tx_fifo_set_hw(struct mvpp2 *priv, int port, int size)
mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), threshold);
}
-/* Initialize TX FIFO's: the total FIFO size is 19kB on PPv2.2.
+/* Initialize TX FIFO's: the total FIFO size is 19kB on PPv2.2 and PPv2.3.
* 3kB fixed space must be assigned for the loopback port.
* Redistribute remaining avialable 16kB space among all active ports.
* The 10G interface should use 10kB (which is maximum possible size
@@ -7071,6 +7071,11 @@ static int mvpp2_probe(struct platform_device *pdev)
priv->port_map |= BIT(i);
}
+ if (priv->hw_version != MVPP21) {
+ if (mvpp2_read(priv, MVPP2_VER_ID_REG) == MVPP2_VER_PP23)
+ priv->hw_version = MVPP23;
+ }
+
/* Initialize network controller */
err = mvpp2_init(pdev, priv);
if (err < 0) {
--
1.9.1
From: Stefan Chulski <[email protected]>
This patch adds CM3 memory map and CM3 read/write callbacks.
No functionality changes.
Signed-off-by: Stefan Chulski <[email protected]>
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 7 +++
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 63 +++++++++++++++++++-
2 files changed, 67 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
index 6bd7e40..aec9179 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
@@ -748,6 +748,9 @@
#define MVPP2_TX_FIFO_THRESHOLD(kb) \
((kb) * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN)
+/* MSS Flow control */
+#define MSS_SRAM_SIZE 0x800
+
/* RX buffer constants */
#define MVPP2_SKB_SHINFO_SIZE \
SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
@@ -925,6 +928,7 @@ struct mvpp2 {
/* Shared registers' base addresses */
void __iomem *lms_base;
void __iomem *iface_base;
+ void __iomem *cm3_base;
/* On PPv2.2, each "software thread" can access the base
* register through a separate address space, each 64 KB apart
@@ -996,6 +1000,9 @@ struct mvpp2 {
/* page_pool allocator */
struct page_pool *page_pool[MVPP2_PORT_MAX_RXQ];
+
+ /* CM3 SRAM pool */
+ struct gen_pool *sram_pool;
};
struct mvpp2_pcpu_stats {
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index a07cf60..307f9fd 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -25,6 +25,7 @@
#include <linux/of_net.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
+#include <linux/genalloc.h>
#include <linux/phy.h>
#include <linux/phylink.h>
#include <linux/phy/phy.h>
@@ -6846,6 +6847,44 @@ static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
return 0;
}
+static int mvpp2_get_sram(struct platform_device *pdev,
+ struct mvpp2 *priv)
+{
+ struct device_node *dn = pdev->dev.of_node;
+ static bool defer_once;
+ struct resource *res;
+
+ if (has_acpi_companion(&pdev->dev)) {
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+ if (!res) {
+ dev_warn(&pdev->dev, "ACPI is too old, Flow control not supported\n");
+ return 0;
+ }
+ priv->cm3_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(priv->cm3_base))
+ return PTR_ERR(priv->cm3_base);
+ } else {
+ priv->sram_pool = of_gen_pool_get(dn, "cm3-mem", 0);
+ if (!priv->sram_pool) {
+ if (!defer_once) {
+ defer_once = true;
+ /* Try defer once */
+ return -EPROBE_DEFER;
+ }
+ dev_warn(&pdev->dev, "DT is too old, Flow control not supported\n");
+ return -ENOMEM;
+ }
+ /* cm3_base allocated with offset zero into the SRAM since mapping size
+ * is equal to requested size.
+ */
+ priv->cm3_base = (void __iomem *)gen_pool_alloc(priv->sram_pool,
+ MSS_SRAM_SIZE);
+ if (!priv->cm3_base)
+ return -ENOMEM;
+ }
+ return 0;
+}
+
static int mvpp2_probe(struct platform_device *pdev)
{
const struct acpi_device_id *acpi_id;
@@ -6902,6 +6941,13 @@ static int mvpp2_probe(struct platform_device *pdev)
priv->iface_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(priv->iface_base))
return PTR_ERR(priv->iface_base);
+
+ /* Map CM3 SRAM */
+ err = mvpp2_get_sram(pdev, priv);
+ if (err == -EPROBE_DEFER)
+ return err;
+ else if (err)
+ dev_warn(&pdev->dev, "Fail to alloc CM3 SRAM\n");
}
if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) {
@@ -6947,11 +6993,13 @@ static int mvpp2_probe(struct platform_device *pdev)
if (dev_of_node(&pdev->dev)) {
priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk");
- if (IS_ERR(priv->pp_clk))
- return PTR_ERR(priv->pp_clk);
+ if (IS_ERR(priv->pp_clk)) {
+ err = PTR_ERR(priv->pp_clk);
+ goto err_cm3;
+ }
err = clk_prepare_enable(priv->pp_clk);
if (err < 0)
- return err;
+ goto err_cm3;
priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk");
if (IS_ERR(priv->gop_clk)) {
@@ -7087,6 +7135,11 @@ static int mvpp2_probe(struct platform_device *pdev)
clk_disable_unprepare(priv->gop_clk);
err_pp_clk:
clk_disable_unprepare(priv->pp_clk);
+err_cm3:
+ if (priv->sram_pool && priv->cm3_base)
+ gen_pool_free(priv->sram_pool, (unsigned long)priv->cm3_base,
+ MSS_SRAM_SIZE);
+
return err;
}
@@ -7127,6 +7180,10 @@ static int mvpp2_remove(struct platform_device *pdev)
aggr_txq->descs_dma);
}
+ if (priv->sram_pool && priv->cm3_base)
+ gen_pool_free(priv->sram_pool, (unsigned long)priv->cm3_base,
+ MSS_SRAM_SIZE);
+
if (is_acpi_node(port_fwnode))
return 0;
--
1.9.1
From: Stefan Chulski <[email protected]>
Patch introduce cm3-mem device tree bindings and add PPv2.3 description.
Signed-off-by: Stefan Chulski <[email protected]>
---
Documentation/devicetree/bindings/net/marvell-pp2.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/marvell-pp2.txt b/Documentation/devicetree/bindings/net/marvell-pp2.txt
index b783976..df80cff 100644
--- a/Documentation/devicetree/bindings/net/marvell-pp2.txt
+++ b/Documentation/devicetree/bindings/net/marvell-pp2.txt
@@ -1,5 +1,6 @@
* Marvell Armada 375 Ethernet Controller (PPv2.1)
Marvell Armada 7K/8K Ethernet Controller (PPv2.2)
+ Marvell CN913X Ethernet Controller (PPv2.3)
Required properties:
@@ -12,7 +13,7 @@ Required properties:
- common controller registers
- LMS registers
- one register area per Ethernet port
- For "marvell,armada-7k-pp2", must contain the following register
+ For "marvell,armada-7k-pp2" used by 7K/8K and CN913X, must contain the following register
sets:
- packet processor registers
- networking interfaces registers
@@ -37,6 +38,7 @@ Required properties (port):
GOP (Group Of Ports) point of view. This ID is used to index the
per-port registers in the second register area.
- phy-mode: See ethernet.txt file in the same directory
+- cm3-mem: phandle to CM3 SRAM definitions
Optional properties (port):
--
1.9.1
From: Stefan Chulski <[email protected]>
BM pool and RXQ size increased to support Firmware Flow Control.
Minimum depletion thresholds to support FC are 1024 buffers.
BM pool size increased to 2048 to have some 1024 buffers
space between depletion thresholds and BM pool size.
Jumbo frames require a 9888B buffer, so memory requirements
for data buffers increased from 7MB to 24MB.
Signed-off-by: Stefan Chulski <[email protected]>
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
index 89b3ede..cac9885 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
@@ -715,8 +715,8 @@
#define MVPP2_PORT_MAX_RXQ 32
/* Max number of Rx descriptors */
-#define MVPP2_MAX_RXD_MAX 1024
-#define MVPP2_MAX_RXD_DFLT 128
+#define MVPP2_MAX_RXD_MAX 2048
+#define MVPP2_MAX_RXD_DFLT 1024
/* Max number of Tx descriptors */
#define MVPP2_MAX_TXD_MAX 2048
@@ -851,8 +851,8 @@ enum mvpp22_ptp_packet_format {
#define MVPP22_PTP_TIMESTAMPQUEUESELECT BIT(18)
/* BM constants */
-#define MVPP2_BM_JUMBO_BUF_NUM 512
-#define MVPP2_BM_LONG_BUF_NUM 1024
+#define MVPP2_BM_JUMBO_BUF_NUM 2048
+#define MVPP2_BM_LONG_BUF_NUM 2048
#define MVPP2_BM_SHORT_BUF_NUM 2048
#define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
#define MVPP2_BM_POOL_PTR_ALIGN 128
--
1.9.1
Hi,
wt., 2 lut 2021 o 09:17 <[email protected]> napisał(a):
>
> From: Stefan Chulski <[email protected]>
>
> This patch add PPv23 version definition.
> PPv23 is new packet processor in CP115.
> Everything that supported by PPv22, also supported by PPv23.
> No functional changes in this stage.
>
> Signed-off-by: Stefan Chulski <[email protected]>
> ---
> drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 24 ++++++++++++--------
> drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 17 +++++++++-----
> 2 files changed, 25 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
> index aec9179..89b3ede 100644
> --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
> +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
> @@ -60,6 +60,9 @@
> /* Top Registers */
> #define MVPP2_MH_REG(port) (0x5040 + 4 * (port))
> #define MVPP2_DSA_EXTENDED BIT(5)
> +#define MVPP2_VER_ID_REG 0x50b0
> +#define MVPP2_VER_PP22 0x10
> +#define MVPP2_VER_PP23 0x11
>
> /* Parser Registers */
> #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
> @@ -469,7 +472,7 @@
> #define MVPP22_GMAC_INT_SUM_MASK_LINK_STAT BIT(1)
> #define MVPP22_GMAC_INT_SUM_MASK_PTP BIT(2)
>
> -/* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
> +/* Per-port XGMAC registers. PPv2.2 and PPv2.3, only for GOP port 0,
> * relative to port->base.
> */
> #define MVPP22_XLG_CTRL0_REG 0x100
> @@ -506,7 +509,7 @@
> #define MVPP22_XLG_CTRL4_MACMODSELECT_GMAC BIT(12)
> #define MVPP22_XLG_CTRL4_EN_IDLE_CHECK BIT(14)
>
> -/* SMI registers. PPv2.2 only, relative to priv->iface_base. */
> +/* SMI registers. PPv2.2 and PPv2.3, relative to priv->iface_base. */
> #define MVPP22_SMI_MISC_CFG_REG 0x1204
> #define MVPP22_SMI_POLLING_EN BIT(10)
>
> @@ -582,7 +585,7 @@
> #define MVPP2_QUEUE_NEXT_DESC(q, index) \
> (((index) < (q)->last_desc) ? ((index) + 1) : 0)
>
> -/* XPCS registers. PPv2.2 only */
> +/* XPCS registers.PPv2.2 and PPv2.3 */
> #define MVPP22_MPCS_BASE(port) (0x7000 + (port) * 0x1000)
> #define MVPP22_MPCS_CTRL 0x14
> #define MVPP22_MPCS_CTRL_FWD_ERR_CONN BIT(10)
> @@ -593,7 +596,7 @@
> #define MVPP22_MPCS_CLK_RESET_DIV_RATIO(n) ((n) << 4)
> #define MVPP22_MPCS_CLK_RESET_DIV_SET BIT(11)
>
> -/* XPCS registers. PPv2.2 only */
> +/* XPCS registers. PPv2.2 and PPv2.3 */
> #define MVPP22_XPCS_BASE(port) (0x7400 + (port) * 0x1000)
> #define MVPP22_XPCS_CFG0 0x0
> #define MVPP22_XPCS_CFG0_RESET_DIS BIT(0)
> @@ -930,15 +933,16 @@ struct mvpp2 {
> void __iomem *iface_base;
> void __iomem *cm3_base;
>
> - /* On PPv2.2, each "software thread" can access the base
> + /* On PPv2.2 and PPv2.3, each "software thread" can access the base
> * register through a separate address space, each 64 KB apart
> * from each other. Typically, such address spaces will be
> * used per CPU.
> */
> void __iomem *swth_base[MVPP2_MAX_THREADS];
>
> - /* On PPv2.2, some port control registers are located into the system
> - * controller space. These registers are accessible through a regmap.
> + /* On PPv2.2 and PPv2.3, some port control registers are located into
> + * the system controller space. These registers are accessible
> + * through a regmap.
> */
> struct regmap *sysctrl_base;
>
> @@ -980,7 +984,7 @@ struct mvpp2 {
> u32 tclk;
>
> /* HW version */
> - enum { MVPP21, MVPP22 } hw_version;
> + enum { MVPP21, MVPP22, MVPP23 } hw_version;
>
> /* Maximum number of RXQs per port */
> unsigned int max_port_rxqs;
> @@ -1227,7 +1231,7 @@ struct mvpp21_rx_desc {
> __le32 reserved8;
> };
>
> -/* HW TX descriptor for PPv2.2 */
> +/* HW TX descriptor for PPv2.2 and PPv2.3 */
> struct mvpp22_tx_desc {
> __le32 command;
> u8 packet_offset;
> @@ -1239,7 +1243,7 @@ struct mvpp22_tx_desc {
> __le64 buf_cookie_misc;
> };
>
> -/* HW RX descriptor for PPv2.2 */
> +/* HW RX descriptor for PPv2.2 and PPv2.3 */
> struct mvpp22_rx_desc {
> __le32 status;
> __le16 reserved1;
> diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
> index 307f9fd..11c56d2 100644
> --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
> +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
> @@ -385,7 +385,7 @@ static int mvpp2_bm_pool_create(struct device *dev, struct mvpp2 *priv,
> if (!IS_ALIGNED(size, 16))
> return -EINVAL;
>
> - /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16
> + /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 and PPv2.3 needs 16
s/needs 16/need 16/
> * bytes per buffer pointer
> */
> if (priv->hw_version == MVPP21)
> @@ -1173,7 +1173,7 @@ static void mvpp2_interrupts_unmask(void *arg)
> u32 val;
> int i;
>
> - if (port->priv->hw_version != MVPP22)
> + if (port->priv->hw_version == MVPP21)
> return;
This change should go to "net: mvpp2: always compare hw-version vs
MVPP21" patch. Please also swap order of those 2 commits - the
preparation patch should go before MVPP23 addition.
Thanks,
Marcin
Hi,
wt., 2 lut 2021 o 09:17 <[email protected]> napisał(a):
>
> From: Stefan Chulski <[email protected]>
>
> Armada hardware has a pause generation mechanism in GOP (MAC).
> The GOP generate flow control frames based on an indication programmed in Ports Control 0 Register. There is a bit per port.
> However assertion of the PortX Pause bits in the ports control 0 register only sends a one time pause.
> To complement the function the GOP has a mechanism to periodically send pause control messages based on periodic counters.
> This mechanism ensures that the pause is effective as long as the Appropriate PortX Pause is asserted.
>
> Problem is that Packet Processor that actually can drop packets due to lack of resources not connected to the GOP flow control generation mechanism.
> To solve this issue Armada has firmware running on CM3 CPU dedicated for Flow Control support.
> Firmware monitors Packet Processor resources and asserts XON/XOFF by writing to Ports Control 0 Register.
>
> MSS shared SRAM memory used to communicate between CM3 firmware and PP2 driver.
> During init PP2 driver informs firmware about used BM pools, RXQs, congestion and depletion thresholds.
>
> The pause frames are generated whenever congestion or depletion in resources is detected.
> The back pressure is stopped when the resource reaches a sufficient level.
> So the congestion/depletion and sufficient level implement a hysteresis that reduces the XON/XOFF toggle frequency.
>
> Packet Processor v23 hardware introduces support for RX FIFO fill level monitor.
> Patch "add PPv23 version definition" to differ between v23 and v22 hardware.
> Patch "add TX FC firmware check" verifies that CM3 firmware supports Flow Control monitoring.
>
> v6 --> v7
> - Reduce patch set from 18 to 15 patches
> - Documentation change combined into a single patch
> - RXQ and BM size change combined into a single patch
> - Ring size change check moved into "add RXQ flow control configurations" commit
>
> v5 --> v6
> - No change
>
> v4 --> v5
> - Add missed Signed-off
> - Fix warnings in patches 3 and 12
> - Add revision requirement to warning message
> - Move mss_spinlock into RXQ flow control configurations patch
> - Improve FCA RXQ non occupied descriptor threshold commit message
>
> v3 --> v4
> - Remove RFC tag
>
> v2 --> v3
> - Remove inline functions
> - Add PPv2.3 description into marvell-pp2.txt
> - Improve mvpp2_interrupts_mask/unmask procedure
> - Improve FC enable/disable procedure
> - Add priv->sram_pool check
> - Remove gen_pool_destroy call
> - Reduce Flow Control timer to x100 faster
>
> v1 --> v2
> - Add memory requirements information
> - Add EPROBE_DEFER if of_gen_pool_get return NULL
> - Move Flow control configuration to mvpp2_mac_link_up callback
> - Add firmware version info with Flow control support
>
> Konstantin Porotchkin (1):
> dts: marvell: add CM3 SRAM memory to cp115 ethernet device tree
>
> Stefan Chulski (14):
> doc: marvell: add cm3-mem and PPv2.3 description
> net: mvpp2: add CM3 SRAM memory map
> net: mvpp2: add PPv23 version definition
> net: mvpp2: always compare hw-version vs MVPP21
> net: mvpp2: increase BM pool and RXQ size
> net: mvpp2: add FCA periodic timer configurations
> net: mvpp2: add FCA RXQ non occupied descriptor threshold
> net: mvpp2: enable global flow control
> net: mvpp2: add RXQ flow control configurations
> net: mvpp2: add ethtool flow control configuration support
> net: mvpp2: add BM protection underrun feature support
> net: mvpp2: add PPv23 RX FIFO flow control
> net: mvpp2: set 802.3x GoP Flow Control mode
> net: mvpp2: add TX FC firmware check
>
> Documentation/devicetree/bindings/net/marvell-pp2.txt | 4 +-
> arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 10 +
> drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 128 ++++-
> drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 563 ++++++++++++++++++--
> 4 files changed, 655 insertions(+), 50 deletions(-)
>
I tested the latest version on CN9132-DB with 2 10G ports bridged and
connected to the packet generator. Under load the interfaces were
capable of generating the pause frames, so all seems to work as
expected. There is also no regression neither with the feature
disabled, nor on Armada boards (I checked MacchiatoBin and Armada 7040
DB).
I added my comments in the patches.
BTW for that I had to enable the ports in device tree:
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dts
b/arch/arm64/boot/dts/marvell/cn9130-db.dts
index 79020e6d2792..9b248e3a1a34 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9130-db.dts
@@ -129,7 +129,7 @@ &cp0_ethernet {
/* SLM-1521-V2, CON9 */
&cp0_eth0 {
- status = "disabled";
+ status = "okay";
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
phys = <&cp0_comphy4 0>;
diff --git a/arch/arm64/boot/dts/marvell/cn9131-db.dts
b/arch/arm64/boot/dts/marvell/cn9131-db.dts
index 3c975f98b2a3..5c081d68941d 100644
--- a/arch/arm64/boot/dts/marvell/cn9131-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9131-db.dts
@@ -85,7 +85,7 @@ &cp1_ethernet {
/* CON50 */
&cp1_eth0 {
- status = "disabled";
+ status = "okay";
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
phys = <&cp1_comphy4 0>;
Best regards,
Marcin