Hello,
Changes from v2:
- Addressed Stephen's comments and made necessary changes.
- Rebased on top
Changes from v1:
- Addressed Mani's comments and made necessary changes.
- Removed the last patch from the series as it became redundant after making changes.
This series adds APCS mailbox and clock support for SDX65. The APCS IP
in SDX65 provides IPC and clock functionalities. Hence, mailbox support
is added to the "qcom-apcs-ipc-mailbox" driver and a dedicated clock
driver "apcs-sdx65" is added.
Thanks,
Rohit
Rohit Agarwal (7):
dt-bindings: mailbox: Add binding for SDX65 APCS
mailbox: qcom: Add support for SDX65 APCS IPC
dt-bindings: clock: Add A7 PLL binding for SDX65
clk: qcom: Add A7 PLL support for SDX65
ARM: dts: qcom: sdx65: Add support for A7 PLL clock
ARM: dts: qcom: sdx65: Add support for APCS block
clk: qcom: Add SDX65 APCS clock controller support
Documentation/devicetree/bindings/clock/qcom,a7pll.yaml | 3 ++-
.../bindings/mailbox/qcom,apcs-kpss-global.yaml | 1 +
arch/arm/boot/dts/qcom-sdx65.dtsi | 17 +++++++++++++++++
drivers/clk/qcom/Kconfig | 12 ++++++------
drivers/clk/qcom/a7-pll.c | 1 +
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 5 +++++
6 files changed, 32 insertions(+), 7 deletions(-)
--
2.7.4
In SDX65, the IPC bits are located in the APCS GCC block. Also, this block
can provide clock functionality. Hence, add support for IPC with correct
offset and name of the clock provider.
Signed-off-by: Rohit Agarwal <[email protected]>
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
index 9325d2a..54d7659 100644
--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
@@ -53,6 +53,10 @@ static const struct qcom_apcs_ipc_data sdx55_apcs_data = {
.offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk"
};
+static const struct qcom_apcs_ipc_data sdx65_apcs_data = {
+ .offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk"
+};
+
static const struct regmap_config apcs_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -159,6 +163,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = {
{ .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data },
{ .compatible = "qcom,sm6115-apcs-hmss-global", .data = &msm8994_apcs_data },
{ .compatible = "qcom,sdx55-apcs-gcc", .data = &sdx55_apcs_data },
+ { .compatible = "qcom,sdx65-apcs-gcc", .data = &sdx65_apcs_data },
{}
};
MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);
--
2.7.4
Add YAML binding for Cortex A7 PLL clock in Qualcomm
platforms like SDX65.
Signed-off-by: Rohit Agarwal <[email protected]>
---
Documentation/devicetree/bindings/clock/qcom,a7pll.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
index 8666e99..b8889dc 100644
--- a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
@@ -10,13 +10,14 @@ maintainers:
- Manivannan Sadhasivam <[email protected]>
description:
- The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high
+ The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high
frequency clock to the CPU.
properties:
compatible:
enum:
- qcom,sdx55-a7pll
+ - qcom,sdx65-a7pll
reg:
maxItems: 1
--
2.7.4
On SDX65 there is a separate A7 PLL which is used to provide high
frequency clock to the Cortex A7 CPU via a MUX.
Signed-off-by: Rohit Agarwal <[email protected]>
---
arch/arm/boot/dts/qcom-sdx65.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 653df15..0219445 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -125,6 +125,14 @@
<0x17802000 0x1000>;
};
+ a7pll: clock@17808000 {
+ compatible = "qcom,sdx65-a7pll";
+ reg = <0x17808000 0x1000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "bi_tcxo";
+ #clock-cells = <0>;
+ };
+
timer@17820000 {
#address-cells = <1>;
#size-cells = <1>;
--
2.7.4