Hello,
Changes from v3:
- Removed the redundant patches after addressing Mani's comments.
- Rebased on top of v5.17-rc5.
Changes from v2:
- Addressed Stephen's comments and made necessary changes.
- Rebased on top
Changes from v1:
- Addressed Mani's comments and made necessary changes.
- Removed the last patch from the series as it became redundant after making changes.
This series adds APCS mailbox and clock support for SDX65. The APCS IP in SDX65
provides IPC and clock functionalities.
Thanks,
Rohit
Rohit Agarwal (5):
dt-bindings: clock: Add A7 PLL binding for SDX65
clk: qcom: Add A7 PLL support for SDX65
ARM: dts: qcom: sdx65: Add support for A7 PLL clock
ARM: dts: qcom: sdx65: Add support for APCS block
clk: qcom: Add SDX65 APCS clock controller support
Documentation/devicetree/bindings/clock/qcom,a7pll.yaml | 2 +-
arch/arm/boot/dts/qcom-sdx65.dtsi | 17 +++++++++++++++++
drivers/clk/qcom/Kconfig | 12 ++++++------
3 files changed, 24 insertions(+), 7 deletions(-)
--
2.7.4
Add information for Cortex A7 PLL clock in Qualcomm
platform SDX65.
Signed-off-by: Rohit Agarwal <[email protected]>
---
Documentation/devicetree/bindings/clock/qcom,a7pll.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
index 8666e99..0e96f69 100644
--- a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
@@ -10,7 +10,7 @@ maintainers:
- Manivannan Sadhasivam <[email protected]>
description:
- The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high
+ The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high
frequency clock to the CPU.
properties:
--
2.7.4
The APCS block on SDX65 acts as a mailbox controller and also provides
clock output for the Cortex A7 CPU.
Signed-off-by: Rohit Agarwal <[email protected]>
---
arch/arm/boot/dts/qcom-sdx65.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index ec80266..af7453a 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -133,6 +133,15 @@
#clock-cells = <0>;
};
+ apcs: mailbox@17810000 {
+ compatible = "qcom,sdx55-apcs-gcc", "syscon";
+ reg = <0x17810000 0x2000>;
+ #mbox-cells = <1>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>;
+ clock-names = "ref", "pll", "aux";
+ #clock-cells = <0>;
+ };
+
timer@17820000 {
#address-cells = <1>;
#size-cells = <1>;
--
2.7.4
Update A7 PLL Kconfig to reflect support for SDX65.
Signed-off-by: Rohit Agarwal <[email protected]>
---
drivers/clk/qcom/Kconfig | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 42c8741..5159a1d 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -29,11 +29,11 @@ config QCOM_A53PLL
devices.
config QCOM_A7PLL
- tristate "SDX55 A7 PLL"
+ tristate "A7 PLL driver for SDX55 and SDX65"
help
- Support for the A7 PLL on SDX55 devices. It provides the CPU with
+ Support for the A7 PLL on SDX55 and SDX65 devices. It provides the CPU with
frequencies above 1GHz.
- Say Y if you want to support higher CPU frequencies on SDX55
+ Say Y if you want to support higher CPU frequencies on SDX55 and SDX65
devices.
config QCOM_CLK_APCS_MSM8916
--
2.7.4
On Tue, 22 Feb 2022 10:26:21 +0530, Rohit Agarwal wrote:
> Add information for Cortex A7 PLL clock in Qualcomm
> platform SDX65.
>
> Signed-off-by: Rohit Agarwal <[email protected]>
> ---
> Documentation/devicetree/bindings/clock/qcom,a7pll.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Acked-by: Rob Herring <[email protected]>
Quoting Rohit Agarwal (2022-02-21 20:56:22)
> Update A7 PLL Kconfig to reflect support for SDX65.
>
> Signed-off-by: Rohit Agarwal <[email protected]>
> ---
Reviewed-by: Stephen Boyd <[email protected]>
Quoting Rohit Agarwal (2022-02-21 20:56:21)
> Add information for Cortex A7 PLL clock in Qualcomm
> platform SDX65.
>
> Signed-off-by: Rohit Agarwal <[email protected]>
> ---
Reviewed-by: Stephen Boyd <[email protected]>
On Tue, Feb 22, 2022 at 10:26:21AM +0530, Rohit Agarwal wrote:
> Add information for Cortex A7 PLL clock in Qualcomm
> platform SDX65.
>
> Signed-off-by: Rohit Agarwal <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Thanks,
Mani
> ---
> Documentation/devicetree/bindings/clock/qcom,a7pll.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
> index 8666e99..0e96f69 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
> @@ -10,7 +10,7 @@ maintainers:
> - Manivannan Sadhasivam <[email protected]>
>
> description:
> - The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high
> + The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high
> frequency clock to the CPU.
>
> properties:
> --
> 2.7.4
>
On Tue, Feb 22, 2022 at 10:26:24AM +0530, Rohit Agarwal wrote:
> The APCS block on SDX65 acts as a mailbox controller and also provides
> clock output for the Cortex A7 CPU.
>
> Signed-off-by: Rohit Agarwal <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Thanks,
Mani
> ---
> arch/arm/boot/dts/qcom-sdx65.dtsi | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
> index ec80266..af7453a 100644
> --- a/arch/arm/boot/dts/qcom-sdx65.dtsi
> +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
> @@ -133,6 +133,15 @@
> #clock-cells = <0>;
> };
>
> + apcs: mailbox@17810000 {
> + compatible = "qcom,sdx55-apcs-gcc", "syscon";
> + reg = <0x17810000 0x2000>;
> + #mbox-cells = <1>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>;
> + clock-names = "ref", "pll", "aux";
> + #clock-cells = <0>;
> + };
> +
> timer@17820000 {
> #address-cells = <1>;
> #size-cells = <1>;
> --
> 2.7.4
>
On Tue, Feb 22, 2022 at 10:26:22AM +0530, Rohit Agarwal wrote:
> Update A7 PLL Kconfig to reflect support for SDX65.
>
> Signed-off-by: Rohit Agarwal <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Thanks,
Mani
> ---
> drivers/clk/qcom/Kconfig | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 42c8741..5159a1d 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -29,11 +29,11 @@ config QCOM_A53PLL
> devices.
>
> config QCOM_A7PLL
> - tristate "SDX55 A7 PLL"
> + tristate "A7 PLL driver for SDX55 and SDX65"
> help
> - Support for the A7 PLL on SDX55 devices. It provides the CPU with
> + Support for the A7 PLL on SDX55 and SDX65 devices. It provides the CPU with
> frequencies above 1GHz.
> - Say Y if you want to support higher CPU frequencies on SDX55
> + Say Y if you want to support higher CPU frequencies on SDX55 and SDX65
> devices.
>
> config QCOM_CLK_APCS_MSM8916
> --
> 2.7.4
>